2005-04-17 06:20:36 +08:00
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/*
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* Contains register definitions common to the Book E PowerPC
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* specification. Notice that while the IBM-40x series of CPUs
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* are not true Book E PowerPCs, they borrowed a number of features
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* before Book E was finalized, and are included here as well. Unfortunatly,
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* they sometimes used different locations than true Book E CPUs did.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_PPC_REG_BOOKE_H__
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#define __ASM_PPC_REG_BOOKE_H__
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2006-12-11 13:15:47 +08:00
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#ifndef __ASSEMBLY__
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2005-04-17 06:20:36 +08:00
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile("mfpmr %0," __stringify(rn) \
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: "=r" (rval)); rval;})
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#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
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#endif /* __ASSEMBLY__ */
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/* Freescale Book E Performance Monitor APU Registers */
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#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
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#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
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#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
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#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
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#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
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#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
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#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
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#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
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#define PMLCA_FC 0x80000000 /* Freeze Counter */
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#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
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#define PMLCA_FCU 0x20000000 /* Freeze in User */
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#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
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#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
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#define PMLCA_CE 0x04000000 /* Condition Enable */
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#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
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#define PMLCA_EVENT_SHIFT 16
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#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
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#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
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#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
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#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
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#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
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#define PMLCB_THRESHMUL_SHIFT 8
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#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
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#define PMLCB_THRESHOLD_SHIFT 0
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#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
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#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
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#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
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#define PMGC0_FCECE 0x20000000 /* Freeze countes on
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Enabled Condition or
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Event */
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#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
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#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
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#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
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#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
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#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
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#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
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#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
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#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
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#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
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#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
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/* Machine State Register (MSR) Fields */
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#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
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#define MSR_SPE (1<<25) /* Enable SPE */
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#define MSR_DWE (1<<10) /* Debug Wait Enable */
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#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
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#define MSR_IS MSR_IR /* Instruction Space */
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#define MSR_DS MSR_DR /* Data Space */
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#define MSR_PMM (1<<2) /* Performance monitor mark bit */
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/* Default MSR for kernel mode. */
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#if defined (CONFIG_40x)
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#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
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#elif defined(CONFIG_BOOKE)
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#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
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#endif
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/* Special Purpose Registers (SPRNs)*/
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#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
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#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
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#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
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#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
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#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
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#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
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#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
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#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
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#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
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#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
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#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
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#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
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#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
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#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
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#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
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#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
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#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
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#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
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#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
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#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
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#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
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#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
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#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
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#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
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#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
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#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
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#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
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#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
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#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
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#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
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#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
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#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
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#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
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#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
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#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
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#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
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#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
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#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
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#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
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#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
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#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
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#define SPRN_MCSR 0x23C /* Machine Check Status Register */
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#define SPRN_MCAR 0x23D /* Machine Check Address Register */
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2005-06-26 05:54:37 +08:00
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#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
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#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
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2005-04-17 06:20:36 +08:00
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#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
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#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
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#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
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#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
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#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
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#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
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#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
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2005-04-17 06:24:22 +08:00
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#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
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2005-04-17 06:20:36 +08:00
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#define SPRN_PID1 0x279 /* Process ID Register 1 */
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#define SPRN_PID2 0x27A /* Process ID Register 2 */
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
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#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
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#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
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#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
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#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
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#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
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#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
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#define SPRN_SLER 0x3BB /* Little-endian real mode */
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#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
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#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
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#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
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#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
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#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
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#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
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#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
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#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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#define SPRN_SVR 0x3FF /* System Version Register */
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/*
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* SPRs which have conflicting definitions on true Book E versus classic,
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* or IBM 40x.
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*/
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#ifdef CONFIG_BOOKE
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#define SPRN_PID 0x030 /* Process ID */
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#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
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#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
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#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
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#define SPRN_DEAR 0x03D /* Data Error Address Register */
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#define SPRN_ESR 0x03E /* Exception Syndrome Register */
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#define SPRN_PIR 0x11E /* Processor Identification Register */
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#define SPRN_DBSR 0x130 /* Debug Status Register */
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#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
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#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
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#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
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#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
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#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
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#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
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#define SPRN_TSR 0x150 /* Timer Status Register */
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#define SPRN_TCR 0x154 /* Timer Control Register */
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#endif /* Book E */
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#ifdef CONFIG_40x
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#define SPRN_PID 0x3B1 /* Process ID */
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#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
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#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
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#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
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#define SPRN_TSR 0x3D8 /* Timer Status Register */
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#define SPRN_TCR 0x3DA /* Timer Control Register */
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#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
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#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
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#define SPRN_DBSR 0x3F0 /* Debug Status Register */
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#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
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#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
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#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
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#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
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#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
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#endif
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/* Bit definitions for CCR1. */
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2006-04-25 16:22:44 +08:00
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#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
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2005-04-17 06:20:36 +08:00
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#define CCR1_TCS 0x00000080 /* Timer Clock Select */
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/* Bit definitions for the MCSR. */
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2007-12-21 12:39:21 +08:00
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#ifdef CONFIG_4xx
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2005-04-17 06:20:36 +08:00
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#define MCSR_MCS 0x80000000 /* Machine Check Summary */
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#define MCSR_IB 0x40000000 /* Instruction PLB Error */
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#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
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#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
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#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
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#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
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#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
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#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
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#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
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#endif
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/* Bit definitions for the DBSR. */
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/*
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* DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
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*/
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#ifdef CONFIG_BOOKE
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#define DBSR_IC 0x08000000 /* Instruction Completion */
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#define DBSR_BT 0x04000000 /* Branch Taken */
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#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
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#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
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#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
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#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
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#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
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#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
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#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
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#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
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#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
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#endif
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#ifdef CONFIG_40x
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#define DBSR_IC 0x80000000 /* Instruction Completion */
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#define DBSR_BT 0x40000000 /* Branch taken */
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#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
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2006-09-20 22:11:59 +08:00
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#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */
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#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */
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#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */
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#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */
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#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */
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#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */
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#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */
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#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */
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2005-04-17 06:20:36 +08:00
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#endif
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/* Bit definitions related to the ESR. */
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#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
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#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
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#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
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#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
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#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
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#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
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2007-12-18 03:30:15 +08:00
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#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
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2005-04-17 06:20:36 +08:00
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#define ESR_PTR 0x02000000 /* Program Exception - Trap */
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2005-05-01 23:58:40 +08:00
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#define ESR_FP 0x01000000 /* Floating Point Operation */
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2005-04-17 06:20:36 +08:00
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#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
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#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
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#define ESR_ST 0x00800000 /* Store Operation */
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#define ESR_DLK 0x00200000 /* Data Cache Locking */
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#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
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2005-06-26 05:54:37 +08:00
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#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
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2005-04-17 06:20:36 +08:00
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#define ESR_BO 0x00020000 /* Byte Ordering */
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/* Bit definitions related to the DBCR0. */
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#define DBCR0_EDM 0x80000000 /* External Debug Mode */
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#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
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#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
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#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
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#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
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#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
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#define DBCR0_RST_NONE 0x00000000 /* No Reset */
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#define DBCR0_IC 0x08000000 /* Instruction Completion */
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#define DBCR0_BT 0x04000000 /* Branch Taken */
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#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
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#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
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#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
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#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
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#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
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#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
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#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
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#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
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#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
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#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
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#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
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#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
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#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
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/* Bit definitions related to the TCR. */
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#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
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#define TCR_WP_MASK TCR_WP(3)
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#define WP_2_17 0 /* 2^17 clocks */
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#define WP_2_21 1 /* 2^21 clocks */
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#define WP_2_25 2 /* 2^25 clocks */
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#define WP_2_29 3 /* 2^29 clocks */
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#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
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#define TCR_WRC_MASK TCR_WRC(3)
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#define WRC_NONE 0 /* No reset will occur */
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#define WRC_CORE 1 /* Core reset will occur */
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#define WRC_CHIP 2 /* Chip reset will occur */
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#define WRC_SYSTEM 3 /* System reset will occur */
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#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
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#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
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#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
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#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
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#define TCR_FP_MASK TCR_FP(3)
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#define FP_2_9 0 /* 2^9 clocks */
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#define FP_2_13 1 /* 2^13 clocks */
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#define FP_2_17 2 /* 2^17 clocks */
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#define FP_2_21 3 /* 2^21 clocks */
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#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
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#define TCR_ARE 0x00400000 /* Auto Reload Enable */
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/* Bit definitions for the TSR. */
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#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
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#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
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#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
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#define WRS_NONE 0 /* No WDT reset occurred */
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#define WRS_CORE 1 /* WDT forced core reset */
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#define WRS_CHIP 2 /* WDT forced chip reset */
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#define WRS_SYSTEM 3 /* WDT forced system reset */
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#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
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#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
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#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
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/* Bit definitions for the DCCR. */
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#define DCCR_NOCACHE 0 /* Noncacheable */
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#define DCCR_CACHE 1 /* Cacheable */
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/* Bit definitions for DCWR. */
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#define DCWR_COPY 0 /* Copy-back */
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#define DCWR_WRITE 1 /* Write-through */
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/* Bit definitions for ICCR. */
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#define ICCR_NOCACHE 0 /* Noncacheable */
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#define ICCR_CACHE 1 /* Cacheable */
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/* Bit definitions for L1CSR0. */
|
2005-06-26 05:54:37 +08:00
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#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
|
2005-04-17 06:20:36 +08:00
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#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
|
2005-06-26 05:54:37 +08:00
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#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
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2005-04-17 06:20:36 +08:00
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#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
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2005-06-26 05:54:37 +08:00
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/* Bit definitions for L1CSR1. */
|
2005-04-17 06:20:36 +08:00
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#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
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#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
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#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
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/* Bit definitions for SGR. */
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#define SGR_NORMAL 0 /* Speculative fetching allowed. */
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#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
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/* Bit definitions for SPEFSCR. */
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#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
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#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
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#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
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#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
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#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
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#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
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#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
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#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
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#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
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#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
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#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
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#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
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#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
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#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
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#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
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#define SPEFSCR_OV 0x00004000 /* Integer overflow */
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#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
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#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
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#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
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#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
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#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
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#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
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#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
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#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
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#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
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#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
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#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
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#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
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/*
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|
|
|
* The IBM-403 is an even more odd special case, as it is much
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* older than the IBM-405 series. We put these down here incase someone
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* wishes to support these machines again.
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*/
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#ifdef CONFIG_403GCX
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/* Special Purpose Registers (SPRNs)*/
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#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
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#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
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#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
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#define SPRN_TBHI 0x3DC /* Time Base High */
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|
#define SPRN_TBLO 0x3DD /* Time Base Low */
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#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
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#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
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#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
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#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
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#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
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/* Bit definitions for the DBCR. */
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#define DBCR_EDM DBCR0_EDM
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#define DBCR_IDM DBCR0_IDM
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#define DBCR_RST(x) (((x) & 0x3) << 28)
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#define DBCR_RST_NONE 0
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#define DBCR_RST_CORE 1
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#define DBCR_RST_CHIP 2
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#define DBCR_RST_SYSTEM 3
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#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
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#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
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#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
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#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
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#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
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#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
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#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
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#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
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#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
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#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
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#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
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#define DAC_BYTE 0
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#define DAC_HALF 1
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#define DAC_WORD 2
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#define DAC_QUAD 3
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#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
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#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
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#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
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#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
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#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
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#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
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#define DBCR_SIA 0x00000008 /* Second IAC Enable */
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#define DBCR_SDA 0x00000004 /* Second DAC Enable */
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#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
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#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
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#endif /* 403GCX */
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#endif /* __ASM_PPC_REG_BOOKE_H__ */
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#endif /* __KERNEL__ */
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