2013-12-11 15:54:50 +08:00
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Hisilicon Platforms Device Tree Bindings
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----------------------------------------------------
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Hi4511 Board
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Required root node properties:
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- compatible = "hisilicon,hi3620-hi4511";
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2013-12-18 08:23:49 +08:00
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2014-05-09 17:10:53 +08:00
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HiP04 D01 Board
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Required root node properties:
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- compatible = "hisilicon,hip04-d01";
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2014-12-24 11:09:58 +08:00
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HiP01 ca9x2 Board
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Required root node properties:
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- compatible = "hisilicon,hip01-ca9x2";
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2014-05-09 17:10:53 +08:00
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2013-12-18 08:23:49 +08:00
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Hisilicon system controller
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Required properties:
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- compatible : "hisilicon,sysctrl"
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- reg : Register address and size
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Optional properties:
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- smp-offset : offset in sysctrl for notifying slave cpu booting
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cpu 1, reg;
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cpu 2, reg + 0x4;
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cpu 3, reg + 0x8;
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If reg value is not zero, cpun exit wfi and go
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- resume-offset : offset in sysctrl for notifying cpu0 when resume
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- reboot-offset : offset in sysctrl for system reboot
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Example:
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/* for Hi3620 */
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sysctrl: system-controller@fc802000 {
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compatible = "hisilicon,sysctrl";
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reg = <0xfc802000 0x1000>;
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smp-offset = <0x31c>;
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resume-offset = <0x308>;
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reboot-offset = <0x4>;
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};
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2014-01-13 17:37:32 +08:00
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2014-12-24 11:09:58 +08:00
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-----------------------------------------------------------------------
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Hisilicon HiP01 system controller
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Required properties:
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- compatible : "hisilicon,hip01-sysctrl"
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- reg : Register address and size
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The HiP01 system controller is mostly compatible with hisilicon
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system controller,but it has some specific control registers for
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HIP01 SoC family, such as slave core boot, and also some same
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registers located at different offset.
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Example:
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/* for hip01-ca9x2 */
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sysctrl: system-controller@10000000 {
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compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
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reg = <0x10000000 0x1000>;
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reboot-offset = <0x4>;
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};
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2014-04-11 11:54:11 +08:00
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-----------------------------------------------------------------------
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Hisilicon CPU controller
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Required properties:
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- compatible : "hisilicon,cpuctrl"
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- reg : Register address and size
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The clock registers and power registers of secondary cores are defined
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in CPU controller, especially in HIX5HD2 SoC.
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-----------------------------------------------------------------------
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2014-01-13 17:37:32 +08:00
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PCTRL: Peripheral misc control register
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Required Properties:
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- compatible: "hisilicon,pctrl"
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- reg: Address and size of pctrl.
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Example:
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/* for Hi3620 */
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pctrl: pctrl@fca09000 {
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compatible = "hisilicon,pctrl";
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reg = <0xfca09000 0x1000>;
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};
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2014-05-09 17:10:53 +08:00
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-----------------------------------------------------------------------
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Fabric:
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Required Properties:
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- compatible: "hisilicon,hip04-fabric";
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- reg: Address and size of Fabric
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-----------------------------------------------------------------------
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Bootwrapper boot method (software protocol on SMP):
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Required Properties:
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- compatible: "hisilicon,hip04-bootwrapper";
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- boot-method: Address and size of boot method.
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[0]: bootwrapper physical address
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[1]: bootwrapper size
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[2]: relocation physical address
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[3]: relocation size
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