2011-12-14 00:36:12 +08:00
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/*
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* r8a7779 processor support
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*
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2013-04-05 02:53:50 +08:00
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* Copyright (C) 2011, 2013 Renesas Solutions Corp.
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2011-12-14 00:36:12 +08:00
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* Copyright (C) 2011 Magnus Damm
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2013-04-05 02:53:50 +08:00
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* Copyright (C) 2013 Cogent Embedded, Inc.
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2011-12-14 00:36:12 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2016-03-08 08:42:07 +08:00
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#include <linux/clk/renesas.h>
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2015-06-25 16:57:39 +08:00
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#include <linux/clocksource.h>
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2011-12-14 00:36:12 +08:00
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#include <linux/init.h>
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#include <linux/irq.h>
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2013-08-02 14:39:56 +08:00
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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2014-06-21 00:53:05 +08:00
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2011-12-14 00:36:12 +08:00
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#include <asm/mach/arch.h>
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2012-02-29 20:37:43 +08:00
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#include <asm/mach/map.h>
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2014-06-21 00:53:05 +08:00
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2014-06-17 15:47:37 +08:00
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#include "common.h"
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2014-06-21 00:53:05 +08:00
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#include "r8a7779.h"
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2012-02-29 20:37:43 +08:00
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static struct map_desc r8a7779_io_desc[] __initdata = {
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2014-11-15 00:07:05 +08:00
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/* 2M identity mapping for 0xf0000000 (MPCORE) */
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2012-02-29 20:37:43 +08:00
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{
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.virtual = 0xf0000000,
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.pfn = __phys_to_pfn(0xf0000000),
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.length = SZ_2M,
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.type = MT_DEVICE_NONSHARED
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},
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2014-11-15 00:07:05 +08:00
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/* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
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2012-02-29 20:37:43 +08:00
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{
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0xfe000000),
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.length = SZ_16M,
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.type = MT_DEVICE_NONSHARED
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},
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};
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2015-07-16 15:54:03 +08:00
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static void __init r8a7779_map_io(void)
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2012-02-29 20:37:43 +08:00
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{
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ARM: shmobile: Add early debugging support using SCIF(A)
Add serial port debug macros for the SCIF(A) serial ports.
This includes all supported shmobile SoCs, except for EMEV2.
The configuration logic (both Kconfig and #ifdef) is more complicated than
one would expect, for several reasons:
1. Not all SoCs have the same serial devices, and they're not always
at the same addresses.
2. There are two different types: SCIF and SCIFA. Fortunately they can
easily be distinguished by physical address.
3. Not all boards use the same serial port for the console.
The defaults correspond to the boards that are supported in
mainline. If you want to use a different serial port, just change
the value of CONFIG_DEBUG_UART_PHYS, and the rest will auto-adapt.
4. debug_ll_io_init() maps the SCIF(A) registers to a fixed virtual
address. 0xfdxxxxxx was chosen, as it should lie below VMALLOC_END
= 0xff000000, and must not conflict with the 2 MiB reserved region
at PCI_IO_VIRT_BASE = 0xfee00000.
- On SoCs not using the legacy machine_desc.map_io(),
debug_ll_io_init() is called by the ARM core code.
- On SoCs using the legacy machine_desc.map_io(),
debug_ll_io_init() must be called explicitly. Calls are added
for r8a7740, r8a7779, sh7372, and sh73a0.
This was derived from the r8a7790 version by Laurent Pinchart.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-11-14 23:49:47 +08:00
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debug_ll_io_init();
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2012-02-29 20:37:43 +08:00
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iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
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}
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2011-12-14 00:36:12 +08:00
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2013-08-02 14:39:56 +08:00
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/* IRQ */
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#define INT2SMSKCR0 IOMEM(0xfe7822a0)
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#define INT2SMSKCR1 IOMEM(0xfe7822a4)
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#define INT2SMSKCR2 IOMEM(0xfe7822a8)
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#define INT2SMSKCR3 IOMEM(0xfe7822ac)
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#define INT2SMSKCR4 IOMEM(0xfe7822b0)
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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2015-07-16 15:54:03 +08:00
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static void __init r8a7779_init_irq_dt(void)
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2013-10-02 16:38:23 +08:00
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{
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2013-08-02 14:39:56 +08:00
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irqchip_init();
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2015-07-16 15:54:03 +08:00
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2013-08-02 14:39:56 +08:00
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/* route all interrupts to ARM */
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__raw_writel(0xffffffff, INT2NTSR0);
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__raw_writel(0x3fffffff, INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0xfffffff0, INT2SMSKCR0);
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__raw_writel(0xfff7ffff, INT2SMSKCR1);
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__raw_writel(0xfffbffdf, INT2SMSKCR2);
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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2014-05-15 19:32:01 +08:00
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#define MODEMR 0xffcc0020
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2015-07-16 15:54:03 +08:00
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static u32 __init r8a7779_read_mode_pins(void)
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2012-11-21 21:00:15 +08:00
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{
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2014-05-15 19:32:01 +08:00
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static u32 mode;
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static bool mode_valid;
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if (!mode_valid) {
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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mode_valid = true;
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}
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2012-11-21 21:00:15 +08:00
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2014-05-15 19:32:01 +08:00
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return mode;
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2012-11-21 21:00:15 +08:00
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}
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2015-06-25 16:57:39 +08:00
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static void __init r8a7779_init_time(void)
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{
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r8a7779_clocks_init(r8a7779_read_mode_pins());
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2015-09-28 22:49:18 +08:00
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clocksource_probe();
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2015-06-25 16:57:39 +08:00
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}
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2015-07-28 06:27:52 +08:00
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static const char *const r8a7779_compat_dt[] __initconst = {
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2012-11-21 21:00:15 +08:00
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"renesas,r8a7779",
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NULL,
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};
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2013-03-04 15:11:20 +08:00
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DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
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2015-07-13 14:15:02 +08:00
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.smp = smp_ops(r8a7779_smp_ops),
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2012-11-21 21:00:15 +08:00
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.map_io = r8a7779_map_io,
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2014-05-16 12:42:59 +08:00
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.init_early = shmobile_init_delay,
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2015-06-25 16:57:39 +08:00
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.init_time = r8a7779_init_time,
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2012-11-21 21:00:15 +08:00
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.init_irq = r8a7779_init_irq_dt,
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2014-07-31 07:32:33 +08:00
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.init_late = shmobile_init_late,
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2012-11-21 21:00:15 +08:00
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.dt_compat = r8a7779_compat_dt,
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MACHINE_END
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