2012-11-15 05:51:08 +08:00
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/*
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* Symmetric Multi Processing (SMP) support for Armada XP
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
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* This file implements the routines for preparing the SMP infrastructure
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* and waking up the secondary CPUs
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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2013-07-26 21:17:54 +08:00
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#include <linux/of_address.h>
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2013-03-22 00:59:15 +08:00
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#include <linux/mbus.h>
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2012-11-15 05:51:08 +08:00
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "armada-370-xp.h"
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#include "pmsu.h"
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#include "coherency.h"
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2013-07-26 21:17:54 +08:00
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#define AXP_BOOTROM_BASE 0xfff00000
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#define AXP_BOOTROM_SIZE 0x100000
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2013-07-03 23:01:42 +08:00
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static struct clk *__init get_cpu_clk(int cpu)
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{
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struct clk *cpu_clk;
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struct device_node *np = of_get_cpu_node(cpu, NULL);
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if (WARN(!np, "missing cpu node\n"))
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return NULL;
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cpu_clk = of_clk_get(np, 0);
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if (WARN_ON(IS_ERR(cpu_clk)))
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return NULL;
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return cpu_clk;
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}
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2013-11-07 17:02:38 +08:00
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static void __init set_secondary_cpus_clock(void)
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2012-11-15 05:51:08 +08:00
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{
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2013-07-03 23:01:42 +08:00
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int thiscpu, cpu;
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2012-11-15 05:51:08 +08:00
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unsigned long rate;
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2013-07-03 23:01:42 +08:00
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struct clk *cpu_clk;
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2012-11-15 05:51:08 +08:00
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thiscpu = smp_processor_id();
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2013-07-03 23:01:42 +08:00
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cpu_clk = get_cpu_clk(thiscpu);
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if (!cpu_clk)
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2012-11-15 05:51:08 +08:00
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return;
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clk_prepare_enable(cpu_clk);
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rate = clk_get_rate(cpu_clk);
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/* set all the other CPU clk to the same rate than the boot CPU */
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2013-07-03 23:01:42 +08:00
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for_each_possible_cpu(cpu) {
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if (cpu == thiscpu)
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continue;
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cpu_clk = get_cpu_clk(cpu);
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if (!cpu_clk)
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2012-11-15 05:51:08 +08:00
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return;
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2013-07-03 23:01:42 +08:00
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clk_set_rate(cpu_clk, rate);
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2012-11-15 05:51:08 +08:00
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}
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}
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2013-06-18 03:43:14 +08:00
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static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-11-15 05:51:08 +08:00
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{
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2014-04-14 21:53:58 +08:00
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int ret, hw_cpu;
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2012-11-15 05:51:08 +08:00
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pr_info("Booting CPU %d\n", cpu);
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2014-04-14 21:53:58 +08:00
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hw_cpu = cpu_logical_map(cpu);
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
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ret = mvebu_cpu_reset_deassert(hw_cpu);
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if (ret) {
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pr_warn("unable to boot CPU: %d\n", ret);
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return ret;
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}
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2012-11-15 05:51:08 +08:00
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return 0;
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}
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static void __init armada_xp_smp_init_cpus(void)
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{
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2013-07-23 19:32:42 +08:00
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unsigned int ncores = num_possible_cpus();
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arm: mvebu: remove dependency of SMP init on static I/O mapping
The ->smp_init_cpus() function is called very early during boot, at a
point where dynamic I/O mappings are not yet possible. However, in the
Armada 370/XP implementation of this function, we have to get the
number of CPUs. We used to do that by accessing a hardware register,
which requires relying on a static I/O mapping set up by
->map_io(). Not only this requires hardcoding a virtual address, but
it also prevents us from removing the static I/O mapping.
So this commit changes the way used to get the number of CPUs: we now
use the Device Tree, which is a representation of the hardware, and
provides us the number of available CPUs. This is also more accurate,
because it potentially allows to boot the Linux kernel on only a
number of CPUs given by the Device Tree, instead of unconditionally on
all CPUs.
As a consequence, the coherency_get_cpu_count() function becomes no
longer used, so we remove it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-06-05 15:04:54 +08:00
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if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
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panic("Invalid number of CPUs in DT\n");
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2012-11-15 05:51:08 +08:00
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}
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2013-11-07 17:02:38 +08:00
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static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
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2012-11-15 05:51:08 +08:00
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{
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2013-07-26 21:17:54 +08:00
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struct device_node *node;
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struct resource res;
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int err;
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2012-11-15 05:51:08 +08:00
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set_secondary_cpus_clock();
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flush_cache_all();
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2014-04-14 23:10:07 +08:00
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set_cpu_coherent();
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2013-07-26 21:17:54 +08:00
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/*
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* In order to boot the secondary CPUs we need to ensure
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* the bootROM is mapped at the correct address.
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*/
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node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
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if (!node)
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panic("Cannot find 'marvell,bootrom' compatible node");
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err = of_address_to_resource(node, 0, &res);
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if (err < 0)
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panic("Cannot get 'bootrom' node address");
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if (res.start != AXP_BOOTROM_BASE ||
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resource_size(&res) != AXP_BOOTROM_SIZE)
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panic("The address for the BootROM is incorrect");
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2012-11-15 05:51:08 +08:00
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}
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struct smp_operations armada_xp_smp_ops __initdata = {
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.smp_init_cpus = armada_xp_smp_init_cpus,
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.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
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.smp_boot_secondary = armada_xp_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = armada_xp_cpu_die,
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#endif
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};
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2014-04-14 21:53:59 +08:00
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CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
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&armada_xp_smp_ops);
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