123 lines
2.9 KiB
C
123 lines
2.9 KiB
C
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/*
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* Symmetric Multi Processing (SMP) support for Armada XP
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
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* This file implements the routines for preparing the SMP infrastructure
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* and waking up the secondary CPUs
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "armada-370-xp.h"
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#include "pmsu.h"
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#include "coherency.h"
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void __init set_secondary_cpus_clock(void)
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{
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int thiscpu;
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unsigned long rate;
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struct clk *cpu_clk = NULL;
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struct device_node *np = NULL;
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thiscpu = smp_processor_id();
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for_each_node_by_type(np, "cpu") {
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int err;
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int cpu;
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err = of_property_read_u32(np, "reg", &cpu);
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if (WARN_ON(err))
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return;
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if (cpu == thiscpu) {
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cpu_clk = of_clk_get(np, 0);
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break;
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}
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}
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if (WARN_ON(IS_ERR(cpu_clk)))
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return;
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clk_prepare_enable(cpu_clk);
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rate = clk_get_rate(cpu_clk);
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/* set all the other CPU clk to the same rate than the boot CPU */
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for_each_node_by_type(np, "cpu") {
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int err;
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int cpu;
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err = of_property_read_u32(np, "reg", &cpu);
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if (WARN_ON(err))
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return;
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if (cpu != thiscpu) {
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cpu_clk = of_clk_get(np, 0);
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clk_set_rate(cpu_clk, rate);
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}
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}
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}
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static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
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{
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armada_xp_mpic_smp_cpu_init();
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}
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static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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pr_info("Booting CPU %d\n", cpu);
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armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
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return 0;
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}
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static void __init armada_xp_smp_init_cpus(void)
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{
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unsigned int i, ncores;
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ncores = coherency_get_cpu_count();
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/* Limit possible CPUs to defconfig */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %d CPUs physically present. Only %d configured.",
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ncores, nr_cpu_ids);
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pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(armada_mpic_send_doorbell);
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}
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void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
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{
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set_secondary_cpus_clock();
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flush_cache_all();
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set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
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}
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struct smp_operations armada_xp_smp_ops __initdata = {
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.smp_init_cpus = armada_xp_smp_init_cpus,
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.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
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.smp_secondary_init = armada_xp_secondary_init,
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.smp_boot_secondary = armada_xp_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = armada_xp_cpu_die,
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#endif
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};
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