2012-05-09 21:27:20 +08:00
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/**
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* tpci200.h
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*
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* driver for the carrier TEWS TPCI-200
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2012-11-16 23:19:58 +08:00
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*
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* Copyright (C) 2009-2012 CERN (www.cern.ch)
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* Author: Nicolas Serafini, EIC2 SA
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* Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
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2012-05-09 21:27:20 +08:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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2012-05-11 16:17:14 +08:00
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* Software Foundation; version 2 of the License.
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2012-05-09 21:27:20 +08:00
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*/
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#ifndef _TPCI200_H_
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#define _TPCI200_H_
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#include <linux/limits.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/swab.h>
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#include <linux/io.h>
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2012-11-17 02:33:45 +08:00
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#include <linux/ipack.h>
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2012-05-09 21:27:20 +08:00
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#define TPCI200_NB_SLOT 0x4
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#define TPCI200_NB_BAR 0x6
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#define TPCI200_VENDOR_ID 0x1498
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#define TPCI200_DEVICE_ID 0x30C8
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#define TPCI200_SUBVENDOR_ID 0x1498
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#define TPCI200_SUBDEVICE_ID 0x300A
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2012-09-04 23:01:07 +08:00
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#define TPCI200_CFG_MEM_BAR 0
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2012-05-09 21:27:20 +08:00
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#define TPCI200_IP_INTERFACE_BAR 2
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#define TPCI200_IO_ID_INT_SPACES_BAR 3
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#define TPCI200_MEM16_SPACE_BAR 4
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#define TPCI200_MEM8_SPACE_BAR 5
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2012-09-11 19:34:54 +08:00
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struct tpci200_regs {
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2012-09-12 20:55:46 +08:00
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__le16 revision;
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2012-09-11 19:34:54 +08:00
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/* writes to control should occur with the mutex held to protect
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* read-modify-write operations */
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2012-09-12 20:55:46 +08:00
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__le16 control[4];
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__le16 reset;
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__le16 status;
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2012-09-11 19:34:54 +08:00
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u8 reserved[242];
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} __packed;
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2012-05-09 21:27:20 +08:00
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#define TPCI200_IFACE_SIZE 0x100
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#define TPCI200_IO_SPACE_OFF 0x0000
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2012-09-27 18:37:30 +08:00
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#define TPCI200_IO_SPACE_INTERVAL 0x0100
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2012-05-09 21:27:20 +08:00
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#define TPCI200_IO_SPACE_SIZE 0x0080
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#define TPCI200_ID_SPACE_OFF 0x0080
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2012-09-27 18:37:30 +08:00
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#define TPCI200_ID_SPACE_INTERVAL 0x0100
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2012-05-09 21:27:20 +08:00
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#define TPCI200_ID_SPACE_SIZE 0x0040
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#define TPCI200_INT_SPACE_OFF 0x00C0
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2012-09-27 18:37:30 +08:00
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#define TPCI200_INT_SPACE_INTERVAL 0x0100
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2012-05-09 21:27:20 +08:00
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#define TPCI200_INT_SPACE_SIZE 0x0040
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#define TPCI200_IOIDINT_SIZE 0x0400
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2012-09-27 18:37:30 +08:00
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#define TPCI200_MEM8_SPACE_INTERVAL 0x00400000
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#define TPCI200_MEM8_SPACE_SIZE 0x00400000
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#define TPCI200_MEM16_SPACE_INTERVAL 0x00800000
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#define TPCI200_MEM16_SPACE_SIZE 0x00800000
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2012-05-09 21:27:20 +08:00
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2012-09-11 19:34:54 +08:00
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/* control field in tpci200_regs */
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2012-05-09 21:27:20 +08:00
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#define TPCI200_INT0_EN 0x0040
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#define TPCI200_INT1_EN 0x0080
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#define TPCI200_INT0_EDGE 0x0010
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#define TPCI200_INT1_EDGE 0x0020
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#define TPCI200_ERR_INT_EN 0x0008
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#define TPCI200_TIME_INT_EN 0x0004
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#define TPCI200_RECOVER_EN 0x0002
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#define TPCI200_CLK32 0x0001
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2012-09-11 19:34:54 +08:00
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/* reset field in tpci200_regs */
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2012-05-09 21:27:20 +08:00
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#define TPCI200_A_RESET 0x0001
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#define TPCI200_B_RESET 0x0002
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#define TPCI200_C_RESET 0x0004
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#define TPCI200_D_RESET 0x0008
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2012-09-11 19:34:54 +08:00
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/* status field in tpci200_regs */
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2012-05-09 21:27:20 +08:00
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#define TPCI200_A_TIMEOUT 0x1000
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#define TPCI200_B_TIMEOUT 0x2000
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#define TPCI200_C_TIMEOUT 0x4000
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#define TPCI200_D_TIMEOUT 0x8000
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#define TPCI200_A_ERROR 0x0100
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#define TPCI200_B_ERROR 0x0200
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#define TPCI200_C_ERROR 0x0400
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#define TPCI200_D_ERROR 0x0800
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#define TPCI200_A_INT0 0x0001
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#define TPCI200_A_INT1 0x0002
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#define TPCI200_B_INT0 0x0004
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#define TPCI200_B_INT1 0x0008
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#define TPCI200_C_INT0 0x0010
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#define TPCI200_C_INT1 0x0020
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#define TPCI200_D_INT0 0x0040
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#define TPCI200_D_INT1 0x0080
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#define TPCI200_SLOT_INT_MASK 0x00FF
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2012-09-04 23:01:07 +08:00
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/* PCI Configuration registers. The PCI bridge is a PLX Technology PCI9030. */
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#define LAS1_DESC 0x2C
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#define LAS2_DESC 0x30
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/* Bits in the LAS?_DESC registers */
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#define LAS_BIT_BIGENDIAN 24
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2012-05-09 21:27:20 +08:00
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#define VME_IOID_SPACE "IOID"
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#define VME_MEM_SPACE "MEM"
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/**
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* struct slot_irq - slot IRQ definition.
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* @vector Vector number
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* @handler Handler called when IRQ arrives
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* @arg Handler argument
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*
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*/
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struct slot_irq {
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2012-09-11 19:35:13 +08:00
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struct ipack_device *holder;
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2012-05-18 17:10:06 +08:00
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int vector;
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2012-09-12 20:55:38 +08:00
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irqreturn_t (*handler)(void *);
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2012-05-18 17:10:06 +08:00
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void *arg;
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2012-05-09 21:27:20 +08:00
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};
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/**
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* struct tpci200_slot - data specific to the tpci200 slot.
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* @slot_id Slot identification gived to external interface
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* @irq Slot IRQ infos
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* @io_phys IO physical base address register of the slot
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* @id_phys ID physical base address register of the slot
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2012-09-13 18:32:19 +08:00
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* @int_phys INT physical base address register of the slot
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2012-05-09 21:27:20 +08:00
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* @mem_phys MEM physical base address register of the slot
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*
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*/
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struct tpci200_slot {
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2012-09-27 18:37:28 +08:00
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struct slot_irq *irq;
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2012-05-09 21:27:20 +08:00
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};
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/**
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* struct tpci200_infos - informations specific of the TPCI200 tpci200.
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* @pci_dev PCI device
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* @interface_regs Pointer to IP interface space (Bar 2)
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* @ioidint_space Pointer to IP ID, IO and INT space (Bar 3)
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* @mem8_space Pointer to MEM space (Bar 4)
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*
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*/
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struct tpci200_infos {
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struct pci_dev *pdev;
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struct pci_device_id *id_table;
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2012-09-11 19:34:54 +08:00
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struct tpci200_regs __iomem *interface_regs;
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2012-09-04 23:01:07 +08:00
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void __iomem *cfg_regs;
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2012-05-18 17:10:05 +08:00
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struct ipack_bus_device *ipack_bus;
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2012-05-09 21:27:20 +08:00
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};
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struct tpci200_board {
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unsigned int number;
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struct mutex mutex;
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2012-09-12 20:55:33 +08:00
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spinlock_t regs_lock;
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2012-05-09 21:27:20 +08:00
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struct tpci200_slot *slots;
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struct tpci200_infos *info;
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2012-09-27 18:37:29 +08:00
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phys_addr_t mod_mem[IPACK_SPACE_COUNT];
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2012-05-09 21:27:20 +08:00
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};
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#endif /* _TPCI200_H_ */
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