2010-09-22 00:34:10 +08:00
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/*
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* OMAP4 PRM module functions
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*
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2011-07-10 19:56:31 +08:00
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* Copyright (C) 2011 Texas Instruments, Inc.
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2010-09-22 00:34:10 +08:00
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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OMAP4: PRCM: add OMAP4-specific accessor/mutator functions
In some ways, the OMAP4 PRCM register layout is quite different than
the OMAP2/3 PRCM register layout. For example, on OMAP2/3, from a
register layout point of view, all CM instances were located in the CM
subsystem, and all PRM instances were located in the PRM subsystem.
OMAP4 changes this. Now, for example, some CM instances, such as
WKUP_CM and EMU_CM, are located in the system PRM subsystem. And a
"local PRCM" exists for the MPU - this PRCM combines registers that
would normally appear in both CM and PRM instances, but uses its own
register layout which matches neither the OMAP2/3 PRCM layout nor the
OMAP4 PRCM layout.
To try to deal with this, introduce some new functions, omap4_cminst*
and omap4_prminst*. The former is to be used when writing to a CM
instance register (no matter what subsystem or hardware module it
exists in), and the latter, similarly, with PRM instance registers.
To determine which "PRCM partition" to write to, the functions take a
PRCM instance ID argument. Subsequent patches add these partition IDs
to the OMAP4 powerdomain and clockdomain definitions.
As far as I can see, there's really no good way to handle these types
of register access inconsistencies. This patch seemed like the least
bad approach.
Moving forward, the long-term goal is to remove all direct PRCM
register access from the PM code. PRCM register access should go
through layers such as the powerdomain and clockdomain code that can
hide the details of how to interact with the specific hardware
variant.
While here, rename cm4xxx.c to cm44xx.c to match the naming convention
of the other OMAP4 PRCM files.
Thanks to Santosh Shilimkar <santosh.shilimkar@ti.com>, Rajendra Nayak
<rnayak@ti.com>, and Benoît Cousson <b-cousson@ti.com> for some comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
2010-12-22 12:05:14 +08:00
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#include <linux/io.h>
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2010-09-22 00:34:10 +08:00
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#include <plat/common.h>
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#include <plat/cpu.h>
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#include <plat/prcm.h>
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2011-03-29 01:52:04 +08:00
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#include "vp.h"
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2010-12-22 06:30:54 +08:00
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#include "prm44xx.h"
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2010-09-22 00:34:10 +08:00
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#include "prm-regbits-44xx.h"
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OMAP4: PRCM: add OMAP4-specific accessor/mutator functions
In some ways, the OMAP4 PRCM register layout is quite different than
the OMAP2/3 PRCM register layout. For example, on OMAP2/3, from a
register layout point of view, all CM instances were located in the CM
subsystem, and all PRM instances were located in the PRM subsystem.
OMAP4 changes this. Now, for example, some CM instances, such as
WKUP_CM and EMU_CM, are located in the system PRM subsystem. And a
"local PRCM" exists for the MPU - this PRCM combines registers that
would normally appear in both CM and PRM instances, but uses its own
register layout which matches neither the OMAP2/3 PRCM layout nor the
OMAP4 PRCM layout.
To try to deal with this, introduce some new functions, omap4_cminst*
and omap4_prminst*. The former is to be used when writing to a CM
instance register (no matter what subsystem or hardware module it
exists in), and the latter, similarly, with PRM instance registers.
To determine which "PRCM partition" to write to, the functions take a
PRCM instance ID argument. Subsequent patches add these partition IDs
to the OMAP4 powerdomain and clockdomain definitions.
As far as I can see, there's really no good way to handle these types
of register access inconsistencies. This patch seemed like the least
bad approach.
Moving forward, the long-term goal is to remove all direct PRCM
register access from the PM code. PRCM register access should go
through layers such as the powerdomain and clockdomain code that can
hide the details of how to interact with the specific hardware
variant.
While here, rename cm4xxx.c to cm44xx.c to match the naming convention
of the other OMAP4 PRCM files.
Thanks to Santosh Shilimkar <santosh.shilimkar@ti.com>, Rajendra Nayak
<rnayak@ti.com>, and Benoît Cousson <b-cousson@ti.com> for some comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
2010-12-22 12:05:14 +08:00
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/* PRM low-level functions */
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/* Read a register in a CM/PRM instance in the PRM module */
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u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
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{
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return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
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}
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/* Write into a register in a CM/PRM instance in the PRM module */
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void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
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{
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__raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
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{
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u32 v;
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v = omap4_prm_read_inst_reg(inst, reg);
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v &= ~mask;
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v |= bits;
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omap4_prm_write_inst_reg(v, inst, reg);
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return v;
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}
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2011-03-29 01:52:04 +08:00
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/* PRM VP */
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/*
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* struct omap4_vp - OMAP4 VP register access description.
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* @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
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*/
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struct omap4_vp {
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u32 irqstatus_mpu;
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u32 tranxdone_status;
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};
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static struct omap4_vp omap4_vp[] = {
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[OMAP4_VP_VDD_MPU_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
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.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_IVA_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_CORE_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
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},
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};
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u32 omap4_prm_vp_check_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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u32 irqstatus;
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irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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return irqstatus & vp->tranxdone_status;
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}
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void omap4_prm_vp_clear_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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omap4_prminst_write_inst_reg(vp->tranxdone_status,
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OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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};
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