2006-05-24 08:18:44 +08:00
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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/*
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* This code implements the DMA subsystem. It provides a HW-neutral interface
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* for other kernel code to use asynchronous memory copy capabilities,
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* if present, and allows different HW DMA drivers to register as providing
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* this capability.
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*
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* Due to the fact we are accelerating what is already a relatively fast
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* operation, the code goes to great lengths to avoid additional overhead,
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* such as locking.
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*
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* LOCKING:
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*
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* The subsystem keeps two global lists, dma_device_list and dma_client_list.
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* Both of these are protected by a mutex, dma_list_mutex.
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*
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* Each device has a channels list, which runs unlocked but is never modified
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* once the device is registered, it's just setup by the driver.
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*
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* Each client has a channels list, it's only modified under the client->lock
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* and in an RCU callback, so it's safe to read under rcu_read_lock().
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*
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* Each device has a kref, which is initialized to 1 when the device is
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* registered. A kref_put is done for each class_device registered. When the
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* class_device is released, the coresponding kref_put is done in the release
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* method. Every time one of the device's channels is allocated to a client,
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* a kref_get occurs. When the channel is freed, the coresponding kref_put
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* happens. The device's release function does a completion, so
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* unregister_device does a remove event, class_device_unregister, a kref_put
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* for the first reference, then waits on the completion for all other
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* references to finish.
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*
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* Each channel has an open-coded implementation of Rusty Russell's "bigref,"
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* with a kref and a per_cpu local_t. A single reference is set when on an
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* ADDED event, and removed with a REMOVE event. Net DMA client takes an
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* extra reference per outstanding transaction. The relase function does a
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* kref_put on the device. -ChrisL
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 02:10:43 +08:00
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#include <linux/mm.h>
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2006-05-24 08:18:44 +08:00
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/hardirq.h>
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#include <linux/spinlock.h>
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#include <linux/percpu.h>
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#include <linux/rcupdate.h>
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#include <linux/mutex.h>
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 02:10:43 +08:00
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#include <linux/jiffies.h>
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2006-05-24 08:18:44 +08:00
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static DEFINE_MUTEX(dma_list_mutex);
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static LIST_HEAD(dma_device_list);
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static LIST_HEAD(dma_client_list);
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/* --- sysfs implementation --- */
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static ssize_t show_memcpy_count(struct class_device *cd, char *buf)
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{
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struct dma_chan *chan = container_of(cd, struct dma_chan, class_dev);
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unsigned long count = 0;
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int i;
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2006-05-26 04:26:53 +08:00
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for_each_possible_cpu(i)
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2006-05-24 08:18:44 +08:00
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count += per_cpu_ptr(chan->local, i)->memcpy_count;
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return sprintf(buf, "%lu\n", count);
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}
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static ssize_t show_bytes_transferred(struct class_device *cd, char *buf)
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{
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struct dma_chan *chan = container_of(cd, struct dma_chan, class_dev);
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unsigned long count = 0;
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int i;
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2006-05-26 04:26:53 +08:00
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for_each_possible_cpu(i)
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2006-05-24 08:18:44 +08:00
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count += per_cpu_ptr(chan->local, i)->bytes_transferred;
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return sprintf(buf, "%lu\n", count);
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}
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static ssize_t show_in_use(struct class_device *cd, char *buf)
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{
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struct dma_chan *chan = container_of(cd, struct dma_chan, class_dev);
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return sprintf(buf, "%d\n", (chan->client ? 1 : 0));
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}
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static struct class_device_attribute dma_class_attrs[] = {
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__ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
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__ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
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__ATTR(in_use, S_IRUGO, show_in_use, NULL),
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__ATTR_NULL
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};
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static void dma_async_device_cleanup(struct kref *kref);
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static void dma_class_dev_release(struct class_device *cd)
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{
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struct dma_chan *chan = container_of(cd, struct dma_chan, class_dev);
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kref_put(&chan->device->refcount, dma_async_device_cleanup);
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}
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static struct class dma_devclass = {
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.name = "dma",
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.class_dev_attrs = dma_class_attrs,
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.release = dma_class_dev_release,
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};
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/* --- client and device registration --- */
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/**
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* dma_client_chan_alloc - try to allocate a channel to a client
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* @client: &dma_client
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*
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* Called with dma_list_mutex held.
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*/
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static struct dma_chan *dma_client_chan_alloc(struct dma_client *client)
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{
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struct dma_device *device;
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struct dma_chan *chan;
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unsigned long flags;
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int desc; /* allocated descriptor count */
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/* Find a channel, any DMA engine will do */
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list_for_each_entry(device, &dma_device_list, global_node) {
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list_for_each_entry(chan, &device->channels, device_node) {
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if (chan->client)
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continue;
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desc = chan->device->device_alloc_chan_resources(chan);
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if (desc >= 0) {
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kref_get(&device->refcount);
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kref_init(&chan->refcount);
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chan->slow_ref = 0;
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INIT_RCU_HEAD(&chan->rcu);
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chan->client = client;
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spin_lock_irqsave(&client->lock, flags);
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list_add_tail_rcu(&chan->client_node,
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&client->channels);
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spin_unlock_irqrestore(&client->lock, flags);
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return chan;
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}
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}
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}
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return NULL;
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}
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 02:10:43 +08:00
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enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
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{
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enum dma_status status;
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unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
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dma_async_issue_pending(chan);
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do {
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status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
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if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
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printk(KERN_ERR "dma_sync_wait_timeout!\n");
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return DMA_ERROR;
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}
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} while (status == DMA_IN_PROGRESS);
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return status;
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}
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EXPORT_SYMBOL(dma_sync_wait);
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2006-05-24 08:18:44 +08:00
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/**
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2006-07-04 10:45:31 +08:00
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* dma_chan_cleanup - release a DMA channel's resources
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* @kref: kernel reference structure that contains the DMA channel device
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2006-05-24 08:18:44 +08:00
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*/
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void dma_chan_cleanup(struct kref *kref)
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{
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struct dma_chan *chan = container_of(kref, struct dma_chan, refcount);
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chan->device->device_free_chan_resources(chan);
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chan->client = NULL;
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kref_put(&chan->device->refcount, dma_async_device_cleanup);
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}
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2007-03-17 05:38:05 +08:00
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EXPORT_SYMBOL(dma_chan_cleanup);
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2006-05-24 08:18:44 +08:00
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static void dma_chan_free_rcu(struct rcu_head *rcu)
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{
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struct dma_chan *chan = container_of(rcu, struct dma_chan, rcu);
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int bias = 0x7FFFFFFF;
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int i;
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2006-05-26 04:26:53 +08:00
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for_each_possible_cpu(i)
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2006-05-24 08:18:44 +08:00
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bias -= local_read(&per_cpu_ptr(chan->local, i)->refcount);
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atomic_sub(bias, &chan->refcount.refcount);
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kref_put(&chan->refcount, dma_chan_cleanup);
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}
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static void dma_client_chan_free(struct dma_chan *chan)
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{
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atomic_add(0x7FFFFFFF, &chan->refcount.refcount);
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chan->slow_ref = 1;
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call_rcu(&chan->rcu, dma_chan_free_rcu);
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}
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/**
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* dma_chans_rebalance - reallocate channels to clients
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*
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* When the number of DMA channel in the system changes,
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2006-07-04 10:45:31 +08:00
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* channels need to be rebalanced among clients.
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2006-05-24 08:18:44 +08:00
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*/
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static void dma_chans_rebalance(void)
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{
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struct dma_client *client;
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struct dma_chan *chan;
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unsigned long flags;
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mutex_lock(&dma_list_mutex);
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list_for_each_entry(client, &dma_client_list, global_node) {
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while (client->chans_desired > client->chan_count) {
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chan = dma_client_chan_alloc(client);
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if (!chan)
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break;
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client->chan_count++;
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client->event_callback(client,
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chan,
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DMA_RESOURCE_ADDED);
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}
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while (client->chans_desired < client->chan_count) {
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spin_lock_irqsave(&client->lock, flags);
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chan = list_entry(client->channels.next,
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struct dma_chan,
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client_node);
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list_del_rcu(&chan->client_node);
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spin_unlock_irqrestore(&client->lock, flags);
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client->chan_count--;
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client->event_callback(client,
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chan,
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|
DMA_RESOURCE_REMOVED);
|
|
|
|
dma_client_chan_free(chan);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_client_register - allocate and register a &dma_client
|
|
|
|
* @event_callback: callback for notification of channel addition/removal
|
|
|
|
*/
|
|
|
|
struct dma_client *dma_async_client_register(dma_event_callback event_callback)
|
|
|
|
{
|
|
|
|
struct dma_client *client;
|
|
|
|
|
|
|
|
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
|
|
|
if (!client)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&client->channels);
|
|
|
|
spin_lock_init(&client->lock);
|
|
|
|
client->chans_desired = 0;
|
|
|
|
client->chan_count = 0;
|
|
|
|
client->event_callback = event_callback;
|
|
|
|
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
|
|
list_add_tail(&client->global_node, &dma_client_list);
|
|
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
|
|
|
|
return client;
|
|
|
|
}
|
2007-03-17 05:38:05 +08:00
|
|
|
EXPORT_SYMBOL(dma_async_client_register);
|
2006-05-24 08:18:44 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_client_unregister - unregister a client and free the &dma_client
|
2006-07-04 10:45:31 +08:00
|
|
|
* @client: &dma_client to free
|
2006-05-24 08:18:44 +08:00
|
|
|
*
|
|
|
|
* Force frees any allocated DMA channels, frees the &dma_client memory
|
|
|
|
*/
|
|
|
|
void dma_async_client_unregister(struct dma_client *client)
|
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
|
|
|
|
if (!client)
|
|
|
|
return;
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
list_for_each_entry_rcu(chan, &client->channels, client_node)
|
|
|
|
dma_client_chan_free(chan);
|
|
|
|
rcu_read_unlock();
|
|
|
|
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
|
|
list_del(&client->global_node);
|
|
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
|
|
|
|
kfree(client);
|
|
|
|
dma_chans_rebalance();
|
|
|
|
}
|
2007-03-17 05:38:05 +08:00
|
|
|
EXPORT_SYMBOL(dma_async_client_unregister);
|
2006-05-24 08:18:44 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_client_chan_request - request DMA channels
|
|
|
|
* @client: &dma_client
|
|
|
|
* @number: count of DMA channels requested
|
|
|
|
*
|
|
|
|
* Clients call dma_async_client_chan_request() to specify how many
|
|
|
|
* DMA channels they need, 0 to free all currently allocated.
|
|
|
|
* The resulting allocations/frees are indicated to the client via the
|
|
|
|
* event callback.
|
|
|
|
*/
|
|
|
|
void dma_async_client_chan_request(struct dma_client *client,
|
|
|
|
unsigned int number)
|
|
|
|
{
|
|
|
|
client->chans_desired = number;
|
|
|
|
dma_chans_rebalance();
|
|
|
|
}
|
2007-03-17 05:38:05 +08:00
|
|
|
EXPORT_SYMBOL(dma_async_client_chan_request);
|
2006-05-24 08:18:44 +08:00
|
|
|
|
|
|
|
/**
|
2006-07-04 10:45:31 +08:00
|
|
|
* dma_async_device_register - registers DMA devices found
|
2006-05-24 08:18:44 +08:00
|
|
|
* @device: &dma_device
|
|
|
|
*/
|
|
|
|
int dma_async_device_register(struct dma_device *device)
|
|
|
|
{
|
|
|
|
static int id;
|
2007-03-09 01:57:34 +08:00
|
|
|
int chancnt = 0, rc;
|
2006-05-24 08:18:44 +08:00
|
|
|
struct dma_chan* chan;
|
|
|
|
|
|
|
|
if (!device)
|
|
|
|
return -ENODEV;
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 02:10:43 +08:00
|
|
|
/* validate device routines */
|
|
|
|
BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
|
|
|
|
!device->device_prep_dma_memcpy);
|
|
|
|
BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
|
|
|
|
!device->device_prep_dma_xor);
|
|
|
|
BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) &&
|
|
|
|
!device->device_prep_dma_zero_sum);
|
|
|
|
BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
|
|
|
|
!device->device_prep_dma_memset);
|
|
|
|
BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) &&
|
|
|
|
!device->device_prep_dma_interrupt);
|
|
|
|
|
|
|
|
BUG_ON(!device->device_alloc_chan_resources);
|
|
|
|
BUG_ON(!device->device_free_chan_resources);
|
|
|
|
BUG_ON(!device->device_dependency_added);
|
|
|
|
BUG_ON(!device->device_is_tx_complete);
|
|
|
|
BUG_ON(!device->device_issue_pending);
|
|
|
|
BUG_ON(!device->dev);
|
|
|
|
|
2006-05-24 08:18:44 +08:00
|
|
|
init_completion(&device->done);
|
|
|
|
kref_init(&device->refcount);
|
|
|
|
device->dev_id = id++;
|
|
|
|
|
|
|
|
/* represent channels in sysfs. Probably want devs too */
|
|
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
|
|
chan->local = alloc_percpu(typeof(*chan->local));
|
|
|
|
if (chan->local == NULL)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
chan->chan_id = chancnt++;
|
|
|
|
chan->class_dev.class = &dma_devclass;
|
|
|
|
chan->class_dev.dev = NULL;
|
|
|
|
snprintf(chan->class_dev.class_id, BUS_ID_SIZE, "dma%dchan%d",
|
|
|
|
device->dev_id, chan->chan_id);
|
|
|
|
|
2007-03-09 01:57:34 +08:00
|
|
|
rc = class_device_register(&chan->class_dev);
|
|
|
|
if (rc) {
|
|
|
|
chancnt--;
|
|
|
|
free_percpu(chan->local);
|
|
|
|
chan->local = NULL;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
2006-05-24 08:18:44 +08:00
|
|
|
kref_get(&device->refcount);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
|
|
list_add_tail(&device->global_node, &dma_device_list);
|
|
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
|
|
|
|
dma_chans_rebalance();
|
|
|
|
|
|
|
|
return 0;
|
2007-03-09 01:57:34 +08:00
|
|
|
|
|
|
|
err_out:
|
|
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
|
|
if (chan->local == NULL)
|
|
|
|
continue;
|
|
|
|
kref_put(&device->refcount, dma_async_device_cleanup);
|
|
|
|
class_device_unregister(&chan->class_dev);
|
|
|
|
chancnt--;
|
|
|
|
free_percpu(chan->local);
|
|
|
|
}
|
|
|
|
return rc;
|
2006-05-24 08:18:44 +08:00
|
|
|
}
|
2007-03-17 05:38:05 +08:00
|
|
|
EXPORT_SYMBOL(dma_async_device_register);
|
2006-05-24 08:18:44 +08:00
|
|
|
|
|
|
|
/**
|
2006-07-04 10:45:31 +08:00
|
|
|
* dma_async_device_cleanup - function called when all references are released
|
|
|
|
* @kref: kernel reference object
|
2006-05-24 08:18:44 +08:00
|
|
|
*/
|
|
|
|
static void dma_async_device_cleanup(struct kref *kref)
|
|
|
|
{
|
|
|
|
struct dma_device *device;
|
|
|
|
|
|
|
|
device = container_of(kref, struct dma_device, refcount);
|
|
|
|
complete(&device->done);
|
|
|
|
}
|
|
|
|
|
2006-07-04 10:45:31 +08:00
|
|
|
/**
|
|
|
|
* dma_async_device_unregister - unregisters DMA devices
|
|
|
|
* @device: &dma_device
|
|
|
|
*/
|
|
|
|
void dma_async_device_unregister(struct dma_device *device)
|
2006-05-24 08:18:44 +08:00
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
mutex_lock(&dma_list_mutex);
|
|
|
|
list_del(&device->global_node);
|
|
|
|
mutex_unlock(&dma_list_mutex);
|
|
|
|
|
|
|
|
list_for_each_entry(chan, &device->channels, device_node) {
|
|
|
|
if (chan->client) {
|
|
|
|
spin_lock_irqsave(&chan->client->lock, flags);
|
|
|
|
list_del(&chan->client_node);
|
|
|
|
chan->client->chan_count--;
|
|
|
|
spin_unlock_irqrestore(&chan->client->lock, flags);
|
|
|
|
chan->client->event_callback(chan->client,
|
|
|
|
chan,
|
|
|
|
DMA_RESOURCE_REMOVED);
|
|
|
|
dma_client_chan_free(chan);
|
|
|
|
}
|
|
|
|
class_device_unregister(&chan->class_dev);
|
|
|
|
}
|
|
|
|
dma_chans_rebalance();
|
|
|
|
|
|
|
|
kref_put(&device->refcount, dma_async_device_cleanup);
|
|
|
|
wait_for_completion(&device->done);
|
|
|
|
}
|
2007-03-17 05:38:05 +08:00
|
|
|
EXPORT_SYMBOL(dma_async_device_unregister);
|
2006-05-24 08:18:44 +08:00
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 02:10:43 +08:00
|
|
|
/**
|
|
|
|
* dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
|
|
|
|
* @chan: DMA channel to offload copy to
|
|
|
|
* @dest: destination address (virtual)
|
|
|
|
* @src: source address (virtual)
|
|
|
|
* @len: length
|
|
|
|
*
|
|
|
|
* Both @dest and @src must be mappable to a bus address according to the
|
|
|
|
* DMA mapping API rules for streaming mappings.
|
|
|
|
* Both @dest and @src must stay memory resident (kernel memory or locked
|
|
|
|
* user space pages).
|
|
|
|
*/
|
|
|
|
dma_cookie_t
|
|
|
|
dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
|
|
|
|
void *src, size_t len)
|
|
|
|
{
|
|
|
|
struct dma_device *dev = chan->device;
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
dma_addr_t addr;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
tx = dev->device_prep_dma_memcpy(chan, len, 0);
|
|
|
|
if (!tx)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
tx->ack = 1;
|
|
|
|
tx->callback = NULL;
|
|
|
|
addr = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
|
|
|
|
tx->tx_set_src(addr, tx, 0);
|
|
|
|
addr = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
|
|
|
|
tx->tx_set_dest(addr, tx, 0);
|
|
|
|
cookie = tx->tx_submit(tx);
|
|
|
|
|
|
|
|
cpu = get_cpu();
|
|
|
|
per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
|
|
|
|
per_cpu_ptr(chan->local, cpu)->memcpy_count++;
|
|
|
|
put_cpu();
|
|
|
|
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_memcpy_buf_to_pg - offloaded copy from address to page
|
|
|
|
* @chan: DMA channel to offload copy to
|
|
|
|
* @page: destination page
|
|
|
|
* @offset: offset in page to copy to
|
|
|
|
* @kdata: source address (virtual)
|
|
|
|
* @len: length
|
|
|
|
*
|
|
|
|
* Both @page/@offset and @kdata must be mappable to a bus address according
|
|
|
|
* to the DMA mapping API rules for streaming mappings.
|
|
|
|
* Both @page/@offset and @kdata must stay memory resident (kernel memory or
|
|
|
|
* locked user space pages)
|
|
|
|
*/
|
|
|
|
dma_cookie_t
|
|
|
|
dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
|
|
|
|
unsigned int offset, void *kdata, size_t len)
|
|
|
|
{
|
|
|
|
struct dma_device *dev = chan->device;
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
dma_addr_t addr;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
tx = dev->device_prep_dma_memcpy(chan, len, 0);
|
|
|
|
if (!tx)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
tx->ack = 1;
|
|
|
|
tx->callback = NULL;
|
|
|
|
addr = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
|
|
|
|
tx->tx_set_src(addr, tx, 0);
|
|
|
|
addr = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
|
|
|
|
tx->tx_set_dest(addr, tx, 0);
|
|
|
|
cookie = tx->tx_submit(tx);
|
|
|
|
|
|
|
|
cpu = get_cpu();
|
|
|
|
per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
|
|
|
|
per_cpu_ptr(chan->local, cpu)->memcpy_count++;
|
|
|
|
put_cpu();
|
|
|
|
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
|
|
|
|
|
|
|
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/**
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* dma_async_memcpy_pg_to_pg - offloaded copy from page to page
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* @chan: DMA channel to offload copy to
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* @dest_pg: destination page
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* @dest_off: offset in page to copy to
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* @src_pg: source page
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* @src_off: offset in page to copy from
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* @len: length
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*
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* Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
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* address according to the DMA mapping API rules for streaming mappings.
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* Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
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* (kernel memory or locked user space pages).
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*/
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dma_cookie_t
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dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
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unsigned int dest_off, struct page *src_pg, unsigned int src_off,
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size_t len)
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{
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struct dma_device *dev = chan->device;
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struct dma_async_tx_descriptor *tx;
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dma_addr_t addr;
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dma_cookie_t cookie;
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int cpu;
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tx = dev->device_prep_dma_memcpy(chan, len, 0);
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if (!tx)
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return -ENOMEM;
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tx->ack = 1;
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tx->callback = NULL;
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addr = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
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tx->tx_set_src(addr, tx, 0);
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addr = dma_map_page(dev->dev, dest_pg, dest_off, len, DMA_FROM_DEVICE);
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tx->tx_set_dest(addr, tx, 0);
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cookie = tx->tx_submit(tx);
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cpu = get_cpu();
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per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
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per_cpu_ptr(chan->local, cpu)->memcpy_count++;
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put_cpu();
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return cookie;
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}
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EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
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void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
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struct dma_chan *chan)
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{
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tx->chan = chan;
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spin_lock_init(&tx->lock);
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INIT_LIST_HEAD(&tx->depend_node);
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INIT_LIST_HEAD(&tx->depend_list);
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}
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EXPORT_SYMBOL(dma_async_tx_descriptor_init);
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2006-05-24 08:18:44 +08:00
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static int __init dma_bus_init(void)
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{
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mutex_init(&dma_list_mutex);
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return class_register(&dma_devclass);
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}
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subsys_initcall(dma_bus_init);
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