2005-04-17 06:20:36 +08:00
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#ifndef _ALPHA_ATOMIC_H
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#define _ALPHA_ATOMIC_H
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2009-01-07 06:40:39 +08:00
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#include <linux/types.h>
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2005-10-25 14:05:58 +08:00
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#include <asm/barrier.h>
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2012-04-03 04:04:13 +08:00
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#include <asm/cmpxchg.h>
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2005-10-25 14:05:58 +08:00
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2005-04-17 06:20:36 +08:00
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc...
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*
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* But use these as seldom as possible since they are much slower
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* than regular operations.
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*/
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2012-08-19 10:41:03 +08:00
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#define ATOMIC_INIT(i) { (i) }
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#define ATOMIC64_INIT(i) { (i) }
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2005-04-17 06:20:36 +08:00
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2010-05-17 12:33:53 +08:00
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#define atomic_read(v) (*(volatile int *)&(v)->counter)
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#define atomic64_read(v) (*(volatile long *)&(v)->counter)
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2005-04-17 06:20:36 +08:00
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#define atomic_set(v,i) ((v)->counter = (i))
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#define atomic64_set(v,i) ((v)->counter = (i))
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/*
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* To get proper branch prediction for the main line, we must branch
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* forward to code at the end of this object's .text section, then
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* branch back to restart the operation.
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*/
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static __inline__ void atomic_add(int i, atomic_t * v)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" addl %0,%2,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter)
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:"Ir" (i), "m" (v->counter));
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}
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static __inline__ void atomic64_add(long i, atomic64_t * v)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldq_l %0,%1\n"
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" addq %0,%2,%0\n"
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" stq_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter)
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:"Ir" (i), "m" (v->counter));
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}
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static __inline__ void atomic_sub(int i, atomic_t * v)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" subl %0,%2,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter)
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:"Ir" (i), "m" (v->counter));
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}
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static __inline__ void atomic64_sub(long i, atomic64_t * v)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldq_l %0,%1\n"
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" subq %0,%2,%0\n"
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" stq_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter)
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:"Ir" (i), "m" (v->counter));
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}
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/*
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* Same as above, but return the result value
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*/
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2008-02-05 14:30:02 +08:00
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static inline int atomic_add_return(int i, atomic_t *v)
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2005-04-17 06:20:36 +08:00
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{
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long temp, result;
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" addl %0,%3,%2\n"
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" addl %0,%3,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter), "=&r" (result)
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:"Ir" (i), "m" (v->counter) : "memory");
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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return result;
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}
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static __inline__ long atomic64_add_return(long i, atomic64_t * v)
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{
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long temp, result;
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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__asm__ __volatile__(
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"1: ldq_l %0,%1\n"
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" addq %0,%3,%2\n"
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" addq %0,%3,%0\n"
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" stq_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter), "=&r" (result)
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:"Ir" (i), "m" (v->counter) : "memory");
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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return result;
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}
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static __inline__ long atomic_sub_return(int i, atomic_t * v)
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{
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long temp, result;
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" subl %0,%3,%2\n"
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" subl %0,%3,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter), "=&r" (result)
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:"Ir" (i), "m" (v->counter) : "memory");
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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return result;
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}
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static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
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{
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long temp, result;
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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__asm__ __volatile__(
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"1: ldq_l %0,%1\n"
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" subq %0,%3,%2\n"
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" subq %0,%3,%0\n"
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" stq_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (v->counter), "=&r" (result)
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:"Ir" (i), "m" (v->counter) : "memory");
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2005-10-22 02:06:15 +08:00
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smp_mb();
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2005-04-17 06:20:36 +08:00
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return result;
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}
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2007-05-08 15:34:18 +08:00
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#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
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2006-01-10 07:59:17 +08:00
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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2005-11-14 08:07:24 +08:00
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2007-05-08 15:34:18 +08:00
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/**
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2011-07-27 07:09:07 +08:00
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* __atomic_add_unless - add unless the number is a given value
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2007-05-08 15:34:18 +08:00
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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2011-07-27 07:09:07 +08:00
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* Returns the old value of @v.
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2007-05-08 15:34:18 +08:00
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*/
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2011-07-27 07:09:07 +08:00
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static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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2007-05-08 15:34:38 +08:00
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{
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2013-07-11 22:42:14 +08:00
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int c, new, old;
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smp_mb();
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__asm__ __volatile__(
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"1: ldl_l %[old],%[mem]\n"
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" cmpeq %[old],%[u],%[c]\n"
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" addl %[old],%[a],%[new]\n"
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" bne %[c],2f\n"
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" stl_c %[new],%[mem]\n"
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" beq %[new],3f\n"
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"2:\n"
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".subsection 2\n"
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"3: br 1b\n"
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".previous"
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: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
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: [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u)
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: "memory");
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smp_mb();
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return old;
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2007-05-08 15:34:38 +08:00
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}
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2005-11-14 08:07:25 +08:00
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2007-05-08 15:34:18 +08:00
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/**
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* atomic64_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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2013-07-11 22:42:14 +08:00
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* Returns true iff @v was not @u.
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2007-05-08 15:34:18 +08:00
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*/
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2007-05-08 15:34:38 +08:00
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static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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2013-07-11 22:42:14 +08:00
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long c, tmp;
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smp_mb();
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__asm__ __volatile__(
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"1: ldq_l %[tmp],%[mem]\n"
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" cmpeq %[tmp],%[u],%[c]\n"
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" addq %[tmp],%[a],%[tmp]\n"
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" bne %[c],2f\n"
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" stq_c %[tmp],%[mem]\n"
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" beq %[tmp],3f\n"
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"2:\n"
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".subsection 2\n"
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"3: br 1b\n"
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".previous"
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: [tmp] "=&r"(tmp), [c] "=&r"(c)
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: [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u)
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: "memory");
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smp_mb();
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return !c;
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2007-05-08 15:34:38 +08:00
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}
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2007-05-08 15:34:18 +08:00
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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2005-11-24 05:37:40 +08:00
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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2005-04-17 06:20:36 +08:00
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#define atomic_dec_return(v) atomic_sub_return(1,(v))
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#define atomic64_dec_return(v) atomic64_sub_return(1,(v))
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#define atomic_inc_return(v) atomic_add_return(1,(v))
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#define atomic64_inc_return(v) atomic64_add_return(1,(v))
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
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#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
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2005-11-24 05:37:40 +08:00
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#define atomic64_inc_and_test(v) (atomic64_add_return(1, (v)) == 0)
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2005-04-17 06:20:36 +08:00
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
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#define atomic_inc(v) atomic_add(1,(v))
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#define atomic64_inc(v) atomic64_add(1,(v))
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#define atomic_dec(v) atomic_sub(1,(v))
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#define atomic64_dec(v) atomic64_sub(1,(v))
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#endif /* _ALPHA_ATOMIC_H */
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