2005-04-17 06:20:36 +08:00
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/*
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* linux/arch/alpha/kernel/sys_noritake.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the NORITAKE (AlphaServer 1000A),
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* CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_apecs.h>
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#include <asm/core_cia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/* Note mask bit is true for ENABLED irqs. */
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static int cached_irq_mask;
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static inline void
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noritake_update_irq_hw(int irq, int mask)
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{
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int port = 0x54a;
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if (irq >= 32) {
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mask >>= 16;
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port = 0x54c;
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}
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outw(mask, port);
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}
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static void
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noritake_enable_irq(unsigned int irq)
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{
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noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
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}
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static void
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noritake_disable_irq(unsigned int irq)
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{
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noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
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}
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static unsigned int
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noritake_startup_irq(unsigned int irq)
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{
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noritake_enable_irq(irq);
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return 0;
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}
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2007-04-17 13:53:17 +08:00
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static void
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noritake_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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noritake_enable_irq(irq);
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}
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2005-04-17 06:20:36 +08:00
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static struct hw_interrupt_type noritake_irq_type = {
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.typename = "NORITAKE",
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.startup = noritake_startup_irq,
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.shutdown = noritake_disable_irq,
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.enable = noritake_enable_irq,
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.disable = noritake_disable_irq,
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.ack = noritake_disable_irq,
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2007-04-17 13:53:17 +08:00
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.end = noritake_end_irq,
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2005-04-17 06:20:36 +08:00
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};
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static void
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2006-10-08 21:36:08 +08:00
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noritake_device_interrupt(unsigned long vector)
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2005-04-17 06:20:36 +08:00
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{
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unsigned long pld;
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unsigned int i;
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/* Read the interrupt summary registers of NORITAKE */
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pld = (((unsigned long) inw(0x54c) << 32)
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| ((unsigned long) inw(0x54a) << 16)
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| ((unsigned long) inb(0xa0) << 8)
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| inb(0x20));
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i < 16) {
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2006-10-08 21:36:08 +08:00
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isa_device_interrupt(vector);
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2005-04-17 06:20:36 +08:00
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} else {
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2006-10-08 21:37:32 +08:00
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handle_irq(i);
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2005-04-17 06:20:36 +08:00
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}
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}
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}
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static void
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2006-10-08 21:36:08 +08:00
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noritake_srm_device_interrupt(unsigned long vector)
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2005-04-17 06:20:36 +08:00
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* I really hate to do this, too, but the NORITAKE SRM console also
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* reports PCI vectors *lower* than I expected from the bit numbers
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* in the documentation.
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* But I really don't want to change the fixup code for allocation
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* of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
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* look nice and clean now.
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* So, here's this additional grotty hack... :-(
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*/
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if (irq >= 16)
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irq = irq + 1;
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2006-10-08 21:37:32 +08:00
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handle_irq(irq);
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2005-04-17 06:20:36 +08:00
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}
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static void __init
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noritake_init_irq(void)
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{
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long i;
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if (alpha_using_srm)
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alpha_mv.device_interrupt = noritake_srm_device_interrupt;
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outw(0, 0x54a);
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outw(0, 0x54c);
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for (i = 16; i < 48; ++i) {
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irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 17:24:36 +08:00
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irq_desc[i].chip = &noritake_irq_type;
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2005-04-17 06:20:36 +08:00
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary @ 0x542, summary register #1:
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* Bit Meaning
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* 0 All valid ints from summary regs 2 & 3
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* 1 QLOGIC ISP1020A SCSI
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* 2 Interrupt Line A from slot 0
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* 3 Interrupt Line B from slot 0
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* 4 Interrupt Line A from slot 1
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* 5 Interrupt line B from slot 1
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* 6 Interrupt Line A from slot 2
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* 7 Interrupt Line B from slot 2
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* 8 Interrupt Line A from slot 3
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* 9 Interrupt Line B from slot 3
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*10 Interrupt Line A from slot 4
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*11 Interrupt Line B from slot 4
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*12 Interrupt Line A from slot 5
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*13 Interrupt Line B from slot 5
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*14 Interrupt Line A from slot 6
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*15 Interrupt Line B from slot 6
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*
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* Summary @ 0x544, summary register #2:
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* Bit Meaning
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* 0 OR of all unmasked ints in SR #2
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* 1 OR of secondary bus ints
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* 2 Interrupt Line C from slot 0
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* 3 Interrupt Line D from slot 0
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* 4 Interrupt Line C from slot 1
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* 5 Interrupt line D from slot 1
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* 6 Interrupt Line C from slot 2
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* 7 Interrupt Line D from slot 2
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* 8 Interrupt Line C from slot 3
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* 9 Interrupt Line D from slot 3
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*10 Interrupt Line C from slot 4
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*11 Interrupt Line D from slot 4
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*12 Interrupt Line C from slot 5
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*13 Interrupt Line D from slot 5
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*14 Interrupt Line C from slot 6
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*15 Interrupt Line D from slot 6
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 7 Intel PCI-EISA bridge chip
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* 8 DEC PCI-PCI bridge chip
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* 11 PCI on board slot 0
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* 12 PCI on board slot 1
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* 13 PCI on board slot 2
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*
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*
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* This two layered interrupt approach means that we allocate IRQ 16 and
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* above for PCI interrupts. The IRQ relates to which bit the interrupt
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* comes in on. This makes interrupt processing much easier.
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*/
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static int __init
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noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[15][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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/* note: IDSELs 16, 17, and 25 are CORELLE only */
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
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{ -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */
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{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
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{ -1, -1, -1, -1, -1}, /* IdSel 19, PPB */
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{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
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{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
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{ 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */
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{ 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */
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{ 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */
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/* The following 5 are actually on PCI bus 1, which is
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across the built-in bridge of the NORITAKE only. */
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */
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{16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */
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{16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */
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{16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */
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};
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const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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static u8 __init
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noritake_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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int slot, pin = *pinp;
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if (dev->bus->number == 0) {
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slot = PCI_SLOT(dev->devfn);
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}
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/* Check for the built-in bridge */
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else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
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slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
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}
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else
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{
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/* Must be a card-based bridge. */
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do {
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if (PCI_SLOT(dev->bus->self->devfn) == 8) {
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slot = PCI_SLOT(dev->devfn) + 15;
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break;
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}
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pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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/* Slot of the next bridge. */
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slot = PCI_SLOT(dev->devfn);
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} while (dev->bus->self);
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}
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*pinp = pin;
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return slot;
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}
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
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static void
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2006-10-08 21:44:38 +08:00
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noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
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2005-04-17 06:20:36 +08:00
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{
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#define MCHK_NO_DEVSEL 0x205U
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#define MCHK_NO_TABT 0x204U
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struct el_common *mchk_header;
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unsigned int code;
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mchk_header = (struct el_common *)la_ptr;
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/* Clear the error before any reporting. */
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mb();
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mb(); /* magic */
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draina();
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apecs_pci_clr_err();
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wrmces(0x7);
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|
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mb();
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|
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code = mchk_header->code;
|
2006-10-08 21:44:38 +08:00
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process_mcheck_info(vector, la_ptr, "NORITAKE APECS",
|
2005-04-17 06:20:36 +08:00
|
|
|
(mcheck_expected(0)
|
|
|
|
|
&& (code == MCHK_NO_DEVSEL
|
|
|
|
|
|| code == MCHK_NO_TABT)));
|
|
|
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}
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|
|
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|
#endif
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vectors
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
|
|
|
|
|
struct alpha_machine_vector noritake_mv __initmv = {
|
|
|
|
|
.vector_name = "Noritake",
|
|
|
|
|
DO_EV4_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_APECS_IO,
|
|
|
|
|
.machine_check = noritake_apecs_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 48,
|
|
|
|
|
.device_interrupt = noritake_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = apecs_init_arch,
|
|
|
|
|
.init_irq = noritake_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = common_init_pci,
|
|
|
|
|
.pci_map_irq = noritake_map_irq,
|
|
|
|
|
.pci_swizzle = noritake_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(noritake)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
|
|
|
|
|
struct alpha_machine_vector noritake_primo_mv __initmv = {
|
|
|
|
|
.vector_name = "Noritake-Primo",
|
|
|
|
|
DO_EV5_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_CIA_IO,
|
|
|
|
|
.machine_check = cia_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = EISA_DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = CIA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 48,
|
|
|
|
|
.device_interrupt = noritake_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = cia_init_arch,
|
|
|
|
|
.init_irq = noritake_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = cia_init_pci,
|
|
|
|
|
.kill_arch = cia_kill_arch,
|
|
|
|
|
.pci_map_irq = noritake_map_irq,
|
|
|
|
|
.pci_swizzle = noritake_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(noritake_primo)
|
|
|
|
|
#endif
|