2017-11-01 22:09:13 +08:00
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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2012-10-13 17:46:48 +08:00
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/*
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* linux/drivers/char/serial_core.h
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _UAPILINUX_SERIAL_CORE_H
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#define _UAPILINUX_SERIAL_CORE_H
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#include <linux/serial.h>
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/*
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* The type definitions. These are from Ted Ts'o's serial.h
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*/
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#define PORT_UNKNOWN 0
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#define PORT_8250 1
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#define PORT_16450 2
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#define PORT_16550 3
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#define PORT_16550A 4
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#define PORT_CIRRUS 5
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#define PORT_16650 6
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#define PORT_16650V2 7
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#define PORT_16750 8
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#define PORT_STARTECH 9
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#define PORT_16C950 10
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#define PORT_16654 11
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#define PORT_16850 12
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#define PORT_RSA 13
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#define PORT_NS16550A 14
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#define PORT_XSCALE 15
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#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
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#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
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#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
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#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
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#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
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#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
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#define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
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#define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */
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2012-11-19 23:12:04 +08:00
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#define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
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2013-01-30 09:54:44 +08:00
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#define PORT_BRCM_TRUMANAGE 25
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2013-03-07 10:28:37 +08:00
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#define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
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#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
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#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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2014-10-17 03:48:21 +08:00
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#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
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2015-01-05 23:44:42 +08:00
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#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
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2012-10-13 17:46:48 +08:00
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/*
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* ARM specific type numbers. These are not currently guaranteed
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* to be implemented, and will change in the future. These are
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* separate so any additions to the old serial.c that occur before
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* we are merged can be easily merged here.
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*/
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#define PORT_PXA 31
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#define PORT_AMBA 32
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#define PORT_CLPS711X 33
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#define PORT_SA1100 34
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#define PORT_UART00 35
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2017-07-10 04:29:42 +08:00
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#define PORT_OWL 36
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2012-10-13 17:46:48 +08:00
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#define PORT_21285 37
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/* Sparc type numbers. */
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#define PORT_SUNZILOG 38
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#define PORT_SUNSAB 39
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2018-03-05 19:47:38 +08:00
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/* Nuvoton UART */
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#define PORT_NPCM 40
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2017-08-22 21:58:20 +08:00
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/* Intel EG20 */
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#define PORT_PCH_8LINE 44
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#define PORT_PCH_2LINE 45
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2012-10-13 17:46:48 +08:00
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/* DEC */
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#define PORT_DZ 46
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#define PORT_ZS 47
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/* Parisc type numbers. */
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#define PORT_MUX 48
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2017-06-07 23:19:31 +08:00
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/* Atmel AT91 SoC */
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2012-10-13 17:46:48 +08:00
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#define PORT_ATMEL 49
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/* Macintosh Zilog type numbers */
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#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
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#define PORT_PMAC_ZILOG 51
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/* SH-SCI */
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#define PORT_SCI 52
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#define PORT_SCIF 53
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#define PORT_IRDA 54
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/* Samsung S3C2410 SoC and derivatives thereof */
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#define PORT_S3C2410 55
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/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
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#define PORT_IP22ZILOG 56
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/* Sharp LH7a40x -- an ARM9 SoC series */
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#define PORT_LH7A40X 57
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/* PPC CPM type number */
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#define PORT_CPM 58
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/* MPC52xx (and MPC512x) type numbers */
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#define PORT_MPC52xx 59
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/* IBM icom */
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#define PORT_ICOM 60
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/* Samsung S3C2440 SoC */
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#define PORT_S3C2440 61
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/* Motorola i.MX SoC */
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#define PORT_IMX 62
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/* Marvell MPSC */
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#define PORT_MPSC 63
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/* TXX9 type number */
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#define PORT_TXX9 64
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/* NEC VR4100 series SIU/DSIU */
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#define PORT_VR41XX_SIU 65
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#define PORT_VR41XX_DSIU 66
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/* Samsung S3C2400 SoC */
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#define PORT_S3C2400 67
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/* M32R SIO */
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#define PORT_M32R_SIO 68
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/*Digi jsm */
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#define PORT_JSM 69
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#define PORT_PNX8XXX 70
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/* Hilscher netx */
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#define PORT_NETX 71
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/* SUN4V Hypervisor Console */
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#define PORT_SUNHV 72
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#define PORT_S3C2412 73
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/* Xilinx uartlite */
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#define PORT_UARTLITE 74
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/* Blackfin bf5xx */
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#define PORT_BFIN 75
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/* Micrel KS8695 */
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#define PORT_KS8695 76
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/* Broadcom SB1250, etc. SOC */
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#define PORT_SB1250_DUART 77
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/* Freescale ColdFire */
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#define PORT_MCF 78
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/* Blackfin SPORT */
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#define PORT_BFIN_SPORT 79
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/* MN10300 on-chip UART numbers */
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#define PORT_MN10300 80
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#define PORT_MN10300_CTS 81
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#define PORT_SC26XX 82
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/* SH-SCI */
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#define PORT_SCIFA 83
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#define PORT_S3C6400 84
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2015-11-16 23:48:12 +08:00
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/* NWPSERIAL, now removed */
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2012-10-13 17:46:48 +08:00
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#define PORT_NWPSERIAL 85
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/* MAX3100 */
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#define PORT_MAX3100 86
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/* Timberdale UART */
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#define PORT_TIMBUART 87
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/* Qualcomm MSM SoCs */
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#define PORT_MSM 88
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/* BCM63xx family SoCs */
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#define PORT_BCM63XX 89
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/* Aeroflex Gaisler GRLIB APBUART */
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#define PORT_APBUART 90
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/* Altera UARTs */
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#define PORT_ALTERA_JTAGUART 91
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#define PORT_ALTERA_UART 92
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/* SH-SCI */
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#define PORT_SCIFB 93
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/* MAX310X */
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#define PORT_MAX310X 94
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2017-08-22 21:58:22 +08:00
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/* TI DA8xx/66AK2x */
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#define PORT_DA830 95
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2012-10-13 17:46:48 +08:00
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/* TI OMAP-UART */
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#define PORT_OMAP 96
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/* VIA VT8500 SoC */
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#define PORT_VT8500 97
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2014-04-05 08:23:43 +08:00
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/* Cadence (Xilinx Zynq) UART */
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2012-10-13 17:46:48 +08:00
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#define PORT_XUARTPS 98
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/* Atheros AR933X SoC */
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#define PORT_AR933X 99
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/* Energy Micro efm32 SoC */
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#define PORT_EFMUART 100
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2012-10-27 15:17:12 +08:00
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/* ARC (Synopsys) on-chip UART */
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#define PORT_ARC 101
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2012-10-13 17:46:48 +08:00
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2013-01-17 12:28:40 +08:00
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/* Rocketport EXPRESS/INFINITY */
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#define PORT_RP2 102
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2013-06-07 09:20:40 +08:00
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/* Freescale lpuart */
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#define PORT_LPUART 103
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2013-05-31 23:57:01 +08:00
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/* SH-SCI */
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2013-07-03 05:42:51 +08:00
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#define PORT_HSCIF 104
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2013-05-31 23:57:01 +08:00
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2013-07-15 19:39:23 +08:00
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/* ST ASC type numbers */
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#define PORT_ASC 105
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2013-08-13 02:11:44 +08:00
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/* Tilera TILE-Gx UART */
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
Pull Tile arch updates from Chris Metcalf:
"These changes bring in a bunch of new functionality that has been
maintained internally at Tilera over the last year, plus other stray
bits of work that I've taken into the tile tree from other folks.
The changes include some PCI root complex work, interrupt-driven
console support, support for performing fast-path unaligned data
fixups by kernel-based JIT code generation, CONFIG_PREEMPT support,
vDSO support for gettimeofday(), a serial driver for the tilegx
on-chip UART, KGDB support, more optimized string routines, support
for ftrace and kprobes, improved ASLR, and many bug fixes.
We also remove support for the old TILE64 chip, which is no longer
buildable"
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (85 commits)
tile: refresh tile defconfig files
tile: rework <asm/cmpxchg.h>
tile PCI RC: make default consistent DMA mask 32-bit
tile: add null check for kzalloc in tile/kernel/setup.c
tile: make __write_once a synonym for __read_mostly
tile: remove support for TILE64
tile: use asm-generic/bitops/builtin-*.h
tile: eliminate no-op "noatomichash" boot argument
tile: use standard tile_bundle_bits type in traps.c
tile: simplify code referencing hypervisor API addresses
tile: change <asm/system.h> to <asm/switch_to.h> in comments
tile: mark pcibios_init() as __init
tile: check for correct compiler earlier in asm-offsets.c
tile: use standard 'generic-y' model for <asm/hw_irq.h>
tile: use asm-generic version of <asm/local64.h>
tile PCI RC: add comment about "PCI hole" problem
tile: remove DEBUG_EXTRA_FLAGS kernel config option
tile: add virt_to_kpte() API and clean up and document behavior
tile: support FRAME_POINTER
tile: support reporting Tilera hypervisor statistics
...
2013-09-07 02:14:33 +08:00
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#define PORT_TILEGX 106
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2013-08-13 02:11:44 +08:00
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2014-04-17 21:47:58 +08:00
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/* MEN 16z135 UART */
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#define PORT_MEN_Z135 107
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2014-04-25 08:56:06 +08:00
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/* SC16IS74xx */
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#define PORT_SC16IS7XX 108
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2014-08-17 18:49:49 +08:00
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/* MESON */
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#define PORT_MESON 109
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2014-12-19 03:45:24 +08:00
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/* Conexant Digicolor */
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#define PORT_DIGICOLOR 110
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2015-01-28 19:08:44 +08:00
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/* SPRD SERIAL */
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#define PORT_SPRD 111
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2015-02-03 06:19:20 +08:00
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/* Cris v10 / v32 SoC */
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#define PORT_CRIS 112
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2015-06-11 03:19:36 +08:00
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/* STM32 USART */
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#define PORT_STM32 113
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2016-02-17 02:14:53 +08:00
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/* MVEBU UART */
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#define PORT_MVEBU 114
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2016-01-14 09:15:43 +08:00
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/* Microchip PIC32 UART */
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2016-05-20 01:02:26 +08:00
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#define PORT_PIC32 115
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2016-01-14 09:15:43 +08:00
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2016-04-25 16:47:47 +08:00
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/* MPS2 UART */
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2016-05-21 11:57:27 +08:00
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#define PORT_MPS2UART 116
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2016-04-25 16:47:47 +08:00
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2017-08-21 01:17:56 +08:00
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/* MediaTek BTIF */
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#define PORT_MTK_BTIF 117
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2012-10-13 17:46:48 +08:00
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#endif /* _UAPILINUX_SERIAL_CORE_H */
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