hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
linux-sg2042/drivers/mmc/host/sdhci-esdhc.h

96 lines
2.7 KiB
C
Raw Normal View History

mmc: sdhci-of-esdhc: factor out common stuff Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-15 18:21:03 +08:00
/*
* Freescale eSDHC controller driver generics for OF and pltfm.
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
* Copyright (c) 2010 Pengutronix e.K.
* Author: Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
#define _DRIVERS_MMC_SDHCI_ESDHC_H
/*
* Ops and quirks for the Freescale eSDHC controller.
*/
#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR The eSDHC can only DMA from 32-bit-aligned addresses. This fixes the following test cases of mmc_test: 11: Badly aligned write 12: Badly aligned read 13: Badly aligned multi-block write 14: Badly aligned multi-block read Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-05-30 17:14:08 +08:00
SDHCI_QUIRK_32BIT_DMA_ADDR | \
mmc: sdhci-of-esdhc: factor out common stuff Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-15 18:21:03 +08:00
SDHCI_QUIRK_NO_BUSY_IRQ | \
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
mmc: sdhci-esdhc: add default quirk SDHCI_QUIRK_NO_HISPD_BIT eSDHC supports high speed mode, but has no enabling bit for it. Add this quirk to avoid writing to eSDHC_PROCTL[DTW] by mistake. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-07-10 11:42:37 +08:00
SDHCI_QUIRK_PIO_NEEDS_DELAY | \
SDHCI_QUIRK_NO_HISPD_BIT)
mmc: sdhci-of-esdhc: factor out common stuff Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-15 18:21:03 +08:00
/* pltfm-specific */
#define ESDHC_HOST_CONTROL_LE 0x20
mmc: esdhc: Add support for 8-bit bus width and non-removable card This patch adds support of connecting an MMC media using an 8-bit bus width connection to Freescale's P2020 H/W SDHC controller. During the probe function, the generic function mmc_of_parse is called to detect whether the controller is configured with 8-bit bus width. Also, the generic function detects if the non-removable property is set in the device tree. The function esdhc_pltfm_bus_width was added because the bus width configuration is platform specific. Signed-off-by: Oded Gabbay <ogabbay@advaoptical.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-06-28 00:00:05 +08:00
/*
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
* eSDHC register definition
mmc: esdhc: Add support for 8-bit bus width and non-removable card This patch adds support of connecting an MMC media using an 8-bit bus width connection to Freescale's P2020 H/W SDHC controller. During the probe function, the generic function mmc_of_parse is called to detect whether the controller is configured with 8-bit bus width. Also, the generic function detects if the non-removable property is set in the device tree. The function esdhc_pltfm_bus_width was added because the bus width configuration is platform specific. Signed-off-by: Oded Gabbay <ogabbay@advaoptical.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-06-28 00:00:05 +08:00
*/
mmc: sdhci-of-esdhc: factor out common stuff Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-15 18:21:03 +08:00
mmc: sdhci-of-esdhc: avoid clock glitch when frequency is changing The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:30 +08:00
/* Present State Register */
#define ESDHC_PRSSTAT 0x24
#define ESDHC_CLOCK_STABLE 0x00000008
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
/* Protocol Control Register */
#define ESDHC_PROCTL 0x28
mmc: sdhci-of-esdhc: add support for signal voltage switch eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:41 +08:00
#define ESDHC_VOLT_SEL 0x00000400
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
#define ESDHC_CTRL_4BITBUS (0x1 << 1)
#define ESDHC_CTRL_8BITBUS (0x2 << 1)
#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
#define ESDHC_HOST_CONTROL_RES 0x01
/* System Control Register */
#define ESDHC_SYSTEM_CONTROL 0x2c
#define ESDHC_CLOCK_MASK 0x0000fff0
#define ESDHC_PREDIV_SHIFT 8
#define ESDHC_DIVIDER_SHIFT 4
mmc: sdhci-of-esdhc: avoid clock glitch when frequency is changing The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:30 +08:00
#define ESDHC_CLOCK_SDCLKEN 0x00000008
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
#define ESDHC_CLOCK_PEREN 0x00000004
#define ESDHC_CLOCK_HCKEN 0x00000002
#define ESDHC_CLOCK_IPGEN 0x00000001
mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessing eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-15 10:17:03 +08:00
/* Host Controller Capabilities Register 2 */
#define ESDHC_CAPABILITIES_1 0x114
mmc: sdhci-of-esdhc: add tuning support eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:42 +08:00
/* Tuning Block Control Register */
#define ESDHC_TBCTL 0x120
mmc: sdhci-of-esdhc: add hs400 mode support 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-11-23 11:15:34 +08:00
#define ESDHC_HS400_WNDW_ADJUST 0x00000040
#define ESDHC_HS400_MODE 0x00000010
mmc: sdhci-of-esdhc: add tuning support eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:42 +08:00
#define ESDHC_TB_EN 0x00000004
mmc: sdhci-of-esdhc: add erratum A008171 support In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-23 16:48:32 +08:00
#define ESDHC_TBPTR 0x128
mmc: sdhci-of-esdhc: add tuning support eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:42 +08:00
mmc: sdhci-of-esdhc: add hs400 mode support 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-11-23 11:15:34 +08:00
/* SD Clock Control Register */
#define ESDHC_SDCLKCTL 0x144
#define ESDHC_LPBK_CLK_SEL 0x80000000
#define ESDHC_CMD_CLK_CTL 0x00008000
/* SD Timing Control Register */
#define ESDHC_SDTIMNGCTL 0x148
#define ESDHC_FLW_CTL_BG 0x00008000
/* DLL Config 0 Register */
#define ESDHC_DLLCFG0 0x160
#define ESDHC_DLL_ENABLE 0x80000000
#define ESDHC_DLL_FREQ_SEL 0x08000000
mmc: sdhci-of-esdhc: workaround for unreliable pulse width detection This was a SoC issue on LX2160A Rev1.0. eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] must be set to 0 to get 4 delay cells in the pulse width detection logic for eMMC HS400 mode. Otherwise it would cause unexpected HS400 issue. This patch is to clear this bit always for affected SoC when reset for all, since this bit doesn't affect other speed modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-11-23 11:15:37 +08:00
/* DLL Config 1 Register */
#define ESDHC_DLLCFG1 0x164
#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
mmc: sdhci-of-esdhc: add hs400 mode support 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-11-23 11:15:34 +08:00
/* DLL Status 0 Register */
#define ESDHC_DLLSTAT0 0x170
#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
/* Control Register for DMA transfer */
#define ESDHC_DMA_SYSCTL 0x40c
mmc: sdhci-of-esdhc: add peripheral clock support eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:40 +08:00
#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
mmc: sdhci-of-esdhc: add tuning support eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-20 16:14:42 +08:00
#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
mmc: sdhci-esdhc: clean up register definitions The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-12-26 17:46:29 +08:00
#define ESDHC_DMA_SNOOP 0x00000040
mmc: sdhci-of-esdhc: factor out common stuff Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-15 18:21:03 +08:00
#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */