2019-05-31 16:09:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-01-27 00:22:01 +08:00
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/*
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2017-03-28 20:42:54 +08:00
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* Functions and macros to control the flowcontroller
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2012-01-27 00:22:01 +08:00
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*/
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2017-03-28 20:42:54 +08:00
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#ifndef __SOC_TEGRA_FLOWCTRL_H__
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#define __SOC_TEGRA_FLOWCTRL_H__
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2012-01-27 00:22:01 +08:00
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#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTRL_WAITEVENT (2 << 29)
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#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
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#define FLOW_CTRL_JTAG_RESUME (1 << 28)
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2013-05-20 18:39:27 +08:00
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#define FLOW_CTRL_SCLK_RESUME (1 << 27)
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2012-01-27 00:22:01 +08:00
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#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
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#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
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2013-07-03 17:50:40 +08:00
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#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
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#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
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2013-07-19 17:25:25 +08:00
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#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
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#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
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2012-01-27 00:22:01 +08:00
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#define FLOW_CTRL_CPU0_CSR 0x8
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#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
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#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
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2013-07-03 17:50:41 +08:00
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#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
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#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
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#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
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FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
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FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
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2012-01-27 00:22:01 +08:00
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#define FLOW_CTRL_CSR_ENABLE (1 << 0)
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#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTRL_CPU1_CSR 0x18
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2013-01-16 06:11:01 +08:00
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#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
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2012-10-31 17:41:20 +08:00
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#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
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#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
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#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
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2012-02-10 07:47:44 +08:00
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#ifndef __ASSEMBLY__
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2017-03-28 20:42:54 +08:00
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#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
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2012-10-31 17:41:20 +08:00
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u32 flowctrl_read_cpu_csr(unsigned int cpuid);
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2012-02-10 07:47:44 +08:00
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void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
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void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
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2012-10-31 17:41:20 +08:00
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void flowctrl_cpu_suspend_enter(unsigned int cpuid);
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void flowctrl_cpu_suspend_exit(unsigned int cpuid);
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2017-03-28 20:42:54 +08:00
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#else
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static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
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{
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return 0;
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}
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static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
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{
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}
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static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
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2014-08-26 14:14:04 +08:00
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2017-03-28 20:42:54 +08:00
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static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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{
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}
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2012-02-10 07:47:44 +08:00
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2017-03-28 20:42:54 +08:00
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static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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{
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}
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#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
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#endif /* __ASSEMBLY */
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#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
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