usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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config USB_DWC3
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tristate "DesignWare USB3 DRD Core Support"
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2013-08-30 15:39:53 +08:00
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depends on (USB || USB_GADGET) && HAS_DMA
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2016-07-22 16:23:18 +08:00
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select USB_XHCI_PLATFORM if USB_XHCI_HCD
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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help
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Say Y or M here if your system has a Dual Role SuperSpeed
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USB controller based on the DesignWare USB3 IP Core.
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If you choose to build this driver is a dynamically linked
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module, the module will be called dwc3.ko.
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if USB_DWC3
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2015-05-13 20:26:51 +08:00
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config USB_DWC3_ULPI
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bool "Register ULPI PHY Interface"
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2015-06-12 21:16:21 +08:00
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depends on USB_ULPI_BUS=y || USB_ULPI_BUS=USB_DWC3
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2015-05-13 20:26:51 +08:00
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help
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Select this if you have ULPI type PHY attached to your DWC3
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controller.
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2013-01-15 18:39:21 +08:00
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choice
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bool "DWC3 Mode Selection"
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default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
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default USB_DWC3_HOST if (USB && !USB_GADGET)
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default USB_DWC3_GADGET if (!USB && USB_GADGET)
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config USB_DWC3_HOST
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bool "Host only mode"
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2013-05-14 20:02:16 +08:00
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depends on USB=y || USB=USB_DWC3
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2013-01-15 18:39:21 +08:00
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help
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Select this when you want to use DWC3 in host mode only,
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thereby the gadget feature will be regressed.
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config USB_DWC3_GADGET
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bool "Gadget only mode"
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2013-05-14 20:02:16 +08:00
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depends on USB_GADGET=y || USB_GADGET=USB_DWC3
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2013-01-15 18:39:21 +08:00
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help
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Select this when you want to use DWC3 in gadget mode only,
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thereby the host feature will be regressed.
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config USB_DWC3_DUAL_ROLE
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bool "Dual Role mode"
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2013-05-14 20:02:16 +08:00
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depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3))
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2013-01-15 18:39:21 +08:00
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help
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This is the default mode of working of DWC3 controller where
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both host and gadget features are enabled.
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endchoice
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2013-06-26 20:14:06 +08:00
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comment "Platform Glue Driver Support"
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config USB_DWC3_OMAP
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tristate "Texas Instruments OMAP5 and similar Platforms"
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2014-04-08 16:42:40 +08:00
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depends on EXTCON && (ARCH_OMAP2PLUS || COMPILE_TEST)
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2014-05-22 12:01:37 +08:00
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depends on OF
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2013-06-26 20:14:06 +08:00
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default USB_DWC3
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help
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Some platforms from Texas Instruments like OMAP5, DRA7xxx and
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AM437x use this IP for USB2/3 functionality.
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Say 'Y' or 'M' here if you have one such device
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config USB_DWC3_EXYNOS
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tristate "Samsung Exynos Platform"
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2014-11-04 10:01:47 +08:00
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depends on ARCH_EXYNOS && OF || COMPILE_TEST
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2013-06-26 20:14:06 +08:00
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default USB_DWC3
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help
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Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
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say 'Y' or 'M' if you have one such device.
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config USB_DWC3_PCI
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tristate "PCIe-based Platforms"
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depends on PCI
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default USB_DWC3
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help
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If you're using the DesignWare Core IP with a PCIe, please say
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'Y' or 'M' here.
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One such PCIe-based platform is Synopsys' PCIe HAPS model of
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this IP.
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2013-12-13 01:25:29 +08:00
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config USB_DWC3_KEYSTONE
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tristate "Texas Instruments Keystone2 Platforms"
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2014-04-08 16:42:40 +08:00
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depends on ARCH_KEYSTONE || COMPILE_TEST
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2013-12-13 01:25:29 +08:00
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default USB_DWC3
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help
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Support of USB2/3 functionality in TI Keystone2 platforms.
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Say 'Y' or 'M' here if you have one such device
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2015-11-19 03:15:20 +08:00
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config USB_DWC3_OF_SIMPLE
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tristate "Generic OF Simple Glue Layer"
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depends on OF && COMMON_CLK
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default USB_DWC3
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help
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Support USB2/3 functionality in simple SoC integrations.
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Currently supports Xilinx and Qualcomm DWC USB3 IP.
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Say 'Y' or 'M' if you have one such device.
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2014-09-05 23:36:30 +08:00
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config USB_DWC3_ST
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tristate "STMicroelectronics Platforms"
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depends on ARCH_STI && OF
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default USB_DWC3
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help
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STMicroelectronics SoCs with one DesignWare Core USB3 IP
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inside (i.e. STiH407).
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Say 'Y' or 'M' if you have one such device.
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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endif
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