2009-07-23 02:01:59 +08:00
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/*
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*
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* isar.h ISAR (Siemens PSB 7110) specific defines
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*
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* Author Karsten Keil (keil@isdn4linux.de)
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*
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* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include "iohelper.h"
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struct isar_hw;
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struct isar_ch {
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struct bchannel bch;
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struct isar_hw *is;
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struct timer_list ftimer;
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u8 nr;
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u8 dpath;
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u8 mml;
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u8 state;
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u8 cmd;
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u8 mod;
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u8 newcmd;
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u8 newmod;
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u8 try_mod;
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u8 conmsg[16];
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};
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struct isar_hw {
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struct isar_ch ch[2];
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void *hw;
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tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-02 03:38:34 +08:00
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spinlock_t *hwlock; /* lock HW access */
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2009-07-23 02:01:59 +08:00
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char *name;
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struct module *owner;
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2009-07-27 23:20:55 +08:00
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read_reg_func *read_reg;
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write_reg_func *write_reg;
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fifo_func *read_fifo;
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fifo_func *write_fifo;
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2009-07-23 02:01:59 +08:00
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int (*ctrl)(void *, u32, u_long);
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void (*release)(struct isar_hw *);
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int (*init)(struct isar_hw *);
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int (*open)(struct isar_hw *, struct channel_req *);
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int (*firmware)(struct isar_hw *, const u8 *, int);
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unsigned long Flags;
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int version;
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u8 bstat;
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u8 iis;
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u8 cmsb;
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u8 clsb;
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u8 buf[256];
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u8 log[256];
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};
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#define ISAR_IRQMSK 0x04
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#define ISAR_IRQSTA 0x04
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#define ISAR_IRQBIT 0x75
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#define ISAR_CTRL_H 0x61
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#define ISAR_CTRL_L 0x60
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#define ISAR_IIS 0x58
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#define ISAR_IIA 0x58
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#define ISAR_HIS 0x50
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#define ISAR_HIA 0x50
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#define ISAR_MBOX 0x4c
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#define ISAR_WADR 0x4a
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#define ISAR_RADR 0x48
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#define ISAR_HIS_VNR 0x14
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#define ISAR_HIS_DKEY 0x02
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#define ISAR_HIS_FIRM 0x1e
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#define ISAR_HIS_STDSP 0x08
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#define ISAR_HIS_DIAG 0x05
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#define ISAR_HIS_P0CFG 0x3c
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#define ISAR_HIS_P12CFG 0x24
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#define ISAR_HIS_SARTCFG 0x25
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#define ISAR_HIS_PUMPCFG 0x26
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#define ISAR_HIS_PUMPCTRL 0x2a
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#define ISAR_HIS_IOM2CFG 0x27
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#define ISAR_HIS_IOM2REQ 0x07
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#define ISAR_HIS_IOM2CTRL 0x2b
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#define ISAR_HIS_BSTREQ 0x0c
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#define ISAR_HIS_PSTREQ 0x0e
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#define ISAR_HIS_SDATA 0x20
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#define ISAR_HIS_DPS1 0x40
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#define ISAR_HIS_DPS2 0x80
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2012-02-20 11:52:38 +08:00
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#define SET_DPS(x) ((x << 6) & 0xc0)
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2009-07-23 02:01:59 +08:00
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#define ISAR_IIS_MSCMSD 0x3f
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#define ISAR_IIS_VNR 0x15
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#define ISAR_IIS_DKEY 0x03
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#define ISAR_IIS_FIRM 0x1f
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#define ISAR_IIS_STDSP 0x09
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#define ISAR_IIS_DIAG 0x25
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#define ISAR_IIS_GSTEV 0x00
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#define ISAR_IIS_BSTEV 0x28
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#define ISAR_IIS_BSTRSP 0x2c
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#define ISAR_IIS_PSTRSP 0x2e
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#define ISAR_IIS_PSTEV 0x2a
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#define ISAR_IIS_IOM2RSP 0x27
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#define ISAR_IIS_RDATA 0x20
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#define ISAR_IIS_INVMSG 0x3f
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#define ISAR_CTRL_SWVER 0x10
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#define ISAR_CTRL_STST 0x40
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#define ISAR_MSG_HWVER 0x20
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#define ISAR_DP1_USE 1
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#define ISAR_DP2_USE 2
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#define ISAR_RATE_REQ 3
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#define PMOD_DISABLE 0
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#define PMOD_FAX 1
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#define PMOD_DATAMODEM 2
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#define PMOD_HALFDUPLEX 3
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#define PMOD_V110 4
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#define PMOD_DTMF 5
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#define PMOD_DTMF_TRANS 6
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#define PMOD_BYPASS 7
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#define PCTRL_ORIG 0x80
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#define PV32P2_V23R 0x40
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#define PV32P2_V22A 0x20
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#define PV32P2_V22B 0x10
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#define PV32P2_V22C 0x08
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#define PV32P2_V21 0x02
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#define PV32P2_BEL 0x01
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/* LSB MSB in ISAR doc wrong !!! Arghhh */
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#define PV32P3_AMOD 0x80
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#define PV32P3_V32B 0x02
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#define PV32P3_V23B 0x01
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#define PV32P4_48 0x11
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#define PV32P5_48 0x05
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#define PV32P4_UT48 0x11
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#define PV32P5_UT48 0x0d
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#define PV32P4_96 0x11
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#define PV32P5_96 0x03
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#define PV32P4_UT96 0x11
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#define PV32P5_UT96 0x0f
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#define PV32P4_B96 0x91
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#define PV32P5_B96 0x0b
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#define PV32P4_UTB96 0xd1
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#define PV32P5_UTB96 0x0f
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#define PV32P4_120 0xb1
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#define PV32P5_120 0x09
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#define PV32P4_UT120 0xf1
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#define PV32P5_UT120 0x0f
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#define PV32P4_144 0x99
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#define PV32P5_144 0x09
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#define PV32P4_UT144 0xf9
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#define PV32P5_UT144 0x0f
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#define PV32P6_CTN 0x01
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#define PV32P6_ATN 0x02
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#define PFAXP2_CTN 0x01
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#define PFAXP2_ATN 0x04
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#define PSEV_10MS_TIMER 0x02
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#define PSEV_CON_ON 0x18
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#define PSEV_CON_OFF 0x19
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#define PSEV_V24_OFF 0x20
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#define PSEV_CTS_ON 0x21
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#define PSEV_CTS_OFF 0x22
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#define PSEV_DCD_ON 0x23
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#define PSEV_DCD_OFF 0x24
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#define PSEV_DSR_ON 0x25
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#define PSEV_DSR_OFF 0x26
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#define PSEV_REM_RET 0xcc
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#define PSEV_REM_REN 0xcd
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#define PSEV_GSTN_CLR 0xd4
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#define PSEV_RSP_READY 0xbc
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#define PSEV_LINE_TX_H 0xb3
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#define PSEV_LINE_TX_B 0xb2
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#define PSEV_LINE_RX_H 0xb1
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#define PSEV_LINE_RX_B 0xb0
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#define PSEV_RSP_CONN 0xb5
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#define PSEV_RSP_DISC 0xb7
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#define PSEV_RSP_FCERR 0xb9
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#define PSEV_RSP_SILDET 0xbe
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#define PSEV_RSP_SILOFF 0xab
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#define PSEV_FLAGS_DET 0xba
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#define PCTRL_CMD_TDTMF 0x5a
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#define PCTRL_CMD_FTH 0xa7
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#define PCTRL_CMD_FRH 0xa5
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#define PCTRL_CMD_FTM 0xa8
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#define PCTRL_CMD_FRM 0xa6
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#define PCTRL_CMD_SILON 0xac
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#define PCTRL_CMD_CONT 0xa2
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#define PCTRL_CMD_ESC 0xa4
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#define PCTRL_CMD_SILOFF 0xab
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#define PCTRL_CMD_HALT 0xa9
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#define PCTRL_LOC_RET 0xcf
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#define PCTRL_LOC_REN 0xce
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#define SMODE_DISABLE 0
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#define SMODE_V14 2
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#define SMODE_HDLC 3
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#define SMODE_BINARY 4
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#define SMODE_FSK_V14 5
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#define SCTRL_HDMC_BOTH 0x00
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#define SCTRL_HDMC_DTX 0x80
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#define SCTRL_HDMC_DRX 0x40
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#define S_P1_OVSP 0x40
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#define S_P1_SNP 0x20
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#define S_P1_EOP 0x10
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#define S_P1_EDP 0x08
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#define S_P1_NSB 0x04
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#define S_P1_CHS_8 0x03
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#define S_P1_CHS_7 0x02
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#define S_P1_CHS_6 0x01
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#define S_P1_CHS_5 0x00
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#define S_P2_BFT_DEF 0x10
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#define IOM_CTRL_ENA 0x80
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#define IOM_CTRL_NOPCM 0x00
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#define IOM_CTRL_ALAW 0x02
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#define IOM_CTRL_ULAW 0x04
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#define IOM_CTRL_RCV 0x01
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#define IOM_P1_TXD 0x10
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#define HDLC_FED 0x40
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#define HDLC_FSD 0x20
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#define HDLC_FST 0x20
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#define HDLC_ERROR 0x1c
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#define HDLC_ERR_FAD 0x10
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#define HDLC_ERR_RER 0x08
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#define HDLC_ERR_CER 0x04
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#define SART_NMD 0x01
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#define BSTAT_RDM0 0x1
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#define BSTAT_RDM1 0x2
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#define BSTAT_RDM2 0x4
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#define BSTAT_RDM3 0x8
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#define BSTEV_TBO 0x1f
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#define BSTEV_RBO 0x2f
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/* FAX State Machine */
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#define STFAX_NULL 0
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#define STFAX_READY 1
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#define STFAX_LINE 2
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#define STFAX_CONT 3
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#define STFAX_ACTIV 4
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#define STFAX_ESCAPE 5
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#define STFAX_SILDET 6
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extern u32 mISDNisar_init(struct isar_hw *, void *);
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extern void mISDNisar_irq(struct isar_hw *);
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