2009-04-08 07:16:42 +08:00
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/*
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* Copyright © 2009 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/i2c.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drm_dp_helper.h>
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#include <drm/drmP.h>
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2009-04-08 07:16:42 +08:00
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2012-11-01 21:45:18 +08:00
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/**
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* DOC: dp helpers
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*
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* These functions contain some common logic and helpers at various abstraction
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* levels to deal with Display Port sink devices and related things like DP aux
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* channel transfers, EDID reading over DP aux channels, decoding certain DPCD
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* blocks, ...
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*/
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2009-04-08 07:16:42 +08:00
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/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
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static int
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i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
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uint8_t write_byte, uint8_t *read_byte)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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2012-10-18 16:15:23 +08:00
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2009-12-04 08:55:24 +08:00
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ret = (*algo_data->aux_ch)(adapter, mode,
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write_byte, read_byte);
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return ret;
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2009-04-08 07:16:42 +08:00
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}
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/*
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* I2C over AUX CH
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*/
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/*
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* Send the address. If the I2C link is running, this 'restarts'
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* the connection with the new address, this is used for doing
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* a write followed by a read (as needed for DDC)
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*/
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static int
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i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int mode = MODE_I2C_START;
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int ret;
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if (reading)
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mode |= MODE_I2C_READ;
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else
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mode |= MODE_I2C_WRITE;
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algo_data->address = address;
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algo_data->running = true;
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ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
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return ret;
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}
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/*
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* Stop the I2C transaction. This closes out the link, sending
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* a bare address packet with the MOT bit turned off
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*/
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static void
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i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int mode = MODE_I2C_STOP;
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if (reading)
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mode |= MODE_I2C_READ;
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else
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mode |= MODE_I2C_WRITE;
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if (algo_data->running) {
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(void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
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algo_data->running = false;
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}
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}
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/*
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* Write a single byte to the current I2C address, the
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* the I2C link must be running or this returns -EIO
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*/
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static int
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i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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if (!algo_data->running)
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return -EIO;
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ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
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return ret;
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}
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/*
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* Read a single byte from the current I2C address, the
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* I2C link must be running or this returns -EIO
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*/
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static int
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i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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if (!algo_data->running)
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return -EIO;
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ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
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return ret;
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}
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static int
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i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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int ret = 0;
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bool reading = false;
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int m;
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int b;
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for (m = 0; m < num; m++) {
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u16 len = msgs[m].len;
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u8 *buf = msgs[m].buf;
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reading = (msgs[m].flags & I2C_M_RD) != 0;
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ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
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if (ret < 0)
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break;
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if (reading) {
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for (b = 0; b < len; b++) {
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ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
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if (ret < 0)
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break;
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}
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} else {
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for (b = 0; b < len; b++) {
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ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
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if (ret < 0)
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break;
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}
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}
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if (ret < 0)
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break;
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}
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if (ret >= 0)
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ret = num;
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i2c_algo_dp_aux_stop(adapter, reading);
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2009-10-09 11:39:41 +08:00
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DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
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2009-04-08 07:16:42 +08:00
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return ret;
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}
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static u32
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i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
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I2C_FUNC_SMBUS_READ_BLOCK_DATA |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
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I2C_FUNC_10BIT_ADDR;
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}
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static const struct i2c_algorithm i2c_dp_aux_algo = {
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.master_xfer = i2c_algo_dp_aux_xfer,
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.functionality = i2c_algo_dp_aux_functionality,
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};
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static void
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i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
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{
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(void) i2c_algo_dp_aux_address(adapter, 0, false);
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(void) i2c_algo_dp_aux_stop(adapter, false);
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}
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static int
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i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
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{
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adapter->algo = &i2c_dp_aux_algo;
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adapter->retries = 3;
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i2c_dp_aux_reset_bus(adapter);
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return 0;
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}
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2012-11-01 21:45:18 +08:00
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/**
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* i2c_dp_aux_add_bus() - register an i2c adapter using the aux ch helper
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* @adapter: i2c adapter to register
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*
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* This registers an i2c adapater that uses dp aux channel as it's underlaying
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* transport. The driver needs to fill out the &i2c_algo_dp_aux_data structure
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* and store it in the algo_data member of the @adapter argument. This will be
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* used by the i2c over dp aux algorithm to drive the hardware.
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*
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* RETURNS:
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* 0 on success, -ERRNO on failure.
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*/
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2009-04-08 07:16:42 +08:00
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int
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i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
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{
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int error;
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2012-10-18 16:15:23 +08:00
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2009-04-08 07:16:42 +08:00
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error = i2c_dp_aux_prepare_bus(adapter);
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if (error)
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return error;
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error = i2c_add_adapter(adapter);
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return error;
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}
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EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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2012-10-18 16:15:24 +08:00
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/* Helpers for DP link training */
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2013-09-28 00:01:01 +08:00
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static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
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2012-10-18 16:15:24 +08:00
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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2013-09-28 00:01:01 +08:00
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static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
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2012-10-18 16:15:24 +08:00
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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2013-09-28 00:01:01 +08:00
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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2012-10-18 16:15:24 +08:00
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_channel_eq_ok);
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2013-09-28 00:01:01 +08:00
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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2012-10-18 16:15:24 +08:00
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
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2012-10-18 16:15:27 +08:00
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2013-09-28 00:01:01 +08:00
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u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
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2012-10-18 16:15:27 +08:00
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
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2013-09-28 00:01:01 +08:00
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u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
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2012-10-18 16:15:27 +08:00
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
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2013-09-28 00:01:01 +08:00
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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2012-10-18 21:32:40 +08:00
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(100);
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else
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mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
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2013-09-28 00:01:01 +08:00
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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2012-10-18 21:32:40 +08:00
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(400);
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else
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mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
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2012-10-18 16:15:31 +08:00
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u8 drm_dp_link_rate_to_bw_code(int link_rate)
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{
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switch (link_rate) {
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case 162000:
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default:
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return DP_LINK_BW_1_62;
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case 270000:
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return DP_LINK_BW_2_7;
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case 540000:
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return DP_LINK_BW_5_4;
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}
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}
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EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
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int drm_dp_bw_code_to_link_rate(u8 link_bw)
|
|
|
|
{
|
|
|
|
switch (link_bw) {
|
|
|
|
case DP_LINK_BW_1_62:
|
|
|
|
default:
|
|
|
|
return 162000;
|
|
|
|
case DP_LINK_BW_2_7:
|
|
|
|
return 270000;
|
|
|
|
case DP_LINK_BW_5_4:
|
|
|
|
return 540000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
|
2013-11-28 18:31:00 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* DOC: dp helpers
|
|
|
|
*
|
|
|
|
* The DisplayPort AUX channel is an abstraction to allow generic, driver-
|
|
|
|
* independent access to AUX functionality. Drivers can take advantage of
|
|
|
|
* this by filling in the fields of the drm_dp_aux structure.
|
|
|
|
*
|
|
|
|
* Transactions are described using a hardware-independent drm_dp_aux_msg
|
|
|
|
* structure, which is passed into a driver's .transfer() implementation.
|
|
|
|
* Both native and I2C-over-AUX transactions are supported.
|
|
|
|
*
|
|
|
|
* An AUX channel can also be used to transport I2C messages to a sink. A
|
|
|
|
* typical application of that is to access an EDID that's present in the
|
|
|
|
* sink device. The .transfer() function can also be used to execute such
|
|
|
|
* transactions. The drm_dp_aux_register_i2c_bus() function registers an
|
|
|
|
* I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
|
|
|
|
* should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
|
|
|
|
unsigned int offset, void *buffer, size_t size)
|
|
|
|
{
|
|
|
|
struct drm_dp_aux_msg msg;
|
|
|
|
unsigned int retry;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
memset(&msg, 0, sizeof(msg));
|
|
|
|
msg.address = offset;
|
|
|
|
msg.request = request;
|
|
|
|
msg.buffer = buffer;
|
|
|
|
msg.size = size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The specification doesn't give any recommendation on how often to
|
|
|
|
* retry native transactions, so retry 7 times like for I2C-over-AUX
|
|
|
|
* transactions.
|
|
|
|
*/
|
|
|
|
for (retry = 0; retry < 7; retry++) {
|
|
|
|
err = aux->transfer(aux, &msg);
|
|
|
|
if (err < 0) {
|
|
|
|
if (err == -EBUSY)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err < size)
|
|
|
|
return -EPROTO;
|
|
|
|
|
|
|
|
switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) {
|
|
|
|
case DP_AUX_NATIVE_REPLY_ACK:
|
|
|
|
return err;
|
|
|
|
|
|
|
|
case DP_AUX_NATIVE_REPLY_NACK:
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
case DP_AUX_NATIVE_REPLY_DEFER:
|
|
|
|
usleep_range(400, 500);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_ERROR("too many retries, giving up\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_dpcd_read() - read a series of bytes from the DPCD
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @offset: address of the (first) register to read
|
|
|
|
* @buffer: buffer to store the register values
|
|
|
|
* @size: number of bytes in @buffer
|
|
|
|
*
|
|
|
|
* Returns the number of bytes transferred on success, or a negative error
|
|
|
|
* code on failure. -EIO is returned if the request was NAKed by the sink or
|
|
|
|
* if the retry count was exceeded. If not all bytes were transferred, this
|
|
|
|
* function returns -EPROTO. Errors from the underlying AUX channel transfer
|
|
|
|
* function, with the exception of -EBUSY (which causes the transaction to
|
|
|
|
* be retried), are propagated to the caller.
|
|
|
|
*/
|
|
|
|
ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
|
|
|
|
void *buffer, size_t size)
|
|
|
|
{
|
|
|
|
return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
|
|
|
|
size);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_dpcd_read);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_dpcd_write() - write a series of bytes to the DPCD
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @offset: address of the (first) register to write
|
|
|
|
* @buffer: buffer containing the values to write
|
|
|
|
* @size: number of bytes in @buffer
|
|
|
|
*
|
|
|
|
* Returns the number of bytes transferred on success, or a negative error
|
|
|
|
* code on failure. -EIO is returned if the request was NAKed by the sink or
|
|
|
|
* if the retry count was exceeded. If not all bytes were transferred, this
|
|
|
|
* function returns -EPROTO. Errors from the underlying AUX channel transfer
|
|
|
|
* function, with the exception of -EBUSY (which causes the transaction to
|
|
|
|
* be retried), are propagated to the caller.
|
|
|
|
*/
|
|
|
|
ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
|
|
|
|
void *buffer, size_t size)
|
|
|
|
{
|
|
|
|
return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
|
|
|
|
size);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_dpcd_write);
|
2013-11-22 23:37:57 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @status: buffer to store the link status in (must be at least 6 bytes)
|
|
|
|
*
|
|
|
|
* Returns the number of bytes transferred on success or a negative error
|
|
|
|
* code on failure.
|
|
|
|
*/
|
|
|
|
int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
|
|
|
|
u8 status[DP_LINK_STATUS_SIZE])
|
|
|
|
{
|
|
|
|
return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
|
|
|
|
DP_LINK_STATUS_SIZE);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
|
2013-12-09 18:47:55 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_link_probe() - probe a DisplayPort link for capabilities
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @link: pointer to structure in which to return link capabilities
|
|
|
|
*
|
|
|
|
* The structure filled in by this function can usually be passed directly
|
|
|
|
* into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
|
|
|
|
* configure the link based on the link's capabilities.
|
|
|
|
*
|
|
|
|
* Returns 0 on success or a negative error code on failure.
|
|
|
|
*/
|
|
|
|
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
|
|
|
|
{
|
|
|
|
u8 values[3];
|
|
|
|
int err;
|
|
|
|
|
|
|
|
memset(link, 0, sizeof(*link));
|
|
|
|
|
|
|
|
err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
link->revision = values[0];
|
|
|
|
link->rate = drm_dp_bw_code_to_link_rate(values[1]);
|
|
|
|
link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
|
|
|
|
|
|
|
|
if (values[2] & DP_ENHANCED_FRAME_CAP)
|
|
|
|
link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_link_probe);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_link_power_up() - power up a DisplayPort link
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @link: pointer to a structure containing the link configuration
|
|
|
|
*
|
|
|
|
* Returns 0 on success or a negative error code on failure.
|
|
|
|
*/
|
|
|
|
int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
|
|
|
|
{
|
|
|
|
u8 value;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* DP_SET_POWER register is only available on DPCD v1.1 and later */
|
|
|
|
if (link->revision < 0x11)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
value &= ~DP_SET_POWER_MASK;
|
|
|
|
value |= DP_SET_POWER_D0;
|
|
|
|
|
|
|
|
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* According to the DP 1.1 specification, a "Sink Device must exit the
|
|
|
|
* power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
|
|
|
|
* Control Field" (register 0x600).
|
|
|
|
*/
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_link_power_up);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* drm_dp_link_configure() - configure a DisplayPort link
|
|
|
|
* @aux: DisplayPort AUX channel
|
|
|
|
* @link: pointer to a structure containing the link configuration
|
|
|
|
*
|
|
|
|
* Returns 0 on success or a negative error code on failure.
|
|
|
|
*/
|
|
|
|
int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
|
|
|
|
{
|
|
|
|
u8 values[2];
|
|
|
|
int err;
|
|
|
|
|
|
|
|
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
|
|
|
|
values[1] = link->num_lanes;
|
|
|
|
|
|
|
|
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
|
|
|
|
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
|
|
|
|
|
|
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(drm_dp_link_configure);
|