2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2009-02-11 17:25:24 +08:00
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/*
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* Copyright (C) 2009 Marvell International Ltd.
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*/
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#ifndef __ASM_MACH_PXA168FB_H
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#define __ASM_MACH_PXA168FB_H
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#include <linux/fb.h>
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#include <linux/interrupt.h>
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/* Dumb interface */
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#define PIN_MODE_DUMB_24 0
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#define PIN_MODE_DUMB_18_SPI 1
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#define PIN_MODE_DUMB_18_GPIO 2
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#define PIN_MODE_DUMB_16_SPI 3
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#define PIN_MODE_DUMB_16_GPIO 4
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#define PIN_MODE_DUMB_12_SPI_GPIO 5
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#define PIN_MODE_SMART_18_SPI 6
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#define PIN_MODE_SMART_16_SPI 7
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#define PIN_MODE_SMART_8_SPI_GPIO 8
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/* Dumb interface pin allocation */
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#define DUMB_MODE_RGB565 0
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#define DUMB_MODE_RGB565_UPPER 1
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#define DUMB_MODE_RGB666 2
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#define DUMB_MODE_RGB666_UPPER 3
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#define DUMB_MODE_RGB444 4
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#define DUMB_MODE_RGB444_UPPER 5
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#define DUMB_MODE_RGB888 6
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/* default fb buffer size WVGA-32bits */
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#define DEFAULT_FB_SIZE (800 * 480 * 4)
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/*
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* Buffer pixel format
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* bit0 is for rb swap.
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* bit12 is for Y UorV swap
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*/
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#define PIX_FMT_RGB565 0
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#define PIX_FMT_BGR565 1
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#define PIX_FMT_RGB1555 2
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#define PIX_FMT_BGR1555 3
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#define PIX_FMT_RGB888PACK 4
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#define PIX_FMT_BGR888PACK 5
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#define PIX_FMT_RGB888UNPACK 6
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#define PIX_FMT_BGR888UNPACK 7
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#define PIX_FMT_RGBA888 8
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#define PIX_FMT_BGRA888 9
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#define PIX_FMT_YUV422PACK 10
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#define PIX_FMT_YVU422PACK 11
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#define PIX_FMT_YUV422PLANAR 12
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#define PIX_FMT_YVU422PLANAR 13
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#define PIX_FMT_YUV420PLANAR 14
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#define PIX_FMT_YVU420PLANAR 15
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#define PIX_FMT_PSEUDOCOLOR 20
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#define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK)
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/*
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* PXA LCD controller private state.
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*/
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struct pxa168fb_info {
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struct device *dev;
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struct clk *clk;
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struct fb_info *info;
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void __iomem *reg_base;
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dma_addr_t fb_start_dma;
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u32 pseudo_palette[16];
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int pix_fmt;
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unsigned is_blanked:1;
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unsigned panel_rbswap:1;
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unsigned active:1;
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};
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/*
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* PXA fb machine information
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*/
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struct pxa168fb_mach_info {
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char id[16];
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int num_modes;
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struct fb_videomode *modes;
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/*
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* Pix_fmt
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*/
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unsigned pix_fmt;
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/*
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* I/O pin allocation.
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*/
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unsigned io_pin_allocation_mode:4;
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/*
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* Dumb panel -- assignment of R/G/B component info to the 24
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* available external data lanes.
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*/
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unsigned dumb_mode:4;
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unsigned panel_rgb_reverse_lanes:1;
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/*
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* Dumb panel -- GPIO output data.
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*/
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unsigned gpio_output_mask:8;
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unsigned gpio_output_data:8;
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/*
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* Dumb panel -- configurable output signal polarity.
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*/
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unsigned invert_composite_blank:1;
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unsigned invert_pix_val_ena:1;
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unsigned invert_pixclock:1;
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unsigned panel_rbswap:1;
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unsigned active:1;
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unsigned enable_lcd:1;
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};
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#endif /* __ASM_MACH_PXA168FB_H */
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