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linux-sg2042/drivers/clk/clk-composite.c

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clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
/*
* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
static u8 clk_composite_get_parent(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk_hw *mux_hw = composite->mux_hw;
mux_hw->clk = hw->clk;
return mux_ops->get_parent(mux_hw);
}
static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk_hw *mux_hw = composite->mux_hw;
mux_hw->clk = hw->clk;
return mux_ops->set_parent(mux_hw, index);
}
static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
rate_hw->clk = hw->clk;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
return rate_ops->recalc_rate(rate_hw, parent_rate);
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
}
static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_composite *composite = to_clk_composite(hw);
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
rate_hw->clk = hw->clk;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
return rate_ops->round_rate(rate_hw, rate, prate);
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
}
static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
rate_hw->clk = hw->clk;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
return rate_ops->set_rate(rate_hw, rate, parent_rate);
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
}
static int clk_composite_is_enabled(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
return gate_ops->is_enabled(gate_hw);
}
static int clk_composite_enable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
return gate_ops->enable(gate_hw);
}
static void clk_composite_disable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
gate_ops->disable(gate_hw);
}
struct clk *clk_register_composite(struct device *dev, const char *name,
const char **parent_names, int num_parents,
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags)
{
struct clk *clk;
struct clk_init_data init;
struct clk_composite *composite;
struct clk_ops *clk_composite_ops;
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite) {
pr_err("%s: could not allocate composite clk\n", __func__);
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.flags = flags | CLK_IS_BASIC;
init.parent_names = parent_names;
init.num_parents = num_parents;
clk_composite_ops = &composite->ops;
if (mux_hw && mux_ops) {
if (!mux_ops->get_parent || !mux_ops->set_parent) {
clk = ERR_PTR(-EINVAL);
goto err;
}
composite->mux_hw = mux_hw;
composite->mux_ops = mux_ops;
clk_composite_ops->get_parent = clk_composite_get_parent;
clk_composite_ops->set_parent = clk_composite_set_parent;
}
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
if (rate_hw && rate_ops) {
clk: composite: allow fixed rates & fixed dividers The composite clock assumes that any clock implementing the .recalc_rate callback will also implement .round_rate and .set_rate. This is not always true; the basic fixed-rate clock will only implement .recalc_rate and a fixed-divider clock may choose to implement .recalc_rate and .round_rate but not .set_rate. Fix this by conditionally registering .round_rate and .set_rate callbacks based on the rate_ops passed in to clk_composite_register. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:37 +08:00
if (!rate_ops->recalc_rate) {
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk = ERR_PTR(-EINVAL);
goto err;
}
clk: composite: allow fixed rates & fixed dividers The composite clock assumes that any clock implementing the .recalc_rate callback will also implement .round_rate and .set_rate. This is not always true; the basic fixed-rate clock will only implement .recalc_rate and a fixed-divider clock may choose to implement .recalc_rate and .round_rate but not .set_rate. Fix this by conditionally registering .round_rate and .set_rate callbacks based on the rate_ops passed in to clk_composite_register. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:37 +08:00
/* .round_rate is a prerequisite for .set_rate */
if (rate_ops->round_rate) {
clk_composite_ops->round_rate = clk_composite_round_rate;
if (rate_ops->set_rate) {
clk_composite_ops->set_rate = clk_composite_set_rate;
}
} else {
WARN(rate_ops->set_rate,
"%s: missing round_rate op is required\n",
__func__);
}
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
composite->rate_hw = rate_hw;
composite->rate_ops = rate_ops;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
}
if (gate_hw && gate_ops) {
if (!gate_ops->is_enabled || !gate_ops->enable ||
!gate_ops->disable) {
clk = ERR_PTR(-EINVAL);
goto err;
}
composite->gate_hw = gate_hw;
composite->gate_ops = gate_ops;
clk_composite_ops->is_enabled = clk_composite_is_enabled;
clk_composite_ops->enable = clk_composite_enable;
clk_composite_ops->disable = clk_composite_disable;
}
init.ops = clk_composite_ops;
composite->hw.init = &init;
clk = clk_register(dev, &composite->hw);
if (IS_ERR(clk))
goto err;
if (composite->mux_hw)
composite->mux_hw->clk = clk;
clk: composite: rename 'div' references to 'rate' Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2013-04-12 02:31:36 +08:00
if (composite->rate_hw)
composite->rate_hw->clk = clk;
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 20:00:34 +08:00
if (composite->gate_hw)
composite->gate_hw->clk = clk;
return clk;
err:
kfree(composite);
return clk;
}