96 lines
3.1 KiB
Plaintext
96 lines
3.1 KiB
Plaintext
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* Generic Exynos Bus frequency device
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The Samsung Exynos SoC has many buses for data transfer between DRAM
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and sub-blocks in SoC. Most Exynos SoCs share the common architecture
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for buses. Generally, each bus of Exynos SoC includes a source clock
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and a power line, which are able to change the clock frequency
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of the bus in runtime. To monitor the usage of each bus in runtime,
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the driver uses the PPMU (Platform Performance Monitoring Unit), which
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is able to measure the current load of sub-blocks.
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There are a little different composition among Exynos SoC because each Exynos
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SoC has different sub-blocks. Therefore, such difference should be specified
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in devicetree file instead of each device driver. In result, this driver
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is able to support the bus frequency for all Exynos SoCs.
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Required properties for bus device:
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- compatible: Should be "samsung,exynos-bus".
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- clock-names : the name of clock used by the bus, "bus".
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- clocks : phandles for clock specified in "clock-names" property.
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- operating-points-v2: the OPP table including frequency/voltage information
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to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
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- vdd-supply: the regulator to provide the buses with the voltage.
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- devfreq-events: the devfreq-event device to monitor the current utilization
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of buses.
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Optional properties for bus device:
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- exynos,saturation-ratio: the percentage value which is used to calibrate
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the performance count against total cycle count.
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- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
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which is used to calculate the max voltage.
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Example1:
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Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
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power line (regulator). The MIF (Memory Interface) AXI bus is used to
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transfer data between DRAM and CPU and uses the VDD_MIF regulator.
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- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
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- MIF bus's frequency/voltage table
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-----------------------
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|Lv| Freq | Voltage |
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-----------------------
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|L1| 50000 |800000 |
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|L2| 100000 |800000 |
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|L3| 134000 |800000 |
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|L4| 200000 |825000 |
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|L5| 400000 |875000 |
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-----------------------
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Example2 :
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The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
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is listed below:
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu_dmc CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <800000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <800000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <800000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <825000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <875000>;
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};
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};
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Usage case to handle the frequency and voltage of bus on runtime
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in exynos3250-rinato.dts is listed below:
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&bus_dmc {
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
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vdd-supply = <&buck1_reg>; /* VDD_MIF */
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status = "okay";
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};
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