2009-12-19 01:07:39 +08:00
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/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
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* Digitizer with Horizontal PLL registers
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*
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* Copyright (C) 2009 Texas Instruments Inc
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* Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
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*
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* This code is partially based upon the TVP5150 driver
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* written by Mauro Carvalho Chehab (mchehab@infradead.org),
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* the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
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* and the TVP7002 driver in the TI LSP 2.10.00.14
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Naming conventions
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* ------------------
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*
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* FDBK: Feedback
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* DIV: Divider
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* CTL: Control
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* SEL: Select
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* IN: Input
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* OUT: Output
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* R: Red
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* G: Green
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* B: Blue
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* OFF: Offset
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* THRS: Threshold
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* DGTL: Digital
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* LVL: Level
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* PWR: Power
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* MVIS: Macrovision
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* W: Width
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* H: Height
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* ALGN: Alignment
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* CLK: Clocks
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* TOL: Tolerance
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* BWTH: Bandwidth
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* COEF: Coefficient
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* STAT: Status
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* AUTO: Automatic
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* FLD: Field
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* L: Line
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*/
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#define TVP7002_CHIP_REV 0x00
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#define TVP7002_HPLL_FDBK_DIV_MSBS 0x01
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#define TVP7002_HPLL_FDBK_DIV_LSBS 0x02
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#define TVP7002_HPLL_CRTL 0x03
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#define TVP7002_HPLL_PHASE_SEL 0x04
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#define TVP7002_CLAMP_START 0x05
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#define TVP7002_CLAMP_W 0x06
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#define TVP7002_HSYNC_OUT_W 0x07
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#define TVP7002_B_FINE_GAIN 0x08
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#define TVP7002_G_FINE_GAIN 0x09
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#define TVP7002_R_FINE_GAIN 0x0a
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#define TVP7002_B_FINE_OFF_MSBS 0x0b
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#define TVP7002_G_FINE_OFF_MSBS 0x0c
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#define TVP7002_R_FINE_OFF_MSBS 0x0d
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#define TVP7002_SYNC_CTL_1 0x0e
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#define TVP7002_HPLL_AND_CLAMP_CTL 0x0f
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#define TVP7002_SYNC_ON_G_THRS 0x10
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#define TVP7002_SYNC_SEPARATOR_THRS 0x11
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#define TVP7002_HPLL_PRE_COAST 0x12
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#define TVP7002_HPLL_POST_COAST 0x13
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#define TVP7002_SYNC_DETECT_STAT 0x14
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#define TVP7002_OUT_FORMATTER 0x15
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#define TVP7002_MISC_CTL_1 0x16
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#define TVP7002_MISC_CTL_2 0x17
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#define TVP7002_MISC_CTL_3 0x18
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#define TVP7002_IN_MUX_SEL_1 0x19
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#define TVP7002_IN_MUX_SEL_2 0x1a
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#define TVP7002_B_AND_G_COARSE_GAIN 0x1b
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#define TVP7002_R_COARSE_GAIN 0x1c
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#define TVP7002_FINE_OFF_LSBS 0x1d
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#define TVP7002_B_COARSE_OFF 0x1e
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#define TVP7002_G_COARSE_OFF 0x1f
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#define TVP7002_R_COARSE_OFF 0x20
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#define TVP7002_HSOUT_OUT_START 0x21
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#define TVP7002_MISC_CTL_4 0x22
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#define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23
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#define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24
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#define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25
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#define TVP7002_AUTO_LVL_CTL_ENABLE 0x26
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#define TVP7002_DGTL_ALC_OUT_MSBS 0x27
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#define TVP7002_AUTO_LVL_CTL_FILTER 0x28
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/* Reserved 0x29*/
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#define TVP7002_FINE_CLAMP_CTL 0x2a
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#define TVP7002_PWR_CTL 0x2b
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#define TVP7002_ADC_SETUP 0x2c
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#define TVP7002_COARSE_CLAMP_CTL 0x2d
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#define TVP7002_SOG_CLAMP 0x2e
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#define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f
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#define TVP7002_SOG_COARSE_CLAMP_CTL 0x30
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#define TVP7002_ALC_PLACEMENT 0x31
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/* Reserved 0x32 */
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/* Reserved 0x33 */
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#define TVP7002_MVIS_STRIPPER_W 0x34
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#define TVP7002_VSYNC_ALGN 0x35
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#define TVP7002_SYNC_BYPASS 0x36
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#define TVP7002_L_FRAME_STAT_LSBS 0x37
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#define TVP7002_L_FRAME_STAT_MSBS 0x38
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#define TVP7002_CLK_L_STAT_LSBS 0x39
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2018-01-05 02:08:56 +08:00
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#define TVP7002_CLK_L_STAT_MSBS 0x3a
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2009-12-19 01:07:39 +08:00
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#define TVP7002_HSYNC_W 0x3b
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#define TVP7002_VSYNC_W 0x3c
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2018-01-05 02:08:56 +08:00
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#define TVP7002_L_LENGTH_TOL 0x3d
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2009-12-19 01:07:39 +08:00
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/* Reserved 0x3e */
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#define TVP7002_VIDEO_BWTH_CTL 0x3f
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#define TVP7002_AVID_START_PIXEL_LSBS 0x40
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#define TVP7002_AVID_START_PIXEL_MSBS 0x41
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2018-01-05 02:08:56 +08:00
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#define TVP7002_AVID_STOP_PIXEL_LSBS 0x42
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2009-12-19 01:07:39 +08:00
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#define TVP7002_AVID_STOP_PIXEL_MSBS 0x43
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#define TVP7002_VBLK_F_0_START_L_OFF 0x44
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#define TVP7002_VBLK_F_1_START_L_OFF 0x45
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#define TVP7002_VBLK_F_0_DURATION 0x46
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#define TVP7002_VBLK_F_1_DURATION 0x47
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#define TVP7002_FBIT_F_0_START_L_OFF 0x48
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#define TVP7002_FBIT_F_1_START_L_OFF 0x49
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#define TVP7002_YUV_Y_G_COEF_LSBS 0x4a
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#define TVP7002_YUV_Y_G_COEF_MSBS 0x4b
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#define TVP7002_YUV_Y_B_COEF_LSBS 0x4c
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#define TVP7002_YUV_Y_B_COEF_MSBS 0x4d
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#define TVP7002_YUV_Y_R_COEF_LSBS 0x4e
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#define TVP7002_YUV_Y_R_COEF_MSBS 0x4f
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#define TVP7002_YUV_U_G_COEF_LSBS 0x50
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#define TVP7002_YUV_U_G_COEF_MSBS 0x51
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#define TVP7002_YUV_U_B_COEF_LSBS 0x52
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#define TVP7002_YUV_U_B_COEF_MSBS 0x53
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#define TVP7002_YUV_U_R_COEF_LSBS 0x54
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#define TVP7002_YUV_U_R_COEF_MSBS 0x55
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#define TVP7002_YUV_V_G_COEF_LSBS 0x56
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#define TVP7002_YUV_V_G_COEF_MSBS 0x57
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#define TVP7002_YUV_V_B_COEF_LSBS 0x58
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#define TVP7002_YUV_V_B_COEF_MSBS 0x59
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#define TVP7002_YUV_V_R_COEF_LSBS 0x5a
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#define TVP7002_YUV_V_R_COEF_MSBS 0x5b
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