365 lines
9.4 KiB
C
365 lines
9.4 KiB
C
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/*
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* arch/arm/mach-orion/db88f5281-setup.c
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*
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* Marvell Orion-2 Development Board Setup
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/nand.h>
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#include <linux/timer.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/i2c.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <asm/arch/orion.h>
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#include <asm/arch/platform.h>
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#include "common.h"
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/*****************************************************************************
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* DB-88F5281 on board devices
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****************************************************************************/
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/*
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* 512K NOR flash Device bus boot chip select
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*/
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#define DB88F5281_NOR_BOOT_BASE 0xf4000000
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#define DB88F5281_NOR_BOOT_SIZE SZ_512K
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/*
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* 7-Segment on Device bus chip select 0
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*/
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#define DB88F5281_7SEG_BASE 0xfa000000
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#define DB88F5281_7SEG_SIZE SZ_1K
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/*
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* 32M NOR flash on Device bus chip select 1
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*/
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#define DB88F5281_NOR_BASE 0xfc000000
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#define DB88F5281_NOR_SIZE SZ_32M
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/*
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* 32M NAND flash on Device bus chip select 2
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*/
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#define DB88F5281_NAND_BASE 0xfa800000
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#define DB88F5281_NAND_SIZE SZ_1K
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/*
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* PCI
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*/
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#define DB88F5281_PCI_SLOT0_OFFS 7
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#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
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#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
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/*****************************************************************************
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* 512M NOR Flash on Device bus Boot CS
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****************************************************************************/
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static struct physmap_flash_data db88f5281_boot_flash_data = {
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.width = 1, /* 8 bit bus width */
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};
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static struct resource db88f5281_boot_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = DB88F5281_NOR_BOOT_BASE,
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.end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device db88f5281_boot_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &db88f5281_boot_flash_data,
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},
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.num_resources = 1,
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.resource = &db88f5281_boot_flash_resource,
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};
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/*****************************************************************************
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* 32M NOR Flash on Device bus CS1
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****************************************************************************/
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static struct physmap_flash_data db88f5281_nor_flash_data = {
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.width = 4, /* 32 bit bus width */
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};
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static struct resource db88f5281_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = DB88F5281_NOR_BASE,
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.end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
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};
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static struct platform_device db88f5281_nor_flash = {
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.name = "physmap-flash",
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.id = 1,
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.dev = {
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.platform_data = &db88f5281_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &db88f5281_nor_flash_resource,
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};
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/*****************************************************************************
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* 32M NAND Flash on Device bus CS2
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****************************************************************************/
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static struct mtd_partition db88f5281_nand_parts[] = {
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{
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.name = "kernel",
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.offset = 0,
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.size = SZ_2M,
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},
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{
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.name = "root",
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.offset = SZ_2M,
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.size = (SZ_16M - SZ_2M),
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},
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{
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.name = "user",
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.offset = SZ_16M,
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.size = SZ_8M,
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},
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{
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.name = "recovery",
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.offset = (SZ_16M + SZ_8M),
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.size = SZ_8M,
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},
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};
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static struct resource db88f5281_nand_resource = {
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.flags = IORESOURCE_MEM,
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.start = DB88F5281_NAND_BASE,
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.end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
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};
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static struct orion_nand_data db88f5281_nand_data = {
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.parts = db88f5281_nand_parts,
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.nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
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.cle = 0,
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.ale = 1,
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.width = 8,
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};
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static struct platform_device db88f5281_nand_flash = {
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.name = "orion_nand",
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.id = -1,
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.dev = {
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.platform_data = &db88f5281_nand_data,
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},
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.resource = &db88f5281_nand_resource,
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.num_resources = 1,
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};
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/*****************************************************************************
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* 7-Segment on Device bus CS0
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* Dummy counter every 2 sec
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****************************************************************************/
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static void __iomem *db88f5281_7seg;
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static struct timer_list db88f5281_timer;
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static void db88f5281_7seg_event(unsigned long data)
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{
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static int count = 0;
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writel(0, db88f5281_7seg + (count << 4));
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count = (count + 1) & 7;
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mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
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}
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static int __init db88f5281_7seg_init(void)
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{
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if (machine_is_db88f5281()) {
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db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
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DB88F5281_7SEG_SIZE);
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if (!db88f5281_7seg) {
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printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
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return -EIO;
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}
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setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
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mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
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}
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return 0;
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}
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__initcall(db88f5281_7seg_init);
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/*****************************************************************************
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* PCI
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****************************************************************************/
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void __init db88f5281_pci_preinit(void)
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{
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int pin;
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/*
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* Configure PCI GPIO IRQ pins
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*/
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pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
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if (gpio_request(pin, "PCI Int1") == 0) {
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if (gpio_direction_input(pin) == 0) {
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set_irq_type(gpio_to_irq(pin), IRQT_LOW);
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} else {
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printk(KERN_ERR "db88f5281_pci_preinit faield to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
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}
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pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
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if (gpio_request(pin, "PCI Int2") == 0) {
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if (gpio_direction_input(pin) == 0) {
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set_irq_type(gpio_to_irq(pin), IRQT_LOW);
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} else {
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printk(KERN_ERR "db88f5281_pci_preinit faield "
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"to set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
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}
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}
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static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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/*
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* PCIE IRQ is connected internally (not GPIO)
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*/
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if (dev->bus->number == orion_pcie_local_bus_nr())
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return IRQ_ORION_PCIE0_INT;
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/*
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* PCI IRQs are connected via GPIOs
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*/
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switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
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case 0:
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return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
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case 1:
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case 2:
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return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
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default:
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return -1;
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}
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}
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static struct hw_pci db88f5281_pci __initdata = {
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.nr_controllers = 2,
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.preinit = db88f5281_pci_preinit,
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.swizzle = pci_std_swizzle,
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.setup = orion_pci_sys_setup,
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.scan = orion_pci_sys_scan_bus,
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.map_irq = db88f5281_pci_map_irq,
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};
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static int __init db88f5281_pci_init(void)
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{
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if (machine_is_db88f5281())
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pci_common_init(&db88f5281_pci);
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return 0;
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}
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subsys_initcall(db88f5281_pci_init);
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data db88f5281_eth_data = {
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.phy_addr = 8,
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.force_phy_addr = 1,
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};
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/*****************************************************************************
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* RTC DS1339 on I2C bus
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****************************************************************************/
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static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
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.driver_name = "rtc-ds1307",
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.type = "ds1339",
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.addr = 0x68,
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static struct platform_device *db88f5281_devs[] __initdata = {
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&db88f5281_boot_flash,
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&db88f5281_nor_flash,
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&db88f5281_nand_flash,
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};
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static void __init db88f5281_init(void)
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{
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/*
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* Basic Orion setup. Need to be called early.
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*/
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orion_init();
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/*
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* Setup the CPU address decode windows for our on-board devices
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*/
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orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
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DB88F5281_NOR_BOOT_SIZE, -1);
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orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
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DB88F5281_7SEG_SIZE, -1);
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orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
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DB88F5281_NOR_SIZE, -1);
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orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
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DB88F5281_NAND_SIZE, -1);
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/*
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* Setup Multiplexing Pins:
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* MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
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* MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
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* MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
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* MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
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* MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
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* MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
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* MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
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* MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
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* MPP16: UART1_RX MPP17: UART1_TX
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* MPP18: UART1_CTS MPP19: UART1_RTS
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* MPP-DEV: DEV_D[16:31]
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*/
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orion_write(MPP_0_7_CTRL, 0x00222203);
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orion_write(MPP_8_15_CTRL, 0x44000000);
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orion_write(MPP_16_19_CTRL, 0);
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orion_write(MPP_DEV_CTRL, 0);
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orion_gpio_set_valid_pins(0x00003fc3);
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platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
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i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
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orion_eth_init(&db88f5281_eth_data);
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}
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MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
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/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
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.phys_io = ORION_REGS_BASE,
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.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = db88f5281_init,
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.map_io = orion_map_io,
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.init_irq = orion_init_irq,
|
||
|
|
.timer = &orion_timer,
|
||
|
|
MACHINE_END
|