46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2M System Controller
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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* Based on Renesas R-Car M3-W System Controller
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* Copyright (C) 2016 Glider bvba
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a774a1-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
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{ "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
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PD_CPU_NOCR },
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{ "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
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PD_CPU_NOCR },
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{ "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
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PD_CPU_NOCR },
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{ "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
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PD_CPU_NOCR },
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{ "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
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PD_CPU_NOCR },
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{ "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
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PD_CPU_NOCR },
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{ "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
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{ "a2vc0", 0x3c0, 0, R8A774A1_PD_A2VC0, R8A774A1_PD_A3VC },
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{ "a2vc1", 0x3c0, 1, R8A774A1_PD_A2VC1, R8A774A1_PD_A3VC },
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{ "3dg-a", 0x100, 0, R8A774A1_PD_3DG_A, R8A774A1_PD_ALWAYS_ON },
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{ "3dg-b", 0x100, 1, R8A774A1_PD_3DG_B, R8A774A1_PD_3DG_A },
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};
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const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
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.areas = r8a774a1_areas,
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.num_areas = ARRAY_SIZE(r8a774a1_areas),
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};
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