mirror of https://github.com/ptitSeb/box64.git
[RV64_DYNAREC] Fix some typos in docs and dynarec/rv64 (#1758)
* [Typo] fix some typo in docs and dynarec/rv64 * [Typo] fix some typo in docs and dynarec/rv64 * [Typo] fix some typo in dynarec/rv64 * [Typo] fix some typo in dynarec/rv64 * [Typo] fix some typo in docs
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@ -98,7 +98,7 @@ Using a 64bit OS:
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Using a 64bit OS:
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Caution: please use gcc-11 or higher, older gcc dosen't know cortex-a78ae
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Caution: please use gcc-11 or higher, older gcc doesn't know cortex-a78ae
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```
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-D TEGRA_T234=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
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```
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@ -211,7 +211,7 @@ If you encounter some linking errors, try using `NOLOADADDR=ON` (`cmake -D NOLOA
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### Use ccmake
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Alternatively, you can **use the curses-bases ccmake (or any other gui frontend for cmake)** to select wich platform to use interactively.
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Alternatively, you can **use the curses-based ccmake (or any other gui frontend for cmake)** to select which platform to use interactively.
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### Customize your build
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@ -245,7 +245,7 @@ You need to add `-DWITH_MOLD=1` if GNU ld is extremely slow. Then run `mold -run
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#### Build a statically linked box64
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You can now build box64 staticaly linked, with `-DSTATICBUILD`. This is to use inside an x86_64 chroot. Note that this version of box64 will have just the minimum of wrapped libs. So only libc, libm and libpthread basically are wrapped. Other libs (like libGL or libvulkan, SDL2, etc...) will not be wrapped and x86_64 version will be used. It's designed to be used in docker image, or in headless server.
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You can now build box64 statically linked, with `-DSTATICBUILD`. This is to use inside an x86_64 chroot. Note that this version of box64 will have just the minimum of wrapped libs. So only libc, libm and libpthread basically are wrapped. Other libs (like libGL or libvulkan, SDL2, etc...) will not be wrapped and x86_64 version will be used. It's designed to be used in docker image, or in headless server.
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Also, the Static Build is highly experimental, but feedback are always welcomed.
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----
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@ -7,7 +7,7 @@ Env. var with * can also be put inside box64rc files.
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Box64 look for 2 places for rcfile: `/etc/box64.box64rc` and `~/.box64rc`
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The second takes precedence to the first, on an APP level
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(that means if an [MYAPP] my appears in both file, only the settings in `~/.box64rc` will be applied)
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There is also some égeneric" name, like [*SETUP*] that will be applied to every program containg "setup" in the name
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There is also some égeneric" name, like [*SETUP*] that will be applied to every program containing "setup" in the name
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(Note that this is not a full regex rules, it's just a name between '[*' and '*]', nothing else)
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#### BOX64_LOG *
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@ -97,7 +97,7 @@ Show Segfault signal even if a signal handler is present
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* 1 : Show SIGSEGV detail, even if a signal handler is present
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#### BOX64_SHOWBT *
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Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
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Show some Backtrace (Native and Emulated) when a signal (SEGV, ILL or BUS) is caught
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* 0 : Don"t show backtraces (Default.)
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* 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)
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@ -151,7 +151,7 @@ Forbid dynablock creation in the interval specified (helpful for debugging behav
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#### BOX64_DYNAREC_TEST *
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Dynarec will compare it's execution with the interpreter (super slow, only for testing)
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* 0 : No comparison. (Default.)
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* 1 : Each opcode runs on interepter and on Dynarec, and regs and memory are compared and print if different.
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* 1 : Each opcode runs on interpreter and on Dynarec, and regs and memory are compared and print if different.
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* 2 : Thread-safe tests, extremely slow.
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* 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynarec is tested (inclusive-exclusive)
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@ -203,7 +203,7 @@ Optimisation of CALL/RET opcodes (not compatible with jit/dynarec/smc)
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#### BOX64_DYNAREC_ALIGNED_ATOMICS *
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Generated code for aligned atomics only
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* 0 : The code generated can handle unaligned atomics (Default)
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* 1 : Generated code only for aligned atomics (faster and less code generated, but will SEGBUS if LOCK prefix is unsed on unaligned data)
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* 1 : Generated code only for aligned atomics (faster and less code generated, but will SEGBUS if LOCK prefix is unused on unaligned data)
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#### BOX64_DYNAREC_BLEEDING_EDGE *
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Detect MonoBleedingEdge and apply conservative settings
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@ -290,7 +290,7 @@ Box64 will use wrapped libs even if the lib is specified with absolute path
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* 1 : Use Wrapped native libs even if path is absolute
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#### BOX64_PREFER_EMULATED *
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Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL, vulkan and X11
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Box64 will prefer emulated libs first (except for glibc, alsa, pulse, GL, vulkan and X11
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* 0 : Native libs are preferred (Default.)
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* 1 : Emulated libs are preferred (Default for program running inside pressure-vessel)
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@ -321,14 +321,14 @@ Disables the load of vulkan libraries.
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* 1 : Disables the load of vulkan libraries, both the native and the i386 version (can be useful on Pi4, where the vulkan driver is not quite there yet.)
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#### BOX64_SHAEXT *
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Expose or not SHAEXT (a.k.a. SHA_NI) capabilites
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* 0 : Do not expose SHAEXT capabilites
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* 1 : Expose SHAEXT capabilites (Default.)
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Expose or not SHAEXT (a.k.a. SHA_NI) capabilities
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* 0 : Do not expose SHAEXT capabilities
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* 1 : Expose SHAEXT capabilities (Default.)
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#### BOX64_SSE42 *
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Expose or not SSE 4.2 capabilites
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* 0 : Do not expose SSE 4.2 capabilites (default when libjvm is detected)
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* 1 : Expose SSE 4.2 capabilites (Default.)
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Expose or not SSE 4.2 capabilities
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* 0 : Do not expose SSE 4.2 capabilities (default when libjvm is detected)
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* 1 : Expose SSE 4.2 capabilities (Default.)
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#### BOX64_FUTEX_WAITV *
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Use of the new fuext_waitc syscall
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@ -205,14 +205,14 @@ Disable handling of SigILL (to ease debugging mainly).
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Show Segfault signal even if a signal handler is present
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* 0 : Don"t force show the SIGSEGV analysis (Default.)
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* 0 : Don't force show the SIGSEGV analysis (Default.)
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* 1 : Show SIGSEGV detail, even if a signal handler is present
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=item B<BOX64_SHOWBT>=I<0|1>
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Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
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Show some Backtrace (Nativ e and Emulated) when a signal (SEGV, ILL or BUS) is caught
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* 0 : Don"t show backtraces (Default.)
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* 0 : Don't show backtraces (Default.)
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* 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)
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=item B<BOX64_X11THREADS>=I<0|1>
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@ -407,7 +407,7 @@ Box64 will use wrapped libs even if the lib is specified with absolute path
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=item B<BOX64_PREFER_EMULATED>=I<0|1>
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Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL,
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Box64 will prefer emulated libs first (except for glibc, alsa, pulse, GL,
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vulkan and X11
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* 0 : Native libs are preferred (Default.)
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@ -1181,7 +1181,7 @@ uintptr_t dynarec64_00_3(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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&& dyn->insts[ninst-1].x64.addr
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&& *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0xB8
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&& *(uint32_t*)(dyn->insts[ninst-1].x64.addr+1)==0) {
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// hack for some protection that check a divide by zero actualy trigger a divide by zero exception
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// hack for some protection that check a divide by zero actually trigger a divide by zero exception
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MESSAGE(LOG_INFO, "Divide by 0 hack\n");
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GETIP(ip);
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STORE_XEMU_CALL(x3);
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@ -1718,7 +1718,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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NOTEST(x1);
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MV(A1, xRAX);
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CALL_(my_cpuid, -1, 0);
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// BX and DX are not synchronized durring the call, so need to force the update
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// BX and DX are not synchronized during the call, so need to force the update
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LD(xRDX, xEmu, offsetof(x64emu_t, regs[_DX]));
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LD(xRBX, xEmu, offsetof(x64emu_t, regs[_BX]));
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break;
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@ -269,7 +269,7 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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ADDI(x5, xEmu, offsetof(x64emu_t, scratch));
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// perserve gd
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// preserve gd
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LD(x3, gback, gdoffset + 0);
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LD(x4, gback, gdoffset + 8);
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SD(x3, x5, 0);
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@ -49,7 +49,7 @@ uintptr_t dynarec64_F0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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GETREX();
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// TODO: Add support for unligned memory access for all the LOCK ones.
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// TODO: Add support for unaligned memory access for all the LOCK ones.
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// TODO: Add support for BOX4_DYNAREC_ALIGNED_ATOMICS.
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switch(opcode) {
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@ -888,7 +888,7 @@ int extcache_st_coherency(dynarec_rv64_t* dyn, int ninst, int a, int b)
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return i1;
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}
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// On step 1, Float/Double for ST is actualy computed and back-propagated
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// On step 1, Float/Double for ST is actually computed and back-propagated
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// On step 2-3, the value is just read for inst[...].n.neocache[..]
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// the reg returned is *2 for FLOAT
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int x87_do_push(dynarec_rv64_t* dyn, int ninst, int s1, int t)
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@ -2229,7 +2229,7 @@ static void fpuCacheTransform(dynarec_rv64_t* dyn, int ninst, int s1, int s2, in
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extcache_t cache = dyn->e;
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int s1_val = 0;
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int s2_val = 0;
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// unload every uneeded cache
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// unload every unneeded cache
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// check SSE first, than MMX, in order, for optimisation issue
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for (int i = 0; i < 16; ++i) {
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int j = findCacheSlot(dyn, ninst, EXT_CACHE_SS, i, &cache);
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@ -2400,7 +2400,7 @@ void CacheTransform(dynarec_rv64_t* dyn, int ninst, int cacheupd, int s1, int s2
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void rv64_move32(dynarec_rv64_t* dyn, int ninst, int reg, int32_t val, int zeroup)
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{
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// Depending on val, the following insns are emitted.
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// Depending on val, the following insts are emitted.
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// val == 0 -> ADDI
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// lo12 != 0 && hi20 == 0 -> ADDI
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// lo12 == 0 && hi20 != 0 -> LUI
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@ -2449,7 +2449,7 @@ void fpu_reflectcache(dynarec_rv64_t* dyn, int ninst, int s1, int s2, int s3)
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void fpu_unreflectcache(dynarec_rv64_t* dyn, int ninst, int s1, int s2, int s3)
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{
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// need to undo the top and stack tracking that must not be reflected permenatly yet
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// need to undo the top and stack tracking that must not be reflected permanently yet
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x87_unreflectcache(dyn, ninst, s1, s2, s3);
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}
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@ -1399,7 +1399,7 @@ void emit_shld16c(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, uin
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void emit_pf(dynarec_rv64_t* dyn, int ninst, int s1, int s3, int s4);
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// x87 helper
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// cache of the local stack counter, to avoid upadte at every call
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// cache of the local stack counter, to avoid update at every call
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int x87_stackcount(dynarec_rv64_t* dyn, int ninst, int scratch);
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// restore local stack counter
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void x87_unstackcount(dynarec_rv64_t* dyn, int ninst, int scratch, int count);
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@ -91,10 +91,10 @@ typedef struct flagcache_s {
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typedef struct instruction_rv64_s {
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instruction_x64_t x64;
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uintptr_t address; // (start) address of the arm emitted instruction
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uintptr_t address; // (start) address of the riscv emitted instruction
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uintptr_t epilog; // epilog of current instruction (can be start of next, or barrier stuff)
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int size; // size of the arm emitted instruction
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int size2; // size of the arm emitted instrucion after pass2
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int size; // size of the riscv emitted instruction
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int size2; // size of the riscv emitted instruction after pass2
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int pred_sz; // size of predecessor list
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int *pred; // predecessor array
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uintptr_t mark[3];
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@ -111,8 +111,8 @@ typedef struct instruction_rv64_s {
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uint16_t ymm0_out; // the ymmm0 at th end of the opcode
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uint16_t ymm0_pass2, ymm0_pass3;
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int barrier_maybe;
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flagcache_t f_exit; // flags status at end of intruction
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extcache_t e; // extcache at end of intruction (but before poping)
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flagcache_t f_exit; // flags status at end of instruction
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extcache_t e; // extcache at end of instruction (but before poping)
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flagcache_t f_entry; // flags status before the instruction begin
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uint8_t vector_sew;
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} instruction_rv64_t;
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@ -124,8 +124,8 @@ typedef struct dynarec_rv64_s {
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uintptr_t start; // start of the block
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uint32_t isize; // size in byte of x64 instructions included
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void* block; // memory pointer where next instruction is emitted
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uintptr_t native_start; // start of the arm code
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size_t native_size; // size of emitted arm code
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uintptr_t native_start; // start of the riscv code
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size_t native_size; // size of emitted riscv code
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uintptr_t last_ip; // last set IP in RIP (or NULL if unclean state) TODO: move to a cache something
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uint64_t* table64; // table of 64bits value
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int table64size;// size of table (will be appended at end of executable code)
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@ -257,7 +257,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define BLTU(rs1, rs2, imm13) EMIT(B_type(imm13, rs2, rs1, 0b110, 0b1100011))
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#define BGEU(rs1, rs2, imm13) EMIT(B_type(imm13, rs2, rs1, 0b111, 0b1100011))
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// TODO: Find a better way to have conditionnal jumps? Imm is a relative jump address, so the the 2nd jump needs to be addapted
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// TODO: Find a better way to have conditionnal jumps? Imm is a relative jump address, so the the 2nd jump needs to be adapted
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#define BEQ_safe(rs1, rs2, imm) \
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if ((imm) > -0x1000 && (imm) < 0x1000) { \
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BEQ(rs1, rs2, imm); \
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@ -605,7 +605,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define FSGNJS(rd, rs1, rs2) EMIT(R_type(0b0010000, rs2, rs1, 0b000, rd, 0b1010011))
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// move rs1 to rd
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#define FMVS(rd, rs1) FSGNJS(rd, rs1, rs1)
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// store rs1 with oposite rs2 sign bit to rd
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// store rs1 with opposite rs2 sign bit to rd
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#define FSGNJNS(rd, rs1, rs2) EMIT(R_type(0b0010000, rs2, rs1, 0b001, rd, 0b1010011))
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// -rs1 => rd
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#define FNEGS(rd, rs1) FSGNJNS(rd, rs1, rs1)
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@ -619,7 +619,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define FMVWX(frd, rs1) EMIT(R_type(0b1111000, 0b00000, rs1, 0b000, frd, 0b1010011))
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// Convert from signed 32bits to Single
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#define FCVTSW(frd, rs1, rm) EMIT(R_type(0b1101000, 0b00000, rs1, rm, frd, 0b1010011))
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// Convert from Single to signed 32bits (trucated)
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// Convert from Single to signed 32bits (truncated)
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#define FCVTWS(rd, frs1, rm) EMIT(R_type(0b1100000, 0b00000, frs1, rm, rd, 0b1010011))
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#define FADDS(frd, frs1, frs2) EMIT(R_type(0b0000000, frs2, frs1, 0b000, frd, 0b1010011))
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@ -644,7 +644,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define FCVTLS(rd, frs1, rm) EMIT(R_type(0b1100000, 0b00010, frs1, rm, rd, 0b1010011))
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// Convert from Single to unsigned 64bits
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#define FCVTLUS(rd, frs1, rm) EMIT(R_type(0b1100000, 0b00011, frs1, rm, rd, 0b1010011))
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// onvert from Single to signed 32/64bits (trucated)
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// Convert from Single to signed 32/64bits (truncated)
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#define FCVTSxw(rd, frs1, rm) EMIT(R_type(0b1100000, rex.w ? 0b00010 : 0b00000, frs1, rm, rd, 0b1010011))
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// RV32D
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@ -664,7 +664,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define FSGNJD(rd, rs1, rs2) EMIT(R_type(0b0010001, rs2, rs1, 0b000, rd, 0b1010011))
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// move rs1 to rd
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#define FMVD(rd, rs1) FSGNJD(rd, rs1, rs1)
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// store rs1 with oposite rs2 sign bit to rd
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// store rs1 with opposite rs2 sign bit to rd
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#define FSGNJND(rd, rs1, rs2) EMIT(R_type(0b0010001, rs2, rs1, 0b001, rd, 0b1010011))
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// -rs1 => rd
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#define FNEGD(rd, rs1) FSGNJND(rd, rs1, rs1)
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@ -939,7 +939,7 @@ f28–31 ft8–11 FP temporaries Caller
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// Zbc
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// Carry-less multily (low-part)
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// Carry-less multiply (low-part)
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#define CLMUL(rd, rs1, rs2) EMIT(R_type(0b0000101, rs2, rs1, 0b001, rd, 0b0110011))
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// Carry-less multiply (high-part)
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#define CLMULH(rd, rs1, rs2) EMIT(R_type(0b0000101, rs2, rs1, 0b011, rd, 0b0110011))
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@ -947,7 +947,7 @@ f28–31 ft8–11 FP temporaries Caller
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#define CLMULR(rd, rs1, rs2) EMIT(R_type(0b0000101, rs2, rs1, 0b010, rd, 0b0110011))
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// Zbs
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// encoding of the "imm" on RV64 use a slight different mask, but it will work using R_type with high bit of imm ovewriting low bit op func
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// encoding of the "imm" on RV64 use a slight different mask, but it will work using R_type with high bit of imm overwriting low bit op func
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// Single-bit Clear (Register)
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#define BCLR(rd, rs1, rs2) EMIT(R_type(0b0100100, rs2, rs1, 0b001, rd, 0b0110011))
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// Single-bit Clear (Immediate)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//arm prologue for dynarec
|
||||
//riscv prologue for dynarec
|
||||
//Save stuff, prepare stack and register
|
||||
//called with pointer to emu as 1st parameter
|
||||
//and address to jump to as 2nd parameter
|
||||
|
|
|
|||
Loading…
Reference in New Issue