mirror of https://github.com/rust-lang/rust.git
Add support for Arm64EC inline assembly
This commit is contained in:
Daniel Paoliello
parent
5974fe87c4
commit
2e44d29460
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@ -220,7 +220,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
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constraints.append(&mut clobbers);
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if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
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match asm_arch {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC | InlineAsmArch::Arm => {
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constraints.push("~{cc}".to_string());
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}
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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@ -87,6 +87,20 @@ fn reserved_x18(
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}
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}
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fn restricted_for_arm64ec(
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arch: InlineAsmArch,
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_reloc_model: RelocModel,
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_target_features: &FxIndexSet<Symbol>,
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_target: &Target,
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_is_clobber: bool,
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) -> Result<(), &'static str> {
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if arch == InlineAsmArch::Arm64EC {
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Err("x13, x14, x23, x24, x28, v16-v31 cannot be used for Arm64EC")
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} else {
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Ok(())
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}
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}
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def_regs! {
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AArch64 AArch64InlineAsmReg AArch64InlineAsmRegClass {
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x0: reg = ["x0", "w0"],
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@ -102,8 +116,8 @@ def_regs! {
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x10: reg = ["x10", "w10"],
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x11: reg = ["x11", "w11"],
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x12: reg = ["x12", "w12"],
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x13: reg = ["x13", "w13"],
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x14: reg = ["x14", "w14"],
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x13: reg = ["x13", "w13"] % restricted_for_arm64ec,
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x14: reg = ["x14", "w14"] % restricted_for_arm64ec,
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x15: reg = ["x15", "w15"],
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x16: reg = ["x16", "w16"],
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x17: reg = ["x17", "w17"],
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@ -111,12 +125,12 @@ def_regs! {
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x20: reg = ["x20", "w20"],
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x21: reg = ["x21", "w21"],
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x22: reg = ["x22", "w22"],
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x23: reg = ["x23", "w23"],
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x24: reg = ["x24", "w24"],
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x23: reg = ["x23", "w23"] % restricted_for_arm64ec,
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x24: reg = ["x24", "w24"] % restricted_for_arm64ec,
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x25: reg = ["x25", "w25"],
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x26: reg = ["x26", "w26"],
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x27: reg = ["x27", "w27"],
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x28: reg = ["x28", "w28"],
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x28: reg = ["x28", "w28"] % restricted_for_arm64ec,
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x30: reg = ["x30", "w30", "lr", "wlr"],
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v0: vreg, vreg_low16 = ["v0", "b0", "h0", "s0", "d0", "q0", "z0"],
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v1: vreg, vreg_low16 = ["v1", "b1", "h1", "s1", "d1", "q1", "z1"],
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@ -134,22 +148,22 @@ def_regs! {
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v13: vreg, vreg_low16 = ["v13", "b13", "h13", "s13", "d13", "q13", "z13"],
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v14: vreg, vreg_low16 = ["v14", "b14", "h14", "s14", "d14", "q14", "z14"],
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v15: vreg, vreg_low16 = ["v15", "b15", "h15", "s15", "d15", "q15", "z15"],
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v16: vreg = ["v16", "b16", "h16", "s16", "d16", "q16", "z16"],
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v17: vreg = ["v17", "b17", "h17", "s17", "d17", "q17", "z17"],
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v18: vreg = ["v18", "b18", "h18", "s18", "d18", "q18", "z18"],
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v19: vreg = ["v19", "b19", "h19", "s19", "d19", "q19", "z19"],
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v20: vreg = ["v20", "b20", "h20", "s20", "d20", "q20", "z20"],
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v21: vreg = ["v21", "b21", "h21", "s21", "d21", "q21", "z21"],
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v22: vreg = ["v22", "b22", "h22", "s22", "d22", "q22", "z22"],
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v23: vreg = ["v23", "b23", "h23", "s23", "d23", "q23", "z23"],
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v24: vreg = ["v24", "b24", "h24", "s24", "d24", "q24", "z24"],
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v25: vreg = ["v25", "b25", "h25", "s25", "d25", "q25", "z25"],
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v26: vreg = ["v26", "b26", "h26", "s26", "d26", "q26", "z26"],
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v27: vreg = ["v27", "b27", "h27", "s27", "d27", "q27", "z27"],
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v28: vreg = ["v28", "b28", "h28", "s28", "d28", "q28", "z28"],
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v29: vreg = ["v29", "b29", "h29", "s29", "d29", "q29", "z29"],
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v30: vreg = ["v30", "b30", "h30", "s30", "d30", "q30", "z30"],
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v31: vreg = ["v31", "b31", "h31", "s31", "d31", "q31", "z31"],
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v16: vreg = ["v16", "b16", "h16", "s16", "d16", "q16", "z16"] % restricted_for_arm64ec,
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v17: vreg = ["v17", "b17", "h17", "s17", "d17", "q17", "z17"] % restricted_for_arm64ec,
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v18: vreg = ["v18", "b18", "h18", "s18", "d18", "q18", "z18"] % restricted_for_arm64ec,
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v19: vreg = ["v19", "b19", "h19", "s19", "d19", "q19", "z19"] % restricted_for_arm64ec,
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v20: vreg = ["v20", "b20", "h20", "s20", "d20", "q20", "z20"] % restricted_for_arm64ec,
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v21: vreg = ["v21", "b21", "h21", "s21", "d21", "q21", "z21"] % restricted_for_arm64ec,
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v22: vreg = ["v22", "b22", "h22", "s22", "d22", "q22", "z22"] % restricted_for_arm64ec,
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v23: vreg = ["v23", "b23", "h23", "s23", "d23", "q23", "z23"] % restricted_for_arm64ec,
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v24: vreg = ["v24", "b24", "h24", "s24", "d24", "q24", "z24"] % restricted_for_arm64ec,
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v25: vreg = ["v25", "b25", "h25", "s25", "d25", "q25", "z25"] % restricted_for_arm64ec,
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v26: vreg = ["v26", "b26", "h26", "s26", "d26", "q26", "z26"] % restricted_for_arm64ec,
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v27: vreg = ["v27", "b27", "h27", "s27", "d27", "q27", "z27"] % restricted_for_arm64ec,
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v28: vreg = ["v28", "b28", "h28", "s28", "d28", "q28", "z28"] % restricted_for_arm64ec,
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v29: vreg = ["v29", "b29", "h29", "s29", "d29", "q29", "z29"] % restricted_for_arm64ec,
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v30: vreg = ["v30", "b30", "h30", "s30", "d30", "q30", "z30"] % restricted_for_arm64ec,
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v31: vreg = ["v31", "b31", "h31", "s31", "d31", "q31", "z31"] % restricted_for_arm64ec,
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p0: preg = ["p0"],
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p1: preg = ["p1"],
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p2: preg = ["p2"],
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@ -217,6 +217,7 @@ pub enum InlineAsmArch {
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X86_64,
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Arm,
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AArch64,
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Arm64EC,
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RiscV32,
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RiscV64,
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Nvptx64,
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@ -246,6 +247,7 @@ impl FromStr for InlineAsmArch {
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"x86_64" => Ok(Self::X86_64),
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"arm" => Ok(Self::Arm),
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"aarch64" => Ok(Self::AArch64),
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"arm64ec" => Ok(Self::Arm64EC),
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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@ -341,7 +343,9 @@ impl InlineAsmReg {
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Ok(match arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => Self::X86(X86InlineAsmReg::parse(name)?),
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InlineAsmArch::Arm => Self::Arm(ArmInlineAsmReg::parse(name)?),
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InlineAsmArch::AArch64 => Self::AArch64(AArch64InlineAsmReg::parse(name)?),
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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Self::AArch64(AArch64InlineAsmReg::parse(name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmReg::parse(name)?)
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}
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@ -610,7 +614,9 @@ impl InlineAsmRegClass {
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Self::X86(X86InlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::Arm => Self::Arm(ArmInlineAsmRegClass::parse(name)?),
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InlineAsmArch::AArch64 => Self::AArch64(AArch64InlineAsmRegClass::parse(name)?),
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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Self::AArch64(AArch64InlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmRegClass::parse(name)?)
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}
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@ -783,7 +789,7 @@ pub fn allocatable_registers(
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arm::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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}
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InlineAsmArch::AArch64 => {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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let mut map = aarch64::regclass_map();
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aarch64::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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@ -909,6 +915,10 @@ impl InlineAsmClobberAbi {
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}),
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_ => Err(&["C", "system", "efiapi"]),
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},
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InlineAsmArch::Arm64EC => match name {
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"C" | "system" => Ok(InlineAsmClobberAbi::AArch64NoX18),
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_ => Err(&["C", "system"]),
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},
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => match name {
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"C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::RiscV),
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_ => Err(&["C", "system", "efiapi"]),
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@ -19,6 +19,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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- M68k
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- CSKY
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- s390x
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- Arm64EC
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## Register classes
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@ -51,6 +52,9 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `freg` | `f[0-31]` | `f` |
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| s390x | `reg` | `r[0-10]`, `r[12-14]` | `r` |
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| s390x | `freg` | `f[0-15]` | `f` |
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| Arm64EC | `reg` | `x[0-12]`, `x[15-22]`, `x[25-27]`, `x30` | `r` |
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| Arm64EC | `vreg` | `v[0-15]` | `w` |
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| Arm64EC | `vreg_low16` | `v[0-15]` | `x` |
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> **Notes**:
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> - NVPTX doesn't have a fixed register set, so named registers are not supported.
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@ -86,6 +90,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `freg` | None | `f32`, |
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| s390x | `reg`, `reg_addr` | None | `i8`, `i16`, `i32`, `i64` |
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| s390x | `freg` | None | `f32`, `f64` |
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| Arm64EC | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| Arm64EC | `vreg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64`, <br> `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2`, `f64x1`, <br> `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` |
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## Register aliases
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@ -118,6 +124,12 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `r29` | `rtb` |
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| CSKY | `r30` | `svbr` |
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| CSKY | `r31` | `tls` |
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| Arm64EC | `x[0-30]` | `w[0-30]` |
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| Arm64EC | `x29` | `fp` |
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| Arm64EC | `x30` | `lr` |
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| Arm64EC | `sp` | `wsp` |
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| Arm64EC | `xzr` | `wzr` |
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| Arm64EC | `v[0-15]` | `b[0-15]`, `h[0-15]`, `s[0-15]`, `d[0-15]`, `q[0-15]` |
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> **Notes**:
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> - TI does not mandate a frame pointer for MSP430, but toolchains are allowed
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@ -128,8 +140,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| Architecture | Unsupported register | Reason |
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| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| All | `sp`, `r15` (s390x) | The stack pointer must be restored to its original value at the end of an asm code block. |
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| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r11` (s390x) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. |
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| All | `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r11` (s390x), `x29` (Arm64EC) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon), `x19` (Arm64EC) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. |
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| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
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| MIPS | `$1` or `$at` | Reserved for assembler. |
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| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
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@ -145,6 +157,9 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `r15` | This is the link register. |
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| CSKY | `r[26-30]` | Reserved by its ABI. |
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| CSKY | `r31` | This is the TLS register. |
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| Arm64EC | `xzr` | This is a constant zero register which can't be modified. |
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| Arm64EC | `x18` | This is an OS-reserved register. |
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| Arm64EC | `x13`, `x14`, `x23`, `x24`, `x28`, `v[16-31]` | These are AArch64 registers that are not supported for Arm64EC. |
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## Template modifiers
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@ -165,6 +180,16 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| s390x | `freg` | None | `%f0` | None |
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| CSKY | `reg` | None | `r0` | None |
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| CSKY | `freg` | None | `f0` | None |
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| Arm64EC | `reg` | None | `x0` | `x` |
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| Arm64EC | `reg` | `w` | `w0` | `w` |
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| Arm64EC | `reg` | `x` | `x0` | `x` |
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| Arm64EC | `vreg` | None | `v0` | None |
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| Arm64EC | `vreg` | `v` | `v0` | None |
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| Arm64EC | `vreg` | `b` | `b0` | `b` |
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| Arm64EC | `vreg` | `h` | `h0` | `h` |
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| Arm64EC | `vreg` | `s` | `s0` | `s` |
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| Arm64EC | `vreg` | `d` | `d0` | `d` |
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| Arm64EC | `vreg` | `q` | `q0` | `q` |
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# Flags covered by `preserves_flags`
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@ -177,3 +202,6 @@ These flags registers must be restored upon exiting the asm block if the `preser
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- The condition code register `ccr`.
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- s390x
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- The condition code register `cc`.
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- Arm64EC
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- Condition flags (`NZCV` register).
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- Floating-point status (`FPSR` register).
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@ -1,8 +1,11 @@
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//@ revisions: aarch64 arm64ec
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//@ assembly-output: emit-asm
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//@ compile-flags: --target aarch64-unknown-linux-gnu
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//@ needs-llvm-components: aarch64
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//@ [aarch64] compile-flags: --target aarch64-unknown-linux-gnu
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//@ [aarch64] needs-llvm-components: aarch64
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//@ [arm64ec] compile-flags: --target arm64ec-pc-windows-msvc
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//@ [arm64ec] needs-llvm-components: aarch64
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#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
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#![feature(no_core, lang_items, rustc_attrs, repr_simd, asm_experimental_arch)]
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#![crate_type = "rlib"]
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#![no_core]
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#![allow(asm_sub_register, non_camel_case_types)]
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@ -77,7 +80,7 @@ extern "C" {
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static extern_static: u8;
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}
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// CHECK-LABEL: sym_fn:
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// CHECK-LABEL: {{("#)?}}sym_fn{{"?}}
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// CHECK: //APP
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// CHECK: bl extern_func
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// CHECK: //NO_APP
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@ -86,7 +89,7 @@ pub unsafe fn sym_fn() {
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asm!("bl {}", sym extern_func);
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}
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// CHECK-LABEL: sym_static:
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// CHECK-LABEL: {{("#)?}}sym_static{{"?}}
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// CHECK: //APP
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// CHECK: adr x0, extern_static
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// CHECK: //NO_APP
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@ -96,7 +99,7 @@ pub unsafe fn sym_static() {
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}
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// Regression test for #75761
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// CHECK-LABEL: issue_75761:
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// CHECK-LABEL: {{("#)?}}issue_75761{{"?}}
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// CHECK: str {{.*}}x30
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// CHECK: //APP
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// CHECK: //NO_APP
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@ -144,421 +147,421 @@ macro_rules! check_reg {
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};
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}
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// CHECK-LABEL: reg_i8:
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// CHECK-LABEL: {{("#)?}}reg_i8{{"?}}
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// CHECK: //APP
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// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
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// CHECK: //NO_APP
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check!(reg_i8 i8 reg "mov" "");
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// CHECK-LABEL: reg_i16:
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// CHECK-LABEL: {{("#)?}}reg_i16{{"?}}
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// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_i16 i16 reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: reg_i32:
|
||||
// CHECK-LABEL: {{("#)?}}reg_i32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_i32 i32 reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: reg_f32:
|
||||
// CHECK-LABEL: {{("#)?}}reg_f32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_f32 f32 reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: reg_i64:
|
||||
// CHECK-LABEL: {{("#)?}}reg_i64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_i64 i64 reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: reg_f64:
|
||||
// CHECK-LABEL: {{("#)?}}reg_f64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_f64 f64 reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: reg_ptr:
|
||||
// CHECK-LABEL: {{("#)?}}reg_ptr{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(reg_ptr ptr reg "mov" "");
|
||||
|
||||
// CHECK-LABEL: vreg_i8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i8 i8 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i16:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i16 i16 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i32:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i32 i32 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f32:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f32 f32 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i64:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i64 i64 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f64:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f64 f64 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_ptr:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_ptr{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_ptr ptr vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i8x8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i8x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i8x8 i8x8 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i16x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i16x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i16x4 i16x4 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i32x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i32x2 i32x2 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i64x1:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i64x1 i64x1 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f32x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f32x2 f32x2 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f64x1:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f64x1 f64x1 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i8x16:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i8x16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i8x16 i8x16 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i16x8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i16x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i16x8 i16x8 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i32x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i32x4 i32x4 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_i64x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_i64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_i64x2 i64x2 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f32x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f32x4 f32x4 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_f64x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_f64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_f64x2 f64x2 vreg "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i8 i8 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i16:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i16 i16 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f32:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f32 f32 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i64:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i64 i64 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f64:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f64 f64 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_ptr:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_ptr{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_ptr ptr vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i8x8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i8x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i8x8 i8x8 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i16x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i16x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i16x4 i16x4 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i32x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i32x2 i32x2 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i64x1:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i64x1 i64x1 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f32x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f32x2 f32x2 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f64x1:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f64x1 f64x1 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i8x16:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i8x16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i8x16 i8x16 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i16x8:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i16x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i16x8 i16x8 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i32x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i32x4 i32x4 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_i64x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_i64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_i64x2 i64x2 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f32x4:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f32x4 f32x4 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: vreg_low16_f64x2:
|
||||
// CHECK-LABEL: {{("#)?}}vreg_low16_f64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s{{[0-9]+}}, s{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check!(vreg_low16_f64x2 f64x2 vreg_low16 "fmov" "s");
|
||||
|
||||
// CHECK-LABEL: x0_i8:
|
||||
// CHECK-LABEL: {{("#)?}}x0_i8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_i8 i8 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_i16:
|
||||
// CHECK-LABEL: {{("#)?}}x0_i16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_i16 i16 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_i32:
|
||||
// CHECK-LABEL: {{("#)?}}x0_i32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_i32 i32 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_f32:
|
||||
// CHECK-LABEL: {{("#)?}}x0_f32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_f32 f32 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_i64:
|
||||
// CHECK-LABEL: {{("#)?}}x0_i64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_i64 i64 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_f64:
|
||||
// CHECK-LABEL: {{("#)?}}x0_f64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_f64 f64 "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: x0_ptr:
|
||||
// CHECK-LABEL: {{("#)?}}x0_ptr{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: mov x{{[0-9]+}}, x{{[0-9]+}}
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(x0_ptr ptr "x0" "mov");
|
||||
|
||||
// CHECK-LABEL: v0_i8:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i8 i8 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i16:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i16 i16 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i32:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i32 i32 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f32:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f32{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_f32 f32 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i64:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i64 i64 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f64:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f64{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_f64 f64 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_ptr:
|
||||
// CHECK-LABEL: {{("#)?}}v0_ptr{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_ptr ptr "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i8x8:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i8x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i8x8 i8x8 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i16x4:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i16x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i16x4 i16x4 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i32x2:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i32x2 i32x2 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i64x1:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i64x1 i64x1 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f32x2:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f32x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_f32x2 f32x2 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f64x1:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f64x1{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_f64x1 f64x1 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i8x16:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i8x16{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i8x16 i8x16 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i16x8:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i16x8{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i16x8 i16x8 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i32x4:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i32x4 i32x4 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_i64x2:
|
||||
// CHECK-LABEL: {{("#)?}}v0_i64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_i64x2 i64x2 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f32x4:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f32x4{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
check_reg!(v0_f32x4 f32x4 "s0" "fmov");
|
||||
|
||||
// CHECK-LABEL: v0_f64x2:
|
||||
// CHECK-LABEL: {{("#)?}}v0_f64x2{{"?}}
|
||||
// CHECK: //APP
|
||||
// CHECK: fmov s0, s0
|
||||
// CHECK: //NO_APP
|
||||
|
|
|
|||
Loading…
Reference in New Issue