From a06ade1796f89f4ae1049b2361ceaa4d5cf0c33e Mon Sep 17 00:00:00 2001 From: pancake Date: Thu, 13 Oct 2022 21:21:34 +0200 Subject: [PATCH] Balance spacings in braces ##indent --- binr/r2r/run.c | 4 +- libr/anal/arch/arc/gnu/arc-opc.c | 70 +- libr/anal/arch/dalvik/opcode.h | 514 +- libr/anal/arch/ebc/ebc_disas.c | 2 +- libr/anal/arch/gb/gb_op_table.h | 540 +- libr/anal/arch/i4004/i4004.c | 334 +- libr/anal/arch/kvx/opc.sed | 0 libr/anal/arch/lm32/lm32_isa.h | 248 +- libr/anal/arch/mcs96/mcs96.h | 512 +- libr/anal/arch/snes/snes_op_table.h | 512 +- libr/anal/arch/v850/opc.inc | 18 +- libr/anal/arch/vax/vax.h | 642 +- libr/anal/arch/wasm/wasm.c | 6 +- libr/anal/arch/z80/z80_tab.h | 980 +-- libr/anal/op.c | 20 +- libr/anal/p/anal_8051.c | 60 +- libr/anal/p/anal_gb.c | 23 +- libr/anal/p/anal_sh.c | 2 +- libr/anal/p/anal_x86_cs.c | 2 +- libr/arch/archop.c | 20 +- libr/asm/arch/arm/aarch64/aarch64-opc-2.c | 388 +- libr/asm/arch/arm/aarch64/aarch64-opc.c | 64 +- libr/asm/arch/arm/aarch64/aarch64-tbl.h | 10 +- libr/asm/arch/arm/armass.c | 22 +- libr/asm/arch/arm/armass64.c | 8 +- libr/asm/arch/arm/gnu/arm-dis.c | 2661 ++++---- libr/asm/arch/avr/assemble.c | 6 +- libr/asm/arch/avr/avr_instructionset.c | 290 +- libr/asm/arch/cris/gnu/cris-opc.c | 630 +- libr/asm/arch/hppa/gnu/hppa-dis.c | 22 +- libr/asm/arch/m68k/gnu/m68k-dis.c | 30 +- libr/asm/arch/m68k/gnu/m68k-opc.c | 3766 +++++------ libr/asm/arch/mips/gnu/micromips-opc.c | 3074 ++++----- libr/asm/arch/mips/gnu/mips-opc.c | 5728 ++++++++-------- libr/asm/arch/mips/gnu/mips16-opc.c | 512 +- libr/asm/arch/nios/gnu/nios2-opc.c | 460 +- libr/asm/arch/pic/pic_midrange.c | 104 +- libr/asm/arch/pic/pic_pic18.c | 2 +- libr/asm/arch/ppc/gnu/ppc-dis.c | 2 +- libr/asm/arch/ppc/gnu/ppc-opc.c | 5768 ++++++++--------- libr/asm/arch/ppc/libps/libps.c | 126 +- libr/asm/arch/riscv/riscv-opc.c | 1086 ++-- libr/asm/arch/sh/gnu/sh-opc.h | 470 +- libr/asm/arch/tricore/gnu/tricore-opc.c | 2786 ++++---- libr/asm/p/asm_x86_nz.c | 718 +- libr/bin/format/pdb/main.c | 8 +- libr/bin/format/xnu/r_cf_dict.c | 30 +- libr/bin/p/bin_vsf.c | 212 +- libr/core/canal.c | 15 +- libr/core/cmd.c | 98 +- libr/core/cmd_debug.c | 2 +- libr/core/cmd_hash.c | 56 +- libr/core/cmd_help.c | 12 +- libr/core/disasm.c | 8 +- libr/core/linux_heap_glibc.c | 4 +- libr/core/linux_heap_jemalloc.c | 8 +- libr/core/p/core_java.c | 4 +- libr/core/rtr.c | 14 +- libr/core/vmenus.c | 2 +- libr/crypto/hash/hash.c | 6 +- libr/debug/dsession.c | 26 +- libr/egg/egg_cfile.c | 6 +- libr/egg/emit_arm.c | 2 +- libr/egg/emit_esil.c | 2 +- libr/fs/fs.c | 16 +- libr/fs/p/fs_r2.c | 12 +- .../heap/r_jemalloc/internal/witness.h | 2 +- libr/io/p/io_zip.c | 16 +- libr/magic/names.h | 100 +- libr/parse/p/parse_6502_pseudo.c | 92 +- libr/parse/p/parse_att2intel.c | 32 +- libr/parse/p/parse_avr_pseudo.c | 162 +- libr/parse/p/parse_dalvik_pseudo.c | 348 +- libr/parse/p/parse_m68k_pseudo.c | 2 +- libr/parse/p/parse_sh_pseudo.c | 210 +- libr/parse/p/parse_tms320_pseudo.c | 156 +- libr/parse/p/parse_v850_pseudo.c | 98 +- libr/parse/p/parse_z80_pseudo.c | 46 +- libr/syscall/d/par.sh | 2 +- libr/syscall/ioports.c | 120 +- libr/util/asn1_oids.h | 4702 +++++++------- libr/util/format.c | 8 +- libr/util/graph_drawable.c | 13 +- libr/util/print.c | 2 +- libr/util/print_code.c | 2 +- libr/util/protobuf.c | 2 +- libr/util/qrcode.c | 2 +- libr/util/regex/cclass.h | 24 +- libr/util/sstext.c | 432 +- libr/util/sys.c | 52 +- shlr/java/class.c | 56 +- sys/lint.sh | 3 + test/db/cmd/types | 8 +- 93 files changed, 20226 insertions(+), 20251 deletions(-) mode change 100755 => 100644 libr/anal/arch/kvx/opc.sed mode change 100755 => 100644 libr/syscall/d/par.sh diff --git a/binr/r2r/run.c b/binr/r2r/run.c index eb61fb4188..e4655fac60 100644 --- a/binr/r2r/run.c +++ b/binr/r2r/run.c @@ -995,7 +995,7 @@ R_API bool r2r_check_cmd_test(R2RProcessOutput *out, R2RCmdTest *test) { #define JQ_CMD "jq" R_API bool r2r_check_jq_available(void) { - const char *args[] = {"."}; + const char *args[] = { "." }; const char *invalid_json = "this is not json lol"; R2RSubprocess *proc = r2r_subprocess_start (JQ_CMD, args, 1, NULL, NULL, 0); if (!proc) { @@ -1038,7 +1038,7 @@ R_API bool r2r_check_json_test(R2RProcessOutput *out, R2RJsonTest *test) { if (!out || out->ret != 0 || !out->out || !out->err || out->timeout) { return false; } - const char *args[] = {"."}; + const char *args[] = { "." }; R2RSubprocess *proc = r2r_subprocess_start (JQ_CMD, args, 1, NULL, NULL, 0); r2r_subprocess_stdin_write (proc, (const ut8 *)out->out, strlen (out->out)); r2r_subprocess_wait (proc, UT64_MAX); diff --git a/libr/anal/arch/arc/gnu/arc-opc.c b/libr/anal/arch/arc/gnu/arc-opc.c index e1bfa58481..374f3658a7 100644 --- a/libr/anal/arch/arc/gnu/arc-opc.c +++ b/libr/anal/arch/arc/gnu/arc-opc.c @@ -4034,62 +4034,62 @@ static const struct arc_operand_value arc_reg_names_a700[] = { "memsubsys",0x67,AUXREG_AC, ARC_REGISTER_READONLY}, { "MEMSUBSYS",0x67,AUXREG_AC, ARC_REGISTER_READONLY}, /* Interrupt vector base register */ - {"vecbase_ac_build",0x68,AUXREG_AC, ARC_REGISTER_READONLY}, - {"VECBASE_AC_BUILD",0x68,AUXREG_AC, ARC_REGISTER_READONLY}, + { "vecbase_ac_build",0x68,AUXREG_AC, ARC_REGISTER_READONLY}, + { "VECBASE_AC_BUILD",0x68,AUXREG_AC, ARC_REGISTER_READONLY}, /* Peripheral base address register */ { "p_base_addr",0x69,AUXREG_AC, ARC_REGISTER_READONLY}, { "P_BASE_ADDR",0x69,AUXREG_AC, ARC_REGISTER_READONLY}, /* MMU BCR . Specifies the associativity of the TLB etc. */ - {"mmu_build",0x6F,AUXREG_AC, ARC_REGISTER_READONLY}, - {"MMU_BUILD",0x6F,AUXREG_AC, ARC_REGISTER_READONLY}, + { "mmu_build",0x6F,AUXREG_AC, ARC_REGISTER_READONLY}, + { "MMU_BUILD",0x6F,AUXREG_AC, ARC_REGISTER_READONLY}, /* ARC Angel BCR . Specifies the version of the ARC Angel Dev. Board */ { "arcangel_build",0x70,AUXREG_AC, ARC_REGISTER_READONLY}, { "ARCANGEL_BUILD",0x70,AUXREG_AC, ARC_REGISTER_READONLY}, /* Data Cache BCR . Associativity/Line Size/ size of the Data Cache etc. */ - {"dcache_build",0x72,AUXREG_AC, ARC_REGISTER_READONLY}, - {"DCACHE_BUILD",0x72,AUXREG_AC, ARC_REGISTER_READONLY}, + { "dcache_build",0x72,AUXREG_AC, ARC_REGISTER_READONLY}, + { "DCACHE_BUILD",0x72,AUXREG_AC, ARC_REGISTER_READONLY}, /* Information regarding multiple arc debug interfaces */ - {"madi_build",0x73,AUXREG_AC, ARC_REGISTER_READONLY}, - {"MADI_BUILD",0x73,AUXREG_AC, ARC_REGISTER_READONLY}, + { "madi_build",0x73,AUXREG_AC, ARC_REGISTER_READONLY}, + { "MADI_BUILD",0x73,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for data closely coupled memory */ - {"dccm_build",0x74,AUXREG_AC, ARC_REGISTER_READONLY}, - {"DCCM_BUILD",0x74,AUXREG_AC, ARC_REGISTER_READONLY}, + { "dccm_build",0x74,AUXREG_AC, ARC_REGISTER_READONLY}, + { "DCCM_BUILD",0x74,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for timers */ - {"timer_build",0x75,AUXREG_AC, ARC_REGISTER_READONLY}, - {"TIMER_BUILD",0x75,AUXREG_AC, ARC_REGISTER_READONLY}, + { "timer_build",0x75,AUXREG_AC, ARC_REGISTER_READONLY}, + { "TIMER_BUILD",0x75,AUXREG_AC, ARC_REGISTER_READONLY}, /* Actionpoints build */ - {"ap_build",0x76,AUXREG_AC, ARC_REGISTER_READONLY}, - {"AP_BUILD",0x76,AUXREG_AC, ARC_REGISTER_READONLY}, + { "ap_build",0x76,AUXREG_AC, ARC_REGISTER_READONLY}, + { "AP_BUILD",0x76,AUXREG_AC, ARC_REGISTER_READONLY}, /* Instruction Cache BCR */ - {"icache_build",0x77,AUXREG_AC, ARC_REGISTER_READONLY}, - {"ICACHE_BUILD",0x77,AUXREG_AC, ARC_REGISTER_READONLY}, + { "icache_build",0x77,AUXREG_AC, ARC_REGISTER_READONLY}, + { "ICACHE_BUILD",0x77,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for Instruction Closely Coupled Memory. Used to be BCR for Saturated ADD/SUB. */ - {"iccm_build",0x78,AUXREG_AC, ARC_REGISTER_READONLY}, - {"ICCM_BUILD",0x78,AUXREG_AC, ARC_REGISTER_READONLY}, + { "iccm_build",0x78,AUXREG_AC, ARC_REGISTER_READONLY}, + { "ICCM_BUILD",0x78,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for X/Y Memory */ - {"dspram_build",0x79,AUXREG_AC, ARC_REGISTER_READONLY}, - {"DSPRAM_BUILD",0x79,AUXREG_AC, ARC_REGISTER_READONLY}, + { "dspram_build",0x79,AUXREG_AC, ARC_REGISTER_READONLY}, + { "DSPRAM_BUILD",0x79,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for MAC / MUL */ - {"mac_build",0x7A,AUXREG_AC, ARC_REGISTER_READONLY}, - {"MAC_BUILD",0x7A,AUXREG_AC, ARC_REGISTER_READONLY}, + { "mac_build",0x7A,AUXREG_AC, ARC_REGISTER_READONLY}, + { "MAC_BUILD",0x7A,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for old 32 * 32 Multiply */ - {"multiply_build",0x7B,AUXREG_AC, ARC_REGISTER_READONLY}, - {"MULTIPLY_BUILD",0x7B,AUXREG_AC, ARC_REGISTER_READONLY}, + { "multiply_build",0x7B,AUXREG_AC, ARC_REGISTER_READONLY}, + { "MULTIPLY_BUILD",0x7B,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for swap */ - {"swap_build",0x7C,AUXREG_AC, ARC_REGISTER_READONLY}, - {"SWAP_BUILD",0x7C,AUXREG_AC, ARC_REGISTER_READONLY}, + { "swap_build",0x7C,AUXREG_AC, ARC_REGISTER_READONLY}, + { "SWAP_BUILD",0x7C,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR For Norm */ - {"norm_build",0x7D,AUXREG_AC, ARC_REGISTER_READONLY}, - {"NORM_BUILD",0x7D,AUXREG_AC, ARC_REGISTER_READONLY}, + { "norm_build",0x7D,AUXREG_AC, ARC_REGISTER_READONLY}, + { "NORM_BUILD",0x7D,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for Min / Max instructions */ - {"minmax_build",0x7E,AUXREG_AC, ARC_REGISTER_READONLY}, - {"MINMAX_BUILD",0x7E,AUXREG_AC, ARC_REGISTER_READONLY}, + { "minmax_build",0x7E,AUXREG_AC, ARC_REGISTER_READONLY}, + { "MINMAX_BUILD",0x7E,AUXREG_AC, ARC_REGISTER_READONLY}, /* BCR for barrel shifter */ - {"barrel_build",0x7F,AUXREG_AC, ARC_REGISTER_READONLY}, - {"BARREL_BUILD",0x7F,AUXREG_AC, ARC_REGISTER_READONLY} + { "barrel_build",0x7F,AUXREG_AC, ARC_REGISTER_READONLY}, + { "BARREL_BUILD",0x7F,AUXREG_AC, ARC_REGISTER_READONLY} }; @@ -4611,9 +4611,9 @@ ARC700_rtie_insn (arc_insn insn) ld/ldb/ldw r0, [gp, var@sda] 1 ldw.as r0, [gp, var@sda] 2 - ld_s r0, [gp, var@sda] 10 - ldb_ r0, [gp, var@sda] 11 - ldw_s r0, [gp, var@sda] 12 + ld_s r0, [gp, var@sda] 10 + ldb_ r0, [gp, var@sda] 11 + ldw_s r0, [gp, var@sda] 12 Any other insn -1 diff --git a/libr/anal/arch/dalvik/opcode.h b/libr/anal/arch/dalvik/opcode.h index ad1406eb07..f245f3cace 100644 --- a/libr/anal/arch/dalvik/opcode.h +++ b/libr/anal/arch/dalvik/opcode.h @@ -49,263 +49,263 @@ struct dalvik_opcodes_t { }; static const struct dalvik_opcodes_t dalvik_opcodes[256] = { - {"nop", 2, fmtop}, /* 0x00 */ - {"move", 2, fmtopvAvB}, - {"move/from16", 4, fmtopvAAvBBBB}, - {"move/16", 6, fmtopvAAAAvBBBB}, - {"move-wide", 2, fmtopvAvB}, - {"move-wide/from16", 4, fmtopvAAvBBBB}, - {"move-wide/16", 6, fmtopvAAAAvBBBB}, - {"move-object", 2, fmtopvAvB}, - {"move-object/from16", 4, fmtopvAAvBBBB}, - {"move-object/16", 6, fmtopvAAAAvBBBB}, - {"move-result", 2, fmtopvAA}, - {"move-result-wide", 2, fmtopvAA}, - {"move-result-object", 2, fmtopvAA}, - {"move-exception", 2, fmtopvAA}, - {"return-void", 2, fmtop}, - {"return", 2, fmtopvAA}, - {"return-wide", 2, fmtopvAA}, /* 0x10 */ - {"return-object", 2, fmtopvAA}, - {"const/4", 2, fmtopvAcB}, - {"const/16", 4, fmtopvAAcBBBB}, - {"const", 6, fmtopvAAcBBBBBBBB}, - {"const/high16", 4, fmtopvAAcBBBB0000}, - {"const-wide/16", 4, fmtopvAAcBBBB}, - {"const-wide/32", 6, fmtopvAAcBBBBBBBB}, - {"const-wide", 10, fmtopvAAcBBBBBBBBBBBBBBBB}, - {"const-wide/high16", 4, fmtopvAAcBBBB0000}, - {"const-string", 4, fmtopvAAtBBBB}, - {"const-string/jumbo", 6, fmtopvAAtBBBBBBBB}, - {"const-class", 4, fmtopvAAtBBBB}, - {"monitor-enter", 2, fmtopvAA}, - {"monitor-exit", 2, fmtopvAA}, - {"check-cast", 4, fmtopvAAtBBBB}, - {"instance-of", 4, fmtopvAvBtCCCC}, /* 0x20 */ - {"array-length", 2, fmtopvAvB}, - {"new-instance", 4, fmtopvAAtBBBB}, - {"new-array", 4, fmtopvAvBtCCCC}, - {"filled-new-array", 6, fmtopvXtBBBB}, - {"filled-new-array/range", 6, fmtopvCCCCmBBBB}, - {"fill-array-data", 6, fmtopvAApBBBBBBBB}, - {"throw", 2, fmtopvAA}, - {"goto", 2, fmtoppAA}, - {"goto/16", 4, fmtoppAAAA}, - {"goto/32", 6, fmtoppAAAAAAAA}, - {"packed-switch", 6, fmtopvAApBBBBBBBB}, - {"sparse-switch", 6, fmtopvAApBBBBBBBB}, - {"cmpl-float", 4, fmtopvAAvBBvCC}, - {"cmpg-float", 4, fmtopvAAvBBvCC}, - {"cmpl-double", 4, fmtopvAAvBBvCC}, - {"cmpg-double", 4, fmtopvAAvBBvCC}, /* 0x30 */ - {"cmp-long", 4, fmtopvAAvBBvCC}, - {"if-eq", 4, fmtopvAvBpCCCC}, - {"if-ne", 4, fmtopvAvBpCCCC}, - {"if-lt", 4, fmtopvAvBpCCCC}, - {"if-ge", 4, fmtopvAvBpCCCC}, - {"if-gt", 4, fmtopvAvBpCCCC}, - {"if-le", 4, fmtopvAvBpCCCC}, - {"if-eqz", 4, fmtopvAApBBBB}, - {"if-nez", 4, fmtopvAApBBBB}, - {"if-ltz", 4, fmtopvAApBBBB}, - {"if-gez", 4, fmtopvAApBBBB}, - {"if-gtz", 4, fmtopvAApBBBB}, - {"if-lez", 4, fmtopvAApBBBB}, - {"UNUSED", 2, fmt00}, - {"UNUSED", 2, fmt00}, - {"UNUSED", 2, fmt00}, /* 0x40 */ - {"UNUSED", 2, fmt00}, - {"UNUSED", 2, fmt00}, - {"UNUSED", 2, fmt00}, - {"aget", 4, fmtopvAAvBBvCC}, - {"aget-wide", 4, fmtopvAAvBBvCC}, - {"aget-object", 4, fmtopvAAvBBvCC}, - {"aget-boolean", 4, fmtopvAAvBBvCC}, - {"aget-byte", 4, fmtopvAAvBBvCC}, - {"aget-char", 4, fmtopvAAvBBvCC}, - {"aget-short", 4, fmtopvAAvBBvCC}, - {"aput", 4, fmtopvAAvBBvCC}, - {"aput-wide", 4, fmtopvAAvBBvCC}, - {"aput-object", 4, fmtopvAAvBBvCC}, - {"aput-boolean", 4, fmtopvAAvBBvCC}, - {"aput-byte", 4, fmtopvAAvBBvCC}, - {"aput-char", 4, fmtopvAAvBBvCC}, /* 0x50 */ - {"aput-short", 4, fmtopvAAvBBvCC}, - {"iget", 4, fmtopvAvBtCCCC}, - {"iget-wide", 4, fmtopvAvBtCCCC}, - {"iget-object", 4, fmtopvAvBtCCCC}, - {"iget-boolean", 4, fmtopvAvBtCCCC}, - {"iget-byte", 4, fmtopvAvBtCCCC}, - {"iget-char", 4, fmtopvAvBtCCCC}, - {"iget-short", 4, fmtopvAvBtCCCC}, - {"iput", 4, fmtopvAvBtCCCC}, - {"iput-wide", 4, fmtopvAvBtCCCC}, - {"iput-object", 4, fmtopvAvBtCCCC}, - {"iput-boolean", 4, fmtopvAvBtCCCC}, - {"iput-byte", 4, fmtopvAvBtCCCC}, - {"iput-char", 4, fmtopvAvBtCCCC}, - {"iput-short", 4, fmtopvAvBtCCCC}, - {"sget", 4, fmtopvAAtBBBB}, /* 0x60 */ - {"sget-wide", 4, fmtopvAAtBBBB}, - {"sget-object", 4, fmtopvAAtBBBB}, - {"sget-boolean", 4, fmtopvAAtBBBB}, - {"sget-byte", 4, fmtopvAAtBBBB}, - {"sget-char", 4, fmtopvAAtBBBB}, - {"sget-short", 4, fmtopvAAtBBBB}, - {"sput", 4, fmtopvAAtBBBB}, - {"sput-wide", 4, fmtopvAAtBBBB}, - {"sput-object", 4, fmtopvAAtBBBB}, - {"sput-boolean", 4, fmtopvAAtBBBB}, - {"sput-byte", 4, fmtopvAAtBBBB}, - {"sput-char", 4, fmtopvAAtBBBB}, - {"sput-short", 4, fmtopvAAtBBBB}, - {"invoke-virtual", 6, fmtopvXtBBBB}, - {"invoke-super", 6, fmtopvXtBBBB}, - {"invoke-direct", 6, fmtopvXtBBBB}, /* 0x70 */ - {"invoke-static", 6, fmtopvXtBBBB}, - {"invoke-interface", 6, fmtopvXtBBBB}, //XXX: Maybe use opt invoke-interface ?? - {"UNUSED", 2, fmt00}, - {"invoke-virtual/range", 6, fmtopvCCCCmBBBB}, - {"invoke-super/range", 6, fmtopvCCCCmBBBB}, - {"invoke-direct/range", 6, fmtopvCCCCmBBBB}, - {"invoke-static/range", 6, fmtopvCCCCmBBBB}, - {"invoke-interface/range", 6, fmtopvCCCCmBBBB}, - {"UNUSED", 2, fmt00}, - {"UNUSED", 2, fmt00}, - {"neg-int", 2, fmtopvAvB}, - {"not-int", 2, fmtopvAvB}, - {"neg-long", 2, fmtopvAvB}, - {"not-long", 2, fmtopvAvB}, - {"neg-float", 2, fmtopvAvB}, - {"neg-double", 2, fmtopvAvB}, /* 0x80 */ - {"int-to-long", 2, fmtopvAvB}, - {"int-to-float", 2, fmtopvAvB}, - {"int-to-double", 2, fmtopvAvB}, - {"long-to-int", 2, fmtopvAvB}, - {"long-to-float", 2, fmtopvAvB}, - {"long-to-double", 2, fmtopvAvB}, - {"float-to-int", 2, fmtopvAvB}, - {"float-to-long", 2, fmtopvAvB}, - {"float-to-double", 2, fmtopvAvB}, - {"double-to-int", 2, fmtopvAvB}, - {"double-to-long", 2, fmtopvAvB}, - {"double-to-float", 2, fmtopvAvB}, - {"int-to-byte", 2, fmtopvAvB}, - {"int-to-char", 2, fmtopvAvB}, - {"int-to-short", 2, fmtopvAvB}, - {"add-int", 4, fmtopvAAvBBvCC}, /* 0x90 */ - {"sub-int", 4, fmtopvAAvBBvCC}, - {"mul-int", 4, fmtopvAAvBBvCC}, - {"div-int", 4, fmtopvAAvBBvCC}, - {"rem-int", 4, fmtopvAAvBBvCC}, - {"and-int", 4, fmtopvAAvBBvCC}, - {"or-int", 4, fmtopvAAvBBvCC}, - {"xor-int", 4, fmtopvAAvBBvCC}, - {"shl-int", 4, fmtopvAAvBBvCC}, - {"shr-int", 4, fmtopvAAvBBvCC}, - {"ushr-int", 4, fmtopvAAvBBvCC}, - {"add-long", 4, fmtopvAAvBBvCC}, - {"sub-long", 4, fmtopvAAvBBvCC}, - {"mul-long", 4, fmtopvAAvBBvCC}, - {"div-long", 4, fmtopvAAvBBvCC}, - {"rem-long", 4, fmtopvAAvBBvCC}, - {"and-long", 4, fmtopvAAvBBvCC}, /* 0xa0 */ - {"or-long", 4, fmtopvAAvBBvCC}, - {"xor-long", 4, fmtopvAAvBBvCC}, - {"shl-long", 4, fmtopvAAvBBvCC}, - {"shr-long", 4, fmtopvAAvBBvCC}, - {"ushr-long", 4, fmtopvAAvBBvCC}, - {"add-float", 4, fmtopvAAvBBvCC}, - {"sub-float", 4, fmtopvAAvBBvCC}, - {"mul-float", 4, fmtopvAAvBBvCC}, - {"div-float", 4, fmtopvAAvBBvCC}, - {"rem-float", 4, fmtopvAAvBBvCC}, - {"add-double", 4, fmtopvAAvBBvCC}, - {"sub-double", 4, fmtopvAAvBBvCC}, - {"mul-double", 4, fmtopvAAvBBvCC}, - {"div-double", 4, fmtopvAAvBBvCC}, - {"rem-double", 4, fmtopvAAvBBvCC}, - {"add-int/2addr", 2, fmtopvAvB}, /* 0xb0 */ - {"sub-int/2addr", 2, fmtopvAvB}, - {"mul-int/2addr", 2, fmtopvAvB}, - {"div-int/2addr", 2, fmtopvAvB}, - {"rem-int/2addr", 2, fmtopvAvB}, - {"and-int/2addr", 2, fmtopvAvB}, - {"or-int/2addr", 2, fmtopvAvB}, - {"xor-int/2addr", 2, fmtopvAvB}, - {"shl-int/2addr", 2, fmtopvAvB}, - {"shr-int/2addr", 2, fmtopvAvB}, - {"ushr-int/2addr", 2, fmtopvAvB}, - {"add-long/2addr", 2, fmtopvAvB}, - {"sub-long/2addr", 2, fmtopvAvB}, - {"mul-long/2addr", 2, fmtopvAvB}, - {"div-long/2addr", 2, fmtopvAvB}, - {"rem-long/2addr", 2, fmtopvAvB}, - {"and-long/2addr", 2, fmtopvAvB}, /* 0xc0 */ - {"or-long/2addr", 2, fmtopvAvB}, - {"xor-long/2addr", 2, fmtopvAvB}, - {"shl-long/2addr", 2, fmtopvAvB}, - {"shr-long/2addr", 2, fmtopvAvB}, - {"ushr-long/2addr", 2, fmtopvAvB}, - {"add-float/2addr", 2, fmtopvAvB}, - {"sub-float/2addr", 2, fmtopvAvB}, - {"mul-float/2addr", 2, fmtopvAvB}, - {"div-float/2addr", 2, fmtopvAvB}, - {"rem-float/2addr", 2, fmtopvAvB}, - {"add-double/2addr", 2, fmtopvAvB}, - {"sub-double/2addr", 2, fmtopvAvB}, - {"mul-double/2addr", 2, fmtopvAvB}, - {"div-double/2addr", 2, fmtopvAvB}, - {"rem-double/2addr", 2, fmtopvAvB}, - {"add-int/lit16", 4, fmtopvAvBcCCCC}, /* 0xd0 */ - {"rsub-int", 4, fmtopvAvBcCCCC}, - {"mul-int/lit16", 4, fmtopvAvBcCCCC}, - {"div-int/lit16", 4, fmtopvAvBcCCCC}, - {"rem-int/lit16", 4, fmtopvAvBcCCCC}, - {"and-int/lit16", 4, fmtopvAvBcCCCC}, - {"or-int/lit16", 4, fmtopvAvBcCCCC}, - {"xor-int/lit16", 4, fmtopvAvBcCCCC}, - {"add-int/lit8", 4, fmtopvAAvBBcCC}, - {"rsub-int/lit8", 4, fmtopvAAvBBcCC}, - {"mul-int/lit8", 4, fmtopvAAvBBcCC}, - {"div-int/lit8", 4, fmtopvAAvBBcCC}, - {"rem-int/lit8", 4, fmtopvAAvBBcCC}, - {"and-int/lit8", 4, fmtopvAAvBBcCC}, - {"or-int/lit8", 4, fmtopvAAvBBcCC}, - {"xor-int/lit8", 4, fmtopvAAvBBcCC}, - {"shl-int/lit8", 4, fmtopvAAvBBcCC}, /* 0xe0 */ - {"shr-int/lit8", 4, fmtopvAAvBBcCC}, - {"ushr-int/lit8", 4, fmtopvAAvBBcCC}, - {"+iget-volatile", 4, fmtopvAvBtCCCC}, - {"+iput-volatile", 4, fmtopvAvBtCCCC}, - {"+sget-volatile", 4, fmtopvAvBtCCCC}, - {"+sput-volatile", 4, fmtopvAvBtCCCC}, - {"+iget-object-volatile", 4, fmtopvAvBtCCCC}, - {"+iget-wide-volatile", 4, fmtopvAvBtCCCC}, - {"+iput-wide-volatile", 4, fmtopvAvBtCCCC}, - {"+sget-wide-volatile", 4, fmtopvAvBtCCCC}, - {"+sput-wide-volatile", 4, fmtopvAvBtCCCC}, - {"^breakpoint", 4, fmtopvAvBtCCCC}, - {"^throw-verification-error", 4, fmtopAAtBBBB}, - {"+execute-inline", 6, fmtoptinlineI}, - {"+execute-inline/range", 6, fmtoptinlineIR}, - //{"+invoke-direct-empty", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range - {"+invoke-object-init-range", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range - {"return-void-barrier", 2, fmtop}, - {"+iget-quick", 4, fmtoptopvAvBoCCCC}, - {"+iget-wide-quick", 4, fmtoptopvAvBoCCCC}, - {"+iget-object-quick", 4, fmtoptopvAvBoCCCC}, - {"+iput-quick", 4, fmtoptopvAvBoCCCC}, - {"+iput-wide-quick", 4, fmtoptopvAvBoCCCC}, - {"+iput-object-quick", 4, fmtoptopvAvBoCCCC}, - {"+invoke-virtual-quick", 6, fmtoptinvokeVS}, - {"+invoke-virtual-quick/range", 6, fmtoptinvokeVSR}, - {"invoke-polymorphic", 8, fmtop45CC}, - {"invoke-polymorphic/range", 8, fmtop4RCC}, - {"invoke-custom", 6, fmtopvXtBBBB}, - {"invoke-custom/range", 6, fmtopvCCCCmBBBB}, - {"+sput-object-volatile", 4, fmtopvAAtBBBB}, - {"invalid", 2, fmtop} + { "nop", 2, fmtop}, /* 0x00 */ + { "move", 2, fmtopvAvB}, + { "move/from16", 4, fmtopvAAvBBBB}, + { "move/16", 6, fmtopvAAAAvBBBB}, + { "move-wide", 2, fmtopvAvB}, + { "move-wide/from16", 4, fmtopvAAvBBBB}, + { "move-wide/16", 6, fmtopvAAAAvBBBB}, + { "move-object", 2, fmtopvAvB}, + { "move-object/from16", 4, fmtopvAAvBBBB}, + { "move-object/16", 6, fmtopvAAAAvBBBB}, + { "move-result", 2, fmtopvAA}, + { "move-result-wide", 2, fmtopvAA}, + { "move-result-object", 2, fmtopvAA}, + { "move-exception", 2, fmtopvAA}, + { "return-void", 2, fmtop}, + { "return", 2, fmtopvAA}, + { "return-wide", 2, fmtopvAA}, /* 0x10 */ + { "return-object", 2, fmtopvAA}, + { "const/4", 2, fmtopvAcB}, + { "const/16", 4, fmtopvAAcBBBB}, + { "const", 6, fmtopvAAcBBBBBBBB}, + { "const/high16", 4, fmtopvAAcBBBB0000}, + { "const-wide/16", 4, fmtopvAAcBBBB}, + { "const-wide/32", 6, fmtopvAAcBBBBBBBB}, + { "const-wide", 10, fmtopvAAcBBBBBBBBBBBBBBBB}, + { "const-wide/high16", 4, fmtopvAAcBBBB0000}, + { "const-string", 4, fmtopvAAtBBBB}, + { "const-string/jumbo", 6, fmtopvAAtBBBBBBBB}, + { "const-class", 4, fmtopvAAtBBBB}, + { "monitor-enter", 2, fmtopvAA}, + { "monitor-exit", 2, fmtopvAA}, + { "check-cast", 4, fmtopvAAtBBBB}, + { "instance-of", 4, fmtopvAvBtCCCC}, /* 0x20 */ + { "array-length", 2, fmtopvAvB}, + { "new-instance", 4, fmtopvAAtBBBB}, + { "new-array", 4, fmtopvAvBtCCCC}, + { "filled-new-array", 6, fmtopvXtBBBB}, + { "filled-new-array/range", 6, fmtopvCCCCmBBBB}, + { "fill-array-data", 6, fmtopvAApBBBBBBBB}, + { "throw", 2, fmtopvAA}, + { "goto", 2, fmtoppAA}, + { "goto/16", 4, fmtoppAAAA}, + { "goto/32", 6, fmtoppAAAAAAAA}, + { "packed-switch", 6, fmtopvAApBBBBBBBB}, + { "sparse-switch", 6, fmtopvAApBBBBBBBB}, + { "cmpl-float", 4, fmtopvAAvBBvCC}, + { "cmpg-float", 4, fmtopvAAvBBvCC}, + { "cmpl-double", 4, fmtopvAAvBBvCC}, + { "cmpg-double", 4, fmtopvAAvBBvCC}, /* 0x30 */ + { "cmp-long", 4, fmtopvAAvBBvCC}, + { "if-eq", 4, fmtopvAvBpCCCC}, + { "if-ne", 4, fmtopvAvBpCCCC}, + { "if-lt", 4, fmtopvAvBpCCCC}, + { "if-ge", 4, fmtopvAvBpCCCC}, + { "if-gt", 4, fmtopvAvBpCCCC}, + { "if-le", 4, fmtopvAvBpCCCC}, + { "if-eqz", 4, fmtopvAApBBBB}, + { "if-nez", 4, fmtopvAApBBBB}, + { "if-ltz", 4, fmtopvAApBBBB}, + { "if-gez", 4, fmtopvAApBBBB}, + { "if-gtz", 4, fmtopvAApBBBB}, + { "if-lez", 4, fmtopvAApBBBB}, + { "UNUSED", 2, fmt00}, + { "UNUSED", 2, fmt00}, + { "UNUSED", 2, fmt00}, /* 0x40 */ + { "UNUSED", 2, fmt00}, + { "UNUSED", 2, fmt00}, + { "UNUSED", 2, fmt00}, + { "aget", 4, fmtopvAAvBBvCC}, + { "aget-wide", 4, fmtopvAAvBBvCC}, + { "aget-object", 4, fmtopvAAvBBvCC}, + { "aget-boolean", 4, fmtopvAAvBBvCC}, + { "aget-byte", 4, fmtopvAAvBBvCC}, + { "aget-char", 4, fmtopvAAvBBvCC}, + { "aget-short", 4, fmtopvAAvBBvCC}, + { "aput", 4, fmtopvAAvBBvCC}, + { "aput-wide", 4, fmtopvAAvBBvCC}, + { "aput-object", 4, fmtopvAAvBBvCC}, + { "aput-boolean", 4, fmtopvAAvBBvCC}, + { "aput-byte", 4, fmtopvAAvBBvCC}, + { "aput-char", 4, fmtopvAAvBBvCC}, /* 0x50 */ + { "aput-short", 4, fmtopvAAvBBvCC}, + { "iget", 4, fmtopvAvBtCCCC}, + { "iget-wide", 4, fmtopvAvBtCCCC}, + { "iget-object", 4, fmtopvAvBtCCCC}, + { "iget-boolean", 4, fmtopvAvBtCCCC}, + { "iget-byte", 4, fmtopvAvBtCCCC}, + { "iget-char", 4, fmtopvAvBtCCCC}, + { "iget-short", 4, fmtopvAvBtCCCC}, + { "iput", 4, fmtopvAvBtCCCC}, + { "iput-wide", 4, fmtopvAvBtCCCC}, + { "iput-object", 4, fmtopvAvBtCCCC}, + { "iput-boolean", 4, fmtopvAvBtCCCC}, + { "iput-byte", 4, fmtopvAvBtCCCC}, + { "iput-char", 4, fmtopvAvBtCCCC}, + { "iput-short", 4, fmtopvAvBtCCCC}, + { "sget", 4, fmtopvAAtBBBB}, /* 0x60 */ + { "sget-wide", 4, fmtopvAAtBBBB}, + { "sget-object", 4, fmtopvAAtBBBB}, + { "sget-boolean", 4, fmtopvAAtBBBB}, + { "sget-byte", 4, fmtopvAAtBBBB}, + { "sget-char", 4, fmtopvAAtBBBB}, + { "sget-short", 4, fmtopvAAtBBBB}, + { "sput", 4, fmtopvAAtBBBB}, + { "sput-wide", 4, fmtopvAAtBBBB}, + { "sput-object", 4, fmtopvAAtBBBB}, + { "sput-boolean", 4, fmtopvAAtBBBB}, + { "sput-byte", 4, fmtopvAAtBBBB}, + { "sput-char", 4, fmtopvAAtBBBB}, + { "sput-short", 4, fmtopvAAtBBBB}, + { "invoke-virtual", 6, fmtopvXtBBBB}, + { "invoke-super", 6, fmtopvXtBBBB}, + { "invoke-direct", 6, fmtopvXtBBBB}, /* 0x70 */ + { "invoke-static", 6, fmtopvXtBBBB}, + { "invoke-interface", 6, fmtopvXtBBBB}, //XXX: Maybe use opt invoke-interface ?? + { "UNUSED", 2, fmt00}, + { "invoke-virtual/range", 6, fmtopvCCCCmBBBB}, + { "invoke-super/range", 6, fmtopvCCCCmBBBB}, + { "invoke-direct/range", 6, fmtopvCCCCmBBBB}, + { "invoke-static/range", 6, fmtopvCCCCmBBBB}, + { "invoke-interface/range", 6, fmtopvCCCCmBBBB}, + { "UNUSED", 2, fmt00}, + { "UNUSED", 2, fmt00}, + { "neg-int", 2, fmtopvAvB}, + { "not-int", 2, fmtopvAvB}, + { "neg-long", 2, fmtopvAvB}, + { "not-long", 2, fmtopvAvB}, + { "neg-float", 2, fmtopvAvB}, + { "neg-double", 2, fmtopvAvB}, /* 0x80 */ + { "int-to-long", 2, fmtopvAvB}, + { "int-to-float", 2, fmtopvAvB}, + { "int-to-double", 2, fmtopvAvB}, + { "long-to-int", 2, fmtopvAvB}, + { "long-to-float", 2, fmtopvAvB}, + { "long-to-double", 2, fmtopvAvB}, + { "float-to-int", 2, fmtopvAvB}, + { "float-to-long", 2, fmtopvAvB}, + { "float-to-double", 2, fmtopvAvB}, + { "double-to-int", 2, fmtopvAvB}, + { "double-to-long", 2, fmtopvAvB}, + { "double-to-float", 2, fmtopvAvB}, + { "int-to-byte", 2, fmtopvAvB}, + { "int-to-char", 2, fmtopvAvB}, + { "int-to-short", 2, fmtopvAvB}, + { "add-int", 4, fmtopvAAvBBvCC}, /* 0x90 */ + { "sub-int", 4, fmtopvAAvBBvCC}, + { "mul-int", 4, fmtopvAAvBBvCC}, + { "div-int", 4, fmtopvAAvBBvCC}, + { "rem-int", 4, fmtopvAAvBBvCC}, + { "and-int", 4, fmtopvAAvBBvCC}, + { "or-int", 4, fmtopvAAvBBvCC}, + { "xor-int", 4, fmtopvAAvBBvCC}, + { "shl-int", 4, fmtopvAAvBBvCC}, + { "shr-int", 4, fmtopvAAvBBvCC}, + { "ushr-int", 4, fmtopvAAvBBvCC}, + { "add-long", 4, fmtopvAAvBBvCC}, + { "sub-long", 4, fmtopvAAvBBvCC}, + { "mul-long", 4, fmtopvAAvBBvCC}, + { "div-long", 4, fmtopvAAvBBvCC}, + { "rem-long", 4, fmtopvAAvBBvCC}, + { "and-long", 4, fmtopvAAvBBvCC}, /* 0xa0 */ + { "or-long", 4, fmtopvAAvBBvCC}, + { "xor-long", 4, fmtopvAAvBBvCC}, + { "shl-long", 4, fmtopvAAvBBvCC}, + { "shr-long", 4, fmtopvAAvBBvCC}, + { "ushr-long", 4, fmtopvAAvBBvCC}, + { "add-float", 4, fmtopvAAvBBvCC}, + { "sub-float", 4, fmtopvAAvBBvCC}, + { "mul-float", 4, fmtopvAAvBBvCC}, + { "div-float", 4, fmtopvAAvBBvCC}, + { "rem-float", 4, fmtopvAAvBBvCC}, + { "add-double", 4, fmtopvAAvBBvCC}, + { "sub-double", 4, fmtopvAAvBBvCC}, + { "mul-double", 4, fmtopvAAvBBvCC}, + { "div-double", 4, fmtopvAAvBBvCC}, + { "rem-double", 4, fmtopvAAvBBvCC}, + { "add-int/2addr", 2, fmtopvAvB}, /* 0xb0 */ + { "sub-int/2addr", 2, fmtopvAvB}, + { "mul-int/2addr", 2, fmtopvAvB}, + { "div-int/2addr", 2, fmtopvAvB}, + { "rem-int/2addr", 2, fmtopvAvB}, + { "and-int/2addr", 2, fmtopvAvB}, + { "or-int/2addr", 2, fmtopvAvB}, + { "xor-int/2addr", 2, fmtopvAvB}, + { "shl-int/2addr", 2, fmtopvAvB}, + { "shr-int/2addr", 2, fmtopvAvB}, + { "ushr-int/2addr", 2, fmtopvAvB}, + { "add-long/2addr", 2, fmtopvAvB}, + { "sub-long/2addr", 2, fmtopvAvB}, + { "mul-long/2addr", 2, fmtopvAvB}, + { "div-long/2addr", 2, fmtopvAvB}, + { "rem-long/2addr", 2, fmtopvAvB}, + { "and-long/2addr", 2, fmtopvAvB}, /* 0xc0 */ + { "or-long/2addr", 2, fmtopvAvB}, + { "xor-long/2addr", 2, fmtopvAvB}, + { "shl-long/2addr", 2, fmtopvAvB}, + { "shr-long/2addr", 2, fmtopvAvB}, + { "ushr-long/2addr", 2, fmtopvAvB}, + { "add-float/2addr", 2, fmtopvAvB}, + { "sub-float/2addr", 2, fmtopvAvB}, + { "mul-float/2addr", 2, fmtopvAvB}, + { "div-float/2addr", 2, fmtopvAvB}, + { "rem-float/2addr", 2, fmtopvAvB}, + { "add-double/2addr", 2, fmtopvAvB}, + { "sub-double/2addr", 2, fmtopvAvB}, + { "mul-double/2addr", 2, fmtopvAvB}, + { "div-double/2addr", 2, fmtopvAvB}, + { "rem-double/2addr", 2, fmtopvAvB}, + { "add-int/lit16", 4, fmtopvAvBcCCCC}, /* 0xd0 */ + { "rsub-int", 4, fmtopvAvBcCCCC}, + { "mul-int/lit16", 4, fmtopvAvBcCCCC}, + { "div-int/lit16", 4, fmtopvAvBcCCCC}, + { "rem-int/lit16", 4, fmtopvAvBcCCCC}, + { "and-int/lit16", 4, fmtopvAvBcCCCC}, + { "or-int/lit16", 4, fmtopvAvBcCCCC}, + { "xor-int/lit16", 4, fmtopvAvBcCCCC}, + { "add-int/lit8", 4, fmtopvAAvBBcCC}, + { "rsub-int/lit8", 4, fmtopvAAvBBcCC}, + { "mul-int/lit8", 4, fmtopvAAvBBcCC}, + { "div-int/lit8", 4, fmtopvAAvBBcCC}, + { "rem-int/lit8", 4, fmtopvAAvBBcCC}, + { "and-int/lit8", 4, fmtopvAAvBBcCC}, + { "or-int/lit8", 4, fmtopvAAvBBcCC}, + { "xor-int/lit8", 4, fmtopvAAvBBcCC}, + { "shl-int/lit8", 4, fmtopvAAvBBcCC}, /* 0xe0 */ + { "shr-int/lit8", 4, fmtopvAAvBBcCC}, + { "ushr-int/lit8", 4, fmtopvAAvBBcCC}, + { "+iget-volatile", 4, fmtopvAvBtCCCC}, + { "+iput-volatile", 4, fmtopvAvBtCCCC}, + { "+sget-volatile", 4, fmtopvAvBtCCCC}, + { "+sput-volatile", 4, fmtopvAvBtCCCC}, + { "+iget-object-volatile", 4, fmtopvAvBtCCCC}, + { "+iget-wide-volatile", 4, fmtopvAvBtCCCC}, + { "+iput-wide-volatile", 4, fmtopvAvBtCCCC}, + { "+sget-wide-volatile", 4, fmtopvAvBtCCCC}, + { "+sput-wide-volatile", 4, fmtopvAvBtCCCC}, + { "^breakpoint", 4, fmtopvAvBtCCCC}, + { "^throw-verification-error", 4, fmtopAAtBBBB}, + { "+execute-inline", 6, fmtoptinlineI}, + { "+execute-inline/range", 6, fmtoptinlineIR}, + //{ "+invoke-direct-empty", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range + { "+invoke-object-init-range", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range + { "return-void-barrier", 2, fmtop}, + { "+iget-quick", 4, fmtoptopvAvBoCCCC}, + { "+iget-wide-quick", 4, fmtoptopvAvBoCCCC}, + { "+iget-object-quick", 4, fmtoptopvAvBoCCCC}, + { "+iput-quick", 4, fmtoptopvAvBoCCCC}, + { "+iput-wide-quick", 4, fmtoptopvAvBoCCCC}, + { "+iput-object-quick", 4, fmtoptopvAvBoCCCC}, + { "+invoke-virtual-quick", 6, fmtoptinvokeVS}, + { "+invoke-virtual-quick/range", 6, fmtoptinvokeVSR}, + { "invoke-polymorphic", 8, fmtop45CC}, + { "invoke-polymorphic/range", 8, fmtop4RCC}, + { "invoke-custom", 6, fmtopvXtBBBB}, + { "invoke-custom/range", 6, fmtopvCCCCmBBBB}, + { "+sput-object-volatile", 4, fmtopvAAtBBBB}, + { "invalid", 2, fmtop} }; #endif diff --git a/libr/anal/arch/ebc/ebc_disas.c b/libr/anal/arch/ebc/ebc_disas.c index ce78148d9f..178d7e82e0 100644 --- a/libr/anal/arch/ebc/ebc_disas.c +++ b/libr/anal/arch/ebc/ebc_disas.c @@ -632,7 +632,7 @@ static int decode_cmpi(const ut8 *bytes, ebc_command_t *cmd) { char op1c[32]; char indx[32] = {0}; char immed[32] = {0}; - char *suff[] = {"eq", "lte", "gte", "ulte", "ugte"}; + char *suff[] = { "eq", "lte", "gte", "ulte", "ugte" }; snprintf (op1c, sizeof (op1c)-1, "%sr%u", TEST_BIT(bytes[1], 3) ? "@" : "", op1); diff --git a/libr/anal/arch/gb/gb_op_table.h b/libr/anal/arch/gb/gb_op_table.h index 63239be41b..f6ddc0f3fe 100644 --- a/libr/anal/arch/gb/gb_op_table.h +++ b/libr/anal/arch/gb/gb_op_table.h @@ -1,294 +1,294 @@ -/* radare - LGPL - Copyright 2013 - 2014 - condret@runas-racer.com */ +/* radare - LGPL - Copyright 2013-2022 - condret */ -#define GB_8BIT 1 -#define GB_16BIT 2 -#define ARG_8 4 -#define ARG_16 8 -#define GB_IO 16 // Most io (Joypad, Sound, Screen ...) +#define GB_8BIT 1 +#define GB_16BIT 2 +#define ARG_8 4 +#define ARG_16 8 +#define GB_IO 16 // Most io (Joypad, Sound, Screen ...) - -typedef struct{ +typedef struct { const char *name; const int type; } gb_opcode; -static const char *cb_ops[]={ "rlc","rrc","rl","rr","sla","sra","swap","srl", - "bit 0,","bit 1,","bit 2,","bit 3,","bit 4,","bit 5,","bit 6,","bit 7,", - "res 0,","res 1,","res 2,","res 3,","res 4,","res 5,","res 6,","res 7,", - "set 0,","set 1,","set 2,","set 3,","set 4,","set 5,","set 6,","set 7,"}; +static const char *cb_ops[] = { + "rlc", "rrc", "rl", "rr", "sla", "sra", "swap", "srl", + "bit 0,", "bit 1,", "bit 2,", "bit 3,", "bit 4,", "bit 5,", "bit 6,", "bit 7,", + "res 0,", "res 1,", "res 2,", "res 3,", "res 4,", "res 5,", "res 6,", "res 7,", + "set 0,", "set 1,", "set 2,", "set 3,", "set 4,", "set 5,", "set 6,", "set 7," +}; -static const char *cb_regs[]={ "b","c","d","e","h","l","[hl]","a"}; +static const char *cb_regs[]= { "b", "c", "d", "e", "h", "l", "[hl]", "a" }; static gb_opcode gb_op[] = { - {"nop" ,GB_8BIT}, //0x00 - {"ld bc, 0x%04x" ,GB_8BIT+ARG_16}, - {"ld [bc], a" ,GB_8BIT}, - {"inc bc" ,GB_8BIT}, - {"inc b" ,GB_8BIT}, - {"dec b" ,GB_8BIT}, - {"ld b, 0x%02x" ,GB_8BIT+ARG_8}, - {"rlca" ,GB_8BIT}, - {"ld [0x%04x], sp" ,GB_8BIT+ARG_16}, //word or byte? - {"add hl, bc" ,GB_8BIT}, - {"ld a, [bc]" ,GB_8BIT}, - {"dec bc" ,GB_8BIT}, - {"inc c" ,GB_8BIT}, - {"dec c" ,GB_8BIT}, - {"ld c, 0x%02x" ,GB_8BIT+ARG_8}, - {"rrca" ,GB_8BIT}, + { "nop", GB_8BIT }, //0x00 + { "ld bc, 0x%04x", GB_8BIT + ARG_16}, + { "ld [bc], a", GB_8BIT }, + { "inc bc", GB_8BIT }, + { "inc b", GB_8BIT }, + { "dec b", GB_8BIT }, + { "ld b, 0x%02x", GB_8BIT + ARG_8 }, + { "rlca", GB_8BIT }, + { "ld [0x%04x], sp", GB_8BIT + ARG_16}, //word or byte? + { "add hl, bc", GB_8BIT }, + { "ld a, [bc]", GB_8BIT }, + { "dec bc", GB_8BIT }, + { "inc c", GB_8BIT }, + { "dec c", GB_8BIT }, + { "ld c, 0x%02x", GB_8BIT + ARG_8 }, + { "rrca", GB_8BIT }, + { "stop", GB_8BIT }, //0x10 + { "ld de, 0x%04x" ,GB_8BIT+ARG_16}, + { "ld [de], a" ,GB_8BIT }, + { "inc de", GB_8BIT }, + { "inc d", GB_8BIT }, + { "dec d", GB_8BIT }, + { "ld d, 0x%02x" ,GB_8BIT+ARG_8 }, + { "rla", GB_8BIT }, + { "jr 0x%02x", GB_8BIT+ARG_8 }, //signed + { "add hl, de" ,GB_8BIT }, + { "ld a, [de]" ,GB_8BIT }, + { "dec de", GB_8BIT }, + { "inc e", GB_8BIT }, + { "dec e", GB_8BIT }, + { "ld e, 0x%02x" ,GB_8BIT+ARG_8 }, + { "rra", GB_8BIT }, - {"stop" ,GB_8BIT}, //0x10 - {"ld de, 0x%04x" ,GB_8BIT+ARG_16}, - {"ld [de], a" ,GB_8BIT}, - {"inc de" ,GB_8BIT}, - {"inc d" ,GB_8BIT}, - {"dec d" ,GB_8BIT}, - {"ld d, 0x%02x" ,GB_8BIT+ARG_8}, - {"rla" ,GB_8BIT}, - {"jr 0x%02x" ,GB_8BIT+ARG_8}, //signed - {"add hl, de" ,GB_8BIT}, - {"ld a, [de]" ,GB_8BIT}, - {"dec de" ,GB_8BIT}, - {"inc e" ,GB_8BIT}, - {"dec e" ,GB_8BIT}, - {"ld e, 0x%02x" ,GB_8BIT+ARG_8}, - {"rra" ,GB_8BIT}, + { "jr nZ, 0x%02x" ,GB_8BIT+ARG_8 }, //0x20 //signed + { "ld hl, 0x%04x" ,GB_8BIT+ARG_16}, + { "ldi [hl], a" ,GB_8BIT }, + { "inc hl", GB_8BIT }, + { "inc h", GB_8BIT }, + { "dec h", GB_8BIT }, + { "ld h, 0x%02x" ,GB_8BIT+ARG_8 }, + { "daa", GB_8BIT }, + { "jr Z, 0x%02x" ,GB_8BIT+ARG_8 }, //signed + { "add hl, hl" ,GB_8BIT }, + { "ldi a, [hl]" ,GB_8BIT }, + { "dec hl", GB_8BIT }, + { "inc l", GB_8BIT }, + { "dec l", GB_8BIT }, + { "ld l, 0x%02x" ,GB_8BIT+ARG_8 }, + { "cpl", GB_8BIT }, - {"jr nZ, 0x%02x" ,GB_8BIT+ARG_8}, //0x20 //signed - {"ld hl, 0x%04x" ,GB_8BIT+ARG_16}, - {"ldi [hl], a" ,GB_8BIT}, - {"inc hl" ,GB_8BIT}, - {"inc h" ,GB_8BIT}, - {"dec h" ,GB_8BIT}, - {"ld h, 0x%02x" ,GB_8BIT+ARG_8}, - {"daa" ,GB_8BIT}, - {"jr Z, 0x%02x" ,GB_8BIT+ARG_8}, //signed - {"add hl, hl" ,GB_8BIT}, - {"ldi a, [hl]" ,GB_8BIT}, - {"dec hl" ,GB_8BIT}, - {"inc l" ,GB_8BIT}, - {"dec l" ,GB_8BIT}, - {"ld l, 0x%02x" ,GB_8BIT+ARG_8}, - {"cpl" ,GB_8BIT}, + { "jr nC, 0x%02x" ,GB_8BIT+ARG_8 }, //0x30 //signed + { "ld sp, 0x%04x" ,GB_8BIT+ARG_16}, + { "ldd [hl], a" ,GB_8BIT }, + { "inc sp", GB_8BIT }, + { "inc [hl]", GB_8BIT }, + { "dec [hl]", GB_8BIT }, + { "ld [hl], 0x%02x" ,GB_8BIT+ARG_8 }, + { "scf", GB_8BIT }, + { "jr C, 0x%02x" ,GB_8BIT+ARG_8 }, //signed + { "add hl, sp" ,GB_8BIT }, + { "ldd a, [hl]" ,GB_8BIT }, + { "dec sp", GB_8BIT }, + { "inc a", GB_8BIT }, + { "dec a", GB_8BIT }, + { "ld a, 0x%02x" ,GB_8BIT+ARG_8 }, + { "ccf", GB_8BIT }, - {"jr nC, 0x%02x" ,GB_8BIT+ARG_8}, //0x30 //signed - {"ld sp, 0x%04x" ,GB_8BIT+ARG_16}, - {"ldd [hl], a" ,GB_8BIT}, - {"inc sp" ,GB_8BIT}, - {"inc [hl]" ,GB_8BIT}, - {"dec [hl]" ,GB_8BIT}, - {"ld [hl], 0x%02x" ,GB_8BIT+ARG_8}, - {"scf" ,GB_8BIT}, - {"jr C, 0x%02x" ,GB_8BIT+ARG_8}, //signed - {"add hl, sp" ,GB_8BIT}, - {"ldd a, [hl]" ,GB_8BIT}, - {"dec sp" ,GB_8BIT}, - {"inc a" ,GB_8BIT}, - {"dec a" ,GB_8BIT}, - {"ld a, 0x%02x" ,GB_8BIT+ARG_8}, - {"ccf" ,GB_8BIT}, + { "ld b, b" ,GB_8BIT }, //0x40 + { "ld b, c" ,GB_8BIT }, + { "ld b, d" ,GB_8BIT }, + { "ld b, e" ,GB_8BIT }, + { "ld b, h" ,GB_8BIT }, + { "ld b, l" ,GB_8BIT }, + { "ld b, [hl]" ,GB_8BIT }, + { "ld b, a" ,GB_8BIT }, + { "ld c, b" ,GB_8BIT }, + { "ld c, c" ,GB_8BIT }, + { "ld c, d" ,GB_8BIT }, + { "ld c, e" ,GB_8BIT }, + { "ld c, h" ,GB_8BIT }, + { "ld c, l" ,GB_8BIT }, + { "ld c, [hl]" ,GB_8BIT }, + { "ld c, a" ,GB_8BIT }, - {"ld b, b" ,GB_8BIT}, //0x40 - {"ld b, c" ,GB_8BIT}, - {"ld b, d" ,GB_8BIT}, - {"ld b, e" ,GB_8BIT}, - {"ld b, h" ,GB_8BIT}, - {"ld b, l" ,GB_8BIT}, - {"ld b, [hl]" ,GB_8BIT}, - {"ld b, a" ,GB_8BIT}, - {"ld c, b" ,GB_8BIT}, - {"ld c, c" ,GB_8BIT}, - {"ld c, d" ,GB_8BIT}, - {"ld c, e" ,GB_8BIT}, - {"ld c, h" ,GB_8BIT}, - {"ld c, l" ,GB_8BIT}, - {"ld c, [hl]" ,GB_8BIT}, - {"ld c, a" ,GB_8BIT}, + { "ld d, b" ,GB_8BIT }, //0x50 + { "ld d, c" ,GB_8BIT }, + { "ld d, d" ,GB_8BIT }, + { "ld d, e" ,GB_8BIT }, + { "ld d, h" ,GB_8BIT }, + { "ld d, l" ,GB_8BIT }, + { "ld d, [hl]" ,GB_8BIT }, + { "ld d, a" ,GB_8BIT }, + { "ld e, b" ,GB_8BIT }, + { "ld e, c" ,GB_8BIT }, + { "ld e, d" ,GB_8BIT }, + { "ld e, e" ,GB_8BIT }, + { "ld e, h" ,GB_8BIT }, + { "ld e, l" ,GB_8BIT }, + { "ld e, [hl]" ,GB_8BIT }, + { "ld e, a" ,GB_8BIT }, - {"ld d, b" ,GB_8BIT}, //0x50 - {"ld d, c" ,GB_8BIT}, - {"ld d, d" ,GB_8BIT}, - {"ld d, e" ,GB_8BIT}, - {"ld d, h" ,GB_8BIT}, - {"ld d, l" ,GB_8BIT}, - {"ld d, [hl]" ,GB_8BIT}, - {"ld d, a" ,GB_8BIT}, - {"ld e, b" ,GB_8BIT}, - {"ld e, c" ,GB_8BIT}, - {"ld e, d" ,GB_8BIT}, - {"ld e, e" ,GB_8BIT}, - {"ld e, h" ,GB_8BIT}, - {"ld e, l" ,GB_8BIT}, - {"ld e, [hl]" ,GB_8BIT}, - {"ld e, a" ,GB_8BIT}, + { "ld h, b" ,GB_8BIT }, //0x60 + { "ld h, c" ,GB_8BIT }, + { "ld h, d" ,GB_8BIT }, + { "ld h, e" ,GB_8BIT }, + { "ld h, h" ,GB_8BIT }, + { "ld h, l" ,GB_8BIT }, + { "ld h, [hl]" ,GB_8BIT }, + { "ld h, a" ,GB_8BIT }, + { "ld l, b" ,GB_8BIT }, + { "ld l, c" ,GB_8BIT }, + { "ld l, d" ,GB_8BIT }, + { "ld l, e" ,GB_8BIT }, + { "ld l, h" ,GB_8BIT }, + { "ld l, l" ,GB_8BIT }, + { "ld l, [hl]" ,GB_8BIT }, + { "ld l, a" ,GB_8BIT }, - {"ld h, b" ,GB_8BIT}, //0x60 - {"ld h, c" ,GB_8BIT}, - {"ld h, d" ,GB_8BIT}, - {"ld h, e" ,GB_8BIT}, - {"ld h, h" ,GB_8BIT}, - {"ld h, l" ,GB_8BIT}, - {"ld h, [hl]" ,GB_8BIT}, - {"ld h, a" ,GB_8BIT}, - {"ld l, b" ,GB_8BIT}, - {"ld l, c" ,GB_8BIT}, - {"ld l, d" ,GB_8BIT}, - {"ld l, e" ,GB_8BIT}, - {"ld l, h" ,GB_8BIT}, - {"ld l, l" ,GB_8BIT}, - {"ld l, [hl]" ,GB_8BIT}, - {"ld l, a" ,GB_8BIT}, + { "ld [hl], b" ,GB_8BIT },//0X70 + { "ld [hl], c" ,GB_8BIT }, + { "ld [hl], d" ,GB_8BIT }, + { "ld [hl], e" ,GB_8BIT }, + { "ld [hl], h" ,GB_8BIT }, + { "ld [hl], l" ,GB_8BIT }, + { "halt", GB_8BIT }, + { "ld [hl], a" ,GB_8BIT }, + { "ld a, b" ,GB_8BIT }, + { "ld a, c" ,GB_8BIT }, + { "ld a, d" ,GB_8BIT }, + { "ld a, e" ,GB_8BIT }, + { "ld a, h" ,GB_8BIT }, + { "ld a, l" ,GB_8BIT }, + { "ld a, [hl]" ,GB_8BIT }, + { "ld a, a" ,GB_8BIT }, - {"ld [hl], b" ,GB_8BIT}, //0X70 - {"ld [hl], c" ,GB_8BIT}, - {"ld [hl], d" ,GB_8BIT}, - {"ld [hl], e" ,GB_8BIT}, - {"ld [hl], h" ,GB_8BIT}, - {"ld [hl], l" ,GB_8BIT}, - {"halt" ,GB_8BIT}, - {"ld [hl], a" ,GB_8BIT}, - {"ld a, b" ,GB_8BIT}, - {"ld a, c" ,GB_8BIT}, - {"ld a, d" ,GB_8BIT}, - {"ld a, e" ,GB_8BIT}, - {"ld a, h" ,GB_8BIT}, - {"ld a, l" ,GB_8BIT}, - {"ld a, [hl]" ,GB_8BIT}, - {"ld a, a" ,GB_8BIT}, + { "add b", GB_8BIT }, //0x80 + { "add c", GB_8BIT }, + { "add d", GB_8BIT }, + { "add e", GB_8BIT }, + { "add h", GB_8BIT }, + { "add l", GB_8BIT }, + { "add [hl]", GB_8BIT }, + { "add a", GB_8BIT }, + { "adc b", GB_8BIT }, + { "adc c", GB_8BIT }, + { "adc d", GB_8BIT }, + { "adc e", GB_8BIT }, + { "adc h", GB_8BIT }, + { "adc l", GB_8BIT }, + { "adc [hl]", GB_8BIT }, + { "adc a", GB_8BIT }, - {"add b" ,GB_8BIT}, //0x80 - {"add c" ,GB_8BIT}, - {"add d" ,GB_8BIT}, - {"add e" ,GB_8BIT}, - {"add h" ,GB_8BIT}, - {"add l" ,GB_8BIT}, - {"add [hl]" ,GB_8BIT}, - {"add a" ,GB_8BIT}, - {"adc b" ,GB_8BIT}, - {"adc c" ,GB_8BIT}, - {"adc d" ,GB_8BIT}, - {"adc e" ,GB_8BIT}, - {"adc h" ,GB_8BIT}, - {"adc l" ,GB_8BIT}, - {"adc [hl]" ,GB_8BIT}, - {"adc a" ,GB_8BIT}, + { "sub b", GB_8BIT }, //0x90 + { "sub c", GB_8BIT }, + { "sub d", GB_8BIT }, + { "sub e", GB_8BIT }, + { "sub h", GB_8BIT }, + { "sub l", GB_8BIT }, + { "sub [hl]", GB_8BIT }, + { "sub a", GB_8BIT }, + { "sbc b", GB_8BIT }, + { "sbc c", GB_8BIT }, + { "sbc d", GB_8BIT }, + { "sbc e", GB_8BIT }, + { "sbc h", GB_8BIT }, + { "sbc l", GB_8BIT }, + { "sbc [hl]", GB_8BIT }, + { "sbc a", GB_8BIT }, - {"sub b" ,GB_8BIT}, //0x90 - {"sub c" ,GB_8BIT}, - {"sub d" ,GB_8BIT}, - {"sub e" ,GB_8BIT}, - {"sub h" ,GB_8BIT}, - {"sub l" ,GB_8BIT}, - {"sub [hl]" ,GB_8BIT}, - {"sub a" ,GB_8BIT}, - {"sbc b" ,GB_8BIT}, - {"sbc c" ,GB_8BIT}, - {"sbc d" ,GB_8BIT}, - {"sbc e" ,GB_8BIT}, - {"sbc h" ,GB_8BIT}, - {"sbc l" ,GB_8BIT}, - {"sbc [hl]" ,GB_8BIT}, - {"sbc a" ,GB_8BIT}, + { "and b", GB_8BIT }, //0xa0 + { "and c", GB_8BIT }, + { "and d", GB_8BIT }, + { "and e", GB_8BIT }, + { "and h", GB_8BIT }, + { "and l", GB_8BIT }, + { "and [hl]", GB_8BIT }, + { "and a", GB_8BIT }, + { "xor b", GB_8BIT }, + { "xor c", GB_8BIT }, + { "xor d", GB_8BIT }, + { "xor e", GB_8BIT }, + { "xor h", GB_8BIT }, + { "xor l", GB_8BIT }, + { "xor [hl]", GB_8BIT }, + { "xor a", GB_8BIT }, - {"and b" ,GB_8BIT}, //0xa0 - {"and c" ,GB_8BIT}, - {"and d" ,GB_8BIT}, - {"and e" ,GB_8BIT}, - {"and h" ,GB_8BIT}, - {"and l" ,GB_8BIT}, - {"and [hl]" ,GB_8BIT}, - {"and a" ,GB_8BIT}, - {"xor b" ,GB_8BIT}, - {"xor c" ,GB_8BIT}, - {"xor d" ,GB_8BIT}, - {"xor e" ,GB_8BIT}, - {"xor h" ,GB_8BIT}, - {"xor l" ,GB_8BIT}, - {"xor [hl]" ,GB_8BIT}, - {"xor a" ,GB_8BIT}, + { "or b", GB_8BIT }, //0xb0 + { "or c", GB_8BIT }, + { "or d", GB_8BIT }, + { "or e", GB_8BIT }, + { "or h", GB_8BIT }, + { "or l", GB_8BIT }, + { "or [hl]", GB_8BIT }, + { "or a", GB_8BIT }, + { "cp b", GB_8BIT }, + { "cp c", GB_8BIT }, + { "cp d", GB_8BIT }, + { "cp e", GB_8BIT }, + { "cp h", GB_8BIT }, + { "cp l", GB_8BIT }, + { "cp [hl]", GB_8BIT }, + { "cp a", GB_8BIT }, - {"or b" ,GB_8BIT}, //0xb0 - {"or c" ,GB_8BIT}, - {"or d" ,GB_8BIT}, - {"or e" ,GB_8BIT}, - {"or h" ,GB_8BIT}, - {"or l" ,GB_8BIT}, - {"or [hl]" ,GB_8BIT}, - {"or a" ,GB_8BIT}, - {"cp b" ,GB_8BIT}, - {"cp c" ,GB_8BIT}, - {"cp d" ,GB_8BIT}, - {"cp e" ,GB_8BIT}, - {"cp h" ,GB_8BIT}, - {"cp l" ,GB_8BIT}, - {"cp [hl]" ,GB_8BIT}, - {"cp a" ,GB_8BIT}, + { "ret nZ", GB_8BIT }, //0xc0 + { "pop bc", GB_8BIT }, + { "jp nZ, 0x%04x", GB_8BIT+ARG_16}, + { "jp 0x%04x", GB_8BIT+ARG_16}, + { "call nZ, 0x%04x", GB_8BIT+ARG_16}, + { "push bc", GB_8BIT }, + { "add 0x%02x", GB_8BIT+ARG_8 }, + { "rst 0", GB_8BIT }, + { "ret Z", GB_8BIT }, + { "ret", GB_8BIT }, + { "jp Z, 0x%04x", GB_8BIT+ARG_16}, + { "", GB_16BIT }, + { "call Z, 0x%04x" ,GB_8BIT+ARG_16}, + { "call 0x%04x", GB_8BIT+ARG_16}, + { "adc 0x%02x", GB_8BIT+ARG_8 }, + { "rst 8", GB_8BIT }, - {"ret nZ" ,GB_8BIT}, //0xc0 - {"pop bc" ,GB_8BIT}, - {"jp nZ, 0x%04x" ,GB_8BIT+ARG_16}, - {"jp 0x%04x" ,GB_8BIT+ARG_16}, - {"call nZ, 0x%04x" ,GB_8BIT+ARG_16}, - {"push bc" ,GB_8BIT}, - {"add 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 0" ,GB_8BIT}, - {"ret Z" ,GB_8BIT}, - {"ret" ,GB_8BIT}, - {"jp Z, 0x%04x" ,GB_8BIT+ARG_16}, - {"" ,GB_16BIT}, - {"call Z, 0x%04x" ,GB_8BIT+ARG_16}, - {"call 0x%04x" ,GB_8BIT+ARG_16}, - {"adc 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 8" ,GB_8BIT}, + { "ret nC", GB_8BIT }, //0xd0 + { "pop de", GB_8BIT }, + { "jp nC, 0x%04x" ,GB_8BIT+ARG_16}, + { "invalid", GB_8BIT }, + { "call nC, 0x%04x" ,GB_8BIT+ARG_16}, + { "push de", GB_8BIT }, + { "sub 0x%02x", GB_8BIT+ARG_8 }, + { "rst 16", GB_8BIT }, + { "ret C", GB_8BIT }, + { "reti", GB_8BIT }, + { "jp C, 0x%04x" ,GB_8BIT+ARG_16}, + { "invalid", GB_8BIT }, + { "call C, 0x%04x" ,GB_8BIT+ARG_16}, + { "invalid", GB_8BIT }, + { "sbc 0x%02x", GB_8BIT+ARG_8 }, + { "rst 24", GB_8BIT }, - {"ret nC" ,GB_8BIT}, //0xd0 - {"pop de" ,GB_8BIT}, - {"jp nC, 0x%04x" ,GB_8BIT+ARG_16}, - {"invalid" ,GB_8BIT}, - {"call nC, 0x%04x" ,GB_8BIT+ARG_16}, - {"push de" ,GB_8BIT}, - {"sub 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 16" ,GB_8BIT}, - {"ret C" ,GB_8BIT}, - {"reti" ,GB_8BIT}, - {"jp C, 0x%04x" ,GB_8BIT+ARG_16}, - {"invalid" ,GB_8BIT}, - {"call C, 0x%04x" ,GB_8BIT+ARG_16}, - {"invalid" ,GB_8BIT}, - {"sbc 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 24" ,GB_8BIT}, + { "ld [%s], a" ,GB_8BIT+ARG_8+GB_IO }, //0xe0 + { "pop hl", GB_8BIT }, + { "ld [0xff00 + c], a" ,GB_8BIT }, + { "invalid", GB_8BIT }, + { "invalid", GB_8BIT }, + { "push hl", GB_8BIT }, + { "and 0x%02x", GB_8BIT+ARG_8 }, + { "rst 32", GB_8BIT }, + { "add sp, 0x%02x" ,GB_8BIT+ARG_8 }, //signed + { "jp hl", GB_8BIT }, + { "ld [0x%04x], a" ,GB_8BIT+ARG_16}, //signed + { "invalid", GB_8BIT }, + { "invalid", GB_8BIT }, + { "invalid", GB_8BIT }, + { "xor 0x%02x", GB_8BIT+ARG_8 }, + { "rst 40", GB_8BIT }, - {"ld [%s], a" ,GB_8BIT+ARG_8+GB_IO}, //0xe0 - {"pop hl" ,GB_8BIT}, - {"ld [0xff00 + c], a" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"push hl" ,GB_8BIT}, - {"and 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 32" ,GB_8BIT}, - {"add sp, 0x%02x" ,GB_8BIT+ARG_8}, //signed - {"jp hl" ,GB_8BIT}, - {"ld [0x%04x], a" ,GB_8BIT+ARG_16}, //signed - {"invalid" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"xor 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 40" ,GB_8BIT}, - - {"ld a, [%s]" ,GB_8BIT+ARG_8+GB_IO}, //0xf0 - {"pop af" ,GB_8BIT}, - {"ld a, [0xff00 + c]" ,GB_8BIT}, - {"di" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"push af" ,GB_8BIT}, - {"or 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 48" ,GB_8BIT}, - {"ld hl, sp + 0x%02x" ,GB_8BIT+ARG_8}, //signed - {"ld sp, hl" ,GB_8BIT}, - {"ld a, [0x%04x]" ,GB_8BIT+ARG_16}, - {"ei" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"invalid" ,GB_8BIT}, - {"cp 0x%02x" ,GB_8BIT+ARG_8}, - {"rst 56" ,GB_8BIT}, + { "ld a, [%s]" ,GB_8BIT+ARG_8+GB_IO }, //0xf0 + { "pop af", GB_8BIT }, + { "ld a, [0xff00 + c]" ,GB_8BIT }, + { "di", GB_8BIT }, + { "invalid", GB_8BIT }, + { "push af", GB_8BIT }, + { "or 0x%02x", GB_8BIT+ARG_8 }, + { "rst 48", GB_8BIT }, + { "ld hl, sp + 0x%02x" ,GB_8BIT+ARG_8 }, //signed + { "ld sp, hl", GB_8BIT }, + { "ld a, [0x%04x]", GB_8BIT+ARG_16}, + { "ei", GB_8BIT }, + { "invalid", GB_8BIT }, + { "invalid", GB_8BIT }, + { "cp 0x%02x", GB_8BIT+ARG_8 }, + { "rst 56", GB_8BIT }, }; diff --git a/libr/anal/arch/i4004/i4004.c b/libr/anal/arch/i4004/i4004.c index a32993a98c..f583bbc653 100644 --- a/libr/anal/arch/i4004/i4004.c +++ b/libr/anal/arch/i4004/i4004.c @@ -111,339 +111,339 @@ static const unsigned char i4004_lengthtable[] = static const struct i4004_kv i4004_wordlist[] = { #line 146 "i4004.gperf" - {"ldm 0xe","de"}, + { "ldm 0xe","de" }, #line 93 "i4004.gperf" - {"ld r9","a9"}, + { "ld r9","a9" }, #line 141 "i4004.gperf" - {"ldm 0x9","d9"}, + { "ldm 0x9","d9" }, #line 29 "i4004.gperf" - {"jin r8r9","39"}, + { "jin r8r9","39" }, #line 142 "i4004.gperf" - {"ldm 0xa","da"}, + { "ldm 0xa","da" }, #line 90 "i4004.gperf" - {"ld r6","a6"}, + { "ld r6","a6" }, #line 61 "i4004.gperf" - {"add r9","89"}, + { "add r9","89" }, #line 138 "i4004.gperf" - {"ldm 0x6","d6"}, + { "ldm 0x6","d6" }, #line 144 "i4004.gperf" - {"ldm 0xc","dc"}, + { "ldm 0xc","dc" }, #line 168 "i4004.gperf" - {"cma","f4"}, + { "cma","f4" }, #line 58 "i4004.gperf" - {"add r6","86"}, + { "add r6","86" }, #line 143 "i4004.gperf" - {"ldm 0xb","db"}, + { "ldm 0xb","db" }, #line 167 "i4004.gperf" - {"cmc","f3"}, + { "cmc","f3" }, #line 166 "i4004.gperf" - {"iac","f2"}, + { "iac","f2" }, #line 130 "i4004.gperf" - {"bbl 0xe","ce"}, + { "bbl 0xe","ce" }, #line 176 "i4004.gperf" - {"kbp","fc"}, + { "kbp","fc" }, #line 125 "i4004.gperf" - {"bbl 0x9","c9"}, + { "bbl 0x9","c9" }, #line 126 "i4004.gperf" - {"bbl 0xa","ca"}, + { "bbl 0xa","ca" }, #line 174 "i4004.gperf" - {"stc","fa"}, + { "stc","fa" }, #line 122 "i4004.gperf" - {"bbl 0x6","c6"}, + { "bbl 0x6","c6" }, #line 128 "i4004.gperf" - {"bbl 0xc","cc"}, + { "bbl 0xc","cc" }, #line 11 "i4004.gperf" - {"nop","00"}, + { "nop","00" }, #line 127 "i4004.gperf" - {"bbl 0xb","cb"}, + { "bbl 0xb","cb" }, #line 87 "i4004.gperf" - {"ld r3","a3"}, + { "ld r3","a3" }, #line 97 "i4004.gperf" - {"ld r13","ad"}, + { "ld r13","ad" }, #line 135 "i4004.gperf" - {"ldm 0x3","d3"}, + { "ldm 0x3","d3" }, #line 23 "i4004.gperf" - {"jin r2r3","33"}, + { "jin r2r3","33" }, #line 33 "i4004.gperf" - {"jin r12r13","3d"}, + { "jin r12r13","3d" }, #line 55 "i4004.gperf" - {"add r3","83"}, + { "add r3","83" }, #line 65 "i4004.gperf" - {"add r13","8d"}, + { "add r13","8d" }, #line 85 "i4004.gperf" - {"ld r1","a1"}, + { "ld r1","a1" }, #line 95 "i4004.gperf" - {"ld r11","ab"}, + { "ld r11","ab" }, #line 133 "i4004.gperf" - {"ldm 0x1","d1"}, + { "ldm 0x1","d1" }, #line 21 "i4004.gperf" - {"jin r0r1","31"}, + { "jin r0r1","31" }, #line 18 "i4004.gperf" - {"src r6","2d"}, + { "src r6","2d" }, #line 31 "i4004.gperf" - {"jin r10r11","3b"}, + { "jin r10r11","3b" }, #line 53 "i4004.gperf" - {"add r1","81"}, + { "add r1","81" }, #line 63 "i4004.gperf" - {"add r11","8b"}, + { "add r11","8b" }, #line 119 "i4004.gperf" - {"bbl 0x3","c3"}, + { "bbl 0x3","c3" }, #line 169 "i4004.gperf" - {"ral","f5"}, + { "ral","f5" }, #line 145 "i4004.gperf" - {"ldm 0xd","dd"}, + { "ldm 0xd","dd" }, #line 149 "i4004.gperf" - {"wmp","e1"}, + { "wmp","e1" }, #line 109 "i4004.gperf" - {"xch r9","b9"}, + { "xch r9","b9" }, #line 117 "i4004.gperf" - {"bbl 0x1","c1"}, + { "bbl 0x1","c1" }, #line 106 "i4004.gperf" - {"xch r6","b6"}, + { "xch r6","b6" }, #line 89 "i4004.gperf" - {"ld r5","a5"}, + { "ld r5","a5" }, #line 99 "i4004.gperf" - {"ld r15","af"}, + { "ld r15","af" }, #line 137 "i4004.gperf" - {"ldm 0x5","d5"}, + { "ldm 0x5","d5" }, #line 25 "i4004.gperf" - {"jin r4r5","35"}, + { "jin r4r5","35" }, #line 35 "i4004.gperf" - {"jin r14r15","3f"}, + { "jin r14r15","3f" }, #line 57 "i4004.gperf" - {"add r5","85"}, + { "add r5","85" }, #line 67 "i4004.gperf" - {"add r15","8f"}, + { "add r15","8f" }, #line 175 "i4004.gperf" - {"daa","fb"}, + { "daa","fb" }, #line 15 "i4004.gperf" - {"src r3","27"}, + { "src r3","27" }, #line 172 "i4004.gperf" - {"dac","f8"}, + { "dac","f8" }, #line 92 "i4004.gperf" - {"ld r8","a8"}, + { "ld r8","a8" }, #line 140 "i4004.gperf" - {"ldm 0x8","d8"}, + { "ldm 0x8","d8" }, #line 129 "i4004.gperf" - {"bbl 0xd","cd"}, + { "bbl 0xd","cd" }, #line 163 "i4004.gperf" - {"rd3","ef"}, + { "rd3","ef" }, #line 60 "i4004.gperf" - {"add r8","88"}, + { "add r8","88" }, #line 13 "i4004.gperf" - {"src r1","23"}, + { "src r1","23" }, #line 171 "i4004.gperf" - {"tcc","f7"}, + { "tcc","f7" }, #line 121 "i4004.gperf" - {"bbl 0x5","c5"}, + { "bbl 0x5","c5" }, #line 161 "i4004.gperf" - {"rd1","ed"}, + { "rd1","ed" }, #line 158 "i4004.gperf" - {"rdr","ea"}, + { "rdr","ea" }, #line 103 "i4004.gperf" - {"xch r3","b3"}, + { "xch r3","b3" }, #line 113 "i4004.gperf" - {"xch r13","bd"}, + { "xch r13","bd" }, #line 173 "i4004.gperf" - {"tcs","f9"}, + { "tcs","f9" }, #line 124 "i4004.gperf" - {"bbl 0x8","c8"}, + { "bbl 0x8","c8" }, #line 155 "i4004.gperf" - {"wr3","e7"}, + { "wr3","e7" }, #line 77 "i4004.gperf" - {"sub r9","99"}, + { "sub r9","99" }, #line 101 "i4004.gperf" - {"xch r1","b1"}, + { "xch r1","b1" }, #line 111 "i4004.gperf" - {"xch r11","bb"}, + { "xch r11","bb" }, #line 170 "i4004.gperf" - {"rar","f6"}, + { "rar","f6" }, #line 74 "i4004.gperf" - {"sub r6","96"}, + { "sub r6","96" }, #line 17 "i4004.gperf" - {"src r5","2b"}, + { "src r5","2b" }, #line 153 "i4004.gperf" - {"wr1","e5"}, + { "wr1","e5" }, #line 86 "i4004.gperf" - {"ld r2","a2"}, + { "ld r2","a2" }, #line 96 "i4004.gperf" - {"ld r12","ac"}, + { "ld r12","ac" }, #line 134 "i4004.gperf" - {"ldm 0x2","d2"}, + { "ldm 0x2","d2" }, #line 150 "i4004.gperf" - {"wrr","e2"}, + { "wrr","e2" }, #line 54 "i4004.gperf" - {"add r2","82"}, + { "add r2","82" }, #line 64 "i4004.gperf" - {"add r12","8c"}, + { "add r12","8c" }, #line 177 "i4004.gperf" - {"dcl","fd"}, + { "dcl","fd" }, #line 84 "i4004.gperf" - {"ld r0","a0"}, + { "ld r0","a0" }, #line 94 "i4004.gperf" - {"ld r10","aa"}, + { "ld r10","aa" }, #line 132 "i4004.gperf" - {"ldm 0x0","d0"}, + { "ldm 0x0","d0" }, #line 52 "i4004.gperf" - {"add r0","80"}, + { "add r0","80" }, #line 62 "i4004.gperf" - {"add r10","8a"}, + { "add r10","8a" }, #line 159 "i4004.gperf" - {"adm","eb"}, + { "adm","eb" }, #line 105 "i4004.gperf" - {"xch r5","b5"}, + { "xch r5","b5" }, #line 115 "i4004.gperf" - {"xch r15","bf"}, + { "xch r15","bf" }, #line 118 "i4004.gperf" - {"bbl 0x2","c2"}, + { "bbl 0x2","c2" }, #line 71 "i4004.gperf" - {"sub r3","93"}, + { "sub r3","93" }, #line 81 "i4004.gperf" - {"sub r13","9d"}, + { "sub r13","9d" }, #line 165 "i4004.gperf" - {"clc","f1"}, + { "clc","f1" }, #line 108 "i4004.gperf" - {"xch r8","b8"}, + { "xch r8","b8" }, #line 116 "i4004.gperf" - {"bbl 0x0","c0"}, + { "bbl 0x0","c0" }, #line 164 "i4004.gperf" - {"clb","f0"}, + { "clb","f0" }, #line 69 "i4004.gperf" - {"sub r1","91"}, + { "sub r1","91" }, #line 79 "i4004.gperf" - {"sub r11","9b"}, + { "sub r11","9b" }, #line 156 "i4004.gperf" - {"sbm","e8"}, + { "sbm","e8" }, #line 14 "i4004.gperf" - {"src r2","25"}, + { "src r2","25" }, #line 91 "i4004.gperf" - {"ld r7","a7"}, + { "ld r7","a7" }, #line 139 "i4004.gperf" - {"ldm 0x7","d7"}, + { "ldm 0x7","d7" }, #line 27 "i4004.gperf" - {"jin r6r7","37"}, + { "jin r6r7","37" }, #line 162 "i4004.gperf" - {"rd2","ee"}, + { "rd2","ee" }, #line 59 "i4004.gperf" - {"add r7","87"}, + { "add r7","87" }, #line 12 "i4004.gperf" - {"src r0","21"}, + { "src r0","21" }, #line 160 "i4004.gperf" - {"rd0","ec"}, + { "rd0","ec" }, #line 73 "i4004.gperf" - {"sub r5","95"}, + { "sub r5","95" }, #line 83 "i4004.gperf" - {"sub r15","9f"}, + { "sub r15","9f" }, #line 157 "i4004.gperf" - {"rdm","e9"}, + { "rdm","e9" }, #line 102 "i4004.gperf" - {"xch r2","b2"}, + { "xch r2","b2" }, #line 112 "i4004.gperf" - {"xch r12","bc"}, + { "xch r12","bc" }, #line 151 "i4004.gperf" - {"wpm","e3"}, + { "wpm","e3" }, #line 123 "i4004.gperf" - {"bbl 0x7","c7"}, + { "bbl 0x7","c7" }, #line 154 "i4004.gperf" - {"wr2","e6"}, + { "wr2","e6" }, #line 76 "i4004.gperf" - {"sub r8","98"}, + { "sub r8","98" }, #line 100 "i4004.gperf" - {"xch r0","b0"}, + { "xch r0","b0" }, #line 110 "i4004.gperf" - {"xch r10","ba"}, + { "xch r10","ba" }, #line 88 "i4004.gperf" - {"ld r4","a4"}, + { "ld r4","a4" }, #line 98 "i4004.gperf" - {"ld r14","ae"}, + { "ld r14","ae" }, #line 136 "i4004.gperf" - {"ldm 0x4","d4"}, + { "ldm 0x4","d4" }, #line 152 "i4004.gperf" - {"wr0","e4"}, + { "wr0","e4" }, #line 56 "i4004.gperf" - {"add r4","84"}, + { "add r4","84" }, #line 66 "i4004.gperf" - {"add r14","8e"}, + { "add r14","8e" }, #line 148 "i4004.gperf" - {"wrm","e0"}, + { "wrm","e0" }, #line 45 "i4004.gperf" - {"inc r9","69"}, + { "inc r9","69" }, #line 19 "i4004.gperf" - {"src r7","2f"}, + { "src r7","2f" }, #line 147 "i4004.gperf" - {"ldm 0xf","df"}, + { "ldm 0xf","df" }, #line 42 "i4004.gperf" - {"inc r6","66"}, + { "inc r6","66" }, #line 28 "i4004.gperf" - {"fin r8r9","38"}, + { "fin r8r9","38" }, #line 120 "i4004.gperf" - {"bbl 0x4","c4"}, + { "bbl 0x4","c4" }, #line 70 "i4004.gperf" - {"sub r2","92"}, + { "sub r2","92" }, #line 80 "i4004.gperf" - {"sub r12","9c"}, + { "sub r12","9c" }, #line 107 "i4004.gperf" - {"xch r7","b7"}, + { "xch r7","b7" }, #line 131 "i4004.gperf" - {"bbl 0xf","cf"}, + { "bbl 0xf","cf" }, #line 68 "i4004.gperf" - {"sub r0","90"}, + { "sub r0","90" }, #line 78 "i4004.gperf" - {"sub r10","9a"}, + { "sub r10","9a" }, #line 16 "i4004.gperf" - {"src r4","29"}, + { "src r4","29" }, #line 39 "i4004.gperf" - {"inc r3","63"}, + { "inc r3","63" }, #line 49 "i4004.gperf" - {"inc r13","6d"}, + { "inc r13","6d" }, #line 22 "i4004.gperf" - {"fin r2r3","32"}, + { "fin r2r3","32" }, #line 32 "i4004.gperf" - {"fin r12r13","3c"}, + { "fin r12r13","3c" }, #line 37 "i4004.gperf" - {"inc r1","61"}, + { "inc r1","61" }, #line 47 "i4004.gperf" - {"inc r11","6b"}, + { "inc r11","6b" }, #line 20 "i4004.gperf" - {"fin r0r1","30"}, + { "fin r0r1","30" }, #line 30 "i4004.gperf" - {"fin r10r11","3a"}, + { "fin r10r11","3a" }, #line 104 "i4004.gperf" - {"xch r4","b4"}, + { "xch r4","b4" }, #line 114 "i4004.gperf" - {"xch r14","be"}, + { "xch r14","be" }, #line 75 "i4004.gperf" - {"sub r7","97"}, + { "sub r7","97" }, #line 41 "i4004.gperf" - {"inc r5","65"}, + { "inc r5","65" }, #line 51 "i4004.gperf" - {"inc r15","6f"}, + { "inc r15","6f" }, #line 24 "i4004.gperf" - {"fin r4r5","34"}, + { "fin r4r5","34" }, #line 34 "i4004.gperf" - {"fin r14r15","3e"}, + { "fin r14r15","3e" }, #line 44 "i4004.gperf" - {"inc r8","68"}, + { "inc r8","68" }, #line 72 "i4004.gperf" - {"sub r4","94"}, + { "sub r4","94" }, #line 82 "i4004.gperf" - {"sub r14","9e"}, + { "sub r14","9e" }, #line 38 "i4004.gperf" - {"inc r2","62"}, + { "inc r2","62" }, #line 48 "i4004.gperf" - {"inc r12","6c"}, + { "inc r12","6c" }, #line 36 "i4004.gperf" - {"inc r0","60"}, + { "inc r0","60" }, #line 46 "i4004.gperf" - {"inc r10","6a"}, + { "inc r10","6a" }, #line 43 "i4004.gperf" - {"inc r7","67"}, + { "inc r7","67" }, #line 26 "i4004.gperf" - {"fin r6r7","36"}, + { "fin r6r7","36" }, #line 40 "i4004.gperf" - {"inc r4","64"}, + { "inc r4","64" }, #line 50 "i4004.gperf" - {"inc r14","6e"} + { "inc r14","6e" } }; static const short i4004_lookup[] = diff --git a/libr/anal/arch/kvx/opc.sed b/libr/anal/arch/kvx/opc.sed old mode 100755 new mode 100644 diff --git a/libr/anal/arch/lm32/lm32_isa.h b/libr/anal/arch/lm32/lm32_isa.h index 76e9a6f051..dc677deb45 100644 --- a/libr/anal/arch/lm32/lm32_isa.h +++ b/libr/anal/arch/lm32/lm32_isa.h @@ -17,27 +17,27 @@ typedef struct r_asm_lm32_csr_t { #define RAsmLm32CsrNumber 21 static const RAsmLm32Csr RAsmLm32Csrs[RAsmLm32CsrNumber] = { - {0x00, "IE"}, - {0x01, "IM"}, - {0x02, "IP"}, - {0x03, "ICC"}, - {0x04, "DCC"}, - {0x05, "CC"}, - {0x06, "CFG"}, - {0x07, "EBA"}, - {0x08, "DC"}, - {0x09, "DEBA"}, - {0x0a, "CFG2"}, - {0x0e, "JTX"}, - {0x0f, "JRX"}, - {0x10, "BP0"}, - {0x11, "BP1"}, - {0x12, "BP2"}, - {0x13, "BP3"}, - {0x18, "WP0"}, - {0x19, "WP1"}, - {0x1a, "WP2"}, - {0x1b, "WP3"}, + {0x00, "IE" }, + {0x01, "IM" }, + {0x02, "IP" }, + {0x03, "ICC" }, + {0x04, "DCC" }, + {0x05, "CC" }, + {0x06, "CFG" }, + {0x07, "EBA" }, + {0x08, "DC" }, + {0x09, "DEBA" }, + {0x0a, "CFG2" }, + {0x0e, "JTX" }, + {0x0f, "JRX" }, + {0x10, "BP0" }, + {0x11, "BP1" }, + {0x12, "BP2" }, + {0x13, "BP3" }, + {0x18, "WP0" }, + {0x19, "WP1" }, + {0x1a, "WP2" }, + {0x1b, "WP3" }, }; typedef struct r_asm_lm32_reg_t { @@ -48,45 +48,45 @@ typedef struct r_asm_lm32_reg_t { #define RAsmLm32RegNumber 39 static const RAsmLm32Reg RAsmLm32Regs[RAsmLm32RegNumber] = { - {0x00, "r0"}, - {0x00, "zero"}, - {0x01, "r1"}, - {0x02, "r2"}, - {0x03, "r3"}, - {0x04, "r4"}, - {0x05, "r5"}, - {0x06, "r6"}, - {0x07, "r7"}, - {0x08, "r8"}, - {0x09, "r9"}, - {0x0a, "r10"}, - {0x0b, "r11"}, - {0x0c, "r12"}, - {0x0d, "r13"}, - {0x0e, "r14"}, - {0x0f, "r15"}, - {0x10, "r16"}, - {0x11, "r17"}, - {0x12, "r18"}, - {0x13, "r19"}, - {0x14, "r20"}, - {0x15, "r21"}, - {0x16, "r22"}, - {0x17, "r23"}, - {0x18, "r24"}, - {0x19, "r25"}, - {0x1a, "gp"}, - {0x1a, "r26"}, - {0x1b, "fp"}, - {0x1b, "r27"}, - {0x1c, "sp"}, - {0x1c, "r28"}, - {0x1d, "ra"}, - {0x1d, "r29"}, - {0x1e, "ea"}, - {0x1e, "r30"}, - {0x1f, "ba"}, - {0x1f, "r31"}, + {0x00, "r0" }, + {0x00, "zero" }, + {0x01, "r1" }, + {0x02, "r2" }, + {0x03, "r3" }, + {0x04, "r4" }, + {0x05, "r5" }, + {0x06, "r6" }, + {0x07, "r7" }, + {0x08, "r8" }, + {0x09, "r9" }, + {0x0a, "r10" }, + {0x0b, "r11" }, + {0x0c, "r12" }, + {0x0d, "r13" }, + {0x0e, "r14" }, + {0x0f, "r15" }, + {0x10, "r16" }, + {0x11, "r17" }, + {0x12, "r18" }, + {0x13, "r19" }, + {0x14, "r20" }, + {0x15, "r21" }, + {0x16, "r22" }, + {0x17, "r23" }, + {0x18, "r24" }, + {0x19, "r25" }, + {0x1a, "gp" }, + {0x1a, "r26" }, + {0x1b, "fp" }, + {0x1b, "r27" }, + {0x1c, "sp" }, + {0x1c, "r28" }, + {0x1d, "ra" }, + {0x1d, "r29" }, + {0x1e, "ea" }, + {0x1e, "r30" }, + {0x1f, "ba" }, + {0x1f, "r31" }, }; typedef enum r_asm_lm32_instr_type_t { @@ -179,70 +179,70 @@ typedef struct r_asm_lm32_opcode { #define RAsmLm32OpcodeNumber 0x40 static const RAsmLm32Opcode RAsmLm32OpcodeList[RAsmLm32OpcodeNumber] = { - {reg_imm5, "srui"}, //0x00 - {reg_imm16_zeroextend, "nori"}, //0x01 - {reg_imm16_signextend, "muli"}, //0x02 - {reg_imm16_signextend, "sh"}, //0x03 - {reg_imm16_signextend, "lb"}, //0x04 - {reg_imm5, "sri"}, //0x05 - {reg_imm16_zeroextend, "xori"}, //0x06 - {reg_imm16_signextend, "lh"}, //0x07 - {reg_imm16_zeroextend, "andi"}, //0x08 - {reg_imm16_zeroextend, "xnori"}, //0x09 - {reg_imm16_signextend, "lw"}, //0x0a - {reg_imm16_signextend, "lhu"}, //0x0b - {reg_imm16_signextend, "sb"}, //0x0c - {reg_imm16_signextend, "addi"}, //0x0d - {reg_imm16_zeroextend, "ori"}, //0x0e - {reg_imm5, "sli"}, //0x0f - {reg_imm16_signextend, "lbu"}, //0x10 - {reg_imm16_shift2_signextend, "be"}, //0x11 - {reg_imm16_shift2_signextend, "bg"}, //0x12 - {reg_imm16_shift2_signextend, "bge"}, //0x13 - {reg_imm16_shift2_signextend, "bgeu"}, //0x14 - {reg_imm16_shift2_signextend, "bgu"}, //0x15 - {reg_imm16_signextend, "sw"}, //0x16 - {reg_imm16_shift2_signextend, "bne"}, //0x17 - {reg_imm16_zeroextend, "andhi"}, //0x18 - {reg_imm16_signextend, "cmpei"}, //0x19 - {reg_imm16_signextend, "cmpgi"}, //0x1a - {reg_imm16_signextend, "cmpgei"}, //0x1b - {reg_imm16_zeroextend, "cmpgeui"}, //0x1c - {reg_imm16_zeroextend, "cmpgui"}, //0x1d - {reg_imm16_zeroextend, "orhi"}, //0x1e - {reg_imm16_signextend, "cmpnei"}, //0x1f - {three_regs, "sru"}, //0x20 - {three_regs, "nor"}, //0x21 - {three_regs, "mul"}, //0x22 - {three_regs, "divu"}, //0x23 - {csr_reg, "rcsr"}, //0x24 - {three_regs, "sr"}, //0x25 - {three_regs, "xor"}, //0x26 - {three_regs, "div"}, //0x27 - {three_regs, "and"}, //0x28 - {three_regs, "xnor"}, //0x29 - {reserved, "reserved"}, //0x2a - {raise_instr, "raise"}, //0x2b (break, scall) - {two_regs, "sextb"}, //0x2c - {three_regs, "add"}, //0x2d - {three_regs, "or"}, //0x2e - {three_regs, "sl"}, //0x2f - {one_reg, "b"}, //0x30 - {three_regs, "modu"}, //0x31 - {three_regs, "sub"}, //0x32 - {reserved, "reserved"}, //0x33 - {reg_csr, "wcsr"}, //0x34 - {three_regs, "mod"}, //0x35 - {one_reg, "call"}, //0x36 - {two_regs, "sexth"}, //0x37 - {imm26, "bi"}, //0x38 - {three_regs, "cmpe"}, //0x39 - {three_regs, "cmpg"}, //0x3a - {three_regs, "cmpge"}, //0x3b - {three_regs, "cmpgeu"}, //0x3c - {three_regs, "cmpgu"}, //0x3d - {imm26, "calli"}, //0x3e - {three_regs, "cmpne"}, //0x3f + {reg_imm5, "srui" }, //0x00 + {reg_imm16_zeroextend, "nori" }, //0x01 + {reg_imm16_signextend, "muli" }, //0x02 + {reg_imm16_signextend, "sh" }, //0x03 + {reg_imm16_signextend, "lb" }, //0x04 + {reg_imm5, "sri" }, //0x05 + {reg_imm16_zeroextend, "xori" }, //0x06 + {reg_imm16_signextend, "lh" }, //0x07 + {reg_imm16_zeroextend, "andi" }, //0x08 + {reg_imm16_zeroextend, "xnori" }, //0x09 + {reg_imm16_signextend, "lw" }, //0x0a + {reg_imm16_signextend, "lhu" }, //0x0b + {reg_imm16_signextend, "sb" }, //0x0c + {reg_imm16_signextend, "addi" }, //0x0d + {reg_imm16_zeroextend, "ori" }, //0x0e + {reg_imm5, "sli" }, //0x0f + {reg_imm16_signextend, "lbu" }, //0x10 + {reg_imm16_shift2_signextend, "be" }, //0x11 + {reg_imm16_shift2_signextend, "bg" }, //0x12 + {reg_imm16_shift2_signextend, "bge" }, //0x13 + {reg_imm16_shift2_signextend, "bgeu" }, //0x14 + {reg_imm16_shift2_signextend, "bgu" }, //0x15 + {reg_imm16_signextend, "sw" }, //0x16 + {reg_imm16_shift2_signextend, "bne" }, //0x17 + {reg_imm16_zeroextend, "andhi" }, //0x18 + {reg_imm16_signextend, "cmpei" }, //0x19 + {reg_imm16_signextend, "cmpgi" }, //0x1a + {reg_imm16_signextend, "cmpgei" }, //0x1b + {reg_imm16_zeroextend, "cmpgeui" }, //0x1c + {reg_imm16_zeroextend, "cmpgui" }, //0x1d + {reg_imm16_zeroextend, "orhi" }, //0x1e + {reg_imm16_signextend, "cmpnei" }, //0x1f + {three_regs, "sru" }, //0x20 + {three_regs, "nor" }, //0x21 + {three_regs, "mul" }, //0x22 + {three_regs, "divu" }, //0x23 + {csr_reg, "rcsr" }, //0x24 + {three_regs, "sr" }, //0x25 + {three_regs, "xor" }, //0x26 + {three_regs, "div" }, //0x27 + {three_regs, "and" }, //0x28 + {three_regs, "xnor" }, //0x29 + {reserved, "reserved" }, //0x2a + {raise_instr, "raise" }, //0x2b (break, scall) + {two_regs, "sextb" }, //0x2c + {three_regs, "add" }, //0x2d + {three_regs, "or" }, //0x2e + {three_regs, "sl" }, //0x2f + {one_reg, "b" }, //0x30 + {three_regs, "modu" }, //0x31 + {three_regs, "sub" }, //0x32 + {reserved, "reserved" }, //0x33 + {reg_csr, "wcsr" }, //0x34 + {three_regs, "mod" }, //0x35 + {one_reg, "call" }, //0x36 + {two_regs, "sexth" }, //0x37 + {imm26, "bi" }, //0x38 + {three_regs, "cmpe" }, //0x39 + {three_regs, "cmpg" }, //0x3a + {three_regs, "cmpge" }, //0x3b + {three_regs, "cmpgeu" }, //0x3c + {three_regs, "cmpgu" }, //0x3d + {imm26, "calli" }, //0x3e + {three_regs, "cmpne" }, //0x3f }; typedef struct r_asm_lm32_instruction { diff --git a/libr/anal/arch/mcs96/mcs96.h b/libr/anal/arch/mcs96/mcs96.h index 3a1914e146..709b213056 100644 --- a/libr/anal/arch/mcs96/mcs96.h +++ b/libr/anal/arch/mcs96/mcs96.h @@ -26,263 +26,263 @@ typedef struct mcs96_op_t { static const Mcs96Op mcs96_op[] = { - {"skip", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"shr", MCS96_3B}, - {"shl", MCS96_3B}, - {"shra", MCS96_3B}, //0x0a - {"invalid", MCS96_1B}, - {"shrl", MCS96_3B}, - {"shll", MCS96_3B}, - {"shral", MCS96_3B}, - {"norml", MCS96_3B}, - {"invalid", MCS96_1B}, //0x10 - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"shrb", MCS96_3B}, - {"shlb", MCS96_3B}, - {"shrab", MCS96_3B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"sjmp", MCS96_2B}, //0x20 - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"sjmp", MCS96_2B}, - {"scall", MCS96_2B}, //0x28 - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"scall", MCS96_2B}, - {"jbc", MCS96_3B}, //0x30 - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbc", MCS96_3B}, - {"jbs", MCS96_3B}, //0x38 - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"jbs", MCS96_3B}, - {"and", MCS96_4B|MCS96_3OP}, //0x40 - {"and", MCS96_5B|MCS96_3OP}, - {"and", MCS96_4B|MCS96_3OP}, - {"and", MCS96_5B_OR_6B|MCS96_3OP}, - {"add", MCS96_4B|MCS96_3OP}, - {"add", MCS96_5B|MCS96_3OP}, - {"add", MCS96_4B|MCS96_3OP}, - {"add", MCS96_5B_OR_6B|MCS96_3OP}, - {"sub", MCS96_4B|MCS96_3OP}, - {"sub", MCS96_5B|MCS96_3OP}, - {"sub", MCS96_4B|MCS96_3OP}, - {"sub", MCS96_5B_OR_6B|MCS96_3OP}, - {"mulu", MCS96_4B|MCS96_3OP|MCS96_FE}, - {"mulu", MCS96_5B|MCS96_3OP|MCS96_FE}, - {"mulu", MCS96_4B|MCS96_3OP|MCS96_FE}, - {"mulu", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x4f - {"andb", MCS96_4B|MCS96_3OP|MCS96_REG_8}, - {"andb", MCS96_4B|MCS96_3OP}, - {"andb", MCS96_4B|MCS96_3OP}, - {"andb", MCS96_5B_OR_6B|MCS96_3OP}, //datasheet says that this is always 5 byte + { "skip", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "shr", MCS96_3B}, + { "shl", MCS96_3B}, + { "shra", MCS96_3B}, //0x0a + { "invalid", MCS96_1B}, + { "shrl", MCS96_3B}, + { "shll", MCS96_3B}, + { "shral", MCS96_3B}, + { "norml", MCS96_3B}, + { "invalid", MCS96_1B}, //0x10 + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "shrb", MCS96_3B}, + { "shlb", MCS96_3B}, + { "shrab", MCS96_3B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "sjmp", MCS96_2B}, //0x20 + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "sjmp", MCS96_2B}, + { "scall", MCS96_2B}, //0x28 + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "scall", MCS96_2B}, + { "jbc", MCS96_3B}, //0x30 + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbc", MCS96_3B}, + { "jbs", MCS96_3B}, //0x38 + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "jbs", MCS96_3B}, + { "and", MCS96_4B|MCS96_3OP}, //0x40 + { "and", MCS96_5B|MCS96_3OP}, + { "and", MCS96_4B|MCS96_3OP}, + { "and", MCS96_5B_OR_6B|MCS96_3OP}, + { "add", MCS96_4B|MCS96_3OP}, + { "add", MCS96_5B|MCS96_3OP}, + { "add", MCS96_4B|MCS96_3OP}, + { "add", MCS96_5B_OR_6B|MCS96_3OP}, + { "sub", MCS96_4B|MCS96_3OP}, + { "sub", MCS96_5B|MCS96_3OP}, + { "sub", MCS96_4B|MCS96_3OP}, + { "sub", MCS96_5B_OR_6B|MCS96_3OP}, + { "mulu", MCS96_4B|MCS96_3OP|MCS96_FE}, + { "mulu", MCS96_5B|MCS96_3OP|MCS96_FE}, + { "mulu", MCS96_4B|MCS96_3OP|MCS96_FE}, + { "mulu", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x4f + { "andb", MCS96_4B|MCS96_3OP|MCS96_REG_8}, + { "andb", MCS96_4B|MCS96_3OP}, + { "andb", MCS96_4B|MCS96_3OP}, + { "andb", MCS96_5B_OR_6B|MCS96_3OP}, //datasheet says that this is always 5 byte //that datasheet already has proven to have typos - {"addb", MCS96_4B|MCS96_3OP}, - {"addb", MCS96_4B|MCS96_3OP}, - {"addb", MCS96_4B|MCS96_3OP}, - {"addb", MCS96_5B_OR_6B|MCS96_3OP}, - {"subb", MCS96_4B|MCS96_3OP}, - {"subb", MCS96_4B|MCS96_3OP}, - {"subb", MCS96_4B|MCS96_3OP}, - {"subb", MCS96_5B_OR_6B|MCS96_3OP}, - {"mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, - {"mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, - {"mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, - {"mulub", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x5f - {"and", MCS96_3B|MCS96_2OP}, - {"and", MCS96_4B|MCS96_2OP}, - {"and", MCS96_3B|MCS96_2OP}, - {"and", MCS96_4B_OR_5B|MCS96_2OP}, - {"add", MCS96_3B|MCS96_2OP}, - {"add", MCS96_4B|MCS96_2OP}, - {"add", MCS96_3B|MCS96_2OP}, - {"add", MCS96_4B_OR_5B|MCS96_2OP}, - {"sub", MCS96_3B|MCS96_2OP}, - {"sub", MCS96_4B|MCS96_2OP}, - {"sub", MCS96_3B|MCS96_2OP}, - {"sub", MCS96_4B_OR_5B|MCS96_2OP}, - {"mulu", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"mulu", MCS96_4B|MCS96_2OP|MCS96_FE}, - {"mulu", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"mulu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x6f - {"andb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"andb", MCS96_3B|MCS96_2OP}, - {"andb", MCS96_3B|MCS96_2OP}, - {"andb", MCS96_4B_OR_5B|MCS96_2OP}, //again i don't trust the data-sheet here - {"addb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"addb", MCS96_3B|MCS96_2OP}, - {"addb", MCS96_3B|MCS96_2OP}, - {"addb", MCS96_4B_OR_5B|MCS96_2OP}, - {"subb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"subb", MCS96_3B|MCS96_2OP}, - {"subb", MCS96_3B|MCS96_2OP}, - {"subb", MCS96_4B_OR_5B|MCS96_2OP}, - {"mulub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8}, - {"mulub", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"mulub", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"mulub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x7f - {"or", MCS96_3B|MCS96_2OP}, - {"or", MCS96_4B|MCS96_2OP}, - {"or", MCS96_3B|MCS96_2OP}, - {"or", MCS96_4B_OR_5B|MCS96_2OP}, - {"xor", MCS96_3B|MCS96_2OP}, - {"xor", MCS96_4B|MCS96_2OP}, - {"xor", MCS96_3B|MCS96_2OP}, - {"xor", MCS96_4B_OR_5B|MCS96_2OP}, - {"cmp", MCS96_3B|MCS96_2OP}, - {"cmp", MCS96_4B|MCS96_2OP}, - {"cmp", MCS96_3B|MCS96_2OP}, - {"cmp", MCS96_4B_OR_5B|MCS96_2OP}, - {"divu", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"divu", MCS96_4B|MCS96_2OP|MCS96_FE}, - {"divu", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"divu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x8f - {"orb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"orb", MCS96_3B|MCS96_2OP}, - {"orb", MCS96_3B|MCS96_2OP}, - {"orb", MCS96_4B_OR_5B|MCS96_2OP}, - {"xorb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"xorb", MCS96_3B|MCS96_2OP}, - {"xorb", MCS96_3B|MCS96_2OP}, - {"xorb", MCS96_4B_OR_5B|MCS96_2OP}, - {"cmpb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"cmpb", MCS96_3B|MCS96_2OP}, - {"cmpb", MCS96_3B|MCS96_2OP}, - {"cmpb", MCS96_4B_OR_5B|MCS96_2OP}, - {"divub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8}, - {"divub", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"divub", MCS96_3B|MCS96_2OP|MCS96_FE}, - {"divub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x9f - {"ld", MCS96_3B|MCS96_2OP}, - {"ld", MCS96_4B|MCS96_2OP}, - {"ld", MCS96_3B|MCS96_2OP}, - {"ld", MCS96_4B_OR_5B|MCS96_2OP}, - {"addc", MCS96_3B|MCS96_2OP}, - {"addc", MCS96_4B|MCS96_2OP}, - {"addc", MCS96_3B|MCS96_2OP}, - {"addc", MCS96_4B_OR_5B|MCS96_2OP}, - {"subc", MCS96_3B|MCS96_2OP}, - {"subc", MCS96_4B|MCS96_2OP}, - {"subc", MCS96_3B|MCS96_2OP}, - {"subc", MCS96_4B_OR_5B|MCS96_2OP}, - {"lbsze", MCS96_3B|MCS96_2OP}, - {"lbsze", MCS96_3B|MCS96_2OP}, - {"lbsze", MCS96_3B|MCS96_2OP}, - {"lbsze", MCS96_4B_OR_5B|MCS96_2OP}, //0xaf - {"ldb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"ldb", MCS96_3B|MCS96_2OP}, - {"ldb", MCS96_3B|MCS96_2OP}, - {"ldb", MCS96_4B_OR_5B|MCS96_2OP}, - {"addcb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"addcb", MCS96_3B|MCS96_2OP}, - {"addcb", MCS96_3B|MCS96_2OP}, - {"addcb", MCS96_4B_OR_5B|MCS96_2OP}, - {"subcb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"subcb", MCS96_3B|MCS96_2OP}, - {"subcb", MCS96_3B|MCS96_2OP}, - {"subcb", MCS96_4B_OR_5B|MCS96_2OP}, - {"ldbse", MCS96_3B|MCS96_2OP|MCS96_REG_8}, - {"ldbse", MCS96_3B|MCS96_2OP}, - {"ldbse", MCS96_3B|MCS96_2OP}, - {"ldbse", MCS96_4B_OR_5B|MCS96_2OP}, //0xbf - {"st", MCS96_3B|MCS96_2OP}, - {"invalid", MCS96_1B}, - {"st", MCS96_3B|MCS96_2OP}, - {"st", MCS96_4B_OR_5B|MCS96_2OP}, - {"stb", MCS96_3B|MCS96_2OP}, - {"invalid", MCS96_1B}, - {"stb", MCS96_3B|MCS96_2OP}, - {"stb", MCS96_4B_OR_5B|MCS96_2OP}, - {"push", MCS96_2B}, - {"push", MCS96_3B}, - {"push", MCS96_2B}, - {"push", MCS96_3B_OR_4B}, - {"pop", MCS96_2B}, - {"invalid", MCS96_1B}, - {"pop", MCS96_2B}, - {"pop", MCS96_3B_OR_4B}, //0xcf - {"jnst", MCS96_2B}, - {"jnh", MCS96_2B}, - {"jgt", MCS96_2B}, - {"jnc", MCS96_2B}, - {"jnvt", MCS96_2B}, - {"jnv", MCS96_2B}, - {"jge", MCS96_2B}, - {"jne", MCS96_2B}, - {"jst", MCS96_2B}, - {"jh", MCS96_2B}, - {"jle", MCS96_2B}, - {"jc", MCS96_2B}, - {"jvt", MCS96_2B}, - {"jv", MCS96_2B}, - {"jlt", MCS96_2B}, - {"je", MCS96_2B}, //0xdf - {"djnz", MCS96_3B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"br", MCS96_2B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"ljmp", MCS96_3B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"lcall", MCS96_3B}, //0xef - {"ret", MCS96_1B}, - {"invalid", MCS96_1B}, - {"pushf", MCS96_1B}, - {"popf", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"invalid", MCS96_1B}, - {"trap", MCS96_1B}, - {"clrc", MCS96_1B}, - {"setc", MCS96_1B}, - {"di", MCS96_1B}, - {"ei", MCS96_1B}, - {"clrvt", MCS96_1B}, - {"nop", MCS96_1B}, - {"invalid", MCS96_1B}, - {"rst", MCS96_1B} + { "addb", MCS96_4B|MCS96_3OP}, + { "addb", MCS96_4B|MCS96_3OP}, + { "addb", MCS96_4B|MCS96_3OP}, + { "addb", MCS96_5B_OR_6B|MCS96_3OP}, + { "subb", MCS96_4B|MCS96_3OP}, + { "subb", MCS96_4B|MCS96_3OP}, + { "subb", MCS96_4B|MCS96_3OP}, + { "subb", MCS96_5B_OR_6B|MCS96_3OP}, + { "mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, + { "mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, + { "mulub", MCS96_4B|MCS96_3OP|MCS96_FE}, + { "mulub", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x5f + { "and", MCS96_3B|MCS96_2OP}, + { "and", MCS96_4B|MCS96_2OP}, + { "and", MCS96_3B|MCS96_2OP}, + { "and", MCS96_4B_OR_5B|MCS96_2OP}, + { "add", MCS96_3B|MCS96_2OP}, + { "add", MCS96_4B|MCS96_2OP}, + { "add", MCS96_3B|MCS96_2OP}, + { "add", MCS96_4B_OR_5B|MCS96_2OP}, + { "sub", MCS96_3B|MCS96_2OP}, + { "sub", MCS96_4B|MCS96_2OP}, + { "sub", MCS96_3B|MCS96_2OP}, + { "sub", MCS96_4B_OR_5B|MCS96_2OP}, + { "mulu", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "mulu", MCS96_4B|MCS96_2OP|MCS96_FE}, + { "mulu", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "mulu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x6f + { "andb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "andb", MCS96_3B|MCS96_2OP}, + { "andb", MCS96_3B|MCS96_2OP}, + { "andb", MCS96_4B_OR_5B|MCS96_2OP}, //again i don't trust the data-sheet here + { "addb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "addb", MCS96_3B|MCS96_2OP}, + { "addb", MCS96_3B|MCS96_2OP}, + { "addb", MCS96_4B_OR_5B|MCS96_2OP}, + { "subb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "subb", MCS96_3B|MCS96_2OP}, + { "subb", MCS96_3B|MCS96_2OP}, + { "subb", MCS96_4B_OR_5B|MCS96_2OP}, + { "mulub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8}, + { "mulub", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "mulub", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "mulub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x7f + { "or", MCS96_3B|MCS96_2OP}, + { "or", MCS96_4B|MCS96_2OP}, + { "or", MCS96_3B|MCS96_2OP}, + { "or", MCS96_4B_OR_5B|MCS96_2OP}, + { "xor", MCS96_3B|MCS96_2OP}, + { "xor", MCS96_4B|MCS96_2OP}, + { "xor", MCS96_3B|MCS96_2OP}, + { "xor", MCS96_4B_OR_5B|MCS96_2OP}, + { "cmp", MCS96_3B|MCS96_2OP}, + { "cmp", MCS96_4B|MCS96_2OP}, + { "cmp", MCS96_3B|MCS96_2OP}, + { "cmp", MCS96_4B_OR_5B|MCS96_2OP}, + { "divu", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "divu", MCS96_4B|MCS96_2OP|MCS96_FE}, + { "divu", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "divu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x8f + { "orb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "orb", MCS96_3B|MCS96_2OP}, + { "orb", MCS96_3B|MCS96_2OP}, + { "orb", MCS96_4B_OR_5B|MCS96_2OP}, + { "xorb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "xorb", MCS96_3B|MCS96_2OP}, + { "xorb", MCS96_3B|MCS96_2OP}, + { "xorb", MCS96_4B_OR_5B|MCS96_2OP}, + { "cmpb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "cmpb", MCS96_3B|MCS96_2OP}, + { "cmpb", MCS96_3B|MCS96_2OP}, + { "cmpb", MCS96_4B_OR_5B|MCS96_2OP}, + { "divub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8}, + { "divub", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "divub", MCS96_3B|MCS96_2OP|MCS96_FE}, + { "divub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x9f + { "ld", MCS96_3B|MCS96_2OP}, + { "ld", MCS96_4B|MCS96_2OP}, + { "ld", MCS96_3B|MCS96_2OP}, + { "ld", MCS96_4B_OR_5B|MCS96_2OP}, + { "addc", MCS96_3B|MCS96_2OP}, + { "addc", MCS96_4B|MCS96_2OP}, + { "addc", MCS96_3B|MCS96_2OP}, + { "addc", MCS96_4B_OR_5B|MCS96_2OP}, + { "subc", MCS96_3B|MCS96_2OP}, + { "subc", MCS96_4B|MCS96_2OP}, + { "subc", MCS96_3B|MCS96_2OP}, + { "subc", MCS96_4B_OR_5B|MCS96_2OP}, + { "lbsze", MCS96_3B|MCS96_2OP}, + { "lbsze", MCS96_3B|MCS96_2OP}, + { "lbsze", MCS96_3B|MCS96_2OP}, + { "lbsze", MCS96_4B_OR_5B|MCS96_2OP}, //0xaf + { "ldb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "ldb", MCS96_3B|MCS96_2OP}, + { "ldb", MCS96_3B|MCS96_2OP}, + { "ldb", MCS96_4B_OR_5B|MCS96_2OP}, + { "addcb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "addcb", MCS96_3B|MCS96_2OP}, + { "addcb", MCS96_3B|MCS96_2OP}, + { "addcb", MCS96_4B_OR_5B|MCS96_2OP}, + { "subcb", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "subcb", MCS96_3B|MCS96_2OP}, + { "subcb", MCS96_3B|MCS96_2OP}, + { "subcb", MCS96_4B_OR_5B|MCS96_2OP}, + { "ldbse", MCS96_3B|MCS96_2OP|MCS96_REG_8}, + { "ldbse", MCS96_3B|MCS96_2OP}, + { "ldbse", MCS96_3B|MCS96_2OP}, + { "ldbse", MCS96_4B_OR_5B|MCS96_2OP}, //0xbf + { "st", MCS96_3B|MCS96_2OP}, + { "invalid", MCS96_1B}, + { "st", MCS96_3B|MCS96_2OP}, + { "st", MCS96_4B_OR_5B|MCS96_2OP}, + { "stb", MCS96_3B|MCS96_2OP}, + { "invalid", MCS96_1B}, + { "stb", MCS96_3B|MCS96_2OP}, + { "stb", MCS96_4B_OR_5B|MCS96_2OP}, + { "push", MCS96_2B}, + { "push", MCS96_3B}, + { "push", MCS96_2B}, + { "push", MCS96_3B_OR_4B}, + { "pop", MCS96_2B}, + { "invalid", MCS96_1B}, + { "pop", MCS96_2B}, + { "pop", MCS96_3B_OR_4B}, //0xcf + { "jnst", MCS96_2B}, + { "jnh", MCS96_2B}, + { "jgt", MCS96_2B}, + { "jnc", MCS96_2B}, + { "jnvt", MCS96_2B}, + { "jnv", MCS96_2B}, + { "jge", MCS96_2B}, + { "jne", MCS96_2B}, + { "jst", MCS96_2B}, + { "jh", MCS96_2B}, + { "jle", MCS96_2B}, + { "jc", MCS96_2B}, + { "jvt", MCS96_2B}, + { "jv", MCS96_2B}, + { "jlt", MCS96_2B}, + { "je", MCS96_2B}, //0xdf + { "djnz", MCS96_3B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "br", MCS96_2B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "ljmp", MCS96_3B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "lcall", MCS96_3B}, //0xef + { "ret", MCS96_1B}, + { "invalid", MCS96_1B}, + { "pushf", MCS96_1B}, + { "popf", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "invalid", MCS96_1B}, + { "trap", MCS96_1B}, + { "clrc", MCS96_1B}, + { "setc", MCS96_1B}, + { "di", MCS96_1B}, + { "ei", MCS96_1B}, + { "clrvt", MCS96_1B}, + { "nop", MCS96_1B}, + { "invalid", MCS96_1B}, + { "rst", MCS96_1B} }; static const char * const mcs96_fe_op[] = { "mul", "mulb", "mul", "mulb", "div", "divb", "invalid", "invalid" }; diff --git a/libr/anal/arch/snes/snes_op_table.h b/libr/anal/arch/snes/snes_op_table.h index b32a18d95c..689c474a05 100644 --- a/libr/anal/arch/snes/snes_op_table.h +++ b/libr/anal/arch/snes/snes_op_table.h @@ -30,262 +30,262 @@ static int snes_op_get_size(int M_flag, int X_flag, snes_op_t* op) { } static snes_op_t snes_op[]={ -{"brk 0x%02x", SNES_OP_16BIT}, -{"ora (0x%02x,x)", SNES_OP_16BIT}, -{"cop 0x%02x", SNES_OP_16BIT}, -{"ora 0x%02x,s", SNES_OP_16BIT}, -{"tsb 0x%02x", SNES_OP_16BIT}, -{"ora 0x%02x", SNES_OP_16BIT}, -{"asl 0x%02x", SNES_OP_16BIT}, -{"ora [0x%02x]", SNES_OP_16BIT}, -{"php", SNES_OP_8BIT}, -{"ora", SNES_OP_IMM_M}, -{"asl a", SNES_OP_8BIT}, -{"phd", SNES_OP_8BIT}, -{"tsb 0x%04x", SNES_OP_24BIT}, -{"ora 0x%04x", SNES_OP_24BIT}, -{"asl 0x%04x", SNES_OP_24BIT}, -{"ora 0x%06x", SNES_OP_32BIT}, -{"bpl 0x%06x", SNES_OP_16BIT}, -{"ora (0x%02x),y", SNES_OP_16BIT}, -{"ora (0x%02x)", SNES_OP_16BIT}, -{"ora (0x%02x,s),y", SNES_OP_16BIT}, -{"trb 0x%02x", SNES_OP_16BIT}, -{"ora 0x%02x,x", SNES_OP_16BIT}, -{"asl 0x%02x,x", SNES_OP_16BIT}, -{"ora [0x%02x],y", SNES_OP_16BIT}, -{"clc", SNES_OP_8BIT}, -{"ora 0x%04x,y", SNES_OP_24BIT}, -{"inc a", SNES_OP_8BIT}, -{"tas", SNES_OP_8BIT}, -{"trb 0x%04x", SNES_OP_24BIT}, -{"ora 0x%04x,x", SNES_OP_24BIT}, -{"asl 0x%04x,x", SNES_OP_24BIT}, -{"ora 0x%06x,x", SNES_OP_32BIT}, -{"jsr 0x%04x", SNES_OP_24BIT}, -{"and (0x%02x,x)", SNES_OP_16BIT}, -{"jsr 0x%06x", SNES_OP_32BIT}, -{"and 0x%02x,s", SNES_OP_16BIT}, -{"bit 0x%02x", SNES_OP_16BIT}, -{"and 0x%02x", SNES_OP_16BIT}, -{"rol 0x%02x", SNES_OP_16BIT}, -{"and [0x%02x]", SNES_OP_16BIT}, -{"plp", SNES_OP_8BIT}, -{"and", SNES_OP_IMM_M}, -{"rol a", SNES_OP_8BIT}, -{"pld", SNES_OP_8BIT}, -{"bit 0x%04x", SNES_OP_24BIT}, -{"and 0x%04x", SNES_OP_24BIT}, -{"rol 0x%04x", SNES_OP_24BIT}, -{"and 0x%06x", SNES_OP_32BIT}, -{"bmi 0x%06x", SNES_OP_16BIT}, -{"and (0x%02x),y", SNES_OP_16BIT}, -{"and (0x%02x)", SNES_OP_16BIT}, -{"and (0x%02x,s),y", SNES_OP_16BIT}, -{"bit 0x%02x,x", SNES_OP_16BIT}, -{"and 0x%02x,x", SNES_OP_16BIT}, -{"rol 0x%02x,x", SNES_OP_16BIT}, -{"and [0x%02x],y", SNES_OP_16BIT}, -{"sec", SNES_OP_8BIT}, -{"and 0x%04x,y", SNES_OP_24BIT}, -{"dec a", SNES_OP_8BIT}, -{"tsa", SNES_OP_8BIT}, -{"bit 0x%04x,x", SNES_OP_24BIT}, -{"and 0x%04x,x", SNES_OP_24BIT}, -{"rol 0x%04x,x", SNES_OP_24BIT}, -{"and 0x%06x,x", SNES_OP_32BIT}, -{"rti", SNES_OP_8BIT}, -{"eor (0x%02x,x)", SNES_OP_16BIT}, -{"wdm 0x%02X", SNES_OP_16BIT}, -{"eor 0x%02x,s", SNES_OP_16BIT}, -{"mvp 0x%02x,0x%02x", SNES_OP_24BIT}, -{"eor 0x%02x", SNES_OP_16BIT}, -{"lsr 0x%02x", SNES_OP_16BIT}, -{"eor [0x%02x]", SNES_OP_16BIT}, -{"pha", SNES_OP_8BIT}, -{"eor", SNES_OP_IMM_M}, -{"lsr a", SNES_OP_8BIT}, -{"phk", SNES_OP_8BIT}, -{"jmp 0x%04x", SNES_OP_24BIT}, -{"eor 0x%04x", SNES_OP_24BIT}, -{"lsr 0x%04x", SNES_OP_24BIT}, -{"eor 0x%06x", SNES_OP_32BIT}, -{"bvc 0x%06x", SNES_OP_16BIT}, -{"eor (0x%02x),y", SNES_OP_16BIT}, -{"eor (0x%02x)", SNES_OP_16BIT}, -{"eor (0x%02x,s),y", SNES_OP_16BIT}, -{"mvn 0x%02x,0x%02x", SNES_OP_16BIT}, -{"eor 0x%02x,x", SNES_OP_16BIT}, -{"lsr 0x%02x,x", SNES_OP_16BIT}, -{"eor [0x%02x],y", SNES_OP_16BIT}, -{"cli", SNES_OP_8BIT}, -{"eor 0x%04x,y", SNES_OP_24BIT}, -{"phy", SNES_OP_8BIT}, -{"tad", SNES_OP_8BIT}, -{"jmp 0x%06x", SNES_OP_32BIT}, -{"eor 0x%04x,x", SNES_OP_24BIT}, -{"lsr 0x%04x,x", SNES_OP_24BIT}, -{"eor 0x%06x,x", SNES_OP_32BIT}, -{"rts", SNES_OP_8BIT}, -{"adc (0x%02x,x)", SNES_OP_16BIT}, -{"per 0x%04x", SNES_OP_24BIT}, -{"adc 0x%02x,s", SNES_OP_16BIT}, -{"stz 0x%02x", SNES_OP_16BIT}, -{"adc 0x%02x", SNES_OP_16BIT}, -{"ror 0x%02x", SNES_OP_16BIT}, -{"adc [0x%02x]", SNES_OP_16BIT}, -{"pla", SNES_OP_8BIT}, -{"adc", SNES_OP_IMM_M}, -{"ror a", SNES_OP_8BIT}, -{"rtl", SNES_OP_8BIT}, -{"jmp (0x%04x)", SNES_OP_24BIT}, -{"adc 0x%04x", SNES_OP_24BIT}, -{"ror 0x%04x", SNES_OP_24BIT}, -{"adc 0x%06x", SNES_OP_32BIT}, -{"bvs 0x%06x", SNES_OP_16BIT}, -{"adc (0x%02x),y", SNES_OP_16BIT}, -{"adc (0x%02x)", SNES_OP_16BIT}, -{"adc (0x%02x,s),y", SNES_OP_16BIT}, -{"stz 0x%02x,x", SNES_OP_16BIT}, -{"adc 0x%02x,x", SNES_OP_16BIT}, -{"ror 0x%02x,x", SNES_OP_16BIT}, -{"adc [0x%02x],y", SNES_OP_16BIT}, -{"sei", SNES_OP_8BIT}, -{"adc 0x%04x,y", SNES_OP_24BIT}, -{"ply", SNES_OP_8BIT}, -{"tda", SNES_OP_8BIT}, -{"jmp (0x%04x,x)", SNES_OP_24BIT}, -{"adc 0x%04x,x", SNES_OP_24BIT}, -{"ror 0x%04x,x", SNES_OP_24BIT}, -{"adc 0x%06x,x", SNES_OP_32BIT}, -{"bra 0x%06x", SNES_OP_16BIT}, -{"sta (0x%02x,x)", SNES_OP_16BIT}, -{"brl 0x%06x", SNES_OP_24BIT}, -{"sta 0x%02x,s", SNES_OP_16BIT}, -{"sty 0x%02x", SNES_OP_16BIT}, -{"sta 0x%02x", SNES_OP_16BIT}, -{"stx 0x%02x", SNES_OP_16BIT}, -{"sta [0x%02x]", SNES_OP_16BIT}, -{"dey", SNES_OP_8BIT}, -{"bit", SNES_OP_IMM_M}, -{"txa", SNES_OP_8BIT}, -{"phb", SNES_OP_8BIT}, -{"sty 0x%04x", SNES_OP_24BIT}, -{"sta 0x%04x", SNES_OP_24BIT}, -{"stx 0x%04x", SNES_OP_24BIT}, -{"sta 0x%06x", SNES_OP_32BIT}, -{"bcc 0x%06x", SNES_OP_16BIT}, -{"sta (0x%02x),y", SNES_OP_16BIT}, -{"sta (0x%02x)", SNES_OP_16BIT}, -{"sta (0x%02x,s),y", SNES_OP_16BIT}, -{"sty 0x%02x,x", SNES_OP_16BIT}, -{"sta 0x%02x,x", SNES_OP_16BIT}, -{"stx 0x%02x,y", SNES_OP_16BIT}, -{"sta [0x%02x],y", SNES_OP_16BIT}, -{"tya", SNES_OP_8BIT}, -{"sta 0x%04x,y", SNES_OP_24BIT}, -{"txs", SNES_OP_8BIT}, -{"txy", SNES_OP_8BIT}, -{"stz 0x%04x", SNES_OP_24BIT}, -{"sta 0x%04x,x", SNES_OP_24BIT}, -{"stz 0x%04x,x", SNES_OP_24BIT}, -{"sta 0x%06x,x", SNES_OP_32BIT}, -{"ldy", SNES_OP_IMM_X}, -{"lda (0x%02x,x)", SNES_OP_16BIT}, -{"ldx", SNES_OP_IMM_X}, -{"lda 0x%02x,s", SNES_OP_16BIT}, -{"ldy 0x%02x", SNES_OP_16BIT}, -{"lda 0x%02x", SNES_OP_16BIT}, -{"ldx 0x%02x", SNES_OP_16BIT}, -{"lda [0x%02x]", SNES_OP_16BIT}, -{"tay", SNES_OP_8BIT}, -{"lda", SNES_OP_IMM_M}, -{"tax", SNES_OP_8BIT}, -{"plb", SNES_OP_8BIT}, -{"ldy 0x%04x", SNES_OP_24BIT}, -{"lda 0x%04x", SNES_OP_24BIT}, -{"ldx 0x%04x", SNES_OP_24BIT}, -{"lda 0x%06x", SNES_OP_32BIT}, -{"bcs 0x%06x", SNES_OP_16BIT}, -{"lda (0x%02x),y", SNES_OP_16BIT}, -{"lda (0x%02x)", SNES_OP_16BIT}, -{"lda (0x%02x,s),y", SNES_OP_16BIT}, -{"ldy 0x%02x,x", SNES_OP_16BIT}, -{"lda 0x%02x,x", SNES_OP_16BIT}, -{"ldx 0x%02x,y", SNES_OP_16BIT}, -{"lda [0x%02x],y", SNES_OP_16BIT}, -{"clv", SNES_OP_8BIT}, -{"lda 0x%04x,y", SNES_OP_24BIT}, -{"tsx", SNES_OP_8BIT}, -{"tyx", SNES_OP_8BIT}, -{"ldy 0x%04x,x", SNES_OP_24BIT}, -{"lda 0x%04x,x", SNES_OP_24BIT}, -{"ldx 0x%04x,y", SNES_OP_24BIT}, -{"lda 0x%06x,x", SNES_OP_32BIT}, -{"cpy", SNES_OP_IMM_X}, -{"cmp (0x%02x,x)", SNES_OP_16BIT}, -{"rep #0x%02x", SNES_OP_16BIT}, -{"cmp 0x%02x,s", SNES_OP_16BIT}, -{"cpy 0x%02x", SNES_OP_16BIT}, -{"cmp 0x%02x", SNES_OP_16BIT}, -{"dec 0x%02x", SNES_OP_16BIT}, -{"cmp [0x%02x]", SNES_OP_16BIT}, -{"iny", SNES_OP_8BIT}, -{"cmp", SNES_OP_IMM_M}, -{"dex", SNES_OP_8BIT}, -{"wai", SNES_OP_8BIT}, -{"cpy 0x%04x", SNES_OP_24BIT}, -{"cmp 0x%04x", SNES_OP_24BIT}, -{"dec 0x%04x", SNES_OP_24BIT}, -{"cmp 0x%06x", SNES_OP_32BIT}, -{"bne 0x%06x", SNES_OP_16BIT}, -{"cmp (0x%02x),y", SNES_OP_16BIT}, -{"cmp (0x%02x)", SNES_OP_16BIT}, -{"cmp (0x%02x,s),y", SNES_OP_16BIT}, -{"pei (0x%02x)", SNES_OP_16BIT}, -{"cmp 0x%02x,x", SNES_OP_16BIT}, -{"dec 0x%02x,x", SNES_OP_16BIT}, -{"cmp [0x%02x],y", SNES_OP_16BIT}, -{"cld", SNES_OP_8BIT}, -{"cmp 0x%04x,y", SNES_OP_24BIT}, -{"phx", SNES_OP_8BIT}, -{"stp", SNES_OP_8BIT}, -{"jmp [0x%04x]", SNES_OP_24BIT}, -{"cmp 0x%04x,x", SNES_OP_24BIT}, -{"dec 0x%04x,x", SNES_OP_24BIT}, -{"cmp 0x%06x,x", SNES_OP_32BIT}, -{"cpx", SNES_OP_IMM_X}, -{"sbc (0x%02x,x)", SNES_OP_16BIT}, -{"sep #0x%02x", SNES_OP_16BIT}, -{"sbc 0x%02x,s", SNES_OP_16BIT}, -{"cpx 0x%02x", SNES_OP_16BIT}, -{"sbc 0x%02x", SNES_OP_16BIT}, -{"inc 0x%02x", SNES_OP_16BIT}, -{"sbc [0x%02x]", SNES_OP_16BIT}, -{"inx", SNES_OP_8BIT}, -{"sbc", SNES_OP_IMM_M}, -{"nop", SNES_OP_8BIT}, -{"swa", SNES_OP_8BIT}, -{"cpx 0x%04x", SNES_OP_24BIT}, -{"sbc 0x%04x", SNES_OP_24BIT}, -{"inc 0x%04x", SNES_OP_24BIT}, -{"sbc 0x%06x", SNES_OP_32BIT}, -{"beq 0x%06x", SNES_OP_16BIT}, -{"sbc (0x%02x),y", SNES_OP_16BIT}, -{"sbc (0x%02x)", SNES_OP_16BIT}, -{"sbc (0x%02x,s),y", SNES_OP_16BIT}, -{"pea 0x%04x", SNES_OP_24BIT}, -{"sbc 0x%02x,x", SNES_OP_16BIT}, -{"inc 0x%02x,x", SNES_OP_16BIT}, -{"sbc [0x%02x],y", SNES_OP_16BIT}, -{"sed", SNES_OP_8BIT}, -{"sbc 0x%04x,y", SNES_OP_24BIT}, -{"plx", SNES_OP_8BIT}, -{"xce", SNES_OP_8BIT}, -{"jsr (0x%04x,x)", SNES_OP_24BIT}, -{"sbc 0x%04x,x", SNES_OP_24BIT}, -{"inc 0x%04x,x", SNES_OP_24BIT}, -{"sbc 0x%06x,x", SNES_OP_32BIT} +{ "brk 0x%02x", SNES_OP_16BIT}, +{ "ora (0x%02x,x)", SNES_OP_16BIT}, +{ "cop 0x%02x", SNES_OP_16BIT}, +{ "ora 0x%02x,s", SNES_OP_16BIT}, +{ "tsb 0x%02x", SNES_OP_16BIT}, +{ "ora 0x%02x", SNES_OP_16BIT}, +{ "asl 0x%02x", SNES_OP_16BIT}, +{ "ora [0x%02x]", SNES_OP_16BIT}, +{ "php", SNES_OP_8BIT}, +{ "ora", SNES_OP_IMM_M}, +{ "asl a", SNES_OP_8BIT}, +{ "phd", SNES_OP_8BIT}, +{ "tsb 0x%04x", SNES_OP_24BIT}, +{ "ora 0x%04x", SNES_OP_24BIT}, +{ "asl 0x%04x", SNES_OP_24BIT}, +{ "ora 0x%06x", SNES_OP_32BIT}, +{ "bpl 0x%06x", SNES_OP_16BIT}, +{ "ora (0x%02x),y", SNES_OP_16BIT}, +{ "ora (0x%02x)", SNES_OP_16BIT}, +{ "ora (0x%02x,s),y", SNES_OP_16BIT}, +{ "trb 0x%02x", SNES_OP_16BIT}, +{ "ora 0x%02x,x", SNES_OP_16BIT}, +{ "asl 0x%02x,x", SNES_OP_16BIT}, +{ "ora [0x%02x],y", SNES_OP_16BIT}, +{ "clc", SNES_OP_8BIT}, +{ "ora 0x%04x,y", SNES_OP_24BIT}, +{ "inc a", SNES_OP_8BIT}, +{ "tas", SNES_OP_8BIT}, +{ "trb 0x%04x", SNES_OP_24BIT}, +{ "ora 0x%04x,x", SNES_OP_24BIT}, +{ "asl 0x%04x,x", SNES_OP_24BIT}, +{ "ora 0x%06x,x", SNES_OP_32BIT}, +{ "jsr 0x%04x", SNES_OP_24BIT}, +{ "and (0x%02x,x)", SNES_OP_16BIT}, +{ "jsr 0x%06x", SNES_OP_32BIT}, +{ "and 0x%02x,s", SNES_OP_16BIT}, +{ "bit 0x%02x", SNES_OP_16BIT}, +{ "and 0x%02x", SNES_OP_16BIT}, +{ "rol 0x%02x", SNES_OP_16BIT}, +{ "and [0x%02x]", SNES_OP_16BIT}, +{ "plp", SNES_OP_8BIT}, +{ "and", SNES_OP_IMM_M}, +{ "rol a", SNES_OP_8BIT}, +{ "pld", SNES_OP_8BIT}, +{ "bit 0x%04x", SNES_OP_24BIT}, +{ "and 0x%04x", SNES_OP_24BIT}, +{ "rol 0x%04x", SNES_OP_24BIT}, +{ "and 0x%06x", SNES_OP_32BIT}, +{ "bmi 0x%06x", SNES_OP_16BIT}, +{ "and (0x%02x),y", SNES_OP_16BIT}, +{ "and (0x%02x)", SNES_OP_16BIT}, +{ "and (0x%02x,s),y", SNES_OP_16BIT}, +{ "bit 0x%02x,x", SNES_OP_16BIT}, +{ "and 0x%02x,x", SNES_OP_16BIT}, +{ "rol 0x%02x,x", SNES_OP_16BIT}, +{ "and [0x%02x],y", SNES_OP_16BIT}, +{ "sec", SNES_OP_8BIT}, +{ "and 0x%04x,y", SNES_OP_24BIT}, +{ "dec a", SNES_OP_8BIT}, +{ "tsa", SNES_OP_8BIT}, +{ "bit 0x%04x,x", SNES_OP_24BIT}, +{ "and 0x%04x,x", SNES_OP_24BIT}, +{ "rol 0x%04x,x", SNES_OP_24BIT}, +{ "and 0x%06x,x", SNES_OP_32BIT}, +{ "rti", SNES_OP_8BIT}, +{ "eor (0x%02x,x)", SNES_OP_16BIT}, +{ "wdm 0x%02X", SNES_OP_16BIT}, +{ "eor 0x%02x,s", SNES_OP_16BIT}, +{ "mvp 0x%02x,0x%02x", SNES_OP_24BIT}, +{ "eor 0x%02x", SNES_OP_16BIT}, +{ "lsr 0x%02x", SNES_OP_16BIT}, +{ "eor [0x%02x]", SNES_OP_16BIT}, +{ "pha", SNES_OP_8BIT}, +{ "eor", SNES_OP_IMM_M}, +{ "lsr a", SNES_OP_8BIT}, +{ "phk", SNES_OP_8BIT}, +{ "jmp 0x%04x", SNES_OP_24BIT}, +{ "eor 0x%04x", SNES_OP_24BIT}, +{ "lsr 0x%04x", SNES_OP_24BIT}, +{ "eor 0x%06x", SNES_OP_32BIT}, +{ "bvc 0x%06x", SNES_OP_16BIT}, +{ "eor (0x%02x),y", SNES_OP_16BIT}, +{ "eor (0x%02x)", SNES_OP_16BIT}, +{ "eor (0x%02x,s),y", SNES_OP_16BIT}, +{ "mvn 0x%02x,0x%02x", SNES_OP_16BIT}, +{ "eor 0x%02x,x", SNES_OP_16BIT}, +{ "lsr 0x%02x,x", SNES_OP_16BIT}, +{ "eor [0x%02x],y", SNES_OP_16BIT}, +{ "cli", SNES_OP_8BIT}, +{ "eor 0x%04x,y", SNES_OP_24BIT}, +{ "phy", SNES_OP_8BIT}, +{ "tad", SNES_OP_8BIT}, +{ "jmp 0x%06x", SNES_OP_32BIT}, +{ "eor 0x%04x,x", SNES_OP_24BIT}, +{ "lsr 0x%04x,x", SNES_OP_24BIT}, +{ "eor 0x%06x,x", SNES_OP_32BIT}, +{ "rts", SNES_OP_8BIT}, +{ "adc (0x%02x,x)", SNES_OP_16BIT}, +{ "per 0x%04x", SNES_OP_24BIT}, +{ "adc 0x%02x,s", SNES_OP_16BIT}, +{ "stz 0x%02x", SNES_OP_16BIT}, +{ "adc 0x%02x", SNES_OP_16BIT}, +{ "ror 0x%02x", SNES_OP_16BIT}, +{ "adc [0x%02x]", SNES_OP_16BIT}, +{ "pla", SNES_OP_8BIT}, +{ "adc", SNES_OP_IMM_M}, +{ "ror a", SNES_OP_8BIT}, +{ "rtl", SNES_OP_8BIT}, +{ "jmp (0x%04x)", SNES_OP_24BIT}, +{ "adc 0x%04x", SNES_OP_24BIT}, +{ "ror 0x%04x", SNES_OP_24BIT}, +{ "adc 0x%06x", SNES_OP_32BIT}, +{ "bvs 0x%06x", SNES_OP_16BIT}, +{ "adc (0x%02x),y", SNES_OP_16BIT}, +{ "adc (0x%02x)", SNES_OP_16BIT}, +{ "adc (0x%02x,s),y", SNES_OP_16BIT}, +{ "stz 0x%02x,x", SNES_OP_16BIT}, +{ "adc 0x%02x,x", SNES_OP_16BIT}, +{ "ror 0x%02x,x", SNES_OP_16BIT}, +{ "adc [0x%02x],y", SNES_OP_16BIT}, +{ "sei", SNES_OP_8BIT}, +{ "adc 0x%04x,y", SNES_OP_24BIT}, +{ "ply", SNES_OP_8BIT}, +{ "tda", SNES_OP_8BIT}, +{ "jmp (0x%04x,x)", SNES_OP_24BIT}, +{ "adc 0x%04x,x", SNES_OP_24BIT}, +{ "ror 0x%04x,x", SNES_OP_24BIT}, +{ "adc 0x%06x,x", SNES_OP_32BIT}, +{ "bra 0x%06x", SNES_OP_16BIT}, +{ "sta (0x%02x,x)", SNES_OP_16BIT}, +{ "brl 0x%06x", SNES_OP_24BIT}, +{ "sta 0x%02x,s", SNES_OP_16BIT}, +{ "sty 0x%02x", SNES_OP_16BIT}, +{ "sta 0x%02x", SNES_OP_16BIT}, +{ "stx 0x%02x", SNES_OP_16BIT}, +{ "sta [0x%02x]", SNES_OP_16BIT}, +{ "dey", SNES_OP_8BIT}, +{ "bit", SNES_OP_IMM_M}, +{ "txa", SNES_OP_8BIT}, +{ "phb", SNES_OP_8BIT}, +{ "sty 0x%04x", SNES_OP_24BIT}, +{ "sta 0x%04x", SNES_OP_24BIT}, +{ "stx 0x%04x", SNES_OP_24BIT}, +{ "sta 0x%06x", SNES_OP_32BIT}, +{ "bcc 0x%06x", SNES_OP_16BIT}, +{ "sta (0x%02x),y", SNES_OP_16BIT}, +{ "sta (0x%02x)", SNES_OP_16BIT}, +{ "sta (0x%02x,s),y", SNES_OP_16BIT}, +{ "sty 0x%02x,x", SNES_OP_16BIT}, +{ "sta 0x%02x,x", SNES_OP_16BIT}, +{ "stx 0x%02x,y", SNES_OP_16BIT}, +{ "sta [0x%02x],y", SNES_OP_16BIT}, +{ "tya", SNES_OP_8BIT}, +{ "sta 0x%04x,y", SNES_OP_24BIT}, +{ "txs", SNES_OP_8BIT}, +{ "txy", SNES_OP_8BIT}, +{ "stz 0x%04x", SNES_OP_24BIT}, +{ "sta 0x%04x,x", SNES_OP_24BIT}, +{ "stz 0x%04x,x", SNES_OP_24BIT}, +{ "sta 0x%06x,x", SNES_OP_32BIT}, +{ "ldy", SNES_OP_IMM_X}, +{ "lda (0x%02x,x)", SNES_OP_16BIT}, +{ "ldx", SNES_OP_IMM_X}, +{ "lda 0x%02x,s", SNES_OP_16BIT}, +{ "ldy 0x%02x", SNES_OP_16BIT}, +{ "lda 0x%02x", SNES_OP_16BIT}, +{ "ldx 0x%02x", SNES_OP_16BIT}, +{ "lda [0x%02x]", SNES_OP_16BIT}, +{ "tay", SNES_OP_8BIT}, +{ "lda", SNES_OP_IMM_M}, +{ "tax", SNES_OP_8BIT}, +{ "plb", SNES_OP_8BIT}, +{ "ldy 0x%04x", SNES_OP_24BIT}, +{ "lda 0x%04x", SNES_OP_24BIT}, +{ "ldx 0x%04x", SNES_OP_24BIT}, +{ "lda 0x%06x", SNES_OP_32BIT}, +{ "bcs 0x%06x", SNES_OP_16BIT}, +{ "lda (0x%02x),y", SNES_OP_16BIT}, +{ "lda (0x%02x)", SNES_OP_16BIT}, +{ "lda (0x%02x,s),y", SNES_OP_16BIT}, +{ "ldy 0x%02x,x", SNES_OP_16BIT}, +{ "lda 0x%02x,x", SNES_OP_16BIT}, +{ "ldx 0x%02x,y", SNES_OP_16BIT}, +{ "lda [0x%02x],y", SNES_OP_16BIT}, +{ "clv", SNES_OP_8BIT}, +{ "lda 0x%04x,y", SNES_OP_24BIT}, +{ "tsx", SNES_OP_8BIT}, +{ "tyx", SNES_OP_8BIT}, +{ "ldy 0x%04x,x", SNES_OP_24BIT}, +{ "lda 0x%04x,x", SNES_OP_24BIT}, +{ "ldx 0x%04x,y", SNES_OP_24BIT}, +{ "lda 0x%06x,x", SNES_OP_32BIT}, +{ "cpy", SNES_OP_IMM_X}, +{ "cmp (0x%02x,x)", SNES_OP_16BIT}, +{ "rep #0x%02x", SNES_OP_16BIT}, +{ "cmp 0x%02x,s", SNES_OP_16BIT}, +{ "cpy 0x%02x", SNES_OP_16BIT}, +{ "cmp 0x%02x", SNES_OP_16BIT}, +{ "dec 0x%02x", SNES_OP_16BIT}, +{ "cmp [0x%02x]", SNES_OP_16BIT}, +{ "iny", SNES_OP_8BIT}, +{ "cmp", SNES_OP_IMM_M}, +{ "dex", SNES_OP_8BIT}, +{ "wai", SNES_OP_8BIT}, +{ "cpy 0x%04x", SNES_OP_24BIT}, +{ "cmp 0x%04x", SNES_OP_24BIT}, +{ "dec 0x%04x", SNES_OP_24BIT}, +{ "cmp 0x%06x", SNES_OP_32BIT}, +{ "bne 0x%06x", SNES_OP_16BIT}, +{ "cmp (0x%02x),y", SNES_OP_16BIT}, +{ "cmp (0x%02x)", SNES_OP_16BIT}, +{ "cmp (0x%02x,s),y", SNES_OP_16BIT}, +{ "pei (0x%02x)", SNES_OP_16BIT}, +{ "cmp 0x%02x,x", SNES_OP_16BIT}, +{ "dec 0x%02x,x", SNES_OP_16BIT}, +{ "cmp [0x%02x],y", SNES_OP_16BIT}, +{ "cld", SNES_OP_8BIT}, +{ "cmp 0x%04x,y", SNES_OP_24BIT}, +{ "phx", SNES_OP_8BIT}, +{ "stp", SNES_OP_8BIT}, +{ "jmp [0x%04x]", SNES_OP_24BIT}, +{ "cmp 0x%04x,x", SNES_OP_24BIT}, +{ "dec 0x%04x,x", SNES_OP_24BIT}, +{ "cmp 0x%06x,x", SNES_OP_32BIT}, +{ "cpx", SNES_OP_IMM_X}, +{ "sbc (0x%02x,x)", SNES_OP_16BIT}, +{ "sep #0x%02x", SNES_OP_16BIT}, +{ "sbc 0x%02x,s", SNES_OP_16BIT}, +{ "cpx 0x%02x", SNES_OP_16BIT}, +{ "sbc 0x%02x", SNES_OP_16BIT}, +{ "inc 0x%02x", SNES_OP_16BIT}, +{ "sbc [0x%02x]", SNES_OP_16BIT}, +{ "inx", SNES_OP_8BIT}, +{ "sbc", SNES_OP_IMM_M}, +{ "nop", SNES_OP_8BIT}, +{ "swa", SNES_OP_8BIT}, +{ "cpx 0x%04x", SNES_OP_24BIT}, +{ "sbc 0x%04x", SNES_OP_24BIT}, +{ "inc 0x%04x", SNES_OP_24BIT}, +{ "sbc 0x%06x", SNES_OP_32BIT}, +{ "beq 0x%06x", SNES_OP_16BIT}, +{ "sbc (0x%02x),y", SNES_OP_16BIT}, +{ "sbc (0x%02x)", SNES_OP_16BIT}, +{ "sbc (0x%02x,s),y", SNES_OP_16BIT}, +{ "pea 0x%04x", SNES_OP_24BIT}, +{ "sbc 0x%02x,x", SNES_OP_16BIT}, +{ "inc 0x%02x,x", SNES_OP_16BIT}, +{ "sbc [0x%02x],y", SNES_OP_16BIT}, +{ "sed", SNES_OP_8BIT}, +{ "sbc 0x%04x,y", SNES_OP_24BIT}, +{ "plx", SNES_OP_8BIT}, +{ "xce", SNES_OP_8BIT}, +{ "jsr (0x%04x,x)", SNES_OP_24BIT}, +{ "sbc 0x%04x,x", SNES_OP_24BIT}, +{ "inc 0x%04x,x", SNES_OP_24BIT}, +{ "sbc 0x%06x,x", SNES_OP_32BIT} }; #endif diff --git a/libr/anal/arch/v850/opc.inc b/libr/anal/arch/v850/opc.inc index 1a1d32de24..cd236011e9 100644 --- a/libr/anal/arch/v850/opc.inc +++ b/libr/anal/arch/v850/opc.inc @@ -709,14 +709,14 @@ const struct v850_operand v850_operands[] = { const struct v850_opcode v850_opcodes[] = { /* Standard instructions. */ - { "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+="}, + { "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+=" }, { "add", OP (0x12), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+=" }, { "addi", OP (0x30), OP_MASK, IF6, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+,#2,=" }, { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, V850_CPU_E2_UP }, { "and", OP (0x0a), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,0,o,:=,$s,s,:=,$z,z,:=" }, { "andi", OP (0x36), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,0,o,:=,$s,s,:=,$z,z,:=" }, /* Signed integer. */ - { "bge", BOP (0xe), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,!,?{,#0,PC,:=,}"}, + { "bge", BOP (0xe), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,!,?{,#0,PC,:=,}" }, { "bgt", BOP (0xf), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP }, { "ble", BOP (0x7), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP }, { "blt", BOP (0x6), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,?{,#0,PC,:=,}" }, @@ -827,7 +827,7 @@ const struct v850_opcode v850_opcodes[] = { { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_POP, "DISPOSE,#1" }, { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_DIV, "#2,#1,/,#2,=,#2,#1,%,#3,=" }, - { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0 , R_ANAL_OP_TYPE_DIV, ""}, + { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0 , R_ANAL_OP_TYPE_DIV, "" }, { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_DIV, "" }, { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, V850_CPU_NON0 | V850_CPU_OPTION_EXTENSION, R_ANAL_OP_TYPE_DIV, "" }, { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_DIV, "" }, @@ -852,9 +852,9 @@ const struct v850_opcode v850_opcodes[] = { { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, V850_CPU_E3V5_UP }, { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, V850_CPU_E3V5_UP }, - { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="}, // TODO: Incorrect? PC+4, PC+6 not impl here? - { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="}, - { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,#0,PC,="}, + { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,=" }, // TODO: Incorrect? PC+4, PC+6 not impl here? + { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,=" }, + { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,#0,PC,=" }, /* Gas local alias (not defined in spec). */ { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_RCALL}, /* Gas local alias of jarl imm22 (not defined in spec). */ @@ -1016,7 +1016,7 @@ const struct v850_opcode v850_opcodes[] = { { "sld.w", one (0x0500), one (0x0781), {D8_6U, EP, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD }, { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, V850_CPU_E3V5_UP }, - { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[1],ep,=[1]"}, + { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[1],ep,=[1]" }, { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[2],ep,=[2]" }, { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[4],ep,=[4]" }, { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION }, @@ -1043,7 +1043,7 @@ const struct v850_opcode v850_opcodes[] = { { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE }, { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE }, { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE }, - { "sub", OP (0x0d), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#0,#1,-,="}, + { "sub", OP (0x0d), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#0,#1,-,=" }, { "subr", OP (0x0c), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#1,#0,-,=" }, { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_RJMP }, { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, V850_CPU_NON0 }, @@ -1058,7 +1058,7 @@ const struct v850_opcode v850_opcodes[] = { { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP }, { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0, R_ANAL_OP_TYPE_CMP }, { "xor", OP (0x09), OP_MASK, IF1, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#1,=" }, - { "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#2,="}, + { "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#2,=" }, { "zxb", one (0x0080), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV }, { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV }, diff --git a/libr/anal/arch/vax/vax.h b/libr/anal/arch/vax/vax.h index f5cdd24397..19a281967d 100644 --- a/libr/anal/arch/vax/vax.h +++ b/libr/anal/arch/vax/vax.h @@ -43,340 +43,340 @@ struct vot /* vax opcode text */ static const struct vot votstrs[] = { -{ "halt", {"", 0x00 } }, -{ "nop", {"", 0x01 } }, -{ "rei", {"", 0x02 } }, -{ "bpt", {"", 0x03 } }, -{ "ret", {"", 0x04 } }, -{ "rsb", {"", 0x05 } }, -{ "ldpctx", {"", 0x06 } }, -{ "svpctx", {"", 0x07 } }, -{ "cvtps", {"rwabrwab", 0x08 } }, -{ "cvtsp", {"rwabrwab", 0x09 } }, -{ "index", {"rlrlrlrlrlwl", 0x0a } }, -{ "crc", {"abrlrwab", 0x0b } }, -{ "prober", {"rbrwab", 0x0c } }, -{ "probew", {"rbrwab", 0x0d } }, -{ "insque", {"abab", 0x0e } }, -{ "remque", {"abwl", 0x0f } }, -{ "bsbb", {"bb", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "bneq", {"bb", 0x12 } }, -{ "bnequ", {"bb", 0x12 } }, -{ "beql", {"bb", 0x13 } }, -{ "beqlu", {"bb", 0x13 } }, -{ "bgtr", {"bb", 0x14 } }, -{ "bleq", {"bb", 0x15 } }, -{ "jsb", {"ab", 0x16 } }, -{ "jmp", {"ab", 0x17 } }, -{ "bgeq", {"bb", 0x18 } }, -{ "blss", {"bb", 0x19 } }, -{ "bgtru", {"bb", 0x1a } }, -{ "blequ", {"bb", 0x1b } }, -{ "bvc", {"bb", 0x1c } }, -{ "bvs", {"bb", 0x1d } }, -{ "bcc", {"bb", 0x1e } }, -{ "bgequ", {"bb", 0x1e } }, -{ "blssu", {"bb", 0x1f } }, -{ "bcs", {"bb", 0x1f } }, -{ "addp4", {"rwabrwab", 0x20 } }, -{ "addp6", {"rwabrwabrwab", 0x21 } }, -{ "subp4", {"rwabrwab", 0x22 } }, -{ "subp6", {"rwabrwabrwab", 0x23 } }, -{ "cvtpt", {"rwababrwab", 0x24 } }, -{ "mulp", {"rwabrwabrwab", 0x25 } }, -{ "cvttp", {"rwababrwab", 0x26 } }, -{ "divp", {"rwabrwabrwab", 0x27 } }, -{ "movc3", {"rwabab", 0x28 } }, -{ "cmpc3", {"rwabab", 0x29 } }, -{ "scanc", {"rwababrb", 0x2a } }, -{ "spanc", {"rwababrb", 0x2b } }, -{ "movc5", {"rwabrbrwab", 0x2c } }, -{ "cmpc5", {"rwabrbrwab", 0x2d } }, -{ "movtc", {"rwabrbabrwab", 0x2e } }, -{ "movtuc", {"rwabrbabrwab", 0x2f } }, -{ "bsbw", {"bw", 0x30 } }, -{ "brw", {"bw", 0x31 } }, -{ "cvtwl", {"rwwl", 0x32 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "movp", {"rwabab", 0x34 } }, -{ "cmpp3", {"rwabab", 0x35 } }, -{ "cvtpl", {"rwabwl", 0x36 } }, -{ "cmpp4", {"rwabrwab", 0x37 } }, -{ "editpc", {"rwababab", 0x38 } }, -{ "matchc", {"rwabrwab", 0x39 } }, -{ "locc", {"rbrwab", 0x3a } }, -{ "skpc", {"rbrwab", 0x3b } }, -{ "movzwl", {"rwwl", 0x3c } }, -{ "acbw", {"rwrwmwbw", 0x3d } }, -{ "movaw", {"awwl", 0x3e } }, -{ "pushaw", {"aw", 0x3f } }, -{ "addf2", {"rfmf", 0x40 } }, -{ "addf3", {"rfrfwf", 0x41 } }, -{ "subf2", {"rfmf", 0x42 } }, -{ "subf3", {"rfrfwf", 0x43 } }, -{ "mulf2", {"rfmf", 0x44 } }, -{ "mulf3", {"rfrfwf", 0x45 } }, -{ "divf2", {"rfmf", 0x46 } }, -{ "divf3", {"rfrfwf", 0x47 } }, -{ "cvtfb", {"rfwb", 0x48 } }, -{ "cvtfw", {"rfww", 0x49 } }, -{ "cvtfl", {"rfwl", 0x4a } }, -{ "cvtrfl", {"rfwl", 0x4b } }, -{ "cvtbf", {"rbwf", 0x4c } }, -{ "cvtwf", {"rwwf", 0x4d } }, -{ "cvtlf", {"rlwf", 0x4e } }, -{ "acbf", {"rfrfmfbw", 0x4f } }, -{ "movf", {"rfwf", 0x50 } }, -{ "cmpf", {"rfrf", 0x51 } }, -{ "mnegf", {"rfwf", 0x52 } }, -{ "tstf", {"rf", 0x53 } }, -{ "emodf", {"rfrbrfwlwf", 0x54 } }, -{ "polyf", {"rfrwab", 0x55 } }, -{ "cvtfd", {"rfwd", 0x56 } }, +{ "halt", { "", 0x00 } }, +{ "nop", { "", 0x01 } }, +{ "rei", { "", 0x02 } }, +{ "bpt", { "", 0x03 } }, +{ "ret", { "", 0x04 } }, +{ "rsb", { "", 0x05 } }, +{ "ldpctx", { "", 0x06 } }, +{ "svpctx", { "", 0x07 } }, +{ "cvtps", { "rwabrwab", 0x08 } }, +{ "cvtsp", { "rwabrwab", 0x09 } }, +{ "index", { "rlrlrlrlrlwl", 0x0a } }, +{ "crc", { "abrlrwab", 0x0b } }, +{ "prober", { "rbrwab", 0x0c } }, +{ "probew", { "rbrwab", 0x0d } }, +{ "insque", { "abab", 0x0e } }, +{ "remque", { "abwl", 0x0f } }, +{ "bsbb", { "bb", 0x10 } }, +{ "brb", { "bb", 0x11 } }, +{ "bneq", { "bb", 0x12 } }, +{ "bnequ", { "bb", 0x12 } }, +{ "beql", { "bb", 0x13 } }, +{ "beqlu", { "bb", 0x13 } }, +{ "bgtr", { "bb", 0x14 } }, +{ "bleq", { "bb", 0x15 } }, +{ "jsb", { "ab", 0x16 } }, +{ "jmp", { "ab", 0x17 } }, +{ "bgeq", { "bb", 0x18 } }, +{ "blss", { "bb", 0x19 } }, +{ "bgtru", { "bb", 0x1a } }, +{ "blequ", { "bb", 0x1b } }, +{ "bvc", { "bb", 0x1c } }, +{ "bvs", { "bb", 0x1d } }, +{ "bcc", { "bb", 0x1e } }, +{ "bgequ", { "bb", 0x1e } }, +{ "blssu", { "bb", 0x1f } }, +{ "bcs", { "bb", 0x1f } }, +{ "addp4", { "rwabrwab", 0x20 } }, +{ "addp6", { "rwabrwabrwab", 0x21 } }, +{ "subp4", { "rwabrwab", 0x22 } }, +{ "subp6", { "rwabrwabrwab", 0x23 } }, +{ "cvtpt", { "rwababrwab", 0x24 } }, +{ "mulp", { "rwabrwabrwab", 0x25 } }, +{ "cvttp", { "rwababrwab", 0x26 } }, +{ "divp", { "rwabrwabrwab", 0x27 } }, +{ "movc3", { "rwabab", 0x28 } }, +{ "cmpc3", { "rwabab", 0x29 } }, +{ "scanc", { "rwababrb", 0x2a } }, +{ "spanc", { "rwababrb", 0x2b } }, +{ "movc5", { "rwabrbrwab", 0x2c } }, +{ "cmpc5", { "rwabrbrwab", 0x2d } }, +{ "movtc", { "rwabrbabrwab", 0x2e } }, +{ "movtuc", { "rwabrbabrwab", 0x2f } }, +{ "bsbw", { "bw", 0x30 } }, +{ "brw", { "bw", 0x31 } }, +{ "cvtwl", { "rwwl", 0x32 } }, +{ "cvtwb", { "rwwb", 0x33 } }, +{ "movp", { "rwabab", 0x34 } }, +{ "cmpp3", { "rwabab", 0x35 } }, +{ "cvtpl", { "rwabwl", 0x36 } }, +{ "cmpp4", { "rwabrwab", 0x37 } }, +{ "editpc", { "rwababab", 0x38 } }, +{ "matchc", { "rwabrwab", 0x39 } }, +{ "locc", { "rbrwab", 0x3a } }, +{ "skpc", { "rbrwab", 0x3b } }, +{ "movzwl", { "rwwl", 0x3c } }, +{ "acbw", { "rwrwmwbw", 0x3d } }, +{ "movaw", { "awwl", 0x3e } }, +{ "pushaw", { "aw", 0x3f } }, +{ "addf2", { "rfmf", 0x40 } }, +{ "addf3", { "rfrfwf", 0x41 } }, +{ "subf2", { "rfmf", 0x42 } }, +{ "subf3", { "rfrfwf", 0x43 } }, +{ "mulf2", { "rfmf", 0x44 } }, +{ "mulf3", { "rfrfwf", 0x45 } }, +{ "divf2", { "rfmf", 0x46 } }, +{ "divf3", { "rfrfwf", 0x47 } }, +{ "cvtfb", { "rfwb", 0x48 } }, +{ "cvtfw", { "rfww", 0x49 } }, +{ "cvtfl", { "rfwl", 0x4a } }, +{ "cvtrfl", { "rfwl", 0x4b } }, +{ "cvtbf", { "rbwf", 0x4c } }, +{ "cvtwf", { "rwwf", 0x4d } }, +{ "cvtlf", { "rlwf", 0x4e } }, +{ "acbf", { "rfrfmfbw", 0x4f } }, +{ "movf", { "rfwf", 0x50 } }, +{ "cmpf", { "rfrf", 0x51 } }, +{ "mnegf", { "rfwf", 0x52 } }, +{ "tstf", { "rf", 0x53 } }, +{ "emodf", { "rfrbrfwlwf", 0x54 } }, +{ "polyf", { "rfrwab", 0x55 } }, +{ "cvtfd", { "rfwd", 0x56 } }, /* opcode 57 is not defined yet */ -{ "adawi", {"rwmw", 0x58 } }, +{ "adawi", { "rwmw", 0x58 } }, /* opcode 59 is not defined yet */ /* opcode 5a is not defined yet */ /* opcode 5b is not defined yet */ -{ "insqhi", {"abaq", 0x5c } }, -{ "insqti", {"abaq", 0x5d } }, -{ "remqhi", {"aqwl", 0x5e } }, -{ "remqti", {"aqwl", 0x5f } }, -{ "addd2", {"rdmd", 0x60 } }, -{ "addd3", {"rdrdwd", 0x61 } }, -{ "subd2", {"rdmd", 0x62 } }, -{ "subd3", {"rdrdwd", 0x63 } }, -{ "muld2", {"rdmd", 0x64 } }, -{ "muld3", {"rdrdwd", 0x65 } }, -{ "divd2", {"rdmd", 0x66 } }, -{ "divd3", {"rdrdwd", 0x67 } }, -{ "cvtdb", {"rdwb", 0x68 } }, -{ "cvtdw", {"rdww", 0x69 } }, -{ "cvtdl", {"rdwl", 0x6a } }, -{ "cvtrdl", {"rdwl", 0x6b } }, -{ "cvtbd", {"rbwd", 0x6c } }, -{ "cvtwd", {"rwwd", 0x6d } }, -{ "cvtld", {"rlwd", 0x6e } }, -{ "acbd", {"rdrdmdbw", 0x6f } }, -{ "movd", {"rdwd", 0x70 } }, -{ "cmpd", {"rdrd", 0x71 } }, -{ "mnegd", {"rdwd", 0x72 } }, -{ "tstd", {"rd", 0x73 } }, -{ "emodd", {"rdrbrdwlwd", 0x74 } }, -{ "polyd", {"rdrwab", 0x75 } }, -{ "cvtdf", {"rdwf", 0x76 } }, +{ "insqhi", { "abaq", 0x5c } }, +{ "insqti", { "abaq", 0x5d } }, +{ "remqhi", { "aqwl", 0x5e } }, +{ "remqti", { "aqwl", 0x5f } }, +{ "addd2", { "rdmd", 0x60 } }, +{ "addd3", { "rdrdwd", 0x61 } }, +{ "subd2", { "rdmd", 0x62 } }, +{ "subd3", { "rdrdwd", 0x63 } }, +{ "muld2", { "rdmd", 0x64 } }, +{ "muld3", { "rdrdwd", 0x65 } }, +{ "divd2", { "rdmd", 0x66 } }, +{ "divd3", { "rdrdwd", 0x67 } }, +{ "cvtdb", { "rdwb", 0x68 } }, +{ "cvtdw", { "rdww", 0x69 } }, +{ "cvtdl", { "rdwl", 0x6a } }, +{ "cvtrdl", { "rdwl", 0x6b } }, +{ "cvtbd", { "rbwd", 0x6c } }, +{ "cvtwd", { "rwwd", 0x6d } }, +{ "cvtld", { "rlwd", 0x6e } }, +{ "acbd", { "rdrdmdbw", 0x6f } }, +{ "movd", { "rdwd", 0x70 } }, +{ "cmpd", { "rdrd", 0x71 } }, +{ "mnegd", { "rdwd", 0x72 } }, +{ "tstd", { "rd", 0x73 } }, +{ "emodd", { "rdrbrdwlwd", 0x74 } }, +{ "polyd", { "rdrwab", 0x75 } }, +{ "cvtdf", { "rdwf", 0x76 } }, /* opcode 77 is not defined yet */ -{ "ashl", {"rbrlwl", 0x78 } }, -{ "ashq", {"rbrqwq", 0x79 } }, -{ "emul", {"rlrlrlwq", 0x7a } }, -{ "ediv", {"rlrqwlwl", 0x7b } }, -{ "clrd", {"wd", 0x7c } }, -{ "clrg", {"wg", 0x7c } }, -{ "clrq", {"wd", 0x7c } }, -{ "movq", {"rqwq", 0x7d } }, -{ "movaq", {"aqwl", 0x7e } }, -{ "movad", {"adwl", 0x7e } }, -{ "pushaq", {"aq", 0x7f } }, -{ "pushad", {"ad", 0x7f } }, -{ "addb2", {"rbmb", 0x80 } }, -{ "addb3", {"rbrbwb", 0x81 } }, -{ "subb2", {"rbmb", 0x82 } }, -{ "subb3", {"rbrbwb", 0x83 } }, -{ "mulb2", {"rbmb", 0x84 } }, -{ "mulb3", {"rbrbwb", 0x85 } }, -{ "divb2", {"rbmb", 0x86 } }, -{ "divb3", {"rbrbwb", 0x87 } }, -{ "bisb2", {"rbmb", 0x88 } }, -{ "bisb3", {"rbrbwb", 0x89 } }, -{ "bicb2", {"rbmb", 0x8a } }, -{ "bicb3", {"rbrbwb", 0x8b } }, -{ "xorb2", {"rbmb", 0x8c } }, -{ "xorb3", {"rbrbwb", 0x8d } }, -{ "mnegb", {"rbwb", 0x8e } }, -{ "caseb", {"rbrbrb", 0x8f } }, -{ "movb", {"rbwb", 0x90 } }, -{ "cmpb", {"rbrb", 0x91 } }, -{ "mcomb", {"rbwb", 0x92 } }, -{ "bitb", {"rbrb", 0x93 } }, -{ "clrb", {"wb", 0x94 } }, -{ "tstb", {"rb", 0x95 } }, -{ "incb", {"mb", 0x96 } }, -{ "decb", {"mb", 0x97 } }, -{ "cvtbl", {"rbwl", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "movzbl", {"rbwl", 0x9a } }, -{ "movzbw", {"rbww", 0x9b } }, -{ "rotl", {"rbrlwl", 0x9c } }, -{ "acbb", {"rbrbmbbw", 0x9d } }, -{ "movab", {"abwl", 0x9e } }, -{ "pushab", {"ab", 0x9f } }, -{ "addw2", {"rwmw", 0xa0 } }, -{ "addw3", {"rwrwww", 0xa1 } }, -{ "subw2", {"rwmw", 0xa2 } }, -{ "subw3", {"rwrwww", 0xa3 } }, -{ "mulw2", {"rwmw", 0xa4 } }, -{ "mulw3", {"rwrwww", 0xa5 } }, -{ "divw2", {"rwmw", 0xa6 } }, -{ "divw3", {"rwrwww", 0xa7 } }, -{ "bisw2", {"rwmw", 0xa8 } }, -{ "bisw3", {"rwrwww", 0xa9 } }, -{ "bicw2", {"rwmw", 0xaa } }, -{ "bicw3", {"rwrwww", 0xab } }, -{ "xorw2", {"rwmw", 0xac } }, -{ "xorw3", {"rwrwww", 0xad } }, -{ "mnegw", {"rwww", 0xae } }, -{ "casew", {"rwrwrw", 0xaf } }, -{ "movw", {"rwww", 0xb0 } }, -{ "cmpw", {"rwrw", 0xb1 } }, -{ "mcomw", {"rwww", 0xb2 } }, -{ "bitw", {"rwrw", 0xb3 } }, -{ "clrw", {"ww", 0xb4 } }, -{ "tstw", {"rw", 0xb5 } }, -{ "incw", {"mw", 0xb6 } }, -{ "decw", {"mw", 0xb7 } }, -{ "bispsw", {"rw", 0xb8 } }, -{ "bicpsw", {"rw", 0xb9 } }, -{ "popr", {"rw", 0xba } }, -{ "pushr", {"rw", 0xbb } }, -{ "chmk", {"rw", 0xbc } }, -{ "chme", {"rw", 0xbd } }, -{ "chms", {"rw", 0xbe } }, -{ "chmu", {"rw", 0xbf } }, -{ "addl2", {"rlml", 0xc0 } }, -{ "addl3", {"rlrlwl", 0xc1 } }, -{ "subl2", {"rlml", 0xc2 } }, -{ "subl3", {"rlrlwl", 0xc3 } }, -{ "mull2", {"rlml", 0xc4 } }, -{ "mull3", {"rlrlwl", 0xc5 } }, -{ "divl2", {"rlml", 0xc6 } }, -{ "divl3", {"rlrlwl", 0xc7 } }, -{ "bisl2", {"rlml", 0xc8 } }, -{ "bisl3", {"rlrlwl", 0xc9 } }, -{ "bicl2", {"rlml", 0xca } }, -{ "bicl3", {"rlrlwl", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "xorl3", {"rlrlwl", 0xcd } }, -{ "mnegl", {"rlwl", 0xce } }, -{ "casel", {"rlrlrl", 0xcf } }, -{ "movl", {"rlwl", 0xd0 } }, -{ "cmpl", {"rlrl", 0xd1 } }, -{ "mcoml", {"rlwl", 0xd2 } }, -{ "bitl", {"rlrl", 0xd3 } }, -{ "clrf", {"wf", 0xd4 } }, -{ "clrl", {"wl", 0xd4 } }, -{ "tstl", {"rl", 0xd5 } }, -{ "incl", {"ml", 0xd6 } }, -{ "decl", {"ml", 0xd7 } }, -{ "adwc", {"rlml", 0xd8 } }, -{ "sbwc", {"rlml", 0xd9 } }, -{ "mtpr", {"rlrl", 0xda } }, -{ "mfpr", {"rlwl", 0xdb } }, -{ "movpsl", {"wl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "moval", {"alwl", 0xde } }, -{ "movaf", {"afwl", 0xde } }, -{ "pushal", {"al", 0xdf } }, -{ "pushaf", {"af", 0xdf } }, -{ "bbs", {"rlvbbb", 0xe0 } }, -{ "bbc", {"rlvbbb", 0xe1 } }, -{ "bbss", {"rlvbbb", 0xe2 } }, -{ "bbcs", {"rlvbbb", 0xe3 } }, -{ "bbsc", {"rlvbbb", 0xe4 } }, -{ "bbcc", {"rlvbbb", 0xe5 } }, -{ "bbssi", {"rlvbbb", 0xe6 } }, -{ "bbcci", {"rlvbbb", 0xe7 } }, -{ "blbs", {"rlbb", 0xe8 } }, -{ "blbc", {"rlbb", 0xe9 } }, -{ "ffs", {"rlrbvbwl", 0xea } }, -{ "ffc", {"rlrbvbwl", 0xeb } }, -{ "cmpv", {"rlrbvbrl", 0xec } }, -{ "cmpzv", {"rlrbvbrl", 0xed } }, -{ "extv", {"rlrbvbwl", 0xee } }, -{ "extzv", {"rlrbvbwl", 0xef } }, -{ "insv", {"rlrlrbvb", 0xf0 } }, -{ "acbl", {"rlrlmlbw", 0xf1 } }, -{ "aoblss", {"rlmlbb", 0xf2 } }, -{ "aobleq", {"rlmlbb", 0xf3 } }, -{ "sobgeq", {"mlbb", 0xf4 } }, -{ "sobgtr", {"mlbb", 0xf5 } }, -{ "cvtlb", {"rlwb", 0xf6 } }, -{ "cvtlw", {"rlww", 0xf7 } }, -{ "ashp", {"rbrwabrbrwab", 0xf8 } }, -{ "cvtlp", {"rlrwab", 0xf9 } }, -{ "callg", {"abab", 0xfa } }, -{ "calls", {"rlab", 0xfb } }, -{ "xfc", {"", 0xfc } }, +{ "ashl", { "rbrlwl", 0x78 } }, +{ "ashq", { "rbrqwq", 0x79 } }, +{ "emul", { "rlrlrlwq", 0x7a } }, +{ "ediv", { "rlrqwlwl", 0x7b } }, +{ "clrd", { "wd", 0x7c } }, +{ "clrg", { "wg", 0x7c } }, +{ "clrq", { "wd", 0x7c } }, +{ "movq", { "rqwq", 0x7d } }, +{ "movaq", { "aqwl", 0x7e } }, +{ "movad", { "adwl", 0x7e } }, +{ "pushaq", { "aq", 0x7f } }, +{ "pushad", { "ad", 0x7f } }, +{ "addb2", { "rbmb", 0x80 } }, +{ "addb3", { "rbrbwb", 0x81 } }, +{ "subb2", { "rbmb", 0x82 } }, +{ "subb3", { "rbrbwb", 0x83 } }, +{ "mulb2", { "rbmb", 0x84 } }, +{ "mulb3", { "rbrbwb", 0x85 } }, +{ "divb2", { "rbmb", 0x86 } }, +{ "divb3", { "rbrbwb", 0x87 } }, +{ "bisb2", { "rbmb", 0x88 } }, +{ "bisb3", { "rbrbwb", 0x89 } }, +{ "bicb2", { "rbmb", 0x8a } }, +{ "bicb3", { "rbrbwb", 0x8b } }, +{ "xorb2", { "rbmb", 0x8c } }, +{ "xorb3", { "rbrbwb", 0x8d } }, +{ "mnegb", { "rbwb", 0x8e } }, +{ "caseb", { "rbrbrb", 0x8f } }, +{ "movb", { "rbwb", 0x90 } }, +{ "cmpb", { "rbrb", 0x91 } }, +{ "mcomb", { "rbwb", 0x92 } }, +{ "bitb", { "rbrb", 0x93 } }, +{ "clrb", { "wb", 0x94 } }, +{ "tstb", { "rb", 0x95 } }, +{ "incb", { "mb", 0x96 } }, +{ "decb", { "mb", 0x97 } }, +{ "cvtbl", { "rbwl", 0x98 } }, +{ "cvtbw", { "rbww", 0x99 } }, +{ "movzbl", { "rbwl", 0x9a } }, +{ "movzbw", { "rbww", 0x9b } }, +{ "rotl", { "rbrlwl", 0x9c } }, +{ "acbb", { "rbrbmbbw", 0x9d } }, +{ "movab", { "abwl", 0x9e } }, +{ "pushab", { "ab", 0x9f } }, +{ "addw2", { "rwmw", 0xa0 } }, +{ "addw3", { "rwrwww", 0xa1 } }, +{ "subw2", { "rwmw", 0xa2 } }, +{ "subw3", { "rwrwww", 0xa3 } }, +{ "mulw2", { "rwmw", 0xa4 } }, +{ "mulw3", { "rwrwww", 0xa5 } }, +{ "divw2", { "rwmw", 0xa6 } }, +{ "divw3", { "rwrwww", 0xa7 } }, +{ "bisw2", { "rwmw", 0xa8 } }, +{ "bisw3", { "rwrwww", 0xa9 } }, +{ "bicw2", { "rwmw", 0xaa } }, +{ "bicw3", { "rwrwww", 0xab } }, +{ "xorw2", { "rwmw", 0xac } }, +{ "xorw3", { "rwrwww", 0xad } }, +{ "mnegw", { "rwww", 0xae } }, +{ "casew", { "rwrwrw", 0xaf } }, +{ "movw", { "rwww", 0xb0 } }, +{ "cmpw", { "rwrw", 0xb1 } }, +{ "mcomw", { "rwww", 0xb2 } }, +{ "bitw", { "rwrw", 0xb3 } }, +{ "clrw", { "ww", 0xb4 } }, +{ "tstw", { "rw", 0xb5 } }, +{ "incw", { "mw", 0xb6 } }, +{ "decw", { "mw", 0xb7 } }, +{ "bispsw", { "rw", 0xb8 } }, +{ "bicpsw", { "rw", 0xb9 } }, +{ "popr", { "rw", 0xba } }, +{ "pushr", { "rw", 0xbb } }, +{ "chmk", { "rw", 0xbc } }, +{ "chme", { "rw", 0xbd } }, +{ "chms", { "rw", 0xbe } }, +{ "chmu", { "rw", 0xbf } }, +{ "addl2", { "rlml", 0xc0 } }, +{ "addl3", { "rlrlwl", 0xc1 } }, +{ "subl2", { "rlml", 0xc2 } }, +{ "subl3", { "rlrlwl", 0xc3 } }, +{ "mull2", { "rlml", 0xc4 } }, +{ "mull3", { "rlrlwl", 0xc5 } }, +{ "divl2", { "rlml", 0xc6 } }, +{ "divl3", { "rlrlwl", 0xc7 } }, +{ "bisl2", { "rlml", 0xc8 } }, +{ "bisl3", { "rlrlwl", 0xc9 } }, +{ "bicl2", { "rlml", 0xca } }, +{ "bicl3", { "rlrlwl", 0xcb } }, +{ "xorl2", { "rlml", 0xcc } }, +{ "xorl3", { "rlrlwl", 0xcd } }, +{ "mnegl", { "rlwl", 0xce } }, +{ "casel", { "rlrlrl", 0xcf } }, +{ "movl", { "rlwl", 0xd0 } }, +{ "cmpl", { "rlrl", 0xd1 } }, +{ "mcoml", { "rlwl", 0xd2 } }, +{ "bitl", { "rlrl", 0xd3 } }, +{ "clrf", { "wf", 0xd4 } }, +{ "clrl", { "wl", 0xd4 } }, +{ "tstl", { "rl", 0xd5 } }, +{ "incl", { "ml", 0xd6 } }, +{ "decl", { "ml", 0xd7 } }, +{ "adwc", { "rlml", 0xd8 } }, +{ "sbwc", { "rlml", 0xd9 } }, +{ "mtpr", { "rlrl", 0xda } }, +{ "mfpr", { "rlwl", 0xdb } }, +{ "movpsl", { "wl", 0xdc } }, +{ "pushl", { "rl", 0xdd } }, +{ "moval", { "alwl", 0xde } }, +{ "movaf", { "afwl", 0xde } }, +{ "pushal", { "al", 0xdf } }, +{ "pushaf", { "af", 0xdf } }, +{ "bbs", { "rlvbbb", 0xe0 } }, +{ "bbc", { "rlvbbb", 0xe1 } }, +{ "bbss", { "rlvbbb", 0xe2 } }, +{ "bbcs", { "rlvbbb", 0xe3 } }, +{ "bbsc", { "rlvbbb", 0xe4 } }, +{ "bbcc", { "rlvbbb", 0xe5 } }, +{ "bbssi", { "rlvbbb", 0xe6 } }, +{ "bbcci", { "rlvbbb", 0xe7 } }, +{ "blbs", { "rlbb", 0xe8 } }, +{ "blbc", { "rlbb", 0xe9 } }, +{ "ffs", { "rlrbvbwl", 0xea } }, +{ "ffc", { "rlrbvbwl", 0xeb } }, +{ "cmpv", { "rlrbvbrl", 0xec } }, +{ "cmpzv", { "rlrbvbrl", 0xed } }, +{ "extv", { "rlrbvbwl", 0xee } }, +{ "extzv", { "rlrbvbwl", 0xef } }, +{ "insv", { "rlrlrbvb", 0xf0 } }, +{ "acbl", { "rlrlmlbw", 0xf1 } }, +{ "aoblss", { "rlmlbb", 0xf2 } }, +{ "aobleq", { "rlmlbb", 0xf3 } }, +{ "sobgeq", { "mlbb", 0xf4 } }, +{ "sobgtr", { "mlbb", 0xf5 } }, +{ "cvtlb", { "rlwb", 0xf6 } }, +{ "cvtlw", { "rlww", 0xf7 } }, +{ "ashp", { "rbrwabrbrwab", 0xf8 } }, +{ "cvtlp", { "rlrwab", 0xf9 } }, +{ "callg", { "abab", 0xfa } }, +{ "calls", { "rlab", 0xfb } }, +{ "xfc", { "", 0xfc } }, /* undefined opcodes here */ -{ "cvtdh", {"rdwh", 0x32fd } }, -{ "cvtgf", {"rgwh", 0x33fd } }, -{ "addg2", {"rgmg", 0x40fd } }, -{ "addg3", {"rgrgwg", 0x41fd } }, -{ "subg2", {"rgmg", 0x42fd } }, -{ "subg3", {"rgrgwg", 0x43fd } }, -{ "mulg2", {"rgmg", 0x44fd } }, -{ "mulg3", {"rgrgwg", 0x45fd } }, -{ "divg2", {"rgmg", 0x46fd } }, -{ "divg3", {"rgrgwg", 0x47fd } }, -{ "cvtgb", {"rgwb", 0x48fd } }, -{ "cvtgw", {"rgww", 0x49fd } }, -{ "cvtgl", {"rgwl", 0x4afd } }, -{ "cvtrgl", {"rgwl", 0x4bfd } }, -{ "cvtbg", {"rbwg", 0x4cfd } }, -{ "cvtwg", {"rwwg", 0x4dfd } }, -{ "cvtlg", {"rlwg", 0x4efd } }, -{ "acbg", {"rgrgmgbw", 0x4ffd } }, -{ "movg", {"rgwg", 0x50fd } }, -{ "cmpg", {"rgrg", 0x51fd } }, -{ "mnegg", {"rgwg", 0x52fd } }, -{ "tstg", {"rg", 0x53fd } }, -{ "emodg", {"rgrwrgwlwg", 0x54fd } }, -{ "polyg", {"rgrwab", 0x55fd } }, -{ "cvtgh", {"rgwh", 0x56fd } }, +{ "cvtdh", { "rdwh", 0x32fd } }, +{ "cvtgf", { "rgwh", 0x33fd } }, +{ "addg2", { "rgmg", 0x40fd } }, +{ "addg3", { "rgrgwg", 0x41fd } }, +{ "subg2", { "rgmg", 0x42fd } }, +{ "subg3", { "rgrgwg", 0x43fd } }, +{ "mulg2", { "rgmg", 0x44fd } }, +{ "mulg3", { "rgrgwg", 0x45fd } }, +{ "divg2", { "rgmg", 0x46fd } }, +{ "divg3", { "rgrgwg", 0x47fd } }, +{ "cvtgb", { "rgwb", 0x48fd } }, +{ "cvtgw", { "rgww", 0x49fd } }, +{ "cvtgl", { "rgwl", 0x4afd } }, +{ "cvtrgl", { "rgwl", 0x4bfd } }, +{ "cvtbg", { "rbwg", 0x4cfd } }, +{ "cvtwg", { "rwwg", 0x4dfd } }, +{ "cvtlg", { "rlwg", 0x4efd } }, +{ "acbg", { "rgrgmgbw", 0x4ffd } }, +{ "movg", { "rgwg", 0x50fd } }, +{ "cmpg", { "rgrg", 0x51fd } }, +{ "mnegg", { "rgwg", 0x52fd } }, +{ "tstg", { "rg", 0x53fd } }, +{ "emodg", { "rgrwrgwlwg", 0x54fd } }, +{ "polyg", { "rgrwab", 0x55fd } }, +{ "cvtgh", { "rgwh", 0x56fd } }, /* undefined opcodes here */ -{ "addh2", {"rhmh", 0x60fd } }, -{ "addh3", {"rhrhwh", 0x61fd } }, -{ "subh2", {"rhmh", 0x62fd } }, -{ "subh3", {"rhrhwh", 0x63fd } }, -{ "mulh2", {"rhmh", 0x64fd } }, -{ "mulh3", {"rhrhwh", 0x65fd } }, -{ "divh2", {"rhmh", 0x66fd } }, -{ "divh3", {"rhrhwh", 0x67fd } }, -{ "cvthb", {"rhwb", 0x68fd } }, -{ "cvthw", {"rhww", 0x69fd } }, -{ "cvthl", {"rhwl", 0x6afd } }, -{ "cvtrhl", {"rhwl", 0x6bfd } }, -{ "cvtbh", {"rbwh", 0x6cfd } }, -{ "cvtwh", {"rwwh", 0x6dfd } }, -{ "cvtlh", {"rlwh", 0x6efd } }, -{ "acbh", {"rhrhmhbw", 0x6ffd } }, -{ "movh", {"rhwh", 0x70fd } }, -{ "cmph", {"rhrh", 0x71fd } }, -{ "mnegh", {"rhwh", 0x72fd } }, -{ "tsth", {"rh", 0x73fd } }, -{ "emodh", {"rhrwrhwlwh", 0x74fd } }, -{ "polyh", {"rhrwab", 0x75fd } }, -{ "cvthg", {"rhwg", 0x76fd } }, +{ "addh2", { "rhmh", 0x60fd } }, +{ "addh3", { "rhrhwh", 0x61fd } }, +{ "subh2", { "rhmh", 0x62fd } }, +{ "subh3", { "rhrhwh", 0x63fd } }, +{ "mulh2", { "rhmh", 0x64fd } }, +{ "mulh3", { "rhrhwh", 0x65fd } }, +{ "divh2", { "rhmh", 0x66fd } }, +{ "divh3", { "rhrhwh", 0x67fd } }, +{ "cvthb", { "rhwb", 0x68fd } }, +{ "cvthw", { "rhww", 0x69fd } }, +{ "cvthl", { "rhwl", 0x6afd } }, +{ "cvtrhl", { "rhwl", 0x6bfd } }, +{ "cvtbh", { "rbwh", 0x6cfd } }, +{ "cvtwh", { "rwwh", 0x6dfd } }, +{ "cvtlh", { "rlwh", 0x6efd } }, +{ "acbh", { "rhrhmhbw", 0x6ffd } }, +{ "movh", { "rhwh", 0x70fd } }, +{ "cmph", { "rhrh", 0x71fd } }, +{ "mnegh", { "rhwh", 0x72fd } }, +{ "tsth", { "rh", 0x73fd } }, +{ "emodh", { "rhrwrhwlwh", 0x74fd } }, +{ "polyh", { "rhrwab", 0x75fd } }, +{ "cvthg", { "rhwg", 0x76fd } }, /* undefined opcodes here */ -{ "clrh", {"wh", 0x7cfd } }, -{ "clro", {"wo", 0x7cfd } }, -{ "movo", {"rowo", 0x7dfd } }, -{ "movah", {"ahwl", 0x7efd } }, -{ "movao", {"aowl", 0x7efd } }, -{ "pushah", {"ah", 0x7ffd } }, -{ "pushao", {"ao", 0x7ffd } }, +{ "clrh", { "wh", 0x7cfd } }, +{ "clro", { "wo", 0x7cfd } }, +{ "movo", { "rowo", 0x7dfd } }, +{ "movah", { "ahwl", 0x7efd } }, +{ "movao", { "aowl", 0x7efd } }, +{ "pushah", { "ah", 0x7ffd } }, +{ "pushao", { "ao", 0x7ffd } }, /* undefined opcodes here */ -{ "cvtfh", {"rfwh", 0x98fd } }, -{ "cvtfg", {"rfwg", 0x99fd } }, +{ "cvtfh", { "rfwh", 0x98fd } }, +{ "cvtfg", { "rfwg", 0x99fd } }, /* undefined opcodes here */ -{ "cvthf", {"rhwf", 0xf6fd } }, -{ "cvthd", {"rhwd", 0xf7fd } }, +{ "cvthf", { "rhwf", 0xf6fd } }, +{ "cvthd", { "rhwd", 0xf7fd } }, /* undefined opcodes here */ -{ "bugl", {"rl", 0xfdff } }, -{ "bugw", {"rw", 0xfeff } }, +{ "bugl", { "rl", 0xfdff } }, +{ "bugw", { "rw", 0xfeff } }, /* undefined opcodes here */ -{ "", {"", 0} } /* empty is end sentinel */ +{ "", { "", 0} } /* empty is end sentinel */ }; /* votstrs */ diff --git a/libr/anal/arch/wasm/wasm.c b/libr/anal/arch/wasm/wasm.c index c4ba984059..f003e93acd 100644 --- a/libr/anal/arch/wasm/wasm.c +++ b/libr/anal/arch/wasm/wasm.c @@ -71,8 +71,8 @@ static WasmOpDef opcodes[256] = { [WASM_OP_I32GES] = { "i32.ge_s", 1, 1 }, [WASM_OP_I32GEU] = { "i32.ge_u", 1, 1 }, [WASM_OP_I64EQZ] = { "i64.eqz", 1, 1 }, - [WASM_OP_I64EQ] = {" i64.eq", 1, 1 }, - [WASM_OP_I64NE] = {" i64.ne", 1, 1 }, + [WASM_OP_I64EQ] = { " i64.eq", 1, 1 }, + [WASM_OP_I64NE] = { " i64.ne", 1, 1 }, [WASM_OP_I64LTS] = { "i64.lt_s", 1, 1 }, [WASM_OP_I64LTU] = { "i64.lt_u", 1, 1 }, [WASM_OP_I64GTS] = { "i64.gt_s", 1, 1 }, @@ -142,7 +142,7 @@ static WasmOpDef opcodes[256] = { [WASM_OP_F32DIV] = { "f32.div", 1, 1 }, [WASM_OP_F32MIN] = { "f32.min", 1, 1 }, [WASM_OP_F32MAX] = { "f32.max", 1, 1 }, - [WASM_OP_F32COPYSIGN] = {" f32.copysign", 1, 1 }, + [WASM_OP_F32COPYSIGN] = { " f32.copysign", 1, 1 }, [WASM_OP_F64ABS] = { "f64.abs", 1, 1 }, [WASM_OP_F64NEG] = { "f64.neg", 1, 1 }, [WASM_OP_F64CEIL] = { "f64.ceil", 1, 1 }, diff --git a/libr/anal/arch/z80/z80_tab.h b/libr/anal/arch/z80/z80_tab.h index 62ff28377b..16711cfdae 100644 --- a/libr/anal/arch/z80/z80_tab.h +++ b/libr/anal/arch/z80/z80_tab.h @@ -841,505 +841,505 @@ static const char *fdcb[]={ static const z80_opcode dd[] = { //dd - {"add ix, bc", Z80_OP16 ,NULL}, - {"add ix, de", Z80_OP16 ,NULL}, - {"ld ix, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL}, - {"ld [0x%04x], ix", Z80_OP16^Z80_ARG16 ,NULL}, - {"inc ix", Z80_OP16 ,NULL}, - {"inc ixh", Z80_OP16 ,NULL}, - {"dec ixh", Z80_OP16 ,NULL}, - {"ld ixh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, - {"add ix, ix", Z80_OP16 ,NULL}, - {"ld ix, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, - {"dec ix", Z80_OP16 ,NULL}, - {"inc ixl", Z80_OP16 ,NULL}, - {"dec ixl", Z80_OP16 ,NULL}, - {"ld ixl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, - {"inc [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"dec [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL}, - {"add ix, sp", Z80_OP16 ,NULL}, - {"ld b, ixh", Z80_OP16 ,NULL}, - {"ld b, ixl", Z80_OP16 ,NULL}, - {"ld b, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld c, ixh", Z80_OP16 ,NULL}, - {"ld c, ixl", Z80_OP16 ,NULL}, - {"ld c, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld d, ixh", Z80_OP16 ,NULL}, - {"ld d, ixl", Z80_OP16 ,NULL}, - {"ld d, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld e, ixh", Z80_OP16 ,NULL}, - {"ld e, ixl", Z80_OP16 ,NULL}, - {"ld e, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld ixh, b", Z80_OP16 ,NULL}, - {"ld ixh, c", Z80_OP16 ,NULL}, - {"ld ixh, d", Z80_OP16 ,NULL}, - {"ld ixh, e", Z80_OP16 ,NULL}, - {"ld ixh, ixh", Z80_OP16 ,NULL}, - {"ld ixh, ixl", Z80_OP16 ,NULL}, - {"ld h, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld ixh, a", Z80_OP16 ,NULL}, - {"ld ixl, b", Z80_OP16 ,NULL}, - {"ld ixl, c", Z80_OP16 ,NULL}, - {"ld ixl, d", Z80_OP16 ,NULL}, - {"ld ixl, e", Z80_OP16 ,NULL}, - {"ld ixl, ixh", Z80_OP16 ,NULL}, - {"ld ixl, ixl", Z80_OP16 ,NULL}, - {"ld l, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld ixl, a", Z80_OP16 ,NULL}, - {"ld [ix+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [ix+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld a, ixh", Z80_OP16 ,NULL}, - {"ld a, ixl", Z80_OP16 ,NULL}, - {"ld a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"add a, ixh", Z80_OP16 ,NULL}, - {"add a, ixl", Z80_OP16 ,NULL}, - {"add a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"adc a, ixh", Z80_OP16 ,NULL}, - {"adc a, ixl", Z80_OP16 ,NULL}, - {"adc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"sub a, ixh", Z80_OP16 ,NULL}, - {"sub a, ixl", Z80_OP16 ,NULL}, - {"sub [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"sbc a, ixh", Z80_OP16 ,NULL}, - {"sbc a, ixl", Z80_OP16 ,NULL}, - {"sbc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"and ixh", Z80_OP16 ,NULL}, - {"and ixl", Z80_OP16 ,NULL}, - {"and [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"xor ixh", Z80_OP16 ,NULL}, - {"xor ixl", Z80_OP16 ,NULL}, - {"xor [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"or ixh", Z80_OP16 ,NULL}, - {"or ixl", Z80_OP16 ,NULL}, - {"or [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"cp ixh", Z80_OP16 ,NULL}, - {"cp ixl", Z80_OP16 ,NULL}, - {"cp [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"", Z80_OP24^Z80_ARG8 ,ddcb}, - {"pop ix", Z80_OP16 ,NULL}, - {"ex [sp], ix", Z80_OP16 ,NULL}, - {"push ix", Z80_OP16 ,NULL}, - {"jp [ix]", Z80_OP16 ,NULL}, - {"ld sp, ix", Z80_OP16 ,NULL}, - {"invalid", Z80_OP16 ,NULL} + { "add ix, bc", Z80_OP16 ,NULL}, + { "add ix, de", Z80_OP16 ,NULL}, + { "ld ix, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL}, + { "ld [0x%04x], ix", Z80_OP16^Z80_ARG16 ,NULL}, + { "inc ix", Z80_OP16 ,NULL}, + { "inc ixh", Z80_OP16 ,NULL}, + { "dec ixh", Z80_OP16 ,NULL}, + { "ld ixh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, + { "add ix, ix", Z80_OP16 ,NULL}, + { "ld ix, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, + { "dec ix", Z80_OP16 ,NULL}, + { "inc ixl", Z80_OP16 ,NULL}, + { "dec ixl", Z80_OP16 ,NULL}, + { "ld ixl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, + { "inc [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "dec [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL}, + { "add ix, sp", Z80_OP16 ,NULL}, + { "ld b, ixh", Z80_OP16 ,NULL}, + { "ld b, ixl", Z80_OP16 ,NULL}, + { "ld b, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld c, ixh", Z80_OP16 ,NULL}, + { "ld c, ixl", Z80_OP16 ,NULL}, + { "ld c, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld d, ixh", Z80_OP16 ,NULL}, + { "ld d, ixl", Z80_OP16 ,NULL}, + { "ld d, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld e, ixh", Z80_OP16 ,NULL}, + { "ld e, ixl", Z80_OP16 ,NULL}, + { "ld e, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld ixh, b", Z80_OP16 ,NULL}, + { "ld ixh, c", Z80_OP16 ,NULL}, + { "ld ixh, d", Z80_OP16 ,NULL}, + { "ld ixh, e", Z80_OP16 ,NULL}, + { "ld ixh, ixh", Z80_OP16 ,NULL}, + { "ld ixh, ixl", Z80_OP16 ,NULL}, + { "ld h, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld ixh, a", Z80_OP16 ,NULL}, + { "ld ixl, b", Z80_OP16 ,NULL}, + { "ld ixl, c", Z80_OP16 ,NULL}, + { "ld ixl, d", Z80_OP16 ,NULL}, + { "ld ixl, e", Z80_OP16 ,NULL}, + { "ld ixl, ixh", Z80_OP16 ,NULL}, + { "ld ixl, ixl", Z80_OP16 ,NULL}, + { "ld l, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld ixl, a", Z80_OP16 ,NULL}, + { "ld [ix+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [ix+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld a, ixh", Z80_OP16 ,NULL}, + { "ld a, ixl", Z80_OP16 ,NULL}, + { "ld a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "add a, ixh", Z80_OP16 ,NULL}, + { "add a, ixl", Z80_OP16 ,NULL}, + { "add a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "adc a, ixh", Z80_OP16 ,NULL}, + { "adc a, ixl", Z80_OP16 ,NULL}, + { "adc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "sub a, ixh", Z80_OP16 ,NULL}, + { "sub a, ixl", Z80_OP16 ,NULL}, + { "sub [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "sbc a, ixh", Z80_OP16 ,NULL}, + { "sbc a, ixl", Z80_OP16 ,NULL}, + { "sbc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "and ixh", Z80_OP16 ,NULL}, + { "and ixl", Z80_OP16 ,NULL}, + { "and [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "xor ixh", Z80_OP16 ,NULL}, + { "xor ixl", Z80_OP16 ,NULL}, + { "xor [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "or ixh", Z80_OP16 ,NULL}, + { "or ixl", Z80_OP16 ,NULL}, + { "or [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "cp ixh", Z80_OP16 ,NULL}, + { "cp ixl", Z80_OP16 ,NULL}, + { "cp [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "", Z80_OP24^Z80_ARG8 ,ddcb}, + { "pop ix", Z80_OP16 ,NULL}, + { "ex [sp], ix", Z80_OP16 ,NULL}, + { "push ix", Z80_OP16 ,NULL}, + { "jp [ix]", Z80_OP16 ,NULL}, + { "ld sp, ix", Z80_OP16 ,NULL}, + { "invalid", Z80_OP16 ,NULL} }; static const z80_opcode ed[]={ //ed - {"in b, [c]", Z80_OP16 ,NULL}, - {"out [c], b", Z80_OP16 ,NULL}, - {"sbc hl, bc", Z80_OP16 ,NULL}, - {"ld [0x%04x], bc", Z80_OP16^Z80_ARG16 ,NULL}, - {"neg", Z80_OP16 ,NULL}, - {"retn", Z80_OP16 ,NULL}, - {"im 0", Z80_OP16 ,NULL}, - {"ld i, a", Z80_OP16 ,NULL}, - {"in c, [c]", Z80_OP16 ,NULL}, - {"out [c], c", Z80_OP16 ,NULL}, - {"adc hl, bc", Z80_OP16 ,NULL}, - {"ld bc, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, - {"reti", Z80_OP16 ,NULL}, - {"ld r, a", Z80_OP16 ,NULL}, - {"in d, [c]", Z80_OP16 ,NULL}, - {"out [c], d", Z80_OP16 ,NULL}, - {"sbc hl, de", Z80_OP16 ,NULL}, - {"ld [0x%04x], de", Z80_OP16^Z80_ARG16 ,NULL}, - {"im 1", Z80_OP16 ,NULL}, - {"ld a, i", Z80_OP16 ,NULL}, - {"in e, [c]", Z80_OP16 ,NULL}, - {"out [c], e", Z80_OP16 ,NULL}, - {"adc hl, de", Z80_OP16 ,NULL}, - {"ld de, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, - {"im 2", Z80_OP16 ,NULL}, - {"ld a, r", Z80_OP16 ,NULL}, - {"in h, [c]", Z80_OP16 ,NULL}, - {"out [c], h", Z80_OP16 ,NULL}, - {"sbc hl, hl", Z80_OP16 ,NULL}, - {"rrd", Z80_OP16 ,NULL}, - {"in l, [c]", Z80_OP16 ,NULL}, - {"out [c], l", Z80_OP16 ,NULL}, - {"adc hl, hl", Z80_OP16 ,NULL}, - {"rld", Z80_OP16 ,NULL}, - {"in [c]", Z80_OP16 ,NULL}, - {"out [c], 0", Z80_OP16 ,NULL}, - {"sbc hl, sp", Z80_OP16 ,NULL}, - {"ld [0x%04x], sp", Z80_OP16^Z80_ARG16 ,NULL}, - {"in a, [c]", Z80_OP16 ,NULL}, - {"out [c], a", Z80_OP16 ,NULL}, - {"adc hl, sp", Z80_OP16 ,NULL}, - {"ld sp, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, - {"ldi", Z80_OP16 ,NULL}, - {"cpi", Z80_OP16 ,NULL}, - {"ini", Z80_OP16 ,NULL}, - {"outi", Z80_OP16 ,NULL}, - {"ldd", Z80_OP16 ,NULL}, - {"cpd", Z80_OP16 ,NULL}, - {"ind", Z80_OP16 ,NULL}, - {"outd", Z80_OP16 ,NULL}, - {"ldir", Z80_OP16 ,NULL}, - {"cpir", Z80_OP16 ,NULL}, - {"inir", Z80_OP16 ,NULL}, - {"otir", Z80_OP16 ,NULL}, - {"lddr", Z80_OP16 ,NULL}, - {"cpdr", Z80_OP16 ,NULL}, - {"indr", Z80_OP16 ,NULL}, - {"otdr", Z80_OP16 ,NULL}, - {"invalid", Z80_OP16 ,NULL}, - {"invalid", Z80_OP16 ,NULL} + { "in b, [c]", Z80_OP16 ,NULL}, + { "out [c], b", Z80_OP16 ,NULL}, + { "sbc hl, bc", Z80_OP16 ,NULL}, + { "ld [0x%04x], bc", Z80_OP16^Z80_ARG16 ,NULL}, + { "neg", Z80_OP16 ,NULL}, + { "retn", Z80_OP16 ,NULL}, + { "im 0", Z80_OP16 ,NULL}, + { "ld i, a", Z80_OP16 ,NULL}, + { "in c, [c]", Z80_OP16 ,NULL}, + { "out [c], c", Z80_OP16 ,NULL}, + { "adc hl, bc", Z80_OP16 ,NULL}, + { "ld bc, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, + { "reti", Z80_OP16 ,NULL}, + { "ld r, a", Z80_OP16 ,NULL}, + { "in d, [c]", Z80_OP16 ,NULL}, + { "out [c], d", Z80_OP16 ,NULL}, + { "sbc hl, de", Z80_OP16 ,NULL}, + { "ld [0x%04x], de", Z80_OP16^Z80_ARG16 ,NULL}, + { "im 1", Z80_OP16 ,NULL}, + { "ld a, i", Z80_OP16 ,NULL}, + { "in e, [c]", Z80_OP16 ,NULL}, + { "out [c], e", Z80_OP16 ,NULL}, + { "adc hl, de", Z80_OP16 ,NULL}, + { "ld de, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, + { "im 2", Z80_OP16 ,NULL}, + { "ld a, r", Z80_OP16 ,NULL}, + { "in h, [c]", Z80_OP16 ,NULL}, + { "out [c], h", Z80_OP16 ,NULL}, + { "sbc hl, hl", Z80_OP16 ,NULL}, + { "rrd", Z80_OP16 ,NULL}, + { "in l, [c]", Z80_OP16 ,NULL}, + { "out [c], l", Z80_OP16 ,NULL}, + { "adc hl, hl", Z80_OP16 ,NULL}, + { "rld", Z80_OP16 ,NULL}, + { "in [c]", Z80_OP16 ,NULL}, + { "out [c], 0", Z80_OP16 ,NULL}, + { "sbc hl, sp", Z80_OP16 ,NULL}, + { "ld [0x%04x], sp", Z80_OP16^Z80_ARG16 ,NULL}, + { "in a, [c]", Z80_OP16 ,NULL}, + { "out [c], a", Z80_OP16 ,NULL}, + { "adc hl, sp", Z80_OP16 ,NULL}, + { "ld sp, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, + { "ldi", Z80_OP16 ,NULL}, + { "cpi", Z80_OP16 ,NULL}, + { "ini", Z80_OP16 ,NULL}, + { "outi", Z80_OP16 ,NULL}, + { "ldd", Z80_OP16 ,NULL}, + { "cpd", Z80_OP16 ,NULL}, + { "ind", Z80_OP16 ,NULL}, + { "outd", Z80_OP16 ,NULL}, + { "ldir", Z80_OP16 ,NULL}, + { "cpir", Z80_OP16 ,NULL}, + { "inir", Z80_OP16 ,NULL}, + { "otir", Z80_OP16 ,NULL}, + { "lddr", Z80_OP16 ,NULL}, + { "cpdr", Z80_OP16 ,NULL}, + { "indr", Z80_OP16 ,NULL}, + { "otdr", Z80_OP16 ,NULL}, + { "invalid", Z80_OP16 ,NULL}, + { "invalid", Z80_OP16 ,NULL} }; static const z80_opcode fd[]={ //fd - {"add iy, bc", Z80_OP16 ,NULL}, - {"add iy, de", Z80_OP16 ,NULL}, - {"ld iy, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL}, - {"ld [0x%04x], iy", Z80_OP16^Z80_ARG16 ,NULL}, - {"inc iy", Z80_OP16 ,NULL}, - {"inc iyh", Z80_OP16 ,NULL}, - {"dec iyh", Z80_OP16 ,NULL}, - {"ld iyh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, - {"add iy, iy", Z80_OP16 ,NULL}, - {"ld iy, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, - {"dec iy", Z80_OP16 ,NULL}, - {"inc iyl", Z80_OP16 ,NULL}, - {"dec iyl", Z80_OP16 ,NULL}, - {"ld iyl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, - {"inc [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"dec [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL}, - {"add iy, sp", Z80_OP16 ,NULL}, - {"ld b, iyh", Z80_OP16 ,NULL}, - {"ld b, iyl", Z80_OP16 ,NULL}, - {"ld b, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld c, iyh", Z80_OP16 ,NULL}, - {"ld c, iyl", Z80_OP16 ,NULL}, - {"ld c, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld d, iyh", Z80_OP16 ,NULL}, - {"ld d, iyl", Z80_OP16 ,NULL}, - {"ld d, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld e, iyh", Z80_OP16 ,NULL}, - {"ld e, iyl", Z80_OP16 ,NULL}, - {"ld e, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld iyh, b", Z80_OP16 ,NULL}, - {"ld iyh, c", Z80_OP16 ,NULL}, - {"ld iyh, d", Z80_OP16 ,NULL}, - {"ld iyh, e", Z80_OP16 ,NULL}, - {"ld iyh, iyh", Z80_OP16 ,NULL}, - {"ld iyh, iyl", Z80_OP16 ,NULL}, - {"ld h, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld iyh, a", Z80_OP16 ,NULL}, - {"ld iyl, b", Z80_OP16 ,NULL}, - {"ld iyl, c", Z80_OP16 ,NULL}, - {"ld iyl, d", Z80_OP16 ,NULL}, - {"ld iyl, e", Z80_OP16 ,NULL}, - {"ld iyl, iyh", Z80_OP16 ,NULL}, - {"ld iyl, iyl", Z80_OP16 ,NULL}, - {"ld l, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld iyl, a", Z80_OP16 ,NULL}, - {"ld [iy+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld [iy+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL}, - {"ld a, iyh", Z80_OP16 ,NULL}, - {"ld a, iyl", Z80_OP16 ,NULL}, - {"ld a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"add a, iyh", Z80_OP16 ,NULL}, - {"add a, iyl", Z80_OP16 ,NULL}, - {"add a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"adc a, iyh", Z80_OP16 ,NULL}, - {"adc a, iyl", Z80_OP16 ,NULL}, - {"adc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"sub iyh", Z80_OP16 ,NULL}, - {"sub iyl", Z80_OP16 ,NULL}, - {"sub [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"sbc a, iyh", Z80_OP16 ,NULL}, - {"sbc a, iyl", Z80_OP16 ,NULL}, - {"sbc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"and iyh", Z80_OP16 ,NULL}, - {"and iyl", Z80_OP16 ,NULL}, - {"and [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"xor iyh", Z80_OP16 ,NULL}, - {"xor iyl", Z80_OP16 ,NULL}, - {"xor [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"or iyh", Z80_OP16 ,NULL}, - {"or iyl", Z80_OP16 ,NULL}, - {"or [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"cp iyh", Z80_OP16 ,NULL}, - {"cp iyl", Z80_OP16 ,NULL}, - {"cp [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, - {"", Z80_OP24^Z80_ARG8 ,fdcb}, - {"pop iy", Z80_OP16 ,NULL}, - {"ex [sp], iy", Z80_OP16 ,NULL}, - {"push iy", Z80_OP16 ,NULL}, - {"jp [iy]", Z80_OP16 ,NULL}, - {"ld sp, iy", Z80_OP16 ,NULL}, - {"invalid", Z80_OP16 ,NULL} + { "add iy, bc", Z80_OP16 ,NULL}, + { "add iy, de", Z80_OP16 ,NULL}, + { "ld iy, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL}, + { "ld [0x%04x], iy", Z80_OP16^Z80_ARG16 ,NULL}, + { "inc iy", Z80_OP16 ,NULL}, + { "inc iyh", Z80_OP16 ,NULL}, + { "dec iyh", Z80_OP16 ,NULL}, + { "ld iyh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, + { "add iy, iy", Z80_OP16 ,NULL}, + { "ld iy, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL}, + { "dec iy", Z80_OP16 ,NULL}, + { "inc iyl", Z80_OP16 ,NULL}, + { "dec iyl", Z80_OP16 ,NULL}, + { "ld iyl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL}, + { "inc [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "dec [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL}, + { "add iy, sp", Z80_OP16 ,NULL}, + { "ld b, iyh", Z80_OP16 ,NULL}, + { "ld b, iyl", Z80_OP16 ,NULL}, + { "ld b, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld c, iyh", Z80_OP16 ,NULL}, + { "ld c, iyl", Z80_OP16 ,NULL}, + { "ld c, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld d, iyh", Z80_OP16 ,NULL}, + { "ld d, iyl", Z80_OP16 ,NULL}, + { "ld d, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld e, iyh", Z80_OP16 ,NULL}, + { "ld e, iyl", Z80_OP16 ,NULL}, + { "ld e, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld iyh, b", Z80_OP16 ,NULL}, + { "ld iyh, c", Z80_OP16 ,NULL}, + { "ld iyh, d", Z80_OP16 ,NULL}, + { "ld iyh, e", Z80_OP16 ,NULL}, + { "ld iyh, iyh", Z80_OP16 ,NULL}, + { "ld iyh, iyl", Z80_OP16 ,NULL}, + { "ld h, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld iyh, a", Z80_OP16 ,NULL}, + { "ld iyl, b", Z80_OP16 ,NULL}, + { "ld iyl, c", Z80_OP16 ,NULL}, + { "ld iyl, d", Z80_OP16 ,NULL}, + { "ld iyl, e", Z80_OP16 ,NULL}, + { "ld iyl, iyh", Z80_OP16 ,NULL}, + { "ld iyl, iyl", Z80_OP16 ,NULL}, + { "ld l, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld iyl, a", Z80_OP16 ,NULL}, + { "ld [iy+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld [iy+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL}, + { "ld a, iyh", Z80_OP16 ,NULL}, + { "ld a, iyl", Z80_OP16 ,NULL}, + { "ld a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "add a, iyh", Z80_OP16 ,NULL}, + { "add a, iyl", Z80_OP16 ,NULL}, + { "add a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "adc a, iyh", Z80_OP16 ,NULL}, + { "adc a, iyl", Z80_OP16 ,NULL}, + { "adc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "sub iyh", Z80_OP16 ,NULL}, + { "sub iyl", Z80_OP16 ,NULL}, + { "sub [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "sbc a, iyh", Z80_OP16 ,NULL}, + { "sbc a, iyl", Z80_OP16 ,NULL}, + { "sbc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "and iyh", Z80_OP16 ,NULL}, + { "and iyl", Z80_OP16 ,NULL}, + { "and [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "xor iyh", Z80_OP16 ,NULL}, + { "xor iyl", Z80_OP16 ,NULL}, + { "xor [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "or iyh", Z80_OP16 ,NULL}, + { "or iyl", Z80_OP16 ,NULL}, + { "or [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "cp iyh", Z80_OP16 ,NULL}, + { "cp iyl", Z80_OP16 ,NULL}, + { "cp [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL}, + { "", Z80_OP24^Z80_ARG8 ,fdcb}, + { "pop iy", Z80_OP16 ,NULL}, + { "ex [sp], iy", Z80_OP16 ,NULL}, + { "push iy", Z80_OP16 ,NULL}, + { "jp [iy]", Z80_OP16 ,NULL}, + { "ld sp, iy", Z80_OP16 ,NULL}, + { "invalid", Z80_OP16 ,NULL} }; static const z80_opcode z80_op[] = { - {"nop", Z80_OP8 ,NULL}, - {"ld bc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ld [bc], a", Z80_OP8 ,NULL}, - {"inc bc", Z80_OP8 ,NULL}, - {"inc b", Z80_OP8 ,NULL}, - {"dec b", Z80_OP8 ,NULL}, - {"ld b, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rlca", Z80_OP8 ,NULL}, - {"ex af, af'", Z80_OP8 ,NULL}, - {"add hl, bc", Z80_OP8 ,NULL}, - {"ld a, [bc]", Z80_OP8 ,NULL}, - {"dec bc", Z80_OP8 ,NULL}, - {"inc c", Z80_OP8 ,NULL}, - {"dec c", Z80_OP8 ,NULL}, - {"ld c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rrca", Z80_OP8 ,NULL}, - {"djnz 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"ld de, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ld [de], a", Z80_OP8 ,NULL}, - {"inc de", Z80_OP8 ,NULL}, - {"inc d", Z80_OP8 ,NULL}, - {"dec d", Z80_OP8 ,NULL}, - {"ld d, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rla", Z80_OP8 ,NULL}, - {"jr 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"add hl, de", Z80_OP8 ,NULL}, - {"ld a, [de]", Z80_OP8 ,NULL}, - {"dec de", Z80_OP8 ,NULL}, - {"inc e", Z80_OP8 ,NULL}, - {"dec e", Z80_OP8 ,NULL}, - {"ld e, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rra", Z80_OP8 ,NULL}, - {"jr nz, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"ld hl, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ld [0x%04x], hl", Z80_OP8^Z80_ARG16 ,NULL}, - {"inc hl", Z80_OP8 ,NULL}, - {"inc h", Z80_OP8 ,NULL}, - {"dec h", Z80_OP8 ,NULL}, - {"ld h, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"daa", Z80_OP8 ,NULL}, - {"jr z, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"add hl, hl", Z80_OP8 ,NULL}, - {"ld hl, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL}, - {"dec hl", Z80_OP8 ,NULL}, - {"inc l", Z80_OP8 ,NULL}, - {"dec l", Z80_OP8 ,NULL}, - {"ld l, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"cpl", Z80_OP8 ,NULL}, - {"jr nc, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"ld sp, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ld [0x%04x], a", Z80_OP8^Z80_ARG16 ,NULL}, - {"inc sp", Z80_OP8 ,NULL}, - {"inc [hl]", Z80_OP8 ,NULL}, - {"dec [hl]", Z80_OP8 ,NULL}, - {"ld [hl], 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"scf", Z80_OP8 ,NULL}, - {"jr c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"add hl, sp", Z80_OP8 ,NULL}, - {"ld a, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL}, - {"dec sp", Z80_OP8 ,NULL}, - {"inc a", Z80_OP8 ,NULL}, - {"dec a", Z80_OP8 ,NULL}, - {"ld a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"ccf", Z80_OP8 ,NULL}, - {"ld b, b", Z80_OP8 ,NULL}, - {"ld b, c", Z80_OP8 ,NULL}, - {"ld b, d", Z80_OP8 ,NULL}, - {"ld b, e", Z80_OP8 ,NULL}, - {"ld b, h", Z80_OP8 ,NULL}, - {"ld b, l", Z80_OP8 ,NULL}, - {"ld b, [hl]", Z80_OP8 ,NULL}, - {"ld b, a", Z80_OP8 ,NULL}, - {"ld c, b", Z80_OP8 ,NULL}, - {"ld c, c", Z80_OP8 ,NULL}, - {"ld c, d", Z80_OP8 ,NULL}, - {"ld c, e", Z80_OP8 ,NULL}, - {"ld c, h", Z80_OP8 ,NULL}, - {"ld c, l", Z80_OP8 ,NULL}, - {"ld c, [hl]", Z80_OP8 ,NULL}, - {"ld c, a", Z80_OP8 ,NULL}, - {"ld d, b", Z80_OP8 ,NULL}, - {"ld d, c", Z80_OP8 ,NULL}, - {"ld d, d", Z80_OP8 ,NULL}, - {"ld d, e", Z80_OP8 ,NULL}, - {"ld d, h", Z80_OP8 ,NULL}, - {"ld d, l", Z80_OP8 ,NULL}, - {"ld d, [hl]", Z80_OP8 ,NULL}, - {"ld d, a", Z80_OP8 ,NULL}, - {"ld e, b", Z80_OP8 ,NULL}, - {"ld e, c", Z80_OP8 ,NULL}, - {"ld e, d", Z80_OP8 ,NULL}, - {"ld e, e", Z80_OP8 ,NULL}, - {"ld e, h", Z80_OP8 ,NULL}, - {"ld e, l", Z80_OP8 ,NULL}, - {"ld e, [hl]", Z80_OP8 ,NULL}, - {"ld e, a", Z80_OP8 ,NULL}, - {"ld h, b", Z80_OP8 ,NULL}, - {"ld h, c", Z80_OP8 ,NULL}, - {"ld h, d", Z80_OP8 ,NULL}, - {"ld h, e", Z80_OP8 ,NULL}, - {"ld h, h", Z80_OP8 ,NULL}, - {"ld h, l", Z80_OP8 ,NULL}, - {"ld h, [hl]", Z80_OP8 ,NULL}, - {"ld h, a", Z80_OP8 ,NULL}, - {"ld l, b", Z80_OP8 ,NULL}, - {"ld l, c", Z80_OP8 ,NULL}, - {"ld l, d", Z80_OP8 ,NULL}, - {"ld l, e", Z80_OP8 ,NULL}, - {"ld l, h", Z80_OP8 ,NULL}, - {"ld l, l", Z80_OP8 ,NULL}, - {"ld l, [hl]", Z80_OP8 ,NULL}, - {"ld l, a", Z80_OP8 ,NULL}, - {"ld [hl], b", Z80_OP8 ,NULL}, - {"ld [hl], c", Z80_OP8 ,NULL}, - {"ld [hl], d", Z80_OP8 ,NULL}, - {"ld [hl], e", Z80_OP8 ,NULL}, - {"ld [hl], h", Z80_OP8 ,NULL}, - {"ld [hl], l", Z80_OP8 ,NULL}, - {"halt", Z80_OP8 ,NULL}, - {"ld [hl], a", Z80_OP8 ,NULL}, - {"ld a, b", Z80_OP8 ,NULL}, - {"ld a, c", Z80_OP8 ,NULL}, - {"ld a, d", Z80_OP8 ,NULL}, - {"ld a, e", Z80_OP8 ,NULL}, - {"ld a, h", Z80_OP8 ,NULL}, - {"ld a, l", Z80_OP8 ,NULL}, - {"ld a, [hl]", Z80_OP8 ,NULL}, - {"ld a, a", Z80_OP8 ,NULL}, - {"add a, b", Z80_OP8 ,NULL}, - {"add a, c", Z80_OP8 ,NULL}, - {"add a, d", Z80_OP8 ,NULL}, - {"add a, e", Z80_OP8 ,NULL}, - {"add a, h", Z80_OP8 ,NULL}, - {"add a, l", Z80_OP8 ,NULL}, - {"add a, [hl]", Z80_OP8 ,NULL}, - {"add a, a", Z80_OP8 ,NULL}, - {"adc a, b", Z80_OP8 ,NULL}, - {"adc a, c", Z80_OP8 ,NULL}, - {"adc a, d", Z80_OP8 ,NULL}, - {"adc a, e", Z80_OP8 ,NULL}, - {"adc a, h", Z80_OP8 ,NULL}, - {"adc a, l", Z80_OP8 ,NULL}, - {"adc a, [hl]", Z80_OP8 ,NULL}, - {"adc a, a", Z80_OP8 ,NULL}, - {"sub b", Z80_OP8 ,NULL}, - {"sub c", Z80_OP8 ,NULL}, - {"sub d", Z80_OP8 ,NULL}, - {"sub e", Z80_OP8 ,NULL}, - {"sub h", Z80_OP8 ,NULL}, - {"sub l", Z80_OP8 ,NULL}, - {"sub [hl]", Z80_OP8 ,NULL}, - {"sub a", Z80_OP8 ,NULL}, - {"sbc a, b", Z80_OP8 ,NULL}, - {"sbc a, c", Z80_OP8 ,NULL}, - {"sbc a, d", Z80_OP8 ,NULL}, - {"sbc a, e", Z80_OP8 ,NULL}, - {"sbc a, h", Z80_OP8 ,NULL}, - {"sbc a, l", Z80_OP8 ,NULL}, - {"sbc a, [hl]", Z80_OP8 ,NULL}, - {"sbc a, a", Z80_OP8 ,NULL}, - {"and b", Z80_OP8 ,NULL}, - {"and c", Z80_OP8 ,NULL}, - {"and d", Z80_OP8 ,NULL}, - {"and e", Z80_OP8 ,NULL}, - {"and h", Z80_OP8 ,NULL}, - {"and l", Z80_OP8 ,NULL}, - {"and [hl]", Z80_OP8 ,NULL}, - {"and a", Z80_OP8 ,NULL}, - {"xor b", Z80_OP8 ,NULL}, - {"xor c", Z80_OP8 ,NULL}, - {"xor d", Z80_OP8 ,NULL}, - {"xor e", Z80_OP8 ,NULL}, - {"xor h", Z80_OP8 ,NULL}, - {"xor l", Z80_OP8 ,NULL}, - {"xor [hl]", Z80_OP8 ,NULL}, - {"xor a", Z80_OP8 ,NULL}, - {"or b", Z80_OP8 ,NULL}, - {"or c", Z80_OP8 ,NULL}, - {"or d", Z80_OP8 ,NULL}, - {"or e", Z80_OP8 ,NULL}, - {"or h", Z80_OP8 ,NULL}, - {"or l", Z80_OP8 ,NULL}, - {"or [hl]", Z80_OP8 ,NULL}, - {"or a", Z80_OP8 ,NULL}, - {"cp b", Z80_OP8 ,NULL}, - {"cp c", Z80_OP8 ,NULL}, - {"cp d", Z80_OP8 ,NULL}, - {"cp e", Z80_OP8 ,NULL}, - {"cp h", Z80_OP8 ,NULL}, - {"cp l", Z80_OP8 ,NULL}, - {"cp [hl]", Z80_OP8 ,NULL}, - {"cp a", Z80_OP8 ,NULL}, - {"ret nz", Z80_OP8 ,NULL}, - {"pop bc", Z80_OP8 ,NULL}, - {"jp nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"jp 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"call nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"push bc", Z80_OP8 ,NULL}, - {"add a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x00", Z80_OP8 ,NULL}, - {"ret z", Z80_OP8 ,NULL}, - {"ret", Z80_OP8 ,NULL}, - {"jp z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"", Z80_OP16 ,cb}, - {"call z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"call 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"adc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x08", Z80_OP8 ,NULL}, - {"ret nc", Z80_OP8 ,NULL}, - {"pop de", Z80_OP8 ,NULL}, - {"jp nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"out [0x%02x], a", Z80_OP8^Z80_ARG8 ,NULL}, - {"call nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"push de", Z80_OP8 ,NULL}, - {"sub 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x10", Z80_OP8 ,NULL}, - {"ret c", Z80_OP8 ,NULL}, - {"exx", Z80_OP8 ,NULL}, - {"jp c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"in a, [0x%02x]", Z80_OP8^Z80_ARG8 ,NULL}, - {"call c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"", Z80_OP_UNK^Z80_ENC0 ,dd}, - {"sbc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x18", Z80_OP8 ,NULL}, - {"ret po", Z80_OP8 ,NULL}, - {"pop hl", Z80_OP8 ,NULL}, - {"jp po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ex [sp], hl", Z80_OP8 ,NULL}, - {"call po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"push hl", Z80_OP8 ,NULL}, - {"and 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x20", Z80_OP8 ,NULL}, - {"ret pe", Z80_OP8 ,NULL}, - {"jp [hl]", Z80_OP8 ,NULL}, - {"jp pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ex de, hl", Z80_OP8 ,NULL}, - {"call pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"", Z80_OP_UNK^Z80_ENC1 ,ed}, - {"xor 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x28", Z80_OP8 ,NULL}, - {"ret p", Z80_OP8 ,NULL}, - {"pop af", Z80_OP8 ,NULL}, - {"jp p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"di", Z80_OP8 ,NULL}, - {"call p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"push af", Z80_OP8 ,NULL}, - {"or 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x30", Z80_OP8 ,NULL}, - {"ret m", Z80_OP8 ,NULL}, - {"ld sp, hl", Z80_OP8 ,NULL}, - {"jp m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"ei", Z80_OP8 ,NULL}, - {"call m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, - {"", Z80_OP_UNK^Z80_ENC0 ,fd}, - {"cp 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, - {"rst 0x38", Z80_OP8 ,NULL}, + { "nop", Z80_OP8 ,NULL}, + { "ld bc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ld [bc], a", Z80_OP8 ,NULL}, + { "inc bc", Z80_OP8 ,NULL}, + { "inc b", Z80_OP8 ,NULL}, + { "dec b", Z80_OP8 ,NULL}, + { "ld b, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rlca", Z80_OP8 ,NULL}, + { "ex af, af'", Z80_OP8 ,NULL}, + { "add hl, bc", Z80_OP8 ,NULL}, + { "ld a, [bc]", Z80_OP8 ,NULL}, + { "dec bc", Z80_OP8 ,NULL}, + { "inc c", Z80_OP8 ,NULL}, + { "dec c", Z80_OP8 ,NULL}, + { "ld c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rrca", Z80_OP8 ,NULL}, + { "djnz 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "ld de, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ld [de], a", Z80_OP8 ,NULL}, + { "inc de", Z80_OP8 ,NULL}, + { "inc d", Z80_OP8 ,NULL}, + { "dec d", Z80_OP8 ,NULL}, + { "ld d, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rla", Z80_OP8 ,NULL}, + { "jr 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "add hl, de", Z80_OP8 ,NULL}, + { "ld a, [de]", Z80_OP8 ,NULL}, + { "dec de", Z80_OP8 ,NULL}, + { "inc e", Z80_OP8 ,NULL}, + { "dec e", Z80_OP8 ,NULL}, + { "ld e, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rra", Z80_OP8 ,NULL}, + { "jr nz, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "ld hl, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ld [0x%04x], hl", Z80_OP8^Z80_ARG16 ,NULL}, + { "inc hl", Z80_OP8 ,NULL}, + { "inc h", Z80_OP8 ,NULL}, + { "dec h", Z80_OP8 ,NULL}, + { "ld h, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "daa", Z80_OP8 ,NULL}, + { "jr z, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "add hl, hl", Z80_OP8 ,NULL}, + { "ld hl, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL}, + { "dec hl", Z80_OP8 ,NULL}, + { "inc l", Z80_OP8 ,NULL}, + { "dec l", Z80_OP8 ,NULL}, + { "ld l, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "cpl", Z80_OP8 ,NULL}, + { "jr nc, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "ld sp, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ld [0x%04x], a", Z80_OP8^Z80_ARG16 ,NULL}, + { "inc sp", Z80_OP8 ,NULL}, + { "inc [hl]", Z80_OP8 ,NULL}, + { "dec [hl]", Z80_OP8 ,NULL}, + { "ld [hl], 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "scf", Z80_OP8 ,NULL}, + { "jr c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "add hl, sp", Z80_OP8 ,NULL}, + { "ld a, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL}, + { "dec sp", Z80_OP8 ,NULL}, + { "inc a", Z80_OP8 ,NULL}, + { "dec a", Z80_OP8 ,NULL}, + { "ld a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "ccf", Z80_OP8 ,NULL}, + { "ld b, b", Z80_OP8 ,NULL}, + { "ld b, c", Z80_OP8 ,NULL}, + { "ld b, d", Z80_OP8 ,NULL}, + { "ld b, e", Z80_OP8 ,NULL}, + { "ld b, h", Z80_OP8 ,NULL}, + { "ld b, l", Z80_OP8 ,NULL}, + { "ld b, [hl]", Z80_OP8 ,NULL}, + { "ld b, a", Z80_OP8 ,NULL}, + { "ld c, b", Z80_OP8 ,NULL}, + { "ld c, c", Z80_OP8 ,NULL}, + { "ld c, d", Z80_OP8 ,NULL}, + { "ld c, e", Z80_OP8 ,NULL}, + { "ld c, h", Z80_OP8 ,NULL}, + { "ld c, l", Z80_OP8 ,NULL}, + { "ld c, [hl]", Z80_OP8 ,NULL}, + { "ld c, a", Z80_OP8 ,NULL}, + { "ld d, b", Z80_OP8 ,NULL}, + { "ld d, c", Z80_OP8 ,NULL}, + { "ld d, d", Z80_OP8 ,NULL}, + { "ld d, e", Z80_OP8 ,NULL}, + { "ld d, h", Z80_OP8 ,NULL}, + { "ld d, l", Z80_OP8 ,NULL}, + { "ld d, [hl]", Z80_OP8 ,NULL}, + { "ld d, a", Z80_OP8 ,NULL}, + { "ld e, b", Z80_OP8 ,NULL}, + { "ld e, c", Z80_OP8 ,NULL}, + { "ld e, d", Z80_OP8 ,NULL}, + { "ld e, e", Z80_OP8 ,NULL}, + { "ld e, h", Z80_OP8 ,NULL}, + { "ld e, l", Z80_OP8 ,NULL}, + { "ld e, [hl]", Z80_OP8 ,NULL}, + { "ld e, a", Z80_OP8 ,NULL}, + { "ld h, b", Z80_OP8 ,NULL}, + { "ld h, c", Z80_OP8 ,NULL}, + { "ld h, d", Z80_OP8 ,NULL}, + { "ld h, e", Z80_OP8 ,NULL}, + { "ld h, h", Z80_OP8 ,NULL}, + { "ld h, l", Z80_OP8 ,NULL}, + { "ld h, [hl]", Z80_OP8 ,NULL}, + { "ld h, a", Z80_OP8 ,NULL}, + { "ld l, b", Z80_OP8 ,NULL}, + { "ld l, c", Z80_OP8 ,NULL}, + { "ld l, d", Z80_OP8 ,NULL}, + { "ld l, e", Z80_OP8 ,NULL}, + { "ld l, h", Z80_OP8 ,NULL}, + { "ld l, l", Z80_OP8 ,NULL}, + { "ld l, [hl]", Z80_OP8 ,NULL}, + { "ld l, a", Z80_OP8 ,NULL}, + { "ld [hl], b", Z80_OP8 ,NULL}, + { "ld [hl], c", Z80_OP8 ,NULL}, + { "ld [hl], d", Z80_OP8 ,NULL}, + { "ld [hl], e", Z80_OP8 ,NULL}, + { "ld [hl], h", Z80_OP8 ,NULL}, + { "ld [hl], l", Z80_OP8 ,NULL}, + { "halt", Z80_OP8 ,NULL}, + { "ld [hl], a", Z80_OP8 ,NULL}, + { "ld a, b", Z80_OP8 ,NULL}, + { "ld a, c", Z80_OP8 ,NULL}, + { "ld a, d", Z80_OP8 ,NULL}, + { "ld a, e", Z80_OP8 ,NULL}, + { "ld a, h", Z80_OP8 ,NULL}, + { "ld a, l", Z80_OP8 ,NULL}, + { "ld a, [hl]", Z80_OP8 ,NULL}, + { "ld a, a", Z80_OP8 ,NULL}, + { "add a, b", Z80_OP8 ,NULL}, + { "add a, c", Z80_OP8 ,NULL}, + { "add a, d", Z80_OP8 ,NULL}, + { "add a, e", Z80_OP8 ,NULL}, + { "add a, h", Z80_OP8 ,NULL}, + { "add a, l", Z80_OP8 ,NULL}, + { "add a, [hl]", Z80_OP8 ,NULL}, + { "add a, a", Z80_OP8 ,NULL}, + { "adc a, b", Z80_OP8 ,NULL}, + { "adc a, c", Z80_OP8 ,NULL}, + { "adc a, d", Z80_OP8 ,NULL}, + { "adc a, e", Z80_OP8 ,NULL}, + { "adc a, h", Z80_OP8 ,NULL}, + { "adc a, l", Z80_OP8 ,NULL}, + { "adc a, [hl]", Z80_OP8 ,NULL}, + { "adc a, a", Z80_OP8 ,NULL}, + { "sub b", Z80_OP8 ,NULL}, + { "sub c", Z80_OP8 ,NULL}, + { "sub d", Z80_OP8 ,NULL}, + { "sub e", Z80_OP8 ,NULL}, + { "sub h", Z80_OP8 ,NULL}, + { "sub l", Z80_OP8 ,NULL}, + { "sub [hl]", Z80_OP8 ,NULL}, + { "sub a", Z80_OP8 ,NULL}, + { "sbc a, b", Z80_OP8 ,NULL}, + { "sbc a, c", Z80_OP8 ,NULL}, + { "sbc a, d", Z80_OP8 ,NULL}, + { "sbc a, e", Z80_OP8 ,NULL}, + { "sbc a, h", Z80_OP8 ,NULL}, + { "sbc a, l", Z80_OP8 ,NULL}, + { "sbc a, [hl]", Z80_OP8 ,NULL}, + { "sbc a, a", Z80_OP8 ,NULL}, + { "and b", Z80_OP8 ,NULL}, + { "and c", Z80_OP8 ,NULL}, + { "and d", Z80_OP8 ,NULL}, + { "and e", Z80_OP8 ,NULL}, + { "and h", Z80_OP8 ,NULL}, + { "and l", Z80_OP8 ,NULL}, + { "and [hl]", Z80_OP8 ,NULL}, + { "and a", Z80_OP8 ,NULL}, + { "xor b", Z80_OP8 ,NULL}, + { "xor c", Z80_OP8 ,NULL}, + { "xor d", Z80_OP8 ,NULL}, + { "xor e", Z80_OP8 ,NULL}, + { "xor h", Z80_OP8 ,NULL}, + { "xor l", Z80_OP8 ,NULL}, + { "xor [hl]", Z80_OP8 ,NULL}, + { "xor a", Z80_OP8 ,NULL}, + { "or b", Z80_OP8 ,NULL}, + { "or c", Z80_OP8 ,NULL}, + { "or d", Z80_OP8 ,NULL}, + { "or e", Z80_OP8 ,NULL}, + { "or h", Z80_OP8 ,NULL}, + { "or l", Z80_OP8 ,NULL}, + { "or [hl]", Z80_OP8 ,NULL}, + { "or a", Z80_OP8 ,NULL}, + { "cp b", Z80_OP8 ,NULL}, + { "cp c", Z80_OP8 ,NULL}, + { "cp d", Z80_OP8 ,NULL}, + { "cp e", Z80_OP8 ,NULL}, + { "cp h", Z80_OP8 ,NULL}, + { "cp l", Z80_OP8 ,NULL}, + { "cp [hl]", Z80_OP8 ,NULL}, + { "cp a", Z80_OP8 ,NULL}, + { "ret nz", Z80_OP8 ,NULL}, + { "pop bc", Z80_OP8 ,NULL}, + { "jp nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "jp 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "call nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "push bc", Z80_OP8 ,NULL}, + { "add a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x00", Z80_OP8 ,NULL}, + { "ret z", Z80_OP8 ,NULL}, + { "ret", Z80_OP8 ,NULL}, + { "jp z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "", Z80_OP16 ,cb}, + { "call z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "call 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "adc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x08", Z80_OP8 ,NULL}, + { "ret nc", Z80_OP8 ,NULL}, + { "pop de", Z80_OP8 ,NULL}, + { "jp nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "out [0x%02x], a", Z80_OP8^Z80_ARG8 ,NULL}, + { "call nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "push de", Z80_OP8 ,NULL}, + { "sub 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x10", Z80_OP8 ,NULL}, + { "ret c", Z80_OP8 ,NULL}, + { "exx", Z80_OP8 ,NULL}, + { "jp c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "in a, [0x%02x]", Z80_OP8^Z80_ARG8 ,NULL}, + { "call c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "", Z80_OP_UNK^Z80_ENC0 ,dd}, + { "sbc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x18", Z80_OP8 ,NULL}, + { "ret po", Z80_OP8 ,NULL}, + { "pop hl", Z80_OP8 ,NULL}, + { "jp po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ex [sp], hl", Z80_OP8 ,NULL}, + { "call po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "push hl", Z80_OP8 ,NULL}, + { "and 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x20", Z80_OP8 ,NULL}, + { "ret pe", Z80_OP8 ,NULL}, + { "jp [hl]", Z80_OP8 ,NULL}, + { "jp pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ex de, hl", Z80_OP8 ,NULL}, + { "call pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "", Z80_OP_UNK^Z80_ENC1 ,ed}, + { "xor 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x28", Z80_OP8 ,NULL}, + { "ret p", Z80_OP8 ,NULL}, + { "pop af", Z80_OP8 ,NULL}, + { "jp p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "di", Z80_OP8 ,NULL}, + { "call p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "push af", Z80_OP8 ,NULL}, + { "or 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x30", Z80_OP8 ,NULL}, + { "ret m", Z80_OP8 ,NULL}, + { "ld sp, hl", Z80_OP8 ,NULL}, + { "jp m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "ei", Z80_OP8 ,NULL}, + { "call m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL}, + { "", Z80_OP_UNK^Z80_ENC0 ,fd}, + { "cp 0x%02x", Z80_OP8^Z80_ARG8 ,NULL}, + { "rst 0x38", Z80_OP8 ,NULL}, }; #endif diff --git a/libr/anal/op.c b/libr/anal/op.c index c677b5e44f..4056b002f7 100644 --- a/libr/anal/op.c +++ b/libr/anal/op.c @@ -686,16 +686,16 @@ struct op_family { int id; }; static const struct op_family of[] = { - {"cpu", R_ANAL_OP_FAMILY_CPU}, - {"fpu", R_ANAL_OP_FAMILY_FPU}, - {"mmx", R_ANAL_OP_FAMILY_MMX}, - {"sse", R_ANAL_OP_FAMILY_SSE}, - {"priv", R_ANAL_OP_FAMILY_PRIV}, - {"virt", R_ANAL_OP_FAMILY_VIRT}, - {"crpt", R_ANAL_OP_FAMILY_CRYPTO}, - {"io", R_ANAL_OP_FAMILY_IO}, - {"sec", R_ANAL_OP_FAMILY_SECURITY}, - {"thread", R_ANAL_OP_FAMILY_THREAD}, + { "cpu", R_ANAL_OP_FAMILY_CPU}, + { "fpu", R_ANAL_OP_FAMILY_FPU}, + { "mmx", R_ANAL_OP_FAMILY_MMX}, + { "sse", R_ANAL_OP_FAMILY_SSE}, + { "priv", R_ANAL_OP_FAMILY_PRIV}, + { "virt", R_ANAL_OP_FAMILY_VIRT}, + { "crpt", R_ANAL_OP_FAMILY_CRYPTO}, + { "io", R_ANAL_OP_FAMILY_IO}, + { "sec", R_ANAL_OP_FAMILY_SECURITY}, + { "thread", R_ANAL_OP_FAMILY_THREAD}, }; R_API int r_anal_op_family_from_string(const char *f) { diff --git a/libr/anal/p/anal_8051.c b/libr/anal/p/anal_8051.c index 92a56d8373..806d5025c1 100644 --- a/libr/anal/p/anal_8051.c +++ b/libr/anal/p/anal_8051.c @@ -181,36 +181,36 @@ typedef struct { // custom reg read/write temporarily disabled - see r2 issue #9242 static RI8051Reg registers[] = { // keep these sorted - {"a", 0xE0, 0x00, 1, 0}, - {"b", 0xF0, 0x00, 1, 0}, - {"dph", 0x83, 0x00, 1, 0}, - {"dpl", 0x82, 0x00, 1, 0}, - {"dptr", 0x82, 0x00, 2, 0, 1}, - {"ie", 0xA8, 0x00, 1, 0}, - {"ip", 0xB8, 0x00, 1, 0}, - {"p0", 0x80, 0xFF, 1, 0}, - {"p1", 0x90, 0xFF, 1, 0}, - {"p2", 0xA0, 0xFF, 1, 0}, - {"p3", 0xB0, 0xFF, 1, 0}, - {"pcon", 0x87, 0x00, 1, 0}, - {"psw", 0xD0, 0x00, 1, 0}, - {"r0", 0x00, 0x00, 1, 1}, - {"r1", 0x01, 0x00, 1, 1}, - {"r2", 0x02, 0x00, 1, 1}, - {"r3", 0x03, 0x00, 1, 1}, - {"r4", 0x04, 0x00, 1, 1}, - {"r5", 0x05, 0x00, 1, 1}, - {"r6", 0x06, 0x00, 1, 1}, - {"r7", 0x07, 0x00, 1, 1}, - {"sbuf", 0x99, 0x00, 1, 0}, - {"scon", 0x98, 0x00, 1, 0}, - {"sp", 0x81, 0x07, 1, 0}, - {"tcon", 0x88, 0x00, 1, 0}, - {"th0", 0x8C, 0x00, 1, 0}, - {"th1", 0x8D, 0x00, 1, 0}, - {"tl0", 0x8A, 0x00, 1, 0}, - {"tl1", 0x8B, 0x00, 1, 0}, - {"tmod", 0x89, 0x00, 1, 0} + { "a", 0xE0, 0x00, 1, 0}, + { "b", 0xF0, 0x00, 1, 0}, + { "dph", 0x83, 0x00, 1, 0}, + { "dpl", 0x82, 0x00, 1, 0}, + { "dptr", 0x82, 0x00, 2, 0, 1}, + { "ie", 0xA8, 0x00, 1, 0}, + { "ip", 0xB8, 0x00, 1, 0}, + { "p0", 0x80, 0xFF, 1, 0}, + { "p1", 0x90, 0xFF, 1, 0}, + { "p2", 0xA0, 0xFF, 1, 0}, + { "p3", 0xB0, 0xFF, 1, 0}, + { "pcon", 0x87, 0x00, 1, 0}, + { "psw", 0xD0, 0x00, 1, 0}, + { "r0", 0x00, 0x00, 1, 1}, + { "r1", 0x01, 0x00, 1, 1}, + { "r2", 0x02, 0x00, 1, 1}, + { "r3", 0x03, 0x00, 1, 1}, + { "r4", 0x04, 0x00, 1, 1}, + { "r5", 0x05, 0x00, 1, 1}, + { "r6", 0x06, 0x00, 1, 1}, + { "r7", 0x07, 0x00, 1, 1}, + { "sbuf", 0x99, 0x00, 1, 0}, + { "scon", 0x98, 0x00, 1, 0}, + { "sp", 0x81, 0x07, 1, 0}, + { "tcon", 0x88, 0x00, 1, 0}, + { "th0", 0x8C, 0x00, 1, 0}, + { "th1", 0x8D, 0x00, 1, 0}, + { "tl0", 0x8A, 0x00, 1, 0}, + { "tl1", 0x8B, 0x00, 1, 0}, + { "tmod", 0x89, 0x00, 1, 0} }; #endif diff --git a/libr/anal/p/anal_gb.c b/libr/anal/p/anal_gb.c index 1ce9f704b7..0be5cd2875 100644 --- a/libr/anal/p/anal_gb.c +++ b/libr/anal/p/anal_gb.c @@ -1,14 +1,9 @@ -/* radare - LGPL - Copyright 2012 - pancake - 2022 - condret - +/* radare - LGPL - Copyright 2012 - pancake 2022 - condret this file was based on anal_i8080.c */ -#include -#include #include #include #include -#include #include "gb/gbdis.c" #include "gb/gbasm.c" #include "gb/gb_makros.h" @@ -16,11 +11,11 @@ #include "gb/gb_makros.h" #include "gb/gb.h" -static const char *regs_1[] = { "Z", "N", "H", "C"}; -static const char *regs_8[] = { "b", "c", "d", "e", "h", "l", "a", "a"}; //deprecate this and rename regs_x -static const char *regs_x[] = { "b", "c", "d", "e", "h", "l", "hl", "a"}; -static const char *regs_16[] = { "bc", "de", "hl", "sp"}; -static const char *regs_16_alt[] = { "bc", "de", "hl", "af" }; +static const char * const regs_1[] = { "Z", "N", "H", "C" }; +static const char * const regs_8[] = { "b", "c", "d", "e", "h", "l", "a", "a" }; //deprecate this and rename regs_x +static const char * const regs_x[] = { "b", "c", "d", "e", "h", "l", "hl", "a" }; +static const char * const regs_16[] = { "bc", "de", "hl", "sp" }; +static const char * const regs_16_alt[] = { "bc", "de", "hl", "af" }; static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr) { if (GB_IS_RAM_DST (data[1],data[2])) { @@ -36,11 +31,11 @@ static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr) { return true; } -#if 0 +#if 0 static inline int gb_anal_esil_banksw(RAnalOp *op) { ut64 base = op->dst->base; if (op->addr < 0x4000 && 0x1fff < base && base < 0x4000) { - r_strbuf_set (&op->esil, "mbcrom=0,?a%0x20,mbcrom=a-1"); //if a is a multiple of 0x20 mbcrom is 0, else it gets its value from a + r_strbuf_set (&op->esil, "mbcrom=0,?a%0x20,mbcrom=a-1"); //if a is a multiple of 0x20 mbcrom is 0, else it gets its value from a return true; } if (base < 0x6000 && 0x3fff < base) { @@ -470,7 +465,7 @@ static void gb_anal_xoaasc_imm(RReg *reg, RAnalOp *op, const ut8 *data) { } } - //load with [hl] as memref +//load with [hl] as memref static inline void gb_anal_load_hl(RReg *reg, RAnalOp *op, const ut8 data) { RAnalValue *dst, *src; dst = r_vector_push (op->dsts, NULL); diff --git a/libr/anal/p/anal_sh.c b/libr/anal/p/anal_sh.c index dcf5ee7dcd..4690b39324 100644 --- a/libr/anal/p/anal_sh.c +++ b/libr/anal/p/anal_sh.c @@ -199,7 +199,7 @@ static ut64 disarm_8bit_offset(ut64 pc, ut32 offs) { return (off << 1) + pc + 4; } -static char *regs[]={"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","pc"}; +static char *regs[]={ "r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","pc" }; static RAnalValue *anal_fill_ai_rg(RAnal *anal, int idx) { RAnalValue *ret = r_anal_value_new (); diff --git a/libr/anal/p/anal_x86_cs.c b/libr/anal/p/anal_x86_cs.c index ea5d198f24..cbf2228e95 100644 --- a/libr/anal/p/anal_x86_cs.c +++ b/libr/anal/p/anal_x86_cs.c @@ -347,7 +347,7 @@ static int cond_x862r2(int id) { /* reg indices are based on Intel doc for 32-bit ModR/M byte */ static const char *reg32_to_name(ut8 reg) { - const char * const names[] = {"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"}; + const char * const names[] = { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi" }; return reg < R_ARRAY_SIZE (names) ? names[reg] : "unk"; } diff --git a/libr/arch/archop.c b/libr/arch/archop.c index 71ae3c6115..3c77921db0 100644 --- a/libr/arch/archop.c +++ b/libr/arch/archop.c @@ -279,16 +279,16 @@ struct op_family { int id; }; static const struct op_family of[] = { - {"cpu", R_ARCH_OP_FAMILY_CPU}, - {"fpu", R_ARCH_OP_FAMILY_FPU}, - {"mmx", R_ARCH_OP_FAMILY_MMX}, - {"sse", R_ARCH_OP_FAMILY_SSE}, - {"priv", R_ARCH_OP_FAMILY_PRIV}, - {"virt", R_ARCH_OP_FAMILY_VIRT}, - {"crpt", R_ARCH_OP_FAMILY_CRYPTO}, - {"io", R_ARCH_OP_FAMILY_IO}, - {"sec", R_ARCH_OP_FAMILY_SECURITY}, - {"thread", R_ARCH_OP_FAMILY_THREAD}, + { "cpu", R_ARCH_OP_FAMILY_CPU}, + { "fpu", R_ARCH_OP_FAMILY_FPU}, + { "mmx", R_ARCH_OP_FAMILY_MMX}, + { "sse", R_ARCH_OP_FAMILY_SSE}, + { "priv", R_ARCH_OP_FAMILY_PRIV}, + { "virt", R_ARCH_OP_FAMILY_VIRT}, + { "crpt", R_ARCH_OP_FAMILY_CRYPTO}, + { "io", R_ARCH_OP_FAMILY_IO}, + { "sec", R_ARCH_OP_FAMILY_SECURITY}, + { "thread", R_ARCH_OP_FAMILY_THREAD}, }; R_API int r_arch_op_family_from_string(const char *f) { diff --git a/libr/asm/arch/arm/aarch64/aarch64-opc-2.c b/libr/asm/arch/arm/aarch64/aarch64-opc-2.c index 56b8118f06..c1304bbdf9 100644 --- a/libr/asm/arch/arm/aarch64/aarch64-opc-2.c +++ b/libr/asm/arch/arm/aarch64/aarch64-opc-2.c @@ -24,200 +24,200 @@ const struct aarch64_operand aarch64_operands[] = { - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, ""}, - {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {0}, "the second reg of a pair"}, - {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional extension"}, - {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional shift"}, - {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"}, - {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector element list"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a left shift amount for an AdvSIMD register"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a right shift amount for an AdvSIMD register"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit unsigned immediate with optional shift"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit floating-point constant"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {0}, "an immediate shift amount of 8, 16 or 32"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {0}, "0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {0}, "0.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {0}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a condition"}, - {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "one of the standard conditions, excluding AL and NV."}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a post-indexed address with immediate or register increment"}, - {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a system register"}, - {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a PSTATE field name"}, - {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address translation operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a data cache maintenance operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an instruction cache maintenance operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a TBL invalidation operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a barrier option name"}, - {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the ISB option name SY or an optional 4-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a prefetch operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the PSB option name CSYNC"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"}, - {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "" }, + {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register" }, + {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register" }, + {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {0}, "the second reg of a pair" }, + {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional extension" }, + {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional shift" }, + {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register" }, + {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register" }, + {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register" }, + {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register" }, + {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register" }, + {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register" }, + {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register" }, + {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register" }, + {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register" }, + {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register" }, + {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register" }, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element" }, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element" }, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element" }, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15" }, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list" }, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list" }, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list" }, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector element list" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a left shift amount for an AdvSIMD register" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a right shift amount for an AdvSIMD register" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit unsigned immediate with optional shift" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit floating-point constant" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {0}, "an immediate shift amount of 8, 16 or 32" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {0}, "0" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {0}, "0.0" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {0}, "an immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations" }, + {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a condition" }, + {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "one of the standard conditions, excluding AL and NV." }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)" }, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a post-indexed address with immediate or register increment" }, + {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a system register" }, + {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a PSTATE field name" }, + {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address translation operation specifier" }, + {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a data cache maintenance operation specifier" }, + {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an instruction cache maintenance operation specifier" }, + {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a TBL invalidation operation specifier" }, + {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a barrier option name" }, + {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the ISB option name SY or an optional 4-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a prefetch operation specifier" }, + {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the PSB option name CSYNC" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register" }, + {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero" }, + {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate" }, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register" }, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register" }, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers" }, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate" }, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY" }, }; /* Indexed by an enum aarch64_op enumerator, the value is the offset of diff --git a/libr/asm/arch/arm/aarch64/aarch64-opc.c b/libr/asm/arch/arm/aarch64/aarch64-opc.c index 2cb721c397..eddb4f34da 100644 --- a/libr/asm/arch/arm/aarch64/aarch64-opc.c +++ b/libr/asm/arch/arm/aarch64/aarch64-opc.c @@ -344,22 +344,22 @@ aarch64_get_operand_desc (enum aarch64_opnd type) /* Table of all conditional affixes. */ const aarch64_cond aarch64_conds[16] = { - {{"eq", "none"}, 0x0}, - {{"ne", "any"}, 0x1}, - {{"cs", "hs", "nlast"}, 0x2}, - {{"cc", "lo", "ul", "last"}, 0x3}, - {{"mi", "first"}, 0x4}, - {{"pl", "nfrst"}, 0x5}, - {{"vs"}, 0x6}, - {{"vc"}, 0x7}, - {{"hi", "pmore"}, 0x8}, - {{"ls", "plast"}, 0x9}, - {{"ge", "tcont"}, 0xa}, - {{"lt", "tstop"}, 0xb}, - {{"gt"}, 0xc}, - {{"le"}, 0xd}, - {{"al"}, 0xe}, - {{"nv"}, 0xf}, + {{ "eq", "none" }, 0x0}, + {{ "ne", "any" }, 0x1}, + {{ "cs", "hs", "nlast" }, 0x2}, + {{ "cc", "lo", "ul", "last" }, 0x3}, + {{ "mi", "first" }, 0x4}, + {{ "pl", "nfrst" }, 0x5}, + {{ "vs" }, 0x6}, + {{ "vc" }, 0x7}, + {{ "hi", "pmore" }, 0x8}, + {{ "ls", "plast" }, 0x9}, + {{ "ge", "tcont" }, 0xa}, + {{ "lt", "tstop" }, 0xb}, + {{ "gt" }, 0xc}, + {{ "le" }, 0xd}, + {{ "al" }, 0xe}, + {{ "nv" }, 0xf}, }; const aarch64_cond * @@ -382,22 +382,22 @@ get_inverted_cond (const aarch64_cond *cond) which enables table-driven encoding/decoding for the modifiers. */ const struct aarch64_name_value_pair aarch64_operand_modifiers [] = { - {"none", 0x0}, - {"msl", 0x0}, - {"ror", 0x3}, - {"asr", 0x2}, - {"lsr", 0x1}, - {"lsl", 0x0}, - {"uxtb", 0x0}, - {"uxth", 0x1}, - {"uxtw", 0x2}, - {"uxtx", 0x3}, - {"sxtb", 0x4}, - {"sxth", 0x5}, - {"sxtw", 0x6}, - {"sxtx", 0x7}, - {"mul", 0x0}, - {"mul vl", 0x0}, + { "none", 0x0}, + { "msl", 0x0}, + { "ror", 0x3}, + { "asr", 0x2}, + { "lsr", 0x1}, + { "lsl", 0x0}, + { "uxtb", 0x0}, + { "uxth", 0x1}, + { "uxtw", 0x2}, + { "uxtx", 0x3}, + { "sxtb", 0x4}, + { "sxth", 0x5}, + { "sxtw", 0x6}, + { "sxtx", 0x7}, + { "mul", 0x0}, + { "mul vl", 0x0}, {NULL, 0}, }; diff --git a/libr/asm/arch/arm/aarch64/aarch64-tbl.h b/libr/asm/arch/arm/aarch64/aarch64-tbl.h index d60f807f40..65b028ba58 100644 --- a/libr/asm/arch/arm/aarch64/aarch64-tbl.h +++ b/libr/asm/arch/arm/aarch64/aarch64-tbl.h @@ -3070,7 +3070,7 @@ struct aarch64_opcode aarch64_opcode_table[] = FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0), __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0), - {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL }, + { "fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL }, /* Floating-point conditional compare. */ __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), @@ -3250,13 +3250,13 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), - {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)}, + { "ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)}, /* Load/store register pair (indexed). */ CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), - {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)}, + { "ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)}, /* Load register (literal). */ CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q), CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0), @@ -3480,8 +3480,8 @@ struct aarch64_opcode aarch64_opcode_table[] = V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS), V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS), V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS), - {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {{0}}, F_ALIAS, 0, NULL}, - {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {{0}}, F_ALIAS, 0, NULL}, + { "esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {{0}}, F_ALIAS, 0, NULL}, + { "psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {{0}}, F_ALIAS, 0, NULL}, CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {{0}}, F_OPD0_OPT | F_DEFAULT (0xF)), CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {{0}}, F_HAS_ALIAS), CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {{0}}, F_ALIAS), diff --git a/libr/asm/arch/arm/armass.c b/libr/asm/arch/arm/armass.c index c4560bc3df..74a1b14079 100644 --- a/libr/asm/arch/arm/armass.c +++ b/libr/asm/arch/arm/armass.c @@ -52,7 +52,7 @@ static int strcmpnull(const char *a, const char *b) { return (a && b) ? strcmp (a, b) : -1; } -// static const char *const arm_shift[] = {"lsl", "lsr", "asr", "ror"}; +// static const char *const arm_shift[] = { "lsl", "lsr", "asr", "ror" }; static ArmOp ops[] = { { "adc", 0xa000, TYPE_ARI }, @@ -136,18 +136,18 @@ static ArmOp ops[] = { { "teq", 0x3001, TYPE_TST }, { "tst", 0x1001, TYPE_TST }, - {"lsr", 0x3000a0e1, TYPE_SHFT}, - {"asr", 0x5000a0e1, TYPE_SHFT}, - {"lsl", 0x1000a0e1, TYPE_SHFT}, - {"ror", 0x7000a0e1, TYPE_SHFT}, + { "lsr", 0x3000a0e1, TYPE_SHFT}, + { "asr", 0x5000a0e1, TYPE_SHFT}, + { "lsl", 0x1000a0e1, TYPE_SHFT}, + { "ror", 0x7000a0e1, TYPE_SHFT}, - {"rev16", 0xb00fbf06, TYPE_REV}, - {"revsh", 0xb00fff06, TYPE_REV}, - {"rev", 0x300fbf06, TYPE_REV}, - {"rbit", 0x300fff06, TYPE_REV}, + { "rev16", 0xb00fbf06, TYPE_REV}, + { "revsh", 0xb00fff06, TYPE_REV}, + { "rev", 0x300fbf06, TYPE_REV}, + { "rbit", 0x300fff06, TYPE_REV}, - {"mrc", 0x100010ee, TYPE_COPROC}, - {"setend", 0x000001f1, TYPE_ENDIAN}, + { "mrc", 0x100010ee, TYPE_COPROC}, + { "setend", 0x000001f1, TYPE_ENDIAN}, { "clz", 0x000f6f01, TYPE_CLZ}, { "neg", 0x7000, TYPE_NEG }, diff --git a/libr/asm/arch/arm/armass64.c b/libr/asm/arch/arm/armass64.c index 46ec2cbcbe..db506c4c54 100644 --- a/libr/asm/arch/arm/armass64.c +++ b/libr/asm/arch/arm/armass64.c @@ -87,9 +87,11 @@ typedef struct Opcode_t { static int get_mem_option(char *token) { // values 4, 8, 12, are unused. XXX to adjust - const char *options[] = {"sy", "st", "ld", "xxx", "ish", "ishst", - "ishld", "xxx", "nsh", "nshst", "nshld", - "xxx", "osh", "oshst", "oshld", NULL}; + const char *options[] = { + "sy", "st", "ld", "xxx", "ish", "ishst", + "ishld", "xxx", "nsh", "nshst", "nshld", + "xxx", "osh", "oshst", "oshld", NULL + }; int i = 0; while (options[i]) { if (!r_str_casecmp (token, options[i])) { diff --git a/libr/asm/arch/arm/gnu/arm-dis.c b/libr/asm/arch/arm/gnu/arm-dis.c index 1e01742bb2..a5eda8834e 100644 --- a/libr/asm/arch/arm/gnu/arm-dis.c +++ b/libr/asm/arch/arm/gnu/arm-dis.c @@ -160,850 +160,850 @@ static const struct opcode32 coprocessor_opcodes[] = /* XScale instructions. */ {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 0x0e200010, 0x0fff0ff0, - "mia%c acc0, %0-3r, %12-15r"}, + "mia%c acc0, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 0x0e280010, 0x0fff0ff0, - "miaph%c acc0, %0-3r, %12-15r"}, + "miaph%c acc0, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c acc0, %0-3r, %12-15r"}, + 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c acc0, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c400000, 0x0ff00fff, "mar%c acc0, %12-15r, %16-19r"}, + 0x0c400000, 0x0ff00fff, "mar%c acc0, %12-15r, %16-19r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c500000, 0x0ff00fff, "mra%c %12-15r, %16-19r, acc0"}, + 0x0c500000, 0x0ff00fff, "mra%c %12-15r, %16-19r, acc0" }, /* Intel Wireless MMX technology instructions. */ {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), - 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c %12-15r"}, + 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c %16-19g, %12-15r"}, + 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c %16-19g, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c %12-15r, %0-2d"}, + 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c %12-15r, %0-2d" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c %12-15r, %16-19g, %0-2d"}, + 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c %12-15r, %16-19g, %0-2d" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c %16-19g, %12-15r, %0-2d"}, + 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c %16-19g, %12-15r, %0-2d" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000110, 0x0ff00fff, "tmcr%c %16-19G, %12-15r"}, + 0x0e000110, 0x0ff00fff, "tmcr%c %16-19G, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c400000, 0x0ff00ff0, "tmcrr%c %0-3g, %12-15r, %16-19r"}, + 0x0c400000, 0x0ff00ff0, "tmcrr%c %0-3g, %12-15r, %16-19r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c %5-8g, %0-3r, %12-15r"}, + 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c %5-8g, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e200010, 0x0fff0e10, "tmia%c %5-8g, %0-3r, %12-15r"}, + 0x0e200010, 0x0fff0e10, "tmia%c %5-8g, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e280010, 0x0fff0e10, "tmiaph%c %5-8g, %0-3r, %12-15r"}, + 0x0e280010, 0x0fff0e10, "tmiaph%c %5-8g, %0-3r, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c %12-15r, %16-19g"}, + 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c %12-15r, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100110, 0x0ff00ff0, "tmrc%c %12-15r, %16-19G"}, + 0x0e100110, 0x0ff00ff0, "tmrc%c %12-15r, %16-19G" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c500000, 0x0ff00ff0, "tmrrc%c %12-15r, %16-19r, %0-3g"}, + 0x0c500000, 0x0ff00ff0, "tmrrc%c %12-15r, %16-19r, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e130150, 0x0f3f0fff, "torc%22-23w%c %12-15r"}, + 0x0e130150, 0x0f3f0fff, "torc%22-23w%c %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c %12-15r"}, + 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c %12-15g, %16-19g"}, + 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c %12-15g, %16-19g"}, + 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000180, 0x0f000ff0, "wadd%20-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e000180, 0x0f000ff0, "wadd%20-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c %12-15g, %16-19g, %0-3g"}, + 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c %12-15g, %16-19g, %0-3g"}, + 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000020, 0x0f800ff0, "waligni%c %12-15g, %16-19g, %0-3g, %20-22d"}, + 0x0e000020, 0x0f800ff0, "waligni%c %12-15g, %16-19g, %0-3g, %20-22d" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c %12-15g, %16-19g, %0-3g"}, + 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e200000, 0x0fe00ff0, "wand%20'n%c %12-15g, %16-19g, %0-3g"}, + 0x0e200000, 0x0fe00ff0, "wand%20'n%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c %12-15g, %16-19g, %0-3g"}, + 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c %12-15g, %16-19g, %0-3g"}, + 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfc500100, 0xfe500f00, "wldrd %12-15g, %r"}, + 0xfc500100, 0xfe500f00, "wldrd %12-15g, %r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfc100100, 0xfe500f00, "wldrw %12-15G, %A"}, + 0xfc100100, 0xfe500f00, "wldrw %12-15G, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c100000, 0x0e100e00, "wldr%L%c %12-15g, %l"}, + 0x0c100000, 0x0e100e00, "wldr%L%c %12-15g, %l" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c %12-15g, %16-19g, %0-3g"}, + 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c %12-15g, %16-19g, %0-3g"}, + 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c %12-15g, %16-19g, %0-3g"}, + 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000080, 0x0f100fe0, "wmerge%c %12-15g, %16-19g, %0-3g, %21-23d"}, + 0x0e000080, 0x0f100fe0, "wmerge%c %12-15g, %16-19g, %0-3g, %21-23d" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"}, + 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 0x0e800120, 0x0f800ff0, - "wmiaw%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"}, + "wmiaw%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c %12-15g, %16-19g, %0-3g"}, + 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c %12-15g, %16-19g, %0-3g"}, + 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c %12-15g, %16-19g, %0-3g"}, + 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c %12-15g, %16-19g, %0-3g"}, + 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0eb000c0, 0x0ff00ff0, "wmulwl%c %12-15g, %16-19g, %0-3g"}, + 0x0eb000c0, 0x0ff00ff0, "wmulwl%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 0x0e8000a0, 0x0f800ff0, - "wqmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"}, + "wqmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c %12-15g, %16-19g, %0-3g"}, + 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c %12-15g, %16-19g, %0-3g"}, + 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000000, 0x0ff00ff0, "wor%c %12-15g, %16-19g, %0-3g"}, + 0x0e000000, 0x0ff00ff0, "wor%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000080, 0x0f000ff0, "wpack%20-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e000080, 0x0f000ff0, "wpack%20-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfe300040, 0xff300ef0, "wror%22-23w %12-15g, %16-19g, %i"}, + 0xfe300040, 0xff300ef0, "wror%22-23w %12-15g, %16-19g, %i" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e300040, 0x0f300ff0, "wror%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e300040, 0x0f300ff0, "wror%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e300140, 0x0f300ff0, "wror%22-23wg%c %12-15g, %16-19g, %0-3G"}, + 0x0e300140, 0x0f300ff0, "wror%22-23wg%c %12-15g, %16-19g, %0-3G" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c %12-15g, %16-19g, %0-3g"}, + 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0001e0, 0x0f000ff0, "wshufh%c %12-15g, %16-19g, %Z"}, + 0x0e0001e0, 0x0f000ff0, "wshufh%c %12-15g, %16-19g, %Z" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfe100040, 0xff300ef0, "wsll%22-23w %12-15g, %16-19g, %i"}, + 0xfe100040, 0xff300ef0, "wsll%22-23w %12-15g, %16-19g, %i" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3g"}, + 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3G"}, + 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3G" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfe000040, 0xff300ef0, "wsra%22-23w %12-15g, %16-19g, %i"}, + 0xfe000040, 0xff300ef0, "wsra%22-23w %12-15g, %16-19g, %i" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3g"}, + 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3G"}, + 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3G" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfe200040, 0xff300ef0, "wsrl%22-23w %12-15g, %16-19g, %i"}, + 0xfe200040, 0xff300ef0, "wsrl%22-23w %12-15g, %16-19g, %i" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3g"}, + 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3G"}, + 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3G" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfc400100, 0xfe500f00, "wstrd %12-15g, %r"}, + 0xfc400100, 0xfe500f00, "wstrd %12-15g, %r" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0xfc000100, 0xfe500f00, "wstrw %12-15G, %A"}, + 0xfc000100, 0xfe500f00, "wstrw %12-15G, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0c000000, 0x0e100e00, "wstr%L%c %12-15g, %l"}, + 0x0c000000, 0x0e100e00, "wstr%L%c %12-15g, %l" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c %12-15g, %16-19g, %0-3g"}, + 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c %12-15g, %16-19g"}, + 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c %12-15g, %16-19g"}, + 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c %12-15g, %16-19g"}, + 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c %12-15g, %16-19g"}, + 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c %12-15g, %16-19g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c %12-15g, %16-19g, %0-3g"}, + 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), - 0x0e100000, 0x0ff00ff0, "wxor%c %12-15g, %16-19g, %0-3g"}, + 0x0e100000, 0x0ff00ff0, "wxor%c %12-15g, %16-19g, %0-3g" }, {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_END, 0, "" }, /* Floating point coprocessor (FPA) instructions. */ {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f"}, + 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f"}, + 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f"}, + 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f"}, + 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f"}, + 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f"}, + 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f"}, + 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f"}, + 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f"}, + 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f"}, + 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f"}, + 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f"}, + 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f"}, + 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f"}, + 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f"}, + 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ee08100, 0x0ff08f10, "urd%c%P%R %12-14f, %0-3f"}, + 0x0ee08100, 0x0ff08f10, "urd%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ef08100, 0x0ff08f10, "nrm%c%P%R %12-14f, %0-3f"}, + 0x0ef08100, 0x0ff08f10, "nrm%c%P%R %12-14f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r"}, + 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f"}, + 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e200110, 0x0fff0fff, "wfs%c %12-15r"}, + 0x0e200110, 0x0fff0fff, "wfs%c %12-15r" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e300110, 0x0fff0fff, "rfs%c %12-15r"}, + 0x0e300110, 0x0fff0fff, "rfs%c %12-15r" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e400110, 0x0fff0fff, "wfc%c %12-15r"}, + 0x0e400110, 0x0fff0fff, "wfc%c %12-15r" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e500110, 0x0fff0fff, "rfc%c %12-15r"}, + 0x0e500110, 0x0fff0fff, "rfc%c %12-15r" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f"}, + 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f"}, + 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f"}, + 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f"}, + 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A"}, + 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A"}, + 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), - 0x0c000200, 0x0e100f00, "sfm%c %12-14f, %F, %A"}, + 0x0c000200, 0x0e100f00, "sfm%c %12-14f, %F, %A" }, {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), - 0x0c100200, 0x0e100f00, "lfm%c %12-14f, %F, %A"}, + 0x0c100200, 0x0e100f00, "lfm%c %12-14f, %F, %A" }, /* ARMv8-M Mainline Security Extensions instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), - 0xec300a00, 0xfff0ffff, "vlldm %16-19r"}, + 0xec300a00, 0xfff0ffff, "vlldm %16-19r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), - 0xec200a00, 0xfff0ffff, "vlstm %16-19r"}, + 0xec200a00, 0xfff0ffff, "vlstm %16-19r" }, /* Register load/store. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0d2d0b00, 0x0fbf0f01, "vpush%c %B"}, + 0x0d2d0b00, 0x0fbf0f01, "vpush%c %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0d200b00, 0x0fb00f01, "vstmdb%c %16-19r!, %B"}, + 0x0d200b00, 0x0fb00f01, "vstmdb%c %16-19r!, %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0d300b00, 0x0fb00f01, "vldmdb%c %16-19r!, %B"}, + 0x0d300b00, 0x0fb00f01, "vldmdb%c %16-19r!, %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0c800b00, 0x0f900f01, "vstmia%c %16-19r%21'!, %B"}, + 0x0c800b00, 0x0f900f01, "vstmia%c %16-19r%21'!, %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0cbd0b00, 0x0fbf0f01, "vpop%c %B"}, + 0x0cbd0b00, 0x0fbf0f01, "vpop%c %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0c900b00, 0x0f900f01, "vldmia%c %16-19r%21'!, %B"}, + 0x0c900b00, 0x0f900f01, "vldmia%c %16-19r%21'!, %B" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0d000b00, 0x0f300f00, "vstr%c %12-15,22D, %A"}, + 0x0d000b00, 0x0f300f00, "vstr%c %12-15,22D, %A" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), - 0x0d100b00, 0x0f300f00, "vldr%c %12-15,22D, %A"}, + 0x0d100b00, 0x0f300f00, "vldr%c %12-15,22D, %A" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d2d0a00, 0x0fbf0f00, "vpush%c %y3"}, + 0x0d2d0a00, 0x0fbf0f00, "vpush%c %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d200a00, 0x0fb00f00, "vstmdb%c %16-19r!, %y3"}, + 0x0d200a00, 0x0fb00f00, "vstmdb%c %16-19r!, %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d300a00, 0x0fb00f00, "vldmdb%c %16-19r!, %y3"}, + 0x0d300a00, 0x0fb00f00, "vldmdb%c %16-19r!, %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0c800a00, 0x0f900f00, "vstmia%c %16-19r%21'!, %y3"}, + 0x0c800a00, 0x0f900f00, "vstmia%c %16-19r%21'!, %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0cbd0a00, 0x0fbf0f00, "vpop%c %y3"}, + 0x0cbd0a00, 0x0fbf0f00, "vpop%c %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0c900a00, 0x0f900f00, "vldmia%c %16-19r%21'!, %y3"}, + 0x0c900a00, 0x0f900f00, "vldmia%c %16-19r%21'!, %y3" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d000a00, 0x0f300f00, "vstr%c %y1, %A"}, + 0x0d000a00, 0x0f300f00, "vstr%c %y1, %A" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d100a00, 0x0f300f00, "vldr%c %y1, %A"}, + 0x0d100a00, 0x0f300f00, "vldr%c %y1, %A" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d200b01, 0x0fb00f01, "fstmdbx%c %16-19r!, %z3 ;@ Deprecated"}, + 0x0d200b01, 0x0fb00f01, "fstmdbx%c %16-19r!, %z3 ;@ Deprecated" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0d300b01, 0x0fb00f01, "fldmdbx%c %16-19r!, %z3 ;@ Deprecated"}, + 0x0d300b01, 0x0fb00f01, "fldmdbx%c %16-19r!, %z3 ;@ Deprecated" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0c800b01, 0x0f900f01, "fstmiax%c %16-19r%21'!, %z3 ;@ Deprecated"}, + 0x0c800b01, 0x0f900f01, "fstmiax%c %16-19r%21'!, %z3 ;@ Deprecated" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0c900b01, 0x0f900f01, "fldmiax%c %16-19r%21'!, %z3 ;@ Deprecated"}, + 0x0c900b01, 0x0f900f01, "fldmiax%c %16-19r%21'!, %z3 ;@ Deprecated" }, /* Data transfer between ARM and NEON registers. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e800b10, 0x0ff00f70, "vdup%c.32 %16-19,7D, %12-15r"}, + 0x0e800b10, 0x0ff00f70, "vdup%c.32 %16-19,7D, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e800b30, 0x0ff00f70, "vdup%c.16 %16-19,7D, %12-15r"}, + 0x0e800b30, 0x0ff00f70, "vdup%c.16 %16-19,7D, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ea00b10, 0x0ff00f70, "vdup%c.32 %16-19,7Q, %12-15r"}, + 0x0ea00b10, 0x0ff00f70, "vdup%c.32 %16-19,7Q, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ea00b30, 0x0ff00f70, "vdup%c.16 %16-19,7Q, %12-15r"}, + 0x0ea00b30, 0x0ff00f70, "vdup%c.16 %16-19,7Q, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ec00b10, 0x0ff00f70, "vdup%c.8 %16-19,7D, %12-15r"}, + 0x0ec00b10, 0x0ff00f70, "vdup%c.8 %16-19,7D, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ee00b10, 0x0ff00f70, "vdup%c.8 %16-19,7Q, %12-15r"}, + 0x0ee00b10, 0x0ff00f70, "vdup%c.8 %16-19,7Q, %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0c400b10, 0x0ff00fd0, "vmov%c %0-3,5D, %12-15r, %16-19r"}, + 0x0c400b10, 0x0ff00fd0, "vmov%c %0-3,5D, %12-15r, %16-19r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0c500b10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %0-3,5D"}, + 0x0c500b10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e000b10, 0x0fd00f70, "vmov%c.32 %16-19,7D[%21d], %12-15r"}, + 0x0e000b10, 0x0fd00f70, "vmov%c.32 %16-19,7D[%21d], %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e100b10, 0x0f500f70, "vmov%c.32 %12-15r, %16-19,7D[%21d]"}, + 0x0e100b10, 0x0f500f70, "vmov%c.32 %12-15r, %16-19,7D[%21d]" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e000b30, 0x0fd00f30, "vmov%c.16 %16-19,7D[%6,21d], %12-15r"}, + 0x0e000b30, 0x0fd00f30, "vmov%c.16 %16-19,7D[%6,21d], %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16 %12-15r, %16-19,7D[%6,21d]"}, + 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16 %12-15r, %16-19,7D[%6,21d]" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e400b10, 0x0fd00f10, "vmov%c.8 %16-19,7D[%5,6,21d], %12-15r"}, + 0x0e400b10, 0x0fd00f10, "vmov%c.8 %16-19,7D[%5,6,21d], %12-15r" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8 %12-15r, %16-19,7D[%5,6,21d]"}, + 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8 %12-15r, %16-19,7D[%5,6,21d]" }, /* Half-precision conversion instructions. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16 %z1, %y0"}, + 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16 %z1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64 %y1, %z0"}, + 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64 %y1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), - 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16 %y1, %y0"}, + 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), - 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32 %y1, %y0"}, + 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32 %y1, %y0" }, /* Floating point coprocessor (VFP) instructions. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee00a10, 0x0fff0fff, "vmsr%c fpsid, %12-15r"}, + 0x0ee00a10, 0x0fff0fff, "vmsr%c fpsid, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee10a10, 0x0fff0fff, "vmsr%c fpscr, %12-15r"}, + 0x0ee10a10, 0x0fff0fff, "vmsr%c fpscr, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee60a10, 0x0fff0fff, "vmsr%c mvfr1, %12-15r"}, + 0x0ee60a10, 0x0fff0fff, "vmsr%c mvfr1, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee70a10, 0x0fff0fff, "vmsr%c mvfr0, %12-15r"}, + 0x0ee70a10, 0x0fff0fff, "vmsr%c mvfr0, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee80a10, 0x0fff0fff, "vmsr%c fpexc, %12-15r"}, + 0x0ee80a10, 0x0fff0fff, "vmsr%c fpexc, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee90a10, 0x0fff0fff, "vmsr%c fpinst, %12-15r @ Impl def"}, + 0x0ee90a10, 0x0fff0fff, "vmsr%c fpinst, %12-15r @ Impl def" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eea0a10, 0x0fff0fff, "vmsr%c fpinst2, %12-15r @ Impl def"}, + 0x0eea0a10, 0x0fff0fff, "vmsr%c fpinst2, %12-15r @ Impl def" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef00a10, 0x0fff0fff, "vmrs%c %12-15r, fpsid"}, + 0x0ef00a10, 0x0fff0fff, "vmrs%c %12-15r, fpsid" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef1fa10, 0x0fffffff, "vmrs%c APSR_nzcv, fpscr"}, + 0x0ef1fa10, 0x0fffffff, "vmrs%c APSR_nzcv, fpscr" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef10a10, 0x0fff0fff, "vmrs%c %12-15r, fpscr"}, + 0x0ef10a10, 0x0fff0fff, "vmrs%c %12-15r, fpscr" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef60a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr1"}, + 0x0ef60a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr1" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef70a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr0"}, + 0x0ef70a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef80a10, 0x0fff0fff, "vmrs%c %12-15r, fpexc"}, + 0x0ef80a10, 0x0fff0fff, "vmrs%c %12-15r, fpexc" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef90a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst @ Impl def"}, + 0x0ef90a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst @ Impl def" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0efa0a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst2 @ Impl def"}, + 0x0efa0a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst2 @ Impl def" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e000b10, 0x0fd00fff, "vmov%c.32 %z2[%21d], %12-15r"}, + 0x0e000b10, 0x0fd00fff, "vmov%c.32 %z2[%21d], %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e100b10, 0x0fd00fff, "vmov%c.32 %12-15r, %z2[%21d]"}, + 0x0e100b10, 0x0fd00fff, "vmov%c.32 %12-15r, %z2[%21d]" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee00a10, 0x0ff00fff, "vmsr%c , %12-15r"}, + 0x0ee00a10, 0x0ff00fff, "vmsr%c , %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef00a10, 0x0ff00fff, "vmrs%c %12-15r, "}, + 0x0ef00a10, 0x0ff00fff, "vmrs%c %12-15r, " }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e000a10, 0x0ff00f7f, "vmov%c %y2, %12-15r"}, + 0x0e000a10, 0x0ff00f7f, "vmov%c %y2, %12-15r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e100a10, 0x0ff00f7f, "vmov%c %12-15r, %y2"}, + 0x0e100a10, 0x0ff00f7f, "vmov%c %12-15r, %y2" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32 %y1, #0.0"}, + 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32 %y1, #0.0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64 %z1, #0.0"}, + 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64 %z1, #0.0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32 %y1, %y0"}, + 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32 %y1, %y0"}, + 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64 %z1, %z0"}, + 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64 %z1, %z0"}, + 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32 %y1, %y0"}, + 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32 %y1, %y0"}, + 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64 %z1, %z0"}, + 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64 %z1, %z0"}, + 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32 %z1, %y0"}, + 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32 %z1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64 %y1, %z0"}, + 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64 %y1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32 %y1, %y0"}, + 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32 %z1, %y0"}, + 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32 %z1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32 %y1, %y0"}, + 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64 %z1, %z0"}, + 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), - 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"}, + 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26 %y1, %y1, %5,0-3k" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), - 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26 %z1, %z1, %5,0-3k"}, + 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26 %z1, %z1, %5,0-3k" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32 %y1, %y0"}, + 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64 %y1, %z0"}, + 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64 %y1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), - 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32 %y1, %y1, %5,0-3k"}, + 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32 %y1, %y1, %5,0-3k" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), - 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64 %z1, %z1, %5,0-3k"}, + 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64 %z1, %z1, %5,0-3k" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0c500b10, 0x0fb00ff0, "vmov%c %12-15r, %16-19r, %z0"}, + 0x0c500b10, 0x0fb00ff0, "vmov%c %12-15r, %16-19r, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), - 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32 %y1, %0-3,16-19E"}, + 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32 %y1, %0-3,16-19E" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), - 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64 %z1, %0-3,16-19E"}, + 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64 %z1, %0-3,16-19E" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), - 0x0c400a10, 0x0ff00fd0, "vmov%c %y4, %12-15r, %16-19r"}, + 0x0c400a10, 0x0ff00fd0, "vmov%c %y4, %12-15r, %16-19r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), - 0x0c400b10, 0x0ff00fd0, "vmov%c %z0, %12-15r, %16-19r"}, + 0x0c400b10, 0x0ff00fd0, "vmov%c %z0, %12-15r, %16-19r" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), - 0x0c500a10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %y4"}, + 0x0c500a10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %y4" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e000a00, 0x0fb00f50, "vmla%c.f32 %y1, %y2, %y0"}, + 0x0e000a00, 0x0fb00f50, "vmla%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e000a40, 0x0fb00f50, "vmls%c.f32 %y1, %y2, %y0"}, + 0x0e000a40, 0x0fb00f50, "vmls%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e000b00, 0x0fb00f50, "vmla%c.f64 %z1, %z2, %z0"}, + 0x0e000b00, 0x0fb00f50, "vmla%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e000b40, 0x0fb00f50, "vmls%c.f64 %z1, %z2, %z0"}, + 0x0e000b40, 0x0fb00f50, "vmls%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e100a00, 0x0fb00f50, "vnmls%c.f32 %y1, %y2, %y0"}, + 0x0e100a00, 0x0fb00f50, "vnmls%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e100a40, 0x0fb00f50, "vnmla%c.f32 %y1, %y2, %y0"}, + 0x0e100a40, 0x0fb00f50, "vnmla%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e100b00, 0x0fb00f50, "vnmls%c.f64 %z1, %z2, %z0"}, + 0x0e100b00, 0x0fb00f50, "vnmls%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e100b40, 0x0fb00f50, "vnmla%c.f64 %z1, %z2, %z0"}, + 0x0e100b40, 0x0fb00f50, "vnmla%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e200a00, 0x0fb00f50, "vmul%c.f32 %y1, %y2, %y0"}, + 0x0e200a00, 0x0fb00f50, "vmul%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e200a40, 0x0fb00f50, "vnmul%c.f32 %y1, %y2, %y0"}, + 0x0e200a40, 0x0fb00f50, "vnmul%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e200b00, 0x0fb00f50, "vmul%c.f64 %z1, %z2, %z0"}, + 0x0e200b00, 0x0fb00f50, "vmul%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e200b40, 0x0fb00f50, "vnmul%c.f64 %z1, %z2, %z0"}, + 0x0e200b40, 0x0fb00f50, "vnmul%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e300a00, 0x0fb00f50, "vadd%c.f32 %y1, %y2, %y0"}, + 0x0e300a00, 0x0fb00f50, "vadd%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e300a40, 0x0fb00f50, "vsub%c.f32 %y1, %y2, %y0"}, + 0x0e300a40, 0x0fb00f50, "vsub%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e300b00, 0x0fb00f50, "vadd%c.f64 %z1, %z2, %z0"}, + 0x0e300b00, 0x0fb00f50, "vadd%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e300b40, 0x0fb00f50, "vsub%c.f64 %z1, %z2, %z0"}, + 0x0e300b40, 0x0fb00f50, "vsub%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0e800a00, 0x0fb00f50, "vdiv%c.f32 %y1, %y2, %y0"}, + 0x0e800a00, 0x0fb00f50, "vdiv%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), - 0x0e800b00, 0x0fb00f50, "vdiv%c.f64 %z1, %z2, %z0"}, + 0x0e800b00, 0x0fb00f50, "vdiv%c.f64 %z1, %z2, %z0" }, /* Cirrus coprocessor instructions. */ {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"}, + 0x0d100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"}, + 0x0c100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"}, + 0x0d500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"}, + 0x0c500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"}, + 0x0d100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"}, + 0x0c100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"}, + 0x0d500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"}, + 0x0c500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"}, + 0x0d000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"}, + 0x0c000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"}, + 0x0d400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"}, + 0x0c400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"}, + 0x0d000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"}, + 0x0c000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0d400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"}, + 0x0d400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0c400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"}, + 0x0c400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000450, 0x0ff00ff0, "cfmvsr%c mvf%16-19d, %12-15r"}, + 0x0e000450, 0x0ff00ff0, "cfmvsr%c mvf%16-19d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100450, 0x0ff00ff0, "cfmvrs%c %12-15r, mvf%16-19d"}, + 0x0e100450, 0x0ff00ff0, "cfmvrs%c %12-15r, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000410, 0x0ff00ff0, "cfmvdlr%c mvd%16-19d, %12-15r"}, + 0x0e000410, 0x0ff00ff0, "cfmvdlr%c mvd%16-19d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100410, 0x0ff00ff0, "cfmvrdl%c %12-15r, mvd%16-19d"}, + 0x0e100410, 0x0ff00ff0, "cfmvrdl%c %12-15r, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000430, 0x0ff00ff0, "cfmvdhr%c mvd%16-19d, %12-15r"}, + 0x0e000430, 0x0ff00ff0, "cfmvdhr%c mvd%16-19d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100430, 0x0ff00fff, "cfmvrdh%c %12-15r, mvd%16-19d"}, + 0x0e100430, 0x0ff00fff, "cfmvrdh%c %12-15r, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000510, 0x0ff00fff, "cfmv64lr%c mvdx%16-19d, %12-15r"}, + 0x0e000510, 0x0ff00fff, "cfmv64lr%c mvdx%16-19d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100510, 0x0ff00fff, "cfmvr64l%c %12-15r, mvdx%16-19d"}, + 0x0e100510, 0x0ff00fff, "cfmvr64l%c %12-15r, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000530, 0x0ff00fff, "cfmv64hr%c mvdx%16-19d, %12-15r"}, + 0x0e000530, 0x0ff00fff, "cfmv64hr%c mvdx%16-19d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100530, 0x0ff00fff, "cfmvr64h%c %12-15r, mvdx%16-19d"}, + 0x0e100530, 0x0ff00fff, "cfmvr64h%c %12-15r, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e200440, 0x0ff00fff, "cfmval32%c mvax%12-15d, mvfx%16-19d"}, + 0x0e200440, 0x0ff00fff, "cfmval32%c mvax%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100440, 0x0ff00fff, "cfmv32al%c mvfx%12-15d, mvax%16-19d"}, + 0x0e100440, 0x0ff00fff, "cfmv32al%c mvfx%12-15d, mvax%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e200460, 0x0ff00fff, "cfmvam32%c mvax%12-15d, mvfx%16-19d"}, + 0x0e200460, 0x0ff00fff, "cfmvam32%c mvax%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100460, 0x0ff00fff, "cfmv32am%c mvfx%12-15d, mvax%16-19d"}, + 0x0e100460, 0x0ff00fff, "cfmv32am%c mvfx%12-15d, mvax%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e200480, 0x0ff00fff, "cfmvah32%c mvax%12-15d, mvfx%16-19d"}, + 0x0e200480, 0x0ff00fff, "cfmvah32%c mvax%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100480, 0x0ff00fff, "cfmv32ah%c mvfx%12-15d, mvax%16-19d"}, + 0x0e100480, 0x0ff00fff, "cfmv32ah%c mvfx%12-15d, mvax%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e2004a0, 0x0ff00fff, "cfmva32%c mvax%12-15d, mvfx%16-19d"}, + 0x0e2004a0, 0x0ff00fff, "cfmva32%c mvax%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1004a0, 0x0ff00fff, "cfmv32a%c mvfx%12-15d, mvax%16-19d"}, + 0x0e1004a0, 0x0ff00fff, "cfmv32a%c mvfx%12-15d, mvax%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e2004c0, 0x0ff00fff, "cfmva64%c mvax%12-15d, mvdx%16-19d"}, + 0x0e2004c0, 0x0ff00fff, "cfmva64%c mvax%12-15d, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1004c0, 0x0ff00fff, "cfmv64a%c mvdx%12-15d, mvax%16-19d"}, + 0x0e1004c0, 0x0ff00fff, "cfmv64a%c mvdx%12-15d, mvax%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c dspsc, mvdx%12-15d"}, + 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c dspsc, mvdx%12-15d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c mvdx%12-15d, dspsc"}, + 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c mvdx%12-15d, dspsc" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000400, 0x0ff00fff, "cfcpys%c mvf%12-15d, mvf%16-19d"}, + 0x0e000400, 0x0ff00fff, "cfcpys%c mvf%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000420, 0x0ff00fff, "cfcpyd%c mvd%12-15d, mvd%16-19d"}, + 0x0e000420, 0x0ff00fff, "cfcpyd%c mvd%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000460, 0x0ff00fff, "cfcvtsd%c mvd%12-15d, mvf%16-19d"}, + 0x0e000460, 0x0ff00fff, "cfcvtsd%c mvd%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000440, 0x0ff00fff, "cfcvtds%c mvf%12-15d, mvd%16-19d"}, + 0x0e000440, 0x0ff00fff, "cfcvtds%c mvf%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000480, 0x0ff00fff, "cfcvt32s%c mvf%12-15d, mvfx%16-19d"}, + 0x0e000480, 0x0ff00fff, "cfcvt32s%c mvf%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c mvd%12-15d, mvfx%16-19d"}, + 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c mvd%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c mvf%12-15d, mvdx%16-19d"}, + 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c mvf%12-15d, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c mvd%12-15d, mvdx%16-19d"}, + 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c mvd%12-15d, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100580, 0x0ff00fff, "cfcvts32%c mvfx%12-15d, mvf%16-19d"}, + 0x0e100580, 0x0ff00fff, "cfcvts32%c mvfx%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c mvfx%12-15d, mvd%16-19d"}, + 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c mvfx%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1005c0, 0x0ff00fff, "cftruncs32%c mvfx%12-15d, mvf%16-19d"}, + 0x0e1005c0, 0x0ff00fff, "cftruncs32%c mvfx%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1005e0, 0x0ff00fff, "cftruncd32%c mvfx%12-15d, mvd%16-19d"}, + 0x0e1005e0, 0x0ff00fff, "cftruncd32%c mvfx%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000550, 0x0ff00ff0, "cfrshl32%c mvfx%16-19d, mvfx%0-3d, %12-15r"}, + 0x0e000550, 0x0ff00ff0, "cfrshl32%c mvfx%16-19d, mvfx%0-3d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000570, 0x0ff00ff0, "cfrshl64%c mvdx%16-19d, mvdx%0-3d, %12-15r"}, + 0x0e000570, 0x0ff00ff0, "cfrshl64%c mvdx%16-19d, mvdx%0-3d, %12-15r" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e000500, 0x0ff00f10, "cfsh32%c mvfx%12-15d, mvfx%16-19d, %I"}, + 0x0e000500, 0x0ff00f10, "cfsh32%c mvfx%12-15d, mvfx%16-19d, %I" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e200500, 0x0ff00f10, "cfsh64%c mvdx%12-15d, mvdx%16-19d, %I"}, + 0x0e200500, 0x0ff00f10, "cfsh64%c mvdx%12-15d, mvdx%16-19d, %I" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100490, 0x0ff00ff0, "cfcmps%c %12-15r, mvf%16-19d, mvf%0-3d"}, + 0x0e100490, 0x0ff00ff0, "cfcmps%c %12-15r, mvf%16-19d, mvf%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c %12-15r, mvd%16-19d, mvd%0-3d"}, + 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c %12-15r, mvd%16-19d, mvd%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100590, 0x0ff00ff0, "cfcmp32%c %12-15r, mvfx%16-19d, mvfx%0-3d"}, + 0x0e100590, 0x0ff00ff0, "cfcmp32%c %12-15r, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c %12-15r, mvdx%16-19d, mvdx%0-3d"}, + 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c %12-15r, mvdx%16-19d, mvdx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300400, 0x0ff00fff, "cfabss%c mvf%12-15d, mvf%16-19d"}, + 0x0e300400, 0x0ff00fff, "cfabss%c mvf%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300420, 0x0ff00fff, "cfabsd%c mvd%12-15d, mvd%16-19d"}, + 0x0e300420, 0x0ff00fff, "cfabsd%c mvd%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300440, 0x0ff00fff, "cfnegs%c mvf%12-15d, mvf%16-19d"}, + 0x0e300440, 0x0ff00fff, "cfnegs%c mvf%12-15d, mvf%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300460, 0x0ff00fff, "cfnegd%c mvd%12-15d, mvd%16-19d"}, + 0x0e300460, 0x0ff00fff, "cfnegd%c mvd%12-15d, mvd%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300480, 0x0ff00ff0, "cfadds%c mvf%12-15d, mvf%16-19d, mvf%0-3d"}, + 0x0e300480, 0x0ff00ff0, "cfadds%c mvf%12-15d, mvf%16-19d, mvf%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3004a0, 0x0ff00ff0, "cfaddd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"}, + 0x0e3004a0, 0x0ff00ff0, "cfaddd%c mvd%12-15d, mvd%16-19d, mvd%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3004c0, 0x0ff00ff0, "cfsubs%c mvf%12-15d, mvf%16-19d, mvf%0-3d"}, + 0x0e3004c0, 0x0ff00ff0, "cfsubs%c mvf%12-15d, mvf%16-19d, mvf%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3004e0, 0x0ff00ff0, "cfsubd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"}, + 0x0e3004e0, 0x0ff00ff0, "cfsubd%c mvd%12-15d, mvd%16-19d, mvd%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100400, 0x0ff00ff0, "cfmuls%c mvf%12-15d, mvf%16-19d, mvf%0-3d"}, + 0x0e100400, 0x0ff00ff0, "cfmuls%c mvf%12-15d, mvf%16-19d, mvf%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100420, 0x0ff00ff0, "cfmuld%c mvd%12-15d, mvd%16-19d, mvd%0-3d"}, + 0x0e100420, 0x0ff00ff0, "cfmuld%c mvd%12-15d, mvd%16-19d, mvd%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300500, 0x0ff00fff, "cfabs32%c mvfx%12-15d, mvfx%16-19d"}, + 0x0e300500, 0x0ff00fff, "cfabs32%c mvfx%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300520, 0x0ff00fff, "cfabs64%c mvdx%12-15d, mvdx%16-19d"}, + 0x0e300520, 0x0ff00fff, "cfabs64%c mvdx%12-15d, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300540, 0x0ff00fff, "cfneg32%c mvfx%12-15d, mvfx%16-19d"}, + 0x0e300540, 0x0ff00fff, "cfneg32%c mvfx%12-15d, mvfx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300560, 0x0ff00fff, "cfneg64%c mvdx%12-15d, mvdx%16-19d"}, + 0x0e300560, 0x0ff00fff, "cfneg64%c mvdx%12-15d, mvdx%16-19d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e300580, 0x0ff00ff0, "cfadd32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + 0x0e300580, 0x0ff00ff0, "cfadd32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3005a0, 0x0ff00ff0, "cfadd64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + 0x0e3005a0, 0x0ff00ff0, "cfadd64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3005c0, 0x0ff00ff0, "cfsub32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + 0x0e3005c0, 0x0ff00ff0, "cfsub32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e3005e0, 0x0ff00ff0, "cfsub64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + 0x0e3005e0, 0x0ff00ff0, "cfsub64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100500, 0x0ff00ff0, "cfmul32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + 0x0e100500, 0x0ff00ff0, "cfmul32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100520, 0x0ff00ff0, "cfmul64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + 0x0e100520, 0x0ff00ff0, "cfmul64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100540, 0x0ff00ff0, "cfmac32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + 0x0e100540, 0x0ff00ff0, "cfmac32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), - 0x0e100560, 0x0ff00ff0, "cfmsc32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + 0x0e100560, 0x0ff00ff0, "cfmsc32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 0x0e000600, 0x0ff00f10, - "cfmadd32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + "cfmadd32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 0x0e100600, 0x0ff00f10, - "cfmsub32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + "cfmsub32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 0x0e200600, 0x0ff00f10, - "cfmadda32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + "cfmadda32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d" }, {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 0x0e300600, 0x0ff00f10, - "cfmsuba32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + "cfmsuba32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d" }, /* VFP Fused multiply add instructions. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0ea00a00, 0x0fb00f50, "vfma%c.f32 %y1, %y2, %y0"}, + 0x0ea00a00, 0x0fb00f50, "vfma%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0ea00b00, 0x0fb00f50, "vfma%c.f64 %z1, %z2, %z0"}, + 0x0ea00b00, 0x0fb00f50, "vfma%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0ea00a40, 0x0fb00f50, "vfms%c.f32 %y1, %y2, %y0"}, + 0x0ea00a40, 0x0fb00f50, "vfms%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0ea00b40, 0x0fb00f50, "vfms%c.f64 %z1, %z2, %z0"}, + 0x0ea00b40, 0x0fb00f50, "vfms%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0e900a40, 0x0fb00f50, "vfnma%c.f32 %y1, %y2, %y0"}, + 0x0e900a40, 0x0fb00f50, "vfnma%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0e900b40, 0x0fb00f50, "vfnma%c.f64 %z1, %z2, %z0"}, + 0x0e900b40, 0x0fb00f50, "vfnma%c.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0e900a00, 0x0fb00f50, "vfnms%c.f32 %y1, %y2, %y0"}, + 0x0e900a00, 0x0fb00f50, "vfnms%c.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), - 0x0e900b00, 0x0fb00f50, "vfnms%c.f64 %z1, %z2, %z0"}, + 0x0e900b00, 0x0fb00f50, "vfnms%c.f64 %z1, %z2, %z0" }, /* FP v5. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32 %y1, %y2, %y0"}, + 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64 %z1, %z2, %z0"}, + 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32 %y1, %y2, %y0"}, + 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64 %z1, %z2, %z0"}, + 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800a40, 0xffb00f50, "vminnm%u.f32 %y1, %y2, %y0"}, + 0xfe800a40, 0xffb00f50, "vminnm%u.f32 %y1, %y2, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800b40, 0xffb00f50, "vminnm%u.f64 %z1, %z2, %z0"}, + 0xfe800b40, 0xffb00f50, "vminnm%u.f64 %z1, %z2, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32 %y1, %y0"}, + 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64 %y1, %z0"}, + 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64 %y1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32 %y1, %y0"}, + 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64 %z1, %z0"}, + 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64 %z1, %z0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32 %y1, %y0"}, + 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32 %y1, %y0" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64 %z1, %z0"}, + 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64 %z1, %z0" }, /* Generic coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), - 0x0c400000, 0x0ff00000, "mcrr%c %8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, + 0x0c400000, 0x0ff00000, "mcrr%c %8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 0x0c500000, 0x0ff00000, - "mrrc%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + "mrrc%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 0x0e000000, 0x0f000010, - "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 0x0e10f010, 0x0f10f010, - "mrc%c %8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, + "mrc%c %8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 0x0e100010, 0x0f100010, - "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 0x0e000010, 0x0f100010, - "mcr%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + "mcr%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), - 0x0c000000, 0x0e100000, "stc%22'l%c %8-11d, cr%12-15d, %A"}, + 0x0c000000, 0x0e100000, "stc%22'l%c %8-11d, cr%12-15d, %A" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), - 0x0c100000, 0x0e100000, "ldc%22'l%c %8-11d, cr%12-15d, %A"}, + 0x0c100000, 0x0e100000, "ldc%22'l%c %8-11d, cr%12-15d, %A" }, /* V6 coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xfc500000, 0xfff00000, - "mrrc2%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + "mrrc2%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xfc400000, 0xfff00000, - "mcrr2%c %8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, + "mcrr2%c %8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d" }, /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfc800800, 0xfeb00f10, "vcadd%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"}, + 0xfc800800, 0xfeb00f10, "vcadd%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfc900800, 0xfeb00f10, "vcadd%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"}, + 0xfc900800, 0xfeb00f10, "vcadd%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfc200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"}, + 0xfc200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23'90" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfd200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"}, + 0xfd200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfc300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"}, + 0xfc300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23'90" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfd300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"}, + 0xfd300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe000800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20'90"}, + 0xfe000800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20'90" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe200800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20?21%20?780"}, + 0xfe200800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20?21%20?780" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe800800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20'90"}, + 0xfe800800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20'90" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfea00800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20?21%20?780"}, + 0xfea00800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20?21%20?780" }, /* V5 coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0xfc100000, 0xfe100000, "ldc2%22'l%c %8-11d, cr%12-15d, %A"}, + 0xfc100000, 0xfe100000, "ldc2%22'l%c %8-11d, cr%12-15d, %A" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0xfc000000, 0xfe100000, "stc2%22'l%c %8-11d, cr%12-15d, %A"}, + 0xfc000000, 0xfe100000, "stc2%22'l%c %8-11d, cr%12-15d, %A" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xfe000000, 0xff000010, - "cdp2%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + "cdp2%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xfe000010, 0xff100010, - "mcr2%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + "mcr2%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xfe100010, 0xff100010, - "mrc2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + "mrc2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}" }, /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. cp_num: bit <11:8> == 0b1001. cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16 %y1, %y0"}, + 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e300900, 0x0fb00f50, "vadd%c.f16 %y1, %y2, %y0"}, + 0x0e300900, 0x0fb00f50, "vadd%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16 %y1, %y0"}, + 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16 %y1, #0.0"}, + 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16 %y1, #0.0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"}, + 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26 %y1, %y1, %5,0-3k" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16 %y1, %y1, %5,0-3k"}, + 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16 %y1, %y1, %5,0-3k" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16 %y1, %y0"}, + 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32 %y1, %y0"}, + 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16 %y1, %y0"}, + 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e800900, 0x0fb00f50, "vdiv%c.f16 %y1, %y2, %y0"}, + 0x0e800900, 0x0fb00f50, "vdiv%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0ea00900, 0x0fb00f50, "vfma%c.f16 %y1, %y2, %y0"}, + 0x0ea00900, 0x0fb00f50, "vfma%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0ea00940, 0x0fb00f50, "vfms%c.f16 %y1, %y2, %y0"}, + 0x0ea00940, 0x0fb00f50, "vfms%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e900940, 0x0fb00f50, "vfnma%c.f16 %y1, %y2, %y0"}, + 0x0e900940, 0x0fb00f50, "vfnma%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e900900, 0x0fb00f50, "vfnms%c.f16 %y1, %y2, %y0"}, + 0x0e900900, 0x0fb00f50, "vfnms%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfeb00ac0, 0xffbf0fd0, "vins.f16 %y1, %y0"}, + 0xfeb00ac0, 0xffbf0fd0, "vins.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16 %y1, %y0"}, + 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0d100900, 0x0f300f00, "vldr%c.16 %y1, %A"}, + 0x0d100900, 0x0f300f00, "vldr%c.16 %y1, %A" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0d000900, 0x0f300f00, "vstr%c.16 %y1, %A"}, + 0x0d000900, 0x0f300f00, "vstr%c.16 %y1, %A" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfe800900, 0xffb00f50, "vmaxnm%c.f16 %y1, %y2, %y0"}, + 0xfe800900, 0xffb00f50, "vmaxnm%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfe800940, 0xffb00f50, "vminnm%c.f16 %y1, %y2, %y0"}, + 0xfe800940, 0xffb00f50, "vminnm%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e000900, 0x0fb00f50, "vmla%c.f16 %y1, %y2, %y0"}, + 0x0e000900, 0x0fb00f50, "vmla%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e000940, 0x0fb00f50, "vmls%c.f16 %y1, %y2, %y0"}, + 0x0e000940, 0x0fb00f50, "vmls%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e100910, 0x0ff00f7f, "vmov%c.f16 %12-15r, %y2"}, + 0x0e100910, 0x0ff00f7f, "vmov%c.f16 %12-15r, %y2" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e000910, 0x0ff00f7f, "vmov%c.f16 %y2, %12-15r"}, + 0x0e000910, 0x0ff00f7f, "vmov%c.f16 %y2, %12-15r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xeb00900, 0x0fb00ff0, "vmov%c.f16 %y1, %0-3,16-19E"}, + 0xeb00900, 0x0fb00ff0, "vmov%c.f16 %y1, %0-3,16-19E" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e200900, 0x0fb00f50, "vmul%c.f16 %y1, %y2, %y0"}, + 0x0e200900, 0x0fb00f50, "vmul%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16 %y1, %y0"}, + 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e100940, 0x0fb00f50, "vnmla%c.f16 %y1, %y2, %y0"}, + 0x0e100940, 0x0fb00f50, "vnmla%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e100900, 0x0fb00f50, "vnmls%c.f16 %y1, %y2, %y0"}, + 0x0e100900, 0x0fb00f50, "vnmls%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e200940, 0x0fb00f50, "vnmul%c.f16 %y1, %y2, %y0"}, + 0x0e200940, 0x0fb00f50, "vnmul%c.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16 %y1, %y0"}, + 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16 %y1, %y0"}, + 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16 %y1, %y2, %y0"}, + 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16 %y1, %y2, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16 %y1, %y0"}, + 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16 %y1, %y0" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0x0e300940, 0x0fb00f50, "vsub%c.f16 %y1, %y2, %y0"}, + 0x0e300940, 0x0fb00f50, "vsub%c.f16 %y1, %y2, %y0" }, /* ARMv8.3 javascript conversion instruction. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64 %y1, %z0"}, + 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64 %y1, %z0" }, {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; @@ -1045,609 +1045,609 @@ static const struct opcode32 neon_opcodes[] = /* Extract. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2b00840, 0xffb00850, - "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d"}, + "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2b00000, 0xffb00810, - "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d"}, + "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d" }, /* Move data element to all lanes. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b40c00, 0xffb70f90, "vdup%c.32 %12-15,22R, %0-3,5D[%19d]"}, + 0xf3b40c00, 0xffb70f90, "vdup%c.32 %12-15,22R, %0-3,5D[%19d]" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20c00, 0xffb30f90, "vdup%c.16 %12-15,22R, %0-3,5D[%18-19d]"}, + 0xf3b20c00, 0xffb30f90, "vdup%c.16 %12-15,22R, %0-3,5D[%18-19d]" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10c00, 0xffb10f90, "vdup%c.8 %12-15,22R, %0-3,5D[%17-19d]"}, + 0xf3b10c00, 0xffb10f90, "vdup%c.8 %12-15,22R, %0-3,5D[%17-19d]" }, /* Table lookup. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00800, 0xffb00c50, "vtbl%c.8 %12-15,22D, %F, %0-3,5D"}, + 0xf3b00800, 0xffb00c50, "vtbl%c.8 %12-15,22D, %F, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00840, 0xffb00c50, "vtbx%c.8 %12-15,22D, %F, %0-3,5D"}, + 0xf3b00840, 0xffb00c50, "vtbx%c.8 %12-15,22D, %F, %0-3,5D" }, /* Half-precision conversions. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), - 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32 %12-15,22D, %0-3,5Q"}, + 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32 %12-15,22D, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), - 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16 %12-15,22Q, %0-3,5D"}, + 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16 %12-15,22Q, %0-3,5D" }, /* NEON fused multiply add instructions. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), - 0xf2000c10, 0xffb00f10, "vfma%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000c10, 0xffb00f10, "vfma%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100c10, 0xffb00f10, "vfma%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100c10, 0xffb00f10, "vfma%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), - 0xf2200c10, 0xffb00f10, "vfms%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200c10, 0xffb00f10, "vfms%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2300c10, 0xffb00f10, "vfms%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300c10, 0xffb00f10, "vfms%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, /* Two registers, miscellaneous. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), - 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32 %12-15,22R, %0-3,5R"}, + 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16 %12-15,22R, %0-3,5R"}, + 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), - 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32 %12-15,22R, %0-3,5R"}, + 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16 %12-15,22R, %0-3,5R"}, + 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3b00300, 0xffbf0fd0, "aese%u.8 %12-15,22Q, %0-3,5Q"}, + 0xf3b00300, 0xffbf0fd0, "aese%u.8 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3b00340, 0xffbf0fd0, "aesd%u.8 %12-15,22Q, %0-3,5Q"}, + 0xf3b00340, 0xffbf0fd0, "aesd%u.8 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3b00380, 0xffbf0fd0, "aesmc%u.8 %12-15,22Q, %0-3,5Q"}, + 0xf3b00380, 0xffbf0fd0, "aesmc%u.8 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8 %12-15,22Q, %0-3,5Q"}, + 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32 %12-15,22Q, %0-3,5Q"}, + 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32 %12-15,22Q, %0-3,5Q"}, + 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32 %12-15,22Q, %0-3,5Q"}, + 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32 %12-15,22Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8 %12-15,22Q, %0-3,5D"}, + 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8 %12-15,22Q, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16 %12-15,22Q, %0-3,5D"}, + 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16 %12-15,22Q, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32 %12-15,22Q, %0-3,5D"}, + 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32 %12-15,22Q, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00500, 0xffbf0f90, "vcnt%c.8 %12-15,22R, %0-3,5R"}, + 0xf3b00500, 0xffbf0f90, "vcnt%c.8 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00580, 0xffbf0f90, "vmvn%c %12-15,22R, %0-3,5R"}, + 0xf3b00580, 0xffbf0f90, "vmvn%c %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20000, 0xffbf0f90, "vswp%c %12-15,22R, %0-3,5R"}, + 0xf3b20000, 0xffbf0f90, "vswp%c %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2 %12-15,22D, %0-3,5Q"}, + 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2 %12-15,22D, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2 %12-15,22D, %0-3,5Q"}, + 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2 %12-15,22D, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2 %12-15,22D, %0-3,5Q"}, + 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2 %12-15,22D, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2 %12-15,22D, %0-3,5Q"}, + 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2 %12-15,22D, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf3b20300, 0xffb30fd0, - "vshll%c.i%18-19S2 %12-15,22Q, %0-3,5D, %18-19S2"}, + "vshll%c.i%18-19S2 %12-15,22Q, %0-3,5D, %18-19S2" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16 %12-15,22R, %0-3,5R"}, + 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16 %12-15,22R, %0-3,5R"}, + 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"}, + 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"}, + 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2 %12-15,22R, %0-3,5R, #0"}, + 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2 %12-15,22R, %0-3,5R, #0" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"}, + 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"}, + 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2 %12-15,22R, %0-3,5R"}, + 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2 %12-15,22R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf3bb0600, 0xffbf0e10, - "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa %12-15,22R, %0-3,5R"}, + "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa %12-15,22R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 0xf3b70600, 0xffbf0e10, - "vcvt%c.%7-8?usff16.%7-8?ffus16 %12-15,22R, %0-3,5R"}, + "vcvt%c.%7-8?usff16.%7-8?ffus16 %12-15,22R, %0-3,5R" }, /* Three registers of the same length. */ {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf2000c40, 0xffb00f50, "sha1c%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf2000c40, 0xffb00f50, "sha1c%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf2100c40, 0xffb00f50, "sha1p%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf2100c40, 0xffb00f50, "sha1p%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf2200c40, 0xffb00f50, "sha1m%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf2200c40, 0xffb00f50, "sha1m%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf2300c40, 0xffb00f50, "sha1su0%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf2300c40, 0xffb00f50, "sha1su0%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3000c40, 0xffb00f50, "sha256h%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf3000c40, 0xffb00f50, "sha256h%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3100c40, 0xffb00f50, "sha256h2%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf3100c40, 0xffb00f50, "sha256h2%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf3200c40, 0xffb00f50, "sha256su1%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"}, + 0xf3200c40, 0xffb00f50, "sha256su1%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), - 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), - 0xf3200f10, 0xffb00f10, "vminnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200f10, 0xffb00f10, "vminnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3300f10, 0xffb00f10, "vminnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300f10, 0xffb00f10, "vminnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000110, 0xffb00f10, "vand%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000110, 0xffb00f10, "vand%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2100110, 0xffb00f10, "vbic%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100110, 0xffb00f10, "vbic%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2200110, 0xffb00f10, "vorr%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200110, 0xffb00f10, "vorr%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2300110, 0xffb00f10, "vorn%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300110, 0xffb00f10, "vorn%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000110, 0xffb00f10, "veor%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000110, 0xffb00f10, "veor%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3100110, 0xffb00f10, "vbsl%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100110, 0xffb00f10, "vbsl%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3200110, 0xffb00f10, "vbit%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200110, 0xffb00f10, "vbit%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3300110, 0xffb00f10, "vbif%c %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300110, 0xffb00f10, "vbif%c %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000d00, 0xffb00f10, "vadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000d00, 0xffb00f10, "vadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100d00, 0xffb00f10, "vadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100d00, 0xffb00f10, "vadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000d10, 0xffb00f10, "vmla%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000d10, 0xffb00f10, "vmla%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100d10, 0xffb00f10, "vmla%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100d10, 0xffb00f10, "vmla%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000e00, 0xffb00f10, "vceq%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000e00, 0xffb00f10, "vceq%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100e00, 0xffb00f10, "vceq%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100e00, 0xffb00f10, "vceq%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000f00, 0xffb00f10, "vmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000f00, 0xffb00f10, "vmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100f00, 0xffb00f10, "vmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100f00, 0xffb00f10, "vmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000f10, 0xffb00f10, "vrecps%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000f10, 0xffb00f10, "vrecps%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2100f10, 0xffb00f10, "vrecps%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2100f10, 0xffb00f10, "vrecps%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2200d00, 0xffb00f10, "vsub%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200d00, 0xffb00f10, "vsub%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2300d00, 0xffb00f10, "vsub%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300d00, 0xffb00f10, "vsub%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2200d10, 0xffb00f10, "vmls%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200d10, 0xffb00f10, "vmls%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2300d10, 0xffb00f10, "vmls%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300d10, 0xffb00f10, "vmls%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2200f00, 0xffb00f10, "vmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200f00, 0xffb00f10, "vmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2300f00, 0xffb00f10, "vmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300f00, 0xffb00f10, "vmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000d00, 0xffb00f10, "vpadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000d00, 0xffb00f10, "vpadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100d00, 0xffb00f10, "vpadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100d00, 0xffb00f10, "vpadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000d10, 0xffb00f10, "vmul%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000d10, 0xffb00f10, "vmul%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100d10, 0xffb00f10, "vmul%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100d10, 0xffb00f10, "vmul%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000e00, 0xffb00f10, "vcge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000e00, 0xffb00f10, "vcge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100e00, 0xffb00f10, "vcge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100e00, 0xffb00f10, "vcge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000e10, 0xffb00f10, "vacge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000e10, 0xffb00f10, "vacge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100e10, 0xffb00f10, "vacge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100e10, 0xffb00f10, "vacge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000f00, 0xffb00f10, "vpmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000f00, 0xffb00f10, "vpmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3100f00, 0xffb00f10, "vpmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3100f00, 0xffb00f10, "vpmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3200d00, 0xffb00f10, "vabd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200d00, 0xffb00f10, "vabd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3300d00, 0xffb00f10, "vabd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300d00, 0xffb00f10, "vabd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3200e00, 0xffb00f10, "vcgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200e00, 0xffb00f10, "vcgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3300e00, 0xffb00f10, "vcgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300e00, 0xffb00f10, "vcgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3200e10, 0xffb00f10, "vacgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200e10, 0xffb00f10, "vacgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3300e10, 0xffb00f10, "vacgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300e10, 0xffb00f10, "vacgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3200f00, 0xffb00f10, "vpmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3200f00, 0xffb00f10, "vpmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), - 0xf3300f00, 0xffb00f10, "vpmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3300f00, 0xffb00f10, "vpmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000810, 0xff800f10, "vtst%c.%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000810, 0xff800f10, "vtst%c.%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000b00, 0xff800f10, - "vqdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000b10, 0xff800f10, - "vpadd%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vpadd%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf3000b00, 0xff800f10, - "vqrdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqrdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000000, 0xfe800f10, - "vhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000010, 0xfe800f10, - "vqadd%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqadd%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000100, 0xfe800f10, - "vrhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vrhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000200, 0xfe800f10, - "vhsub%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vhsub%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000210, 0xfe800f10, - "vqsub%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqsub%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000300, 0xfe800f10, - "vcgt%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vcgt%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000310, 0xfe800f10, - "vcge%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vcge%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000400, 0xfe800f10, - "vshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"}, + "vshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000410, 0xfe800f10, - "vqshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"}, + "vqshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000500, 0xfe800f10, - "vrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"}, + "vrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000510, 0xfe800f10, - "vqrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"}, + "vqrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000600, 0xfe800f10, - "vmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000610, 0xfe800f10, - "vmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000700, 0xfe800f10, - "vabd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vabd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000710, 0xfe800f10, - "vaba%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vaba%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000910, 0xfe800f10, - "vmul%c.%24?pi%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vmul%c.%24?pi%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000a00, 0xfe800f10, - "vpmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vpmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2000a10, 0xfe800f10, - "vpmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vpmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf3000b10, 0xff800f10, - "vqrdmlah%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqrdmlah%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf3000c10, 0xff800f10, - "vqrdmlsh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"}, + "vqrdmlsh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R" }, /* One register and an immediate value. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800e10, 0xfeb80fb0, "vmov%c.i8 %12-15,22R, %E"}, + 0xf2800e10, 0xfeb80fb0, "vmov%c.i8 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800e30, 0xfeb80fb0, "vmov%c.i64 %12-15,22R, %E"}, + 0xf2800e30, 0xfeb80fb0, "vmov%c.i64 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800f10, 0xfeb80fb0, "vmov%c.f32 %12-15,22R, %E"}, + 0xf2800f10, 0xfeb80fb0, "vmov%c.f32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800810, 0xfeb80db0, "vmov%c.i16 %12-15,22R, %E"}, + 0xf2800810, 0xfeb80db0, "vmov%c.i16 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800830, 0xfeb80db0, "vmvn%c.i16 %12-15,22R, %E"}, + 0xf2800830, 0xfeb80db0, "vmvn%c.i16 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800910, 0xfeb80db0, "vorr%c.i16 %12-15,22R, %E"}, + 0xf2800910, 0xfeb80db0, "vorr%c.i16 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800930, 0xfeb80db0, "vbic%c.i16 %12-15,22R, %E"}, + 0xf2800930, 0xfeb80db0, "vbic%c.i16 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800c10, 0xfeb80eb0, "vmov%c.i32 %12-15,22R, %E"}, + 0xf2800c10, 0xfeb80eb0, "vmov%c.i32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32 %12-15,22R, %E"}, + 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800110, 0xfeb809b0, "vorr%c.i32 %12-15,22R, %E"}, + 0xf2800110, 0xfeb809b0, "vorr%c.i32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800130, 0xfeb809b0, "vbic%c.i32 %12-15,22R, %E"}, + 0xf2800130, 0xfeb809b0, "vbic%c.i32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800010, 0xfeb808b0, "vmov%c.i32 %12-15,22R, %E"}, + 0xf2800010, 0xfeb808b0, "vmov%c.i32 %12-15,22R, %E" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800030, 0xfeb808b0, "vmvn%c.i32 %12-15,22R, %E"}, + 0xf2800030, 0xfeb808b0, "vmvn%c.i32 %12-15,22R, %E" }, /* Two registers and a shift amount. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880810, 0xffb80fd0, "vshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e"}, + 0xf2880810, 0xffb80fd0, "vshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880850, 0xffb80fd0, "vrshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e"}, + 0xf2880850, 0xffb80fd0, "vrshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e"}, + 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e"}, + 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e"}, + 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2880950, 0xfeb80fd0, - "vqrshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e"}, + "vqrshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8 %12-15,22Q, %0-3,5D, %16-18d"}, + 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8 %12-15,22Q, %0-3,5D, %16-18d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900810, 0xffb00fd0, "vshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e"}, + 0xf2900810, 0xffb00fd0, "vshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900850, 0xffb00fd0, "vrshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e"}, + 0xf2900850, 0xffb00fd0, "vrshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880510, 0xffb80f90, "vshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d"}, + 0xf2880510, 0xffb80f90, "vshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3880410, 0xffb80f90, "vsri%c.8 %12-15,22R, %0-3,5R, %16-18e"}, + 0xf3880410, 0xffb80f90, "vsri%c.8 %12-15,22R, %0-3,5R, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3880510, 0xffb80f90, "vsli%c.8 %12-15,22R, %0-3,5R, %16-18d"}, + 0xf3880510, 0xffb80f90, "vsli%c.8 %12-15,22R, %0-3,5R, %16-18d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3880610, 0xffb80f90, "vqshlu%c.s8 %12-15,22R, %0-3,5R, %16-18d"}, + 0xf3880610, 0xffb80f90, "vqshlu%c.s8 %12-15,22R, %0-3,5R, %16-18d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e"}, + 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e"}, + 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e"}, + 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2900950, 0xfeb00fd0, - "vqrshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e"}, + "vqrshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16 %12-15,22Q, %0-3,5D, %16-19d"}, + 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16 %12-15,22Q, %0-3,5D, %16-19d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"}, + 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"}, + 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"}, + 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"}, + 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d"}, + 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00810, 0xffa00fd0, "vshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e"}, + 0xf2a00810, 0xffa00fd0, "vshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e"}, + 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900510, 0xffb00f90, "vshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d"}, + 0xf2900510, 0xffb00f90, "vshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3900410, 0xffb00f90, "vsri%c.16 %12-15,22R, %0-3,5R, %16-19e"}, + 0xf3900410, 0xffb00f90, "vsri%c.16 %12-15,22R, %0-3,5R, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3900510, 0xffb00f90, "vsli%c.16 %12-15,22R, %0-3,5R, %16-19d"}, + 0xf3900510, 0xffb00f90, "vsli%c.16 %12-15,22R, %0-3,5R, %16-19d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3900610, 0xffb00f90, "vqshlu%c.s16 %12-15,22R, %0-3,5R, %16-19d"}, + 0xf3900610, 0xffb00f90, "vqshlu%c.s16 %12-15,22R, %0-3,5R, %16-19d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32 %12-15,22Q, %0-3,5D, %16-20d"}, + 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32 %12-15,22Q, %0-3,5D, %16-20d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"}, + 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"}, + 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"}, + 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"}, + 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d"}, + 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e"}, + 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e"}, + 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e"}, + 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2a00950, 0xfea00fd0, - "vqrshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e"}, + "vqrshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d"}, + 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3a00410, 0xffa00f90, "vsri%c.32 %12-15,22R, %0-3,5R, %16-20e"}, + 0xf3a00410, 0xffa00f90, "vsri%c.32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3a00510, 0xffa00f90, "vsli%c.32 %12-15,22R, %0-3,5R, %16-20d"}, + 0xf3a00510, 0xffa00f90, "vsli%c.32 %12-15,22R, %0-3,5R, %16-20d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3a00610, 0xffa00f90, "vqshlu%c.s32 %12-15,22R, %0-3,5R, %16-20d"}, + 0xf3a00610, 0xffa00f90, "vqshlu%c.s32 %12-15,22R, %0-3,5R, %16-20d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"}, + 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"}, + 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"}, + 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"}, + 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d"}, + 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800590, 0xff800f90, "vshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d"}, + 0xf2800590, 0xff800f90, "vshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800490, 0xff800f90, "vsri%c.64 %12-15,22R, %0-3,5R, %16-21e"}, + 0xf3800490, 0xff800f90, "vsri%c.64 %12-15,22R, %0-3,5R, %16-21e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800590, 0xff800f90, "vsli%c.64 %12-15,22R, %0-3,5R, %16-21d"}, + 0xf3800590, 0xff800f90, "vsli%c.64 %12-15,22R, %0-3,5R, %16-21d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800690, 0xff800f90, "vqshlu%c.s64 %12-15,22R, %0-3,5R, %16-21d"}, + 0xf3800690, 0xff800f90, "vqshlu%c.s64 %12-15,22R, %0-3,5R, %16-21d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800090, 0xfe800f90, "vshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"}, + 0xf2800090, 0xfe800f90, "vshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800190, 0xfe800f90, "vsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"}, + 0xf2800190, 0xfe800f90, "vsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"}, + 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"}, + 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d"}, + 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2a00e10, 0xfea00e90, - "vcvt%c.%24,8?usff32.%24,8?ffus32 %12-15,22R, %0-3,5R, %16-20e"}, + "vcvt%c.%24,8?usff32.%24,8?ffus32 %12-15,22R, %0-3,5R, %16-20e" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 0xf2a00c10, 0xfea00e90, - "vcvt%c.%24,8?usff16.%24,8?ffus16 %12-15,22R, %0-3,5R, %16-20e"}, + "vcvt%c.%24,8?usff16.%24,8?ffus16 %12-15,22R, %0-3,5R, %16-20e" }, /* Three registers of different lengths. */ {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), - 0xf2a00e00, 0xfeb00f50, "vmull%c.p64 %12-15,22Q, %16-19,7D, %0-3,5D"}, + 0xf2a00e00, 0xfeb00f50, "vmull%c.p64 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0 %12-15,22Q, %16-19,7D, %0-3,5D"}, + 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800400, 0xff800f50, - "vaddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"}, + "vaddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800600, 0xff800f50, - "vsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"}, + "vsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800900, 0xff800f50, - "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800b00, 0xff800f50, - "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800d00, 0xff800f50, - "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf3800400, 0xff800f50, - "vraddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"}, + "vraddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf3800600, 0xff800f50, - "vrsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"}, + "vrsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800000, 0xfe800f50, - "vaddl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vaddl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800100, 0xfe800f50, - "vaddw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D"}, + "vaddw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800200, 0xfe800f50, - "vsubl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vsubl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800300, 0xfe800f50, - "vsubw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D"}, + "vsubw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800500, 0xfe800f50, - "vabal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vabal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800700, 0xfe800f50, - "vabdl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vabdl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800800, 0xfe800f50, - "vmlal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vmlal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800a00, 0xfe800f50, - "vmlsl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vmlsl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800c00, 0xfe800f50, - "vmull%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"}, + "vmull%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D" }, /* Two registers and a scalar. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22D, %16-19,7D, %D"}, + 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf2900140, 0xffb00f50, "vmla%c.f16 %12-15,22D, %16-19,7D, %D"}, + 0xf2900140, 0xffb00f50, "vmla%c.f16 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf2900540, 0xffb00f50, "vmls%c.f16 %12-15,22D, %16-19,7D, %D"}, + 0xf2900540, 0xffb00f50, "vmls%c.f16 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22D, %16-19,7D, %D"}, + 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf2900940, 0xffb00f50, "vmul%c.f16 %12-15,22D, %16-19,7D, %D"}, + 0xf2900940, 0xffb00f50, "vmul%c.f16 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"}, + 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf3900140, 0xffb00f50, "vmla%c.f16 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3900140, 0xffb00f50, "vmla%c.f16 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf3900540, 0xffb00f50, "vmls%c.f16 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3900540, 0xffb00f50, "vmls%c.f16 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), - 0xf3900940, 0xffb00f50, "vmul%c.f16 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3900940, 0xffb00f50, "vmul%c.f16 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800240, 0xfe800f50, - "vmlal%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + "vmlal%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800640, 0xfe800f50, - "vmlsl%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + "vmlsl%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 0xf2800a40, 0xfe800f50, - "vmull%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"}, + "vmull%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf2800e40, 0xff800f50, - "vqrdmlah%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"}, + "vqrdmlah%c.s%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf2800f40, 0xff800f50, - "vqrdmlsh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"}, + "vqrdmlsh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf3800e40, 0xff800f50, - "vqrdmlah%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"}, + "vqrdmlah%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 0xf3800f40, 0xff800f50, "vqrdmlsh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D" @@ -1655,43 +1655,43 @@ static const struct opcode32 neon_opcodes[] = /* Element and structure load/store. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4a00fc0, 0xffb00fc0, "vld4%c.32 %C"}, + 0xf4a00fc0, 0xffb00fc0, "vld4%c.32 %C" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2 %C"}, + 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2 %C" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2 %C"}, + 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2 %C" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2 %C"}, + 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2 %C" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2 %C"}, + 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2 %C" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"}, + 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"}, + 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A"}, + 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A"}, + 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"}, + 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"}, + 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"}, + 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"}, + 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"}, + 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2 %A"}, + 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2 %A" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2 %B"}, + 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2 %B" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2 %B"}, + 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2 %B" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2 %B"}, + 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2 %B" }, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2 %B"}, + 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2 %B" }, {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} }; @@ -1741,733 +1741,733 @@ static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0xe1a00000, 0xffffffff, "nop ; (mov r0, r0)"}, + 0xe1a00000, 0xffffffff, "nop ; (mov r0, r0)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0xe7f000f0, 0xfff000f0, "udf %e"}, + 0xe7f000f0, 0xfff000f0, "udf %e" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), - 0x012FFF10, 0x0ffffff0, "bx%c %0-3r"}, + 0x012FFF10, 0x0ffffff0, "bx%c %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), - 0x00000090, 0x0fe000f0, "mul%20's%c %16-19R, %0-3R, %8-11R"}, + 0x00000090, 0x0fe000f0, "mul%20's%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), - 0x00200090, 0x0fe000f0, "mla%20's%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x00200090, 0x0fe000f0, "mla%20's%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), - 0x01000090, 0x0fb00ff0, "swp%22'b%c %12-15RU, %0-3Ru, [%16-19RuU]"}, + 0x01000090, 0x0fb00ff0, "swp%22'b%c %12-15RU, %0-3Ru, [%16-19RuU]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 0x00800090, 0x0fa000f0, - "%22?sumull%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + "%22?sumull%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 0x00a00090, 0x0fa000f0, - "%22?sumlal%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + "%22?sumlal%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, /* V8.2 RAS extension instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), - 0xe320f010, 0xffffffff, "esb"}, + 0xe320f010, 0xffffffff, "esb" }, /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0x0320f005, 0x0fffffff, "sevl"}, + 0x0320f005, 0x0fffffff, "sevl" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe1000070, 0xfff000f0, "hlt 0x%16-19X%12-15X%8-11X%0-3X"}, + 0xe1000070, 0xfff000f0, "hlt 0x%16-19X%12-15X%8-11X%0-3X" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), - 0x01800e90, 0x0ff00ff0, "stlex%c %12-15r, %0-3r, [%16-19R]"}, + 0x01800e90, 0x0ff00ff0, "stlex%c %12-15r, %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01900e9f, 0x0ff00fff, "ldaex%c %12-15r, [%16-19R]"}, + 0x01900e9f, 0x0ff00fff, "ldaex%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0x01a00e90, 0x0ff00ff0, "stlexd%c %12-15r, %0-3r, %0-3T, [%16-19R]"}, + 0x01a00e90, 0x0ff00ff0, "stlexd%c %12-15r, %0-3r, %0-3T, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0x01b00e9f, 0x0ff00fff, "ldaexd%c %12-15r, %12-15T, [%16-19R]"}, + 0x01b00e9f, 0x0ff00fff, "ldaexd%c %12-15r, %12-15T, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01c00e90, 0x0ff00ff0, "stlexb%c %12-15r, %0-3r, [%16-19R]"}, + 0x01c00e90, 0x0ff00ff0, "stlexb%c %12-15r, %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01d00e9f, 0x0ff00fff, "ldaexb%c %12-15r, [%16-19R]"}, + 0x01d00e9f, 0x0ff00fff, "ldaexb%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01e00e90, 0x0ff00ff0, "stlexh%c %12-15r, %0-3r, [%16-19R]"}, + 0x01e00e90, 0x0ff00ff0, "stlexh%c %12-15r, %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01f00e9f, 0x0ff00fff, "ldaexh%c %12-15r, [%16-19R]"}, + 0x01f00e9f, 0x0ff00fff, "ldaexh%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x0180fc90, 0x0ff0fff0, "stl%c %0-3r, [%16-19R]"}, + 0x0180fc90, 0x0ff0fff0, "stl%c %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01900c9f, 0x0ff00fff, "lda%c %12-15r, [%16-19R]"}, + 0x01900c9f, 0x0ff00fff, "lda%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01c0fc90, 0x0ff0fff0, "stlb%c %0-3r, [%16-19R]"}, + 0x01c0fc90, 0x0ff0fff0, "stlb%c %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01d00c9f, 0x0ff00fff, "ldab%c %12-15r, [%16-19R]"}, + 0x01d00c9f, 0x0ff00fff, "ldab%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01e0fc90, 0x0ff0fff0, "stlh%c %0-3r, [%16-19R]"}, + 0x01e0fc90, 0x0ff0fff0, "stlh%c %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), - 0x01f00c9f, 0x0ff00fff, "ldah%c %12-15r, [%16-19R]"}, + 0x01f00c9f, 0x0ff00fff, "ldah%c %12-15r, [%16-19R]" }, /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1000040, 0xfff00ff0, "crc32b %12-15R, %16-19R, %0-3R"}, + 0xe1000040, 0xfff00ff0, "crc32b %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1200040, 0xfff00ff0, "crc32h %12-15R, %16-19R, %0-3R"}, + 0xe1200040, 0xfff00ff0, "crc32h %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1400040, 0xfff00ff0, "crc32w %12-15R, %16-19R, %0-3R"}, + 0xe1400040, 0xfff00ff0, "crc32w %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1000240, 0xfff00ff0, "crc32cb %12-15R, %16-19R, %0-3R"}, + 0xe1000240, 0xfff00ff0, "crc32cb %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1200240, 0xfff00ff0, "crc32ch %12-15R, %16-19R, %0-3R"}, + 0xe1200240, 0xfff00ff0, "crc32ch %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xe1400240, 0xfff00ff0, "crc32cw %12-15R, %16-19R, %0-3R"}, + 0xe1400240, 0xfff00ff0, "crc32cw %12-15R, %16-19R, %0-3R" }, /* Privileged Access Never extension instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), - 0xf1100000, 0xfffffdff, "setpan %9-9d"}, + 0xf1100000, 0xfffffdff, "setpan %9-9d" }, /* Virtualization Extension instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c %e"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c %e" }, /* Integer Divide Extension instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), - 0x0710f010, 0x0ff0f0f0, "sdiv%c %16-19r, %0-3r, %8-11r"}, + 0x0710f010, 0x0ff0f0f0, "sdiv%c %16-19r, %0-3r, %8-11r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), - 0x0730f010, 0x0ff0f0f0, "udiv%c %16-19r, %0-3r, %8-11r"}, + 0x0730f010, 0x0ff0f0f0, "udiv%c %16-19r, %0-3r, %8-11r" }, /* MP Extension instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw %a" }, /* V7 instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli %P"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c %0-3d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb %U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli %P" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c %0-3d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb %U" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), - 0x0320f000, 0x0fffffff, "nop%c {%0-7d}"}, + 0x0320f000, 0x0fffffff, "nop%c {%0-7d}" }, /* ARM V6T2 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x07c0001f, 0x0fe0007f, "bfc%c %12-15R, %E"}, + 0x07c0001f, 0x0fe0007f, "bfc%c %12-15R, %E" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x07c00010, 0x0fe00070, "bfi%c %12-15R, %0-3r, %E"}, + 0x07c00010, 0x0fe00070, "bfi%c %12-15R, %0-3r, %E" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x00600090, 0x0ff000f0, "mls%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x00600090, 0x0ff000f0, "mls%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x002000b0, 0x0f3000f0, "strht%c %12-15R, %S"}, + 0x002000b0, 0x0f3000f0, "strht%c %12-15R, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c %12-15R, %S"}, + 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c %12-15R, %S" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0x03000000, 0x0ff00000, "movw%c %12-15R, %V"}, + 0x03000000, 0x0ff00000, "movw%c %12-15R, %V" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0x03400000, 0x0ff00000, "movt%c %12-15R, %V"}, + 0x03400000, 0x0ff00000, "movt%c %12-15R, %V" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x06ff0f30, 0x0fff0ff0, "rbit%c %12-15R, %0-3R"}, + 0x06ff0f30, 0x0fff0ff0, "rbit%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0x07a00050, 0x0fa00070, "%22?usbfx%c %12-15r, %0-3r, %7-11d, #%16-20W"}, + 0x07a00050, 0x0fa00070, "%22?usbfx%c %12-15r, %0-3r, %7-11d, #%16-20W" }, /* ARM Security extension instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), - 0x01600070, 0x0ff000f0, "smc%c %e"}, + 0x01600070, 0x0ff000f0, "smc%c %e" }, /* ARM V6K instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0xf57ff01f, 0xffffffff, "clrex"}, + 0xf57ff01f, 0xffffffff, "clrex" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01d00f9f, 0x0ff00fff, "ldrexb%c %12-15R, [%16-19R]"}, + 0x01d00f9f, 0x0ff00fff, "ldrexb%c %12-15R, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01b00f9f, 0x0ff00fff, "ldrexd%c %12-15r, [%16-19R]"}, + 0x01b00f9f, 0x0ff00fff, "ldrexd%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01f00f9f, 0x0ff00fff, "ldrexh%c %12-15R, [%16-19R]"}, + 0x01f00f9f, 0x0ff00fff, "ldrexh%c %12-15R, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01c00f90, 0x0ff00ff0, "strexb%c %12-15R, %0-3R, [%16-19R]"}, + 0x01c00f90, 0x0ff00ff0, "strexb%c %12-15R, %0-3R, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01a00f90, 0x0ff00ff0, "strexd%c %12-15R, %0-3r, [%16-19R]"}, + 0x01a00f90, 0x0ff00ff0, "strexd%c %12-15R, %0-3r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x01e00f90, 0x0ff00ff0, "strexh%c %12-15R, %0-3R, [%16-19R]"}, + 0x01e00f90, 0x0ff00ff0, "strexh%c %12-15R, %0-3R, [%16-19R]" }, /* ARM V6K NOP hints. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x0320f001, 0x0fffffff, "yield%c"}, + 0x0320f001, 0x0fffffff, "yield%c" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x0320f002, 0x0fffffff, "wfe%c"}, + 0x0320f002, 0x0fffffff, "wfe%c" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x0320f003, 0x0fffffff, "wfi%c"}, + 0x0320f003, 0x0fffffff, "wfi%c" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x0320f004, 0x0fffffff, "sev%c"}, + 0x0320f004, 0x0fffffff, "sev%c" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), - 0x0320f000, 0x0fffff00, "nop%c {%0-7d}"}, + 0x0320f000, 0x0fffff00, "nop%c {%0-7d}" }, /* ARM V6 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf1080000, 0xfffffe3f, "cpsie %8'a%7'i%6'f"}, + 0xf1080000, 0xfffffe3f, "cpsie %8'a%7'i%6'f" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf10a0000, 0xfffffe20, "cpsie %8'a%7'i%6'f,%0-4d"}, + 0xf10a0000, 0xfffffe20, "cpsie %8'a%7'i%6'f,%0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf10C0000, 0xfffffe3f, "cpsid %8'a%7'i%6'f"}, + 0xf10C0000, 0xfffffe3f, "cpsid %8'a%7'i%6'f" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf10e0000, 0xfffffe20, "cpsid %8'a%7'i%6'f,%0-4d"}, + 0xf10e0000, 0xfffffe20, "cpsid %8'a%7'i%6'f,%0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf1000000, 0xfff1fe20, "cps %0-4d"}, + 0xf1000000, 0xfff1fe20, "cps %0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800010, 0x0ff00ff0, "pkhbt%c %12-15R, %16-19R, %0-3R"}, + 0x06800010, 0x0ff00ff0, "pkhbt%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800010, 0x0ff00070, "pkhbt%c %12-15R, %16-19R, %0-3R, lsl %7-11d"}, + 0x06800010, 0x0ff00070, "pkhbt%c %12-15R, %16-19R, %0-3R, lsl %7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800050, 0x0ff00ff0, "pkhtb%c %12-15R, %16-19R, %0-3R, asr #32"}, + 0x06800050, 0x0ff00ff0, "pkhtb%c %12-15R, %16-19R, %0-3R, asr #32" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800050, 0x0ff00070, "pkhtb%c %12-15R, %16-19R, %0-3R, asr %7-11d"}, + 0x06800050, 0x0ff00070, "pkhtb%c %12-15R, %16-19R, %0-3R, asr %7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x01900f9f, 0x0ff00fff, "ldrex%c r%12-15d, [%16-19R]"}, + 0x01900f9f, 0x0ff00fff, "ldrex%c r%12-15d, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200f10, 0x0ff00ff0, "qadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06200f10, 0x0ff00ff0, "qadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200f90, 0x0ff00ff0, "qadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06200f90, 0x0ff00ff0, "qadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200f30, 0x0ff00ff0, "qasx%c %12-15R, %16-19R, %0-3R"}, + 0x06200f30, 0x0ff00ff0, "qasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200f70, 0x0ff00ff0, "qsub16%c %12-15R, %16-19R, %0-3R"}, + 0x06200f70, 0x0ff00ff0, "qsub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200ff0, 0x0ff00ff0, "qsub8%c %12-15R, %16-19R, %0-3R"}, + 0x06200ff0, 0x0ff00ff0, "qsub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06200f50, 0x0ff00ff0, "qsax%c %12-15R, %16-19R, %0-3R"}, + 0x06200f50, 0x0ff00ff0, "qsax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100f10, 0x0ff00ff0, "sadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06100f10, 0x0ff00ff0, "sadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100f90, 0x0ff00ff0, "sadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06100f90, 0x0ff00ff0, "sadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100f30, 0x0ff00ff0, "sasx%c %12-15R, %16-19R, %0-3R"}, + 0x06100f30, 0x0ff00ff0, "sasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300f10, 0x0ff00ff0, "shadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06300f10, 0x0ff00ff0, "shadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300f90, 0x0ff00ff0, "shadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06300f90, 0x0ff00ff0, "shadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300f30, 0x0ff00ff0, "shasx%c %12-15R, %16-19R, %0-3R"}, + 0x06300f30, 0x0ff00ff0, "shasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300f70, 0x0ff00ff0, "shsub16%c %12-15R, %16-19R, %0-3R"}, + 0x06300f70, 0x0ff00ff0, "shsub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300ff0, 0x0ff00ff0, "shsub8%c %12-15R, %16-19R, %0-3R"}, + 0x06300ff0, 0x0ff00ff0, "shsub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06300f50, 0x0ff00ff0, "shsax%c %12-15R, %16-19R, %0-3R"}, + 0x06300f50, 0x0ff00ff0, "shsax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100f70, 0x0ff00ff0, "ssub16%c %12-15R, %16-19R, %0-3R"}, + 0x06100f70, 0x0ff00ff0, "ssub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100ff0, 0x0ff00ff0, "ssub8%c %12-15R, %16-19R, %0-3R"}, + 0x06100ff0, 0x0ff00ff0, "ssub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06100f50, 0x0ff00ff0, "ssax%c %12-15R, %16-19R, %0-3R"}, + 0x06100f50, 0x0ff00ff0, "ssax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500f10, 0x0ff00ff0, "uadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06500f10, 0x0ff00ff0, "uadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500f90, 0x0ff00ff0, "uadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06500f90, 0x0ff00ff0, "uadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500f30, 0x0ff00ff0, "uasx%c %12-15R, %16-19R, %0-3R"}, + 0x06500f30, 0x0ff00ff0, "uasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700f10, 0x0ff00ff0, "uhadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06700f10, 0x0ff00ff0, "uhadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700f90, 0x0ff00ff0, "uhadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06700f90, 0x0ff00ff0, "uhadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700f30, 0x0ff00ff0, "uhasx%c %12-15R, %16-19R, %0-3R"}, + 0x06700f30, 0x0ff00ff0, "uhasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700f70, 0x0ff00ff0, "uhsub16%c %12-15R, %16-19R, %0-3R"}, + 0x06700f70, 0x0ff00ff0, "uhsub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700ff0, 0x0ff00ff0, "uhsub8%c %12-15R, %16-19R, %0-3R"}, + 0x06700ff0, 0x0ff00ff0, "uhsub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06700f50, 0x0ff00ff0, "uhsax%c %12-15R, %16-19R, %0-3R"}, + 0x06700f50, 0x0ff00ff0, "uhsax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600f10, 0x0ff00ff0, "uqadd16%c %12-15R, %16-19R, %0-3R"}, + 0x06600f10, 0x0ff00ff0, "uqadd16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600f90, 0x0ff00ff0, "uqadd8%c %12-15R, %16-19R, %0-3R"}, + 0x06600f90, 0x0ff00ff0, "uqadd8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600f30, 0x0ff00ff0, "uqasx%c %12-15R, %16-19R, %0-3R"}, + 0x06600f30, 0x0ff00ff0, "uqasx%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600f70, 0x0ff00ff0, "uqsub16%c %12-15R, %16-19R, %0-3R"}, + 0x06600f70, 0x0ff00ff0, "uqsub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600ff0, 0x0ff00ff0, "uqsub8%c %12-15R, %16-19R, %0-3R"}, + 0x06600ff0, 0x0ff00ff0, "uqsub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06600f50, 0x0ff00ff0, "uqsax%c %12-15R, %16-19R, %0-3R"}, + 0x06600f50, 0x0ff00ff0, "uqsax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500f70, 0x0ff00ff0, "usub16%c %12-15R, %16-19R, %0-3R"}, + 0x06500f70, 0x0ff00ff0, "usub16%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500ff0, 0x0ff00ff0, "usub8%c %12-15R, %16-19R, %0-3R"}, + 0x06500ff0, 0x0ff00ff0, "usub8%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06500f50, 0x0ff00ff0, "usax%c %12-15R, %16-19R, %0-3R"}, + 0x06500f50, 0x0ff00ff0, "usax%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0f30, 0x0fff0ff0, "rev%c %12-15R, %0-3R"}, + 0x06bf0f30, 0x0fff0ff0, "rev%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0fb0, 0x0fff0ff0, "rev16%c %12-15R, %0-3R"}, + 0x06bf0fb0, 0x0fff0ff0, "rev16%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ff0fb0, 0x0fff0ff0, "revsh%c %12-15R, %0-3R"}, + 0x06ff0fb0, 0x0fff0ff0, "revsh%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba %16-19r%21'!"}, + 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba %16-19r%21'!" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15R, %0-3R"}, + 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #8"}, + 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #16"}, + 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #24"}, + 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R"}, + 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #8"}, + 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #16"}, + 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #24"}, + 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R"}, + 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #8"}, + 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #16"}, + 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #24"}, + 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15R, %0-3R"}, + 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #8"}, + 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #16"}, + 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #24"}, + 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R"}, + 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #8"}, + 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #16"}, + 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #24"}, + 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R"}, + 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #8"}, + 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #16"}, + 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #24"}, + 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06b00070, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R"}, + 0x06b00070, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06b00470, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06b00470, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06b00870, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06b00870, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06b00c70, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #24"}, + 0x06b00c70, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800070, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R"}, + 0x06800070, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800470, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06800470, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800870, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06800870, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800c70, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #24"}, + 0x06800c70, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00070, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R"}, + 0x06a00070, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00470, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06a00470, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00870, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06a00870, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00c70, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #24"}, + 0x06a00c70, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06f00070, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R"}, + 0x06f00070, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06f00470, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06f00470, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06f00870, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06f00870, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06f00c70, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #24"}, + 0x06f00c70, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06c00070, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R"}, + 0x06c00070, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06c00470, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06c00470, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06c00870, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06c00870, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06c00c70, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ROR #24"}, + 0x06c00c70, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ROR #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00070, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R"}, + 0x06e00070, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00470, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #8"}, + 0x06e00470, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #8" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00870, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #16"}, + 0x06e00870, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #16" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00c70, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #24"}, + 0x06e00c70, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #24" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06800fb0, 0x0ff00ff0, "sel%c %12-15R, %16-19R, %0-3R"}, + 0x06800fb0, 0x0ff00ff0, "sel%c %12-15R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf1010000, 0xfffffc00, "setend %9?ble"}, + 0xf1010000, 0xfffffc00, "setend %9?ble" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c %16-19R, %0-3R, %8-11R"}, + 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c %16-19R, %0-3R, %8-11R"}, + 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07000010, 0x0ff000d0, "smlad%5'x%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x07000010, 0x0ff000d0, "smlad%5'x%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07400010, 0x0ff000d0, "smlald%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x07400010, 0x0ff000d0, "smlald%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07000050, 0x0ff000d0, "smlsd%5'x%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x07000050, 0x0ff000d0, "smlsd%5'x%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07400050, 0x0ff000d0, "smlsld%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x07400050, 0x0ff000d0, "smlsld%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c %16-19R, %0-3R, %8-11R"}, + 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07500010, 0x0ff000d0, "smmla%5'r%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x07500010, 0x0ff000d0, "smmla%5'r%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x075000d0, 0x0ff000d0, "smmls%5'r%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x075000d0, 0x0ff000d0, "smmls%5'r%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba %16-19r%21'!, %0-4d"}, + 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba %16-19r%21'!, %0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00010, 0x0fe00ff0, "ssat%c %12-15R, %16-20W, %0-3R"}, + 0x06a00010, 0x0fe00ff0, "ssat%c %12-15R, %16-20W, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00010, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, lsl #%7-11d"}, + 0x06a00010, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, lsl #%7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00050, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, asr #%7-11d"}, + 0x06a00050, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, asr #%7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06a00f30, 0x0ff00ff0, "ssat16%c %12-15r, %16-19W, %0-3r"}, + 0x06a00f30, 0x0ff00ff0, "ssat16%c %12-15r, %16-19W, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x01800f90, 0x0ff00ff0, "strex%c %12-15R, %0-3R, [%16-19R]"}, + 0x01800f90, 0x0ff00ff0, "strex%c %12-15R, %0-3R, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x00400090, 0x0ff000f0, "umaal%c %12-15R, %16-19R, %0-3R, %8-11R"}, + 0x00400090, 0x0ff000f0, "umaal%c %12-15R, %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x0780f010, 0x0ff0f0f0, "usad8%c %16-19R, %0-3R, %8-11R"}, + 0x0780f010, 0x0ff0f0f0, "usad8%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x07800010, 0x0ff000f0, "usada8%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x07800010, 0x0ff000f0, "usada8%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00010, 0x0fe00ff0, "usat%c %12-15R, %16-20d, %0-3R"}, + 0x06e00010, 0x0fe00ff0, "usat%c %12-15R, %16-20d, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00010, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, lsl #%7-11d"}, + 0x06e00010, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, lsl #%7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00050, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, asr #%7-11d"}, + 0x06e00050, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, asr #%7-11d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), - 0x06e00f30, 0x0ff00ff0, "usat16%c %12-15R, %16-19d, %0-3R"}, + 0x06e00f30, 0x0ff00ff0, "usat16%c %12-15R, %16-19d, %0-3R" }, /* V5J instruction. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), - 0x012fff20, 0x0ffffff0, "bxj%c %0-3R"}, + 0x012fff20, 0x0ffffff0, "bxj%c %0-3R" }, /* V5 Instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xe1200070, 0xfff000f0, - "bkpt 0x%16-19X%12-15X%8-11X%0-3X"}, + "bkpt 0x%16-19X%12-15X%8-11X%0-3X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0xfa000000, 0xfe000000, "blx %B"}, + 0xfa000000, 0xfe000000, "blx %B" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0x012fff30, 0x0ffffff0, "blx%c %0-3R"}, + 0x012fff30, 0x0ffffff0, "blx%c %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0x016f0f10, 0x0fff0ff0, "clz%c %12-15R, %0-3R"}, + 0x016f0f10, 0x0fff0ff0, "clz%c %12-15R, %0-3R" }, /* V5E "El Segundo" Instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), - 0x000000d0, 0x0e1000f0, "ldrd%c %12-15r, %s"}, + 0x000000d0, 0x0e1000f0, "ldrd%c %12-15r, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), - 0x000000f0, 0x0e1000f0, "strd%c %12-15r, %s"}, + 0x000000f0, 0x0e1000f0, "strd%c %12-15r, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), - 0xf450f000, 0xfc70f000, "pld %a"}, + 0xf450f000, 0xfc70f000, "pld %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01000080, 0x0ff000f0, "smlabb%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x01000080, 0x0ff000f0, "smlabb%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x010000a0, 0x0ff000f0, "smlatb%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x010000a0, 0x0ff000f0, "smlatb%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x010000c0, 0x0ff000f0, "smlabt%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x010000c0, 0x0ff000f0, "smlabt%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x010000e0, 0x0ff000f0, "smlatt%c %16-19r, %0-3r, %8-11R, %12-15R"}, + 0x010000e0, 0x0ff000f0, "smlatt%c %16-19r, %0-3r, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01200080, 0x0ff000f0, "smlawb%c %16-19R, %0-3R, %8-11R, %12-15R"}, + 0x01200080, 0x0ff000f0, "smlawb%c %16-19R, %0-3R, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x012000c0, 0x0ff000f0, "smlawt%c %16-19R, %0-3r, %8-11R, %12-15R"}, + 0x012000c0, 0x0ff000f0, "smlawt%c %16-19R, %0-3r, %8-11R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01400080, 0x0ff000f0, "smlalbb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x01400080, 0x0ff000f0, "smlalbb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x014000a0, 0x0ff000f0, "smlaltb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x014000a0, 0x0ff000f0, "smlaltb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x014000c0, 0x0ff000f0, "smlalbt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x014000c0, 0x0ff000f0, "smlalbt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x014000e0, 0x0ff000f0, "smlaltt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + 0x014000e0, 0x0ff000f0, "smlaltt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01600080, 0x0ff0f0f0, "smulbb%c %16-19R, %0-3R, %8-11R"}, + 0x01600080, 0x0ff0f0f0, "smulbb%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x016000a0, 0x0ff0f0f0, "smultb%c %16-19R, %0-3R, %8-11R"}, + 0x016000a0, 0x0ff0f0f0, "smultb%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x016000c0, 0x0ff0f0f0, "smulbt%c %16-19R, %0-3R, %8-11R"}, + 0x016000c0, 0x0ff0f0f0, "smulbt%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x016000e0, 0x0ff0f0f0, "smultt%c %16-19R, %0-3R, %8-11R"}, + 0x016000e0, 0x0ff0f0f0, "smultt%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x012000a0, 0x0ff0f0f0, "smulwb%c %16-19R, %0-3R, %8-11R"}, + 0x012000a0, 0x0ff0f0f0, "smulwb%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x012000e0, 0x0ff0f0f0, "smulwt%c %16-19R, %0-3R, %8-11R"}, + 0x012000e0, 0x0ff0f0f0, "smulwt%c %16-19R, %0-3R, %8-11R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01000050, 0x0ff00ff0, "qadd%c %12-15R, %0-3R, %16-19R"}, + 0x01000050, 0x0ff00ff0, "qadd%c %12-15R, %0-3R, %16-19R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01400050, 0x0ff00ff0, "qdadd%c %12-15R, %0-3R, %16-19R"}, + 0x01400050, 0x0ff00ff0, "qdadd%c %12-15R, %0-3R, %16-19R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01200050, 0x0ff00ff0, "qsub%c %12-15R, %0-3R, %16-19R"}, + 0x01200050, 0x0ff00ff0, "qsub%c %12-15R, %0-3R, %16-19R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), - 0x01600050, 0x0ff00ff0, "qdsub%c %12-15R, %0-3R, %16-19R"}, + 0x01600050, 0x0ff00ff0, "qdsub%c %12-15R, %0-3R, %16-19R" }, /* ARM Instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x052d0004, 0x0fff0fff, "push%c {%12-15r} ; (str%c %12-15r, %a)"}, + 0x052d0004, 0x0fff0fff, "push%c {%12-15r} ; (str%c %12-15r, %a)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04400000, 0x0e500000, "strb%t%c %12-15R, %a"}, + 0x04400000, 0x0e500000, "strb%t%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04000000, 0x0e500000, "str%t%c %12-15r, %a"}, + 0x04000000, 0x0e500000, "str%t%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x06400000, 0x0e500ff0, "strb%t%c %12-15R, %a"}, + 0x06400000, 0x0e500ff0, "strb%t%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x06000000, 0x0e500ff0, "str%t%c %12-15r, %a"}, + 0x06000000, 0x0e500ff0, "str%t%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04400000, 0x0c500010, "strb%t%c %12-15R, %a"}, + 0x04400000, 0x0c500010, "strb%t%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04000000, 0x0c500010, "str%t%c %12-15r, %a"}, + 0x04000000, 0x0c500010, "str%t%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04400000, 0x0e500000, "strb%c %12-15R, %a"}, + 0x04400000, 0x0e500000, "strb%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x06400000, 0x0e500010, "strb%c %12-15R, %a"}, + 0x06400000, 0x0e500010, "strb%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x004000b0, 0x0e5000f0, "strh%c %12-15R, %s"}, + 0x004000b0, 0x0e5000f0, "strh%c %12-15R, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x000000b0, 0x0e500ff0, "strh%c %12-15R, %s"}, + 0x000000b0, 0x0e500ff0, "strh%c %12-15R, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00500090, 0x0e500090, "ldr%6's%5?hb%c %12-15R, %s"}, + 0x00500090, 0x0e500090, "ldr%6's%5?hb%c %12-15R, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c %12-15R, %s"}, + 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c %12-15R, %s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02000000, 0x0fe00000, "and%20's%c %12-15r, %16-19r, %o"}, + 0x02000000, 0x0fe00000, "and%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00000000, 0x0fe00010, "and%20's%c %12-15r, %16-19r, %o"}, + 0x00000000, 0x0fe00010, "and%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00000010, 0x0fe00090, "and%20's%c %12-15R, %16-19R, %o"}, + 0x00000010, 0x0fe00090, "and%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02200000, 0x0fe00000, "eor%20's%c %12-15r, %16-19r, %o"}, + 0x02200000, 0x0fe00000, "eor%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00200000, 0x0fe00010, "eor%20's%c %12-15r, %16-19r, %o"}, + 0x00200000, 0x0fe00010, "eor%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00200010, 0x0fe00090, "eor%20's%c %12-15R, %16-19R, %o"}, + 0x00200010, 0x0fe00090, "eor%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02400000, 0x0fe00000, "sub%20's%c %12-15r, %16-19r, %o"}, + 0x02400000, 0x0fe00000, "sub%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00400000, 0x0fe00010, "sub%20's%c %12-15r, %16-19r, %o"}, + 0x00400000, 0x0fe00010, "sub%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00400010, 0x0fe00090, "sub%20's%c %12-15R, %16-19R, %o"}, + 0x00400010, 0x0fe00090, "sub%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02600000, 0x0fe00000, "rsb%20's%c %12-15r, %16-19r, %o"}, + 0x02600000, 0x0fe00000, "rsb%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00600000, 0x0fe00010, "rsb%20's%c %12-15r, %16-19r, %o"}, + 0x00600000, 0x0fe00010, "rsb%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00600010, 0x0fe00090, "rsb%20's%c %12-15R, %16-19R, %o"}, + 0x00600010, 0x0fe00090, "rsb%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02800000, 0x0fe00000, "add%20's%c %12-15r, %16-19r, %o"}, + 0x02800000, 0x0fe00000, "add%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00800000, 0x0fe00010, "add%20's%c %12-15r, %16-19r, %o"}, + 0x00800000, 0x0fe00010, "add%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00800010, 0x0fe00090, "add%20's%c %12-15R, %16-19R, %o"}, + 0x00800010, 0x0fe00090, "add%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02a00000, 0x0fe00000, "adc%20's%c %12-15r, %16-19r, %o"}, + 0x02a00000, 0x0fe00000, "adc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00a00000, 0x0fe00010, "adc%20's%c %12-15r, %16-19r, %o"}, + 0x00a00000, 0x0fe00010, "adc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00a00010, 0x0fe00090, "adc%20's%c %12-15R, %16-19R, %o"}, + 0x00a00010, 0x0fe00090, "adc%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02c00000, 0x0fe00000, "sbc%20's%c %12-15r, %16-19r, %o"}, + 0x02c00000, 0x0fe00000, "sbc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00c00000, 0x0fe00010, "sbc%20's%c %12-15r, %16-19r, %o"}, + 0x00c00000, 0x0fe00010, "sbc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00c00010, 0x0fe00090, "sbc%20's%c %12-15R, %16-19R, %o"}, + 0x00c00010, 0x0fe00090, "sbc%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x02e00000, 0x0fe00000, "rsc%20's%c %12-15r, %16-19r, %o"}, + 0x02e00000, 0x0fe00000, "rsc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00e00000, 0x0fe00010, "rsc%20's%c %12-15r, %16-19r, %o"}, + 0x00e00000, 0x0fe00010, "rsc%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x00e00010, 0x0fe00090, "rsc%20's%c %12-15R, %16-19R, %o"}, + 0x00e00010, 0x0fe00090, "rsc%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), - 0x0120f200, 0x0fb0f200, "msr%c %C, %0-3r"}, + 0x0120f200, 0x0fb0f200, "msr%c %C, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), - 0x0120f000, 0x0db0f000, "msr%c %C, %o"}, + 0x0120f000, 0x0db0f000, "msr%c %C, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), - 0x01000000, 0x0fb00cff, "mrs%c %12-15R, %R"}, + 0x01000000, 0x0fb00cff, "mrs%c %12-15R, %R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03000000, 0x0fe00000, "tst%p%c %16-19r, %o"}, + 0x03000000, 0x0fe00000, "tst%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000000, 0x0fe00010, "tst%p%c %16-19r, %o"}, + 0x01000000, 0x0fe00010, "tst%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000010, 0x0fe00090, "tst%p%c %16-19R, %o"}, + 0x01000010, 0x0fe00090, "tst%p%c %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03300000, 0x0ff00000, "teq%p%c %16-19r, %o"}, + 0x03300000, 0x0ff00000, "teq%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300000, 0x0ff00010, "teq%p%c %16-19r, %o"}, + 0x01300000, 0x0ff00010, "teq%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300010, 0x0ff00010, "teq%p%c %16-19R, %o"}, + 0x01300010, 0x0ff00010, "teq%p%c %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), - 0x0130f000, 0x0ff0f010, "bx%c %0-3r"}, + 0x0130f000, 0x0ff0f010, "bx%c %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03400000, 0x0fe00000, "cmp%p%c %16-19r, %o"}, + 0x03400000, 0x0fe00000, "cmp%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400000, 0x0fe00010, "cmp%p%c %16-19r, %o"}, + 0x01400000, 0x0fe00010, "cmp%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400010, 0x0fe00090, "cmp%p%c %16-19R, %o"}, + 0x01400010, 0x0fe00090, "cmp%p%c %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03600000, 0x0fe00000, "cmn%p%c %16-19r, %o"}, + 0x03600000, 0x0fe00000, "cmn%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600000, 0x0fe00010, "cmn%p%c %16-19r, %o"}, + 0x01600000, 0x0fe00010, "cmn%p%c %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600010, 0x0fe00090, "cmn%p%c %16-19R, %o"}, + 0x01600010, 0x0fe00090, "cmn%p%c %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03800000, 0x0fe00000, "orr%20's%c %12-15r, %16-19r, %o"}, + 0x03800000, 0x0fe00000, "orr%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01800000, 0x0fe00010, "orr%20's%c %12-15r, %16-19r, %o"}, + 0x01800000, 0x0fe00010, "orr%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01800010, 0x0fe00090, "orr%20's%c %12-15R, %16-19R, %o"}, + 0x01800010, 0x0fe00090, "orr%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03a00000, 0x0fef0000, "mov%20's%c %12-15r, %o"}, + 0x03a00000, 0x0fef0000, "mov%20's%c %12-15r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00000, 0x0def0ff0, "mov%20's%c %12-15r, %0-3r"}, + 0x01a00000, 0x0def0ff0, "mov%20's%c %12-15r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00000, 0x0def0060, "lsl%20's%c %12-15R, %q"}, + 0x01a00000, 0x0def0060, "lsl%20's%c %12-15R, %q" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00020, 0x0def0060, "lsr%20's%c %12-15R, %q"}, + 0x01a00020, 0x0def0060, "lsr%20's%c %12-15R, %q" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00040, 0x0def0060, "asr%20's%c %12-15R, %q"}, + 0x01a00040, 0x0def0060, "asr%20's%c %12-15R, %q" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00060, 0x0def0ff0, "rrx%20's%c %12-15r, %0-3r"}, + 0x01a00060, 0x0def0ff0, "rrx%20's%c %12-15r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01a00060, 0x0def0060, "ror%20's%c %12-15R, %q"}, + 0x01a00060, 0x0def0060, "ror%20's%c %12-15R, %q" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03c00000, 0x0fe00000, "bic%20's%c %12-15r, %16-19r, %o"}, + 0x03c00000, 0x0fe00000, "bic%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01c00000, 0x0fe00010, "bic%20's%c %12-15r, %16-19r, %o"}, + 0x01c00000, 0x0fe00010, "bic%20's%c %12-15r, %16-19r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01c00010, 0x0fe00090, "bic%20's%c %12-15R, %16-19R, %o"}, + 0x01c00010, 0x0fe00090, "bic%20's%c %12-15R, %16-19R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03e00000, 0x0fe00000, "mvn%20's%c %12-15r, %o"}, + 0x03e00000, 0x0fe00000, "mvn%20's%c %12-15r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01e00000, 0x0fe00010, "mvn%20's%c %12-15r, %o"}, + 0x01e00000, 0x0fe00010, "mvn%20's%c %12-15r, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01e00010, 0x0fe00090, "mvn%20's%c %12-15R, %o"}, + 0x01e00010, 0x0fe00090, "mvn%20's%c %12-15R, %o" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x049d0004, 0x0fff0fff, "pop%c {%12-15r} ; (ldr%c %12-15r, %a)"}, + 0x049d0004, 0x0fff0fff, "pop%c {%12-15r} ; (ldr%c %12-15r, %a)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04500000, 0x0c500000, "ldrb%t%c %12-15R, %a"}, + 0x04500000, 0x0c500000, "ldrb%t%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04300000, 0x0d700000, "ldrt%c %12-15R, %a"}, + 0x04300000, 0x0d700000, "ldrt%c %12-15R, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x04100000, 0x0c500000, "ldr%c %12-15r, %a"}, + 0x04100000, 0x0c500000, "ldr%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0001, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0001, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0002, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0002, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0004, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0004, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0008, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0008, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0010, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0010, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0020, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0020, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0040, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0040, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0080, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0080, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0100, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0100, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0200, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0200, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0400, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0400, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0800, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d0800, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d1000, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d1000, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d2000, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d2000, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d4000, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d4000, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d8000, 0x0fffffff, "stmfd%c %16-19R!, %m"}, + 0x092d8000, 0x0fffffff, "stmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x092d0000, 0x0fff0000, "push%c %m"}, + 0x092d0000, 0x0fff0000, "push%c %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08800000, 0x0ff00000, "stm%c %16-19R%21'!, %m%22'^"}, + 0x08800000, 0x0ff00000, "stm%c %16-19R%21'!, %m%22'^" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08000000, 0x0e100000, "stm%23?id%24?ba%c %16-19R%21'!, %m%22'^"}, + 0x08000000, 0x0e100000, "stm%23?id%24?ba%c %16-19R%21'!, %m%22'^" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0001, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0001, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0002, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0002, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0004, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0004, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0008, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0008, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0010, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0010, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0020, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0020, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0040, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0040, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0080, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0080, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0100, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0100, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0200, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0200, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0400, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0400, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0800, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd0800, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd1000, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd1000, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd2000, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd2000, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd4000, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd4000, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd8000, 0x0fffffff, "ldmfd%c %16-19R!, %m"}, + 0x08bd8000, 0x0fffffff, "ldmfd%c %16-19R!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08bd0000, 0x0fff0000, "pop%c %m"}, + 0x08bd0000, 0x0fff0000, "pop%c %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08900000, 0x0f900000, "ldm%c %16-19R%21'!, %m%22'^"}, + 0x08900000, 0x0f900000, "ldm%c %16-19R%21'!, %m%22'^" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c %16-19R%21'!, %m%22'^"}, + 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c %16-19R%21'!, %m%22'^" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x0a000000, 0x0e000000, "b%24'l%c %b"}, + 0x0a000000, 0x0e000000, "b%24'l%c %b" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x0f000000, 0x0f000000, "svc%c %0-23x"}, + 0x0f000000, 0x0f000000, "svc%c %0-23x" }, /* The rest. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), @@ -2510,151 +2510,151 @@ static const struct opcode16 thumb_opcodes[] = /* Thumb instructions. */ /* ARMv8-M Security Extensions instructions. */ - {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns %3-6r"}, - {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns %3-6r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns %3-6r" }, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns %3-6r" }, /* ARM V8 instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt %0-5x"}, - {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan %3-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt %0-5x" }, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan %3-3d" }, /* ARM V6K no-argument instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c {%4-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c {%4-7d}" }, /* ARM V6T2 instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xb900, 0xfd00, "cbnz %0-2r, %b%X"}, + 0xb900, 0xfd00, "cbnz %0-2r, %b%X" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xb100, 0xfd00, "cbz %0-2r, %b%X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, + 0xb100, 0xfd00, "cbz %0-2r, %b%X" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X" }, /* ARM V6. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie %2'a%1'i%0'f%X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid %2'a%1'i%0'f%X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend %3?ble%X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c %0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie %2'a%1'i%0'f%X" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid %2'a%1'i%0'f%X" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend %3?ble%X" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c %0-2r, %3-5r" }, /* ARM V5 ISA extends Thumb. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), - 0xbe00, 0xff00, "bkpt %0-7x"}, /* Is always unconditional. */ + 0xbe00, 0xff00, "bkpt %0-7x" }, /* Is always unconditional. */ /* This is BLX(2). BLX(1) is a 32-bit instruction. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), - 0x4780, 0xff87, "blx%c %3-6r%x"}, /* note: 4 bit register number. */ + 0x4780, 0xff87, "blx%c %3-6r%x" }, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x46C0, 0xFFFF, "nop%c ; (mov r8, r8)"}, + 0x46C0, 0xFFFF, "nop%c ; (mov r8, r8)" }, /* Format 4. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C %0-2r, %3-5r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C %0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C %0-2r, %3-5r" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C %0-2r, %3-5r" }, /* format 13 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c sp, %0-6W"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c sp, %0-6W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c sp, %0-6W" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c sp, %0-6W" }, /* format 5 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c %S%x"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c %D, %S"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c %D, %S"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c %D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c %S%x" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c %D, %S" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c %D, %S" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c %D, %S" }, /* format 14 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c %N"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c %O"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c %N" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c %O" }, /* format 2 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x1800, 0xFE00, "add%C %0-2r, %3-5r, %6-8r"}, + 0x1800, 0xFE00, "add%C %0-2r, %3-5r, %6-8r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x1A00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8r"}, + 0x1A00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x1C00, 0xFE00, "add%C %0-2r, %3-5r, %6-8d"}, + 0x1C00, 0xFE00, "add%C %0-2r, %3-5r, %6-8d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x1E00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8d"}, + 0x1E00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8d" }, /* format 8 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x5200, 0xFE00, "strh%c %0-2r, [%3-5r, %6-8r]"}, + 0x5200, 0xFE00, "strh%c %0-2r, [%3-5r, %6-8r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x5A00, 0xFE00, "ldrh%c %0-2r, [%3-5r, %6-8r]"}, + 0x5A00, 0xFE00, "ldrh%c %0-2r, [%3-5r, %6-8r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x5600, 0xF600, "ldrs%11?hb%c %0-2r, [%3-5r, %6-8r]"}, + 0x5600, 0xF600, "ldrs%11?hb%c %0-2r, [%3-5r, %6-8r]" }, /* format 7 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x5000, 0xFA00, "str%10'b%c %0-2r, [%3-5r, %6-8r]"}, + 0x5000, 0xFA00, "str%10'b%c %0-2r, [%3-5r, %6-8r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x5800, 0xFA00, "ldr%10'b%c %0-2r, [%3-5r, %6-8r]"}, + 0x5800, 0xFA00, "ldr%10'b%c %0-2r, [%3-5r, %6-8r]" }, /* format 1 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C %0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C %0-2r, %3-5r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x0000, 0xF800, "lsl%C %0-2r, %3-5r, %6-10d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C %0-2r, %3-5r, %s"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C %0-2r, %3-5r, %s"}, + 0x0000, 0xF800, "lsl%C %0-2r, %3-5r, %6-10d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C %0-2r, %3-5r, %s" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C %0-2r, %3-5r, %s" }, /* format 3 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C %8-10r, %0-7d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c %8-10r, %0-7d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C %8-10r, %0-7d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C %8-10r, %0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C %8-10r, %0-7d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c %8-10r, %0-7d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C %8-10r, %0-7d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C %8-10r, %0-7d" }, /* format 6 */ /* TODO: Disassemble PC relative "LDR rD,=" */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4800, 0xF800, - "ldr%c %8-10r, [pc, %0-7W] ; (%0-7a)"}, + "ldr%c %8-10r, [pc, %0-7W] ; (%0-7a)" }, /* format 9 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x6000, 0xF800, "str%c %0-2r, [%3-5r, %6-10W]"}, + 0x6000, 0xF800, "str%c %0-2r, [%3-5r, %6-10W]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x6800, 0xF800, "ldr%c %0-2r, [%3-5r, %6-10W]"}, + 0x6800, 0xF800, "ldr%c %0-2r, [%3-5r, %6-10W]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x7000, 0xF800, "strb%c %0-2r, [%3-5r, %6-10d]"}, + 0x7000, 0xF800, "strb%c %0-2r, [%3-5r, %6-10d]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x7800, 0xF800, "ldrb%c %0-2r, [%3-5r, %6-10d]"}, + 0x7800, 0xF800, "ldrb%c %0-2r, [%3-5r, %6-10d]" }, /* format 10 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x8000, 0xF800, "strh%c %0-2r, [%3-5r, %6-10H]"}, + 0x8000, 0xF800, "strh%c %0-2r, [%3-5r, %6-10H]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x8800, 0xF800, "ldrh%c %0-2r, [%3-5r, %6-10H]"}, + 0x8800, 0xF800, "ldrh%c %0-2r, [%3-5r, %6-10H]" }, /* format 11 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x9000, 0xF800, "str%c %8-10r, [sp, %0-7W]"}, + 0x9000, 0xF800, "str%c %8-10r, [sp, %0-7W]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0x9800, 0xF800, "ldr%c %8-10r, [sp, %0-7W]"}, + 0x9800, 0xF800, "ldr%c %8-10r, [sp, %0-7W]" }, /* format 12 */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0xA000, 0xF800, "add%c %8-10r, pc, %0-7W ; (adr %8-10r, %0-7a)"}, + 0xA000, 0xF800, "add%c %8-10r, pc, %0-7W ; (adr %8-10r, %0-7a)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0xA800, 0xF800, "add%c %8-10r, sp, %0-7W"}, + 0xA800, 0xF800, "add%c %8-10r, sp, %0-7W" }, /* format 15 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c %8-10r!, %M"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c %8-10r%W, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c %8-10r!, %M" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c %8-10r%W, %M" }, /* format 17 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c %0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c %0-7d" }, /* format 16 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c %0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c %0-7d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n %0-7B%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n %0-7B%X" }, /* format 18 */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n %0-10B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n %0-10B%x" }, /* The E800 .. FFFF range is unconditionally redirected to the 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs @@ -2719,465 +2719,465 @@ static const struct opcode16 thumb_opcodes[] = static const struct opcode32 thumb32_opcodes[] = { /* ARMv8-M and ARMv8-M Security Extensions instructions. */ - {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), - 0xe840f000, 0xfff0f0ff, "tt %8-11r, %16-19r"}, + 0xe840f000, 0xfff0f0ff, "tt %8-11r, %16-19r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), - 0xe840f040, 0xfff0f0ff, "ttt %8-11r, %16-19r"}, + 0xe840f040, 0xfff0f0ff, "ttt %8-11r, %16-19r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), - 0xe840f080, 0xfff0f0ff, "tta %8-11r, %16-19r"}, + 0xe840f080, 0xfff0f0ff, "tta %8-11r, %16-19r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), - 0xe840f0c0, 0xfff0f0ff, "ttat %8-11r, %16-19r"}, + 0xe840f0c0, 0xfff0f0ff, "ttat %8-11r, %16-19r" }, /* ARM V8.2 RAS extension instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), - 0xf3af8010, 0xffffffff, "esb"}, + 0xf3af8010, 0xffffffff, "esb" }, /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xf3af8005, 0xffffffff, "sevl%c.w"}, + 0xf3af8005, 0xffffffff, "sevl%c.w" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, + 0xf78f8000, 0xfffffffc, "dcps%0-1d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00f8f, 0xfff00fff, "stlb%c %12-15r, [%16-19R]"}, + 0xe8c00f8f, 0xfff00fff, "stlb%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00f9f, 0xfff00fff, "stlh%c %12-15r, [%16-19R]"}, + 0xe8c00f9f, 0xfff00fff, "stlh%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00faf, 0xfff00fff, "stl%c %12-15r, [%16-19R]"}, + 0xe8c00faf, 0xfff00fff, "stl%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00fc0, 0xfff00ff0, "stlexb%c %0-3r, %12-15r, [%16-19R]"}, + 0xe8c00fc0, 0xfff00ff0, "stlexb%c %0-3r, %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00fd0, 0xfff00ff0, "stlexh%c %0-3r, %12-15r, [%16-19R]"}, + 0xe8c00fd0, 0xfff00ff0, "stlexh%c %0-3r, %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c00fe0, 0xfff00ff0, "stlex%c %0-3r, %12-15r, [%16-19R]"}, + 0xe8c00fe0, 0xfff00ff0, "stlex%c %0-3r, %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8c000f0, 0xfff000f0, "stlexd%c %0-3r, %12-15r, %8-11r, [%16-19R]"}, + 0xe8c000f0, 0xfff000f0, "stlexd%c %0-3r, %12-15r, %8-11r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00f8f, 0xfff00fff, "ldab%c %12-15r, [%16-19R]"}, + 0xe8d00f8f, 0xfff00fff, "ldab%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00f9f, 0xfff00fff, "ldah%c %12-15r, [%16-19R]"}, + 0xe8d00f9f, 0xfff00fff, "ldah%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00faf, 0xfff00fff, "lda%c %12-15r, [%16-19R]"}, + 0xe8d00faf, 0xfff00fff, "lda%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00fcf, 0xfff00fff, "ldaexb%c %12-15r, [%16-19R]"}, + 0xe8d00fcf, 0xfff00fff, "ldaexb%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00fdf, 0xfff00fff, "ldaexh%c %12-15r, [%16-19R]"}, + 0xe8d00fdf, 0xfff00fff, "ldaexh%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d00fef, 0xfff00fff, "ldaex%c %12-15r, [%16-19R]"}, + 0xe8d00fef, 0xfff00fff, "ldaex%c %12-15r, [%16-19R]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), - 0xe8d000ff, 0xfff000ff, "ldaexd%c %12-15r, %8-11r, [%16-19R]"}, + 0xe8d000ff, 0xfff000ff, "ldaexd%c %12-15r, %8-11r, [%16-19R]" }, /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f080, 0xfff0f0f0, "crc32b %8-11S, %16-19S, %0-3S"}, + 0xfac0f080, 0xfff0f0f0, "crc32b %8-11S, %16-19S, %0-3S" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f090, 0xfff0f0f0, "crc32h %9-11S, %16-19S, %0-3S"}, + 0xfac0f090, 0xfff0f0f0, "crc32h %9-11S, %16-19S, %0-3S" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f0a0, 0xfff0f0f0, "crc32w %8-11S, %16-19S, %0-3S"}, + 0xfac0f0a0, 0xfff0f0f0, "crc32w %8-11S, %16-19S, %0-3S" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f080, 0xfff0f0f0, "crc32cb %8-11S, %16-19S, %0-3S"}, + 0xfad0f080, 0xfff0f0f0, "crc32cb %8-11S, %16-19S, %0-3S" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f090, 0xfff0f0f0, "crc32ch %8-11S, %16-19S, %0-3S"}, + 0xfad0f090, 0xfff0f0f0, "crc32ch %8-11S, %16-19S, %0-3S" }, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f0a0, 0xfff0f0f0, "crc32cw %8-11S, %16-19S, %0-3S"}, + 0xfad0f0a0, 0xfff0f0f0, "crc32cw %8-11S, %16-19S, %0-3S" }, /* V7 instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c %a"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c %0-3d"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c %U"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c %U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c %a" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c %0-3d" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c %U" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c %U" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), - 0xfb90f0f0, 0xfff0f0f0, "sdiv%c %8-11r, %16-19r, %0-3r"}, + 0xfb90f0f0, 0xfff0f0f0, "sdiv%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), - 0xfbb0f0f0, 0xfff0f0f0, "udiv%c %8-11r, %16-19r, %0-3r"}, + 0xfbb0f0f0, 0xfff0f0f0, "udiv%c %8-11r, %16-19r, %0-3r" }, /* Virtualization Extension instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c %V"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c %V" }, /* We skip ERET as that is SUBS pc, lr, #0. */ /* MP Extension instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c %a" }, /* Security extension instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c %K"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c %K" }, /* Instructions defined in the basic V6T2 set. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8000, 0xffffff00, "nop%c.w {%0-7d}"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w %H"}, + 0xf3af8000, 0xffffff00, "nop%c.w {%0-7d}" }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w %H" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xf3bf8f2f, 0xffffffff, "clrex%c"}, + 0xf3bf8f2f, 0xffffffff, "clrex%c" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8400, 0xffffff1f, "cpsie.w %7'a%6'i%5'f%X"}, + 0xf3af8400, 0xffffff1f, "cpsie.w %7'a%6'i%5'f%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8600, 0xffffff1f, "cpsid.w %7'a%6'i%5'f%X"}, + 0xf3af8600, 0xffffff1f, "cpsid.w %7'a%6'i%5'f%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3c08f00, 0xfff0ffff, "bxj%c %16-19r%x"}, + 0xf3c08f00, 0xfff0ffff, "bxj%c %16-19r%x" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe810c000, 0xffd0ffff, "rfedb%c %16-19r%21'!"}, + 0xe810c000, 0xffd0ffff, "rfedb%c %16-19r%21'!" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe990c000, 0xffd0ffff, "rfeia%c %16-19r%21'!"}, + 0xe990c000, 0xffd0ffff, "rfeia%c %16-19r%21'!" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3e08000, 0xffe0f000, "mrs%c %8-11r, %D"}, + 0xf3e08000, 0xffe0f000, "mrs%c %8-11r, %D" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8100, 0xffffffe0, "cps %0-4d%X"}, + 0xf3af8100, 0xffffffe0, "cps %0-4d%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8d0f000, 0xfff0fff0, "tbb%c [%16-19r, %0-3r]%x"}, + 0xe8d0f000, 0xfff0fff0, "tbb%c [%16-19r, %0-3r]%x" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8d0f010, 0xfff0fff0, "tbh%c [%16-19r, %0-3r, lsl #1]%x"}, + 0xe8d0f010, 0xfff0fff0, "tbh%c [%16-19r, %0-3r, lsl #1]%x" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8500, 0xffffff00, "cpsie %7'a%6'i%5'f, %0-4d%X"}, + 0xf3af8500, 0xffffff00, "cpsie %7'a%6'i%5'f, %0-4d%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3af8700, 0xffffff00, "cpsid %7'a%6'i%5'f, %0-4d%X"}, + 0xf3af8700, 0xffffff00, "cpsid %7'a%6'i%5'f, %0-4d%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3de8f00, 0xffffff00, "subs%c pc, lr, %0-7d"}, + 0xf3de8f00, 0xffffff00, "subs%c pc, lr, %0-7d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3808000, 0xffe0f000, "msr%c %C, %16-19r"}, + 0xf3808000, 0xffe0f000, "msr%c %C, %16-19r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8500f00, 0xfff00fff, "ldrex%c %12-15r, [%16-19r]"}, + 0xe8500f00, 0xfff00fff, "ldrex%c %12-15r, [%16-19r]" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c %12-15r, [%16-19r]"}, + 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c %12-15r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe800c000, 0xffd0ffe0, "srsdb%c %16-19r%21'!, %0-4d"}, + 0xe800c000, 0xffd0ffe0, "srsdb%c %16-19r%21'!, %0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe980c000, 0xffd0ffe0, "srsia%c %16-19r%21'!, %0-4d"}, + 0xe980c000, 0xffd0ffe0, "srsia%c %16-19r%21'!, %0-4d" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa0ff080, 0xfffff0c0, "sxth%c.w %8-11r, %0-3r%R"}, + 0xfa0ff080, 0xfffff0c0, "sxth%c.w %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa1ff080, 0xfffff0c0, "uxth%c.w %8-11r, %0-3r%R"}, + 0xfa1ff080, 0xfffff0c0, "uxth%c.w %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa2ff080, 0xfffff0c0, "sxtb16%c %8-11r, %0-3r%R"}, + 0xfa2ff080, 0xfffff0c0, "sxtb16%c %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa3ff080, 0xfffff0c0, "uxtb16%c %8-11r, %0-3r%R"}, + 0xfa3ff080, 0xfffff0c0, "uxtb16%c %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa4ff080, 0xfffff0c0, "sxtb%c.w %8-11r, %0-3r%R"}, + 0xfa4ff080, 0xfffff0c0, "sxtb%c.w %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa5ff080, 0xfffff0c0, "uxtb%c.w %8-11r, %0-3r%R"}, + 0xfa5ff080, 0xfffff0c0, "uxtb%c.w %8-11r, %0-3r%R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8400000, 0xfff000ff, "strex%c %8-11r, %12-15r, [%16-19r]"}, + 0xe8400000, 0xfff000ff, "strex%c %8-11r, %12-15r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8d0007f, 0xfff000ff, "ldrexd%c %12-15r, %8-11r, [%16-19r]"}, + 0xe8d0007f, 0xfff000ff, "ldrexd%c %12-15r, %8-11r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f000, 0xfff0f0f0, "sadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f000, 0xfff0f0f0, "sadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f010, 0xfff0f0f0, "qadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f010, 0xfff0f0f0, "qadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f020, 0xfff0f0f0, "shadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f020, 0xfff0f0f0, "shadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f040, 0xfff0f0f0, "uadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f040, 0xfff0f0f0, "uadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f050, 0xfff0f0f0, "uqadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f050, 0xfff0f0f0, "uqadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f060, 0xfff0f0f0, "uhadd8%c %8-11r, %16-19r, %0-3r"}, + 0xfa80f060, 0xfff0f0f0, "uhadd8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f080, 0xfff0f0f0, "qadd%c %8-11r, %0-3r, %16-19r"}, + 0xfa80f080, 0xfff0f0f0, "qadd%c %8-11r, %0-3r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f090, 0xfff0f0f0, "qdadd%c %8-11r, %0-3r, %16-19r"}, + 0xfa80f090, 0xfff0f0f0, "qdadd%c %8-11r, %0-3r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f0a0, 0xfff0f0f0, "qsub%c %8-11r, %0-3r, %16-19r"}, + 0xfa80f0a0, 0xfff0f0f0, "qsub%c %8-11r, %0-3r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa80f0b0, 0xfff0f0f0, "qdsub%c %8-11r, %0-3r, %16-19r"}, + 0xfa80f0b0, 0xfff0f0f0, "qdsub%c %8-11r, %0-3r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f000, 0xfff0f0f0, "sadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f000, 0xfff0f0f0, "sadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f010, 0xfff0f0f0, "qadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f010, 0xfff0f0f0, "qadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f020, 0xfff0f0f0, "shadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f020, 0xfff0f0f0, "shadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f040, 0xfff0f0f0, "uadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f040, 0xfff0f0f0, "uadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f050, 0xfff0f0f0, "uqadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f050, 0xfff0f0f0, "uqadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f060, 0xfff0f0f0, "uhadd16%c %8-11r, %16-19r, %0-3r"}, + 0xfa90f060, 0xfff0f0f0, "uhadd16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f080, 0xfff0f0f0, "rev%c.w %8-11r, %16-19r"}, + 0xfa90f080, 0xfff0f0f0, "rev%c.w %8-11r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f090, 0xfff0f0f0, "rev16%c.w %8-11r, %16-19r"}, + 0xfa90f090, 0xfff0f0f0, "rev16%c.w %8-11r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f0a0, 0xfff0f0f0, "rbit%c %8-11r, %16-19r"}, + 0xfa90f0a0, 0xfff0f0f0, "rbit%c %8-11r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w %8-11r, %16-19r"}, + 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w %8-11r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f000, 0xfff0f0f0, "sasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f000, 0xfff0f0f0, "sasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f010, 0xfff0f0f0, "qasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f010, 0xfff0f0f0, "qasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f020, 0xfff0f0f0, "shasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f020, 0xfff0f0f0, "shasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f040, 0xfff0f0f0, "uasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f040, 0xfff0f0f0, "uasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f050, 0xfff0f0f0, "uqasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f050, 0xfff0f0f0, "uqasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f060, 0xfff0f0f0, "uhasx%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f060, 0xfff0f0f0, "uhasx%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfaa0f080, 0xfff0f0f0, "sel%c %8-11r, %16-19r, %0-3r"}, + 0xfaa0f080, 0xfff0f0f0, "sel%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfab0f080, 0xfff0f0f0, "clz%c %8-11r, %16-19r"}, + 0xfab0f080, 0xfff0f0f0, "clz%c %8-11r, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f000, 0xfff0f0f0, "ssub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f000, 0xfff0f0f0, "ssub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f010, 0xfff0f0f0, "qsub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f010, 0xfff0f0f0, "qsub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f020, 0xfff0f0f0, "shsub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f020, 0xfff0f0f0, "shsub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f040, 0xfff0f0f0, "usub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f040, 0xfff0f0f0, "usub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f050, 0xfff0f0f0, "uqsub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f050, 0xfff0f0f0, "uqsub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfac0f060, 0xfff0f0f0, "uhsub8%c %8-11r, %16-19r, %0-3r"}, + 0xfac0f060, 0xfff0f0f0, "uhsub8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f000, 0xfff0f0f0, "ssub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f000, 0xfff0f0f0, "ssub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f010, 0xfff0f0f0, "qsub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f010, 0xfff0f0f0, "qsub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f020, 0xfff0f0f0, "shsub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f020, 0xfff0f0f0, "shsub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f040, 0xfff0f0f0, "usub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f040, 0xfff0f0f0, "usub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f050, 0xfff0f0f0, "uqsub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f050, 0xfff0f0f0, "uqsub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfad0f060, 0xfff0f0f0, "uhsub16%c %8-11r, %16-19r, %0-3r"}, + 0xfad0f060, 0xfff0f0f0, "uhsub16%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f000, 0xfff0f0f0, "ssax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f000, 0xfff0f0f0, "ssax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f010, 0xfff0f0f0, "qsax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f010, 0xfff0f0f0, "qsax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f020, 0xfff0f0f0, "shsax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f020, 0xfff0f0f0, "shsax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f040, 0xfff0f0f0, "usax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f040, 0xfff0f0f0, "usax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f050, 0xfff0f0f0, "uqsax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f050, 0xfff0f0f0, "uqsax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfae0f060, 0xfff0f0f0, "uhsax%c %8-11r, %16-19r, %0-3r"}, + 0xfae0f060, 0xfff0f0f0, "uhsax%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb00f000, 0xfff0f0f0, "mul%c.w %8-11r, %16-19r, %0-3r"}, + 0xfb00f000, 0xfff0f0f0, "mul%c.w %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb70f000, 0xfff0f0f0, "usad8%c %8-11r, %16-19r, %0-3r"}, + 0xfb70f000, 0xfff0f0f0, "usad8%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w %8-11R, %16-19R, %0-3R"}, + 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w %8-11R, %16-19R, %0-3R"}, + 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w %8-11R, %16-19R, %0-3R"}, + 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w %8-11r, %16-19r, %0-3r"}, + 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c %0-3r, %12-15r, [%16-19r]"}, + 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c %0-3r, %12-15r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3200000, 0xfff0f0e0, "ssat16%c %8-11r, %0-4D, %16-19r"}, + 0xf3200000, 0xfff0f0e0, "ssat16%c %8-11r, %0-4D, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3a00000, 0xfff0f0e0, "usat16%c %8-11r, %0-4d, %16-19r"}, + 0xf3a00000, 0xfff0f0e0, "usat16%c %8-11r, %0-4d, %16-19r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c %8-11r, %16-19r, %0-3r"}, + 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c %8-11r, %16-19r, %0-3r"}, + 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c %8-11r, %16-19r, %0-3r"}, + 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c %8-11r, %16-19r, %0-3r"}, + 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa00f080, 0xfff0f0c0, "sxtah%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa00f080, 0xfff0f0c0, "sxtah%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa10f080, 0xfff0f0c0, "uxtah%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa10f080, 0xfff0f0c0, "uxtah%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa20f080, 0xfff0f0c0, "sxtab16%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa20f080, 0xfff0f0c0, "sxtab16%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa30f080, 0xfff0f0c0, "uxtab16%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa30f080, 0xfff0f0c0, "uxtab16%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa40f080, 0xfff0f0c0, "sxtab%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa40f080, 0xfff0f0c0, "sxtab%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfa50f080, 0xfff0f0c0, "uxtab%c %8-11r, %16-19r, %0-3r%R"}, + 0xfa50f080, 0xfff0f0c0, "uxtab%c %8-11r, %16-19r, %0-3r%R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c %8-11r, %16-19r, %0-3r"}, + 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf36f0000, 0xffff8020, "bfc%c %8-11r, %E"}, + 0xf36f0000, 0xffff8020, "bfc%c %8-11r, %E" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea100f00, 0xfff08f00, "tst%c.w %16-19r, %S"}, + 0xea100f00, 0xfff08f00, "tst%c.w %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea900f00, 0xfff08f00, "teq%c %16-19r, %S"}, + 0xea900f00, 0xfff08f00, "teq%c %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeb100f00, 0xfff08f00, "cmn%c.w %16-19r, %S"}, + 0xeb100f00, 0xfff08f00, "cmn%c.w %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xebb00f00, 0xfff08f00, "cmp%c.w %16-19r, %S"}, + 0xebb00f00, 0xfff08f00, "cmp%c.w %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0100f00, 0xfbf08f00, "tst%c.w %16-19r, %M"}, + 0xf0100f00, 0xfbf08f00, "tst%c.w %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0900f00, 0xfbf08f00, "teq%c %16-19r, %M"}, + 0xf0900f00, 0xfbf08f00, "teq%c %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1100f00, 0xfbf08f00, "cmn%c.w %16-19r, %M"}, + 0xf1100f00, 0xfbf08f00, "cmn%c.w %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1b00f00, 0xfbf08f00, "cmp%c.w %16-19r, %M"}, + 0xf1b00f00, 0xfbf08f00, "cmp%c.w %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea4f0000, 0xffef8000, "mov%20's%c.w %8-11r, %S"}, + 0xea4f0000, 0xffef8000, "mov%20's%c.w %8-11r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea6f0000, 0xffef8000, "mvn%20's%c.w %8-11r, %S"}, + 0xea6f0000, 0xffef8000, "mvn%20's%c.w %8-11r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8c00070, 0xfff000f0, "strexd%c %0-3r, %12-15r, %8-11r, [%16-19r]"}, + 0xe8c00070, 0xfff000f0, "strexd%c %0-3r, %12-15r, %8-11r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb000000, 0xfff000f0, "mla%c %8-11r, %16-19r, %0-3r, %12-15r"}, + 0xfb000000, 0xfff000f0, "mla%c %8-11r, %16-19r, %0-3r, %12-15r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb000010, 0xfff000f0, "mls%c %8-11r, %16-19r, %0-3r, %12-15r"}, + 0xfb000010, 0xfff000f0, "mls%c %8-11r, %16-19r, %0-3r, %12-15r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb700000, 0xfff000f0, "usada8%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb700000, 0xfff000f0, "usada8%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb800000, 0xfff000f0, "smull%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfb800000, 0xfff000f0, "smull%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfba00000, 0xfff000f0, "umull%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfba00000, 0xfff000f0, "umull%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfbc00000, 0xfff000f0, "smlal%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfbc00000, 0xfff000f0, "smlal%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfbe00000, 0xfff000f0, "umlal%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfbe00000, 0xfff000f0, "umlal%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfbe00060, 0xfff000f0, "umaal%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfbe00060, 0xfff000f0, "umaal%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8500f00, 0xfff00f00, "ldrex%c %12-15r, [%16-19r, %0-7W]"}, + 0xe8500f00, 0xfff00f00, "ldrex%c %12-15r, [%16-19r, %0-7W]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf04f0000, 0xfbef8000, "mov%20's%c.w %8-11r, %M"}, + 0xf04f0000, 0xfbef8000, "mov%20's%c.w %8-11r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf06f0000, 0xfbef8000, "mvn%20's%c.w %8-11r, %M"}, + 0xf06f0000, 0xfbef8000, "mvn%20's%c.w %8-11r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf810f000, 0xff70f000, "pld%c %a"}, + 0xf810f000, 0xff70f000, "pld%c %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb200000, 0xfff000e0, "smlad%4'x%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb200000, 0xfff000e0, "smlad%4'x%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb300000, 0xfff000e0, "smlaw%4?tb%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb300000, 0xfff000e0, "smlaw%4?tb%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb400000, 0xfff000e0, "smlsd%4'x%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb400000, 0xfff000e0, "smlsd%4'x%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb500000, 0xfff000e0, "smmla%4'r%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb500000, 0xfff000e0, "smmla%4'r%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfb600000, 0xfff000e0, "smmls%4'r%c %8-11R, %16-19R, %0-3R, %12-15R"}, + 0xfb600000, 0xfff000e0, "smmls%4'r%c %8-11R, %16-19R, %0-3R, %12-15R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfbc000c0, 0xfff000e0, "smlald%4'x%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfbc000c0, 0xfff000e0, "smlald%4'x%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c %12-15R, %8-11R, %16-19R, %0-3R"}, + 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c %12-15R, %8-11R, %16-19R, %0-3R" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeac00000, 0xfff08030, "pkhbt%c %8-11r, %16-19r, %S"}, + 0xeac00000, 0xfff08030, "pkhbt%c %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeac00020, 0xfff08030, "pkhtb%c %8-11r, %16-19r, %S"}, + 0xeac00020, 0xfff08030, "pkhtb%c %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3400000, 0xfff08020, "sbfx%c %8-11r, %16-19r, %F"}, + 0xf3400000, 0xfff08020, "sbfx%c %8-11r, %16-19r, %F" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3c00000, 0xfff08020, "ubfx%c %8-11r, %16-19r, %F"}, + 0xf3c00000, 0xfff08020, "ubfx%c %8-11r, %16-19r, %F" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf8000e00, 0xff900f00, "str%wt%c %12-15r, %a"}, + 0xf8000e00, 0xff900f00, "str%wt%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xfb100000, 0xfff000c0, - "smla%5?tb%4?tb%c %8-11r, %16-19r, %0-3r, %12-15r"}, + "smla%5?tb%4?tb%c %8-11r, %16-19r, %0-3r, %12-15r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xfbc00080, 0xfff000c0, - "smlal%5?tb%4?tb%c %12-15r, %8-11r, %16-19r, %0-3r"}, + "smlal%5?tb%4?tb%c %12-15r, %8-11r, %16-19r, %0-3r" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3600000, 0xfff08020, "bfi%c %8-11r, %16-19r, %E"}, + 0xf3600000, 0xfff08020, "bfi%c %8-11r, %16-19r, %E" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf8100e00, 0xfe900f00, "ldr%wt%c %12-15r, %a"}, + 0xf8100e00, 0xfe900f00, "ldr%wt%c %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3000000, 0xffd08020, "ssat%c %8-11r, %0-4D, %16-19r%s"}, + 0xf3000000, 0xffd08020, "ssat%c %8-11r, %0-4D, %16-19r%s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3800000, 0xffd08020, "usat%c %8-11r, %0-4d, %16-19r%s"}, + 0xf3800000, 0xffd08020, "usat%c %8-11r, %0-4d, %16-19r%s" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf2000000, 0xfbf08000, "addw%c %8-11r, %16-19r, %I"}, + 0xf2000000, 0xfbf08000, "addw%c %8-11r, %16-19r, %I" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xf2400000, 0xfbf08000, "movw%c %8-11r, %J"}, + 0xf2400000, 0xfbf08000, "movw%c %8-11r, %J" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf2a00000, 0xfbf08000, "subw%c %8-11r, %16-19r, %I"}, + 0xf2a00000, 0xfbf08000, "subw%c %8-11r, %16-19r, %I" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xf2c00000, 0xfbf08000, "movt%c %8-11r, %J"}, + 0xf2c00000, 0xfbf08000, "movt%c %8-11r, %J" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea000000, 0xffe08000, "and%20's%c.w %8-11r, %16-19r, %S"}, + 0xea000000, 0xffe08000, "and%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea200000, 0xffe08000, "bic%20's%c.w %8-11r, %16-19r, %S"}, + 0xea200000, 0xffe08000, "bic%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea400000, 0xffe08000, "orr%20's%c.w %8-11r, %16-19r, %S"}, + 0xea400000, 0xffe08000, "orr%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea600000, 0xffe08000, "orn%20's%c %8-11r, %16-19r, %S"}, + 0xea600000, 0xffe08000, "orn%20's%c %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xea800000, 0xffe08000, "eor%20's%c.w %8-11r, %16-19r, %S"}, + 0xea800000, 0xffe08000, "eor%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeb000000, 0xffe08000, "add%20's%c.w %8-11r, %16-19r, %S"}, + 0xeb000000, 0xffe08000, "add%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeb400000, 0xffe08000, "adc%20's%c.w %8-11r, %16-19r, %S"}, + 0xeb400000, 0xffe08000, "adc%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeb600000, 0xffe08000, "sbc%20's%c.w %8-11r, %16-19r, %S"}, + 0xeb600000, 0xffe08000, "sbc%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xeba00000, 0xffe08000, "sub%20's%c.w %8-11r, %16-19r, %S"}, + 0xeba00000, 0xffe08000, "sub%20's%c.w %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xebc00000, 0xffe08000, "rsb%20's%c %8-11r, %16-19r, %S"}, + 0xebc00000, 0xffe08000, "rsb%20's%c %8-11r, %16-19r, %S" }, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), - 0xe8400000, 0xfff00000, "strex%c %8-11r, %12-15r, [%16-19r, %0-7W]"}, + 0xe8400000, 0xfff00000, "strex%c %8-11r, %12-15r, [%16-19r, %0-7W]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0000000, 0xfbe08000, "and%20's%c.w %8-11r, %16-19r, %M"}, + 0xf0000000, 0xfbe08000, "and%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0200000, 0xfbe08000, "bic%20's%c.w %8-11r, %16-19r, %M"}, + 0xf0200000, 0xfbe08000, "bic%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0400000, 0xfbe08000, "orr%20's%c.w %8-11r, %16-19r, %M"}, + 0xf0400000, 0xfbe08000, "orr%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0600000, 0xfbe08000, "orn%20's%c %8-11r, %16-19r, %M"}, + 0xf0600000, 0xfbe08000, "orn%20's%c %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0800000, 0xfbe08000, "eor%20's%c.w %8-11r, %16-19r, %M"}, + 0xf0800000, 0xfbe08000, "eor%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1000000, 0xfbe08000, "add%20's%c.w %8-11r, %16-19r, %M"}, + 0xf1000000, 0xfbe08000, "add%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1400000, 0xfbe08000, "adc%20's%c.w %8-11r, %16-19r, %M"}, + 0xf1400000, 0xfbe08000, "adc%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1600000, 0xfbe08000, "sbc%20's%c.w %8-11r, %16-19r, %M"}, + 0xf1600000, 0xfbe08000, "sbc%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1a00000, 0xfbe08000, "sub%20's%c.w %8-11r, %16-19r, %M"}, + 0xf1a00000, 0xfbe08000, "sub%20's%c.w %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf1c00000, 0xfbe08000, "rsb%20's%c %8-11r, %16-19r, %M"}, + 0xf1c00000, 0xfbe08000, "rsb%20's%c %8-11r, %16-19r, %M" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8800000, 0xffd00000, "stmia%c.w %16-19r%21'!, %m"}, + 0xe8800000, 0xffd00000, "stmia%c.w %16-19r%21'!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe8900000, 0xffd00000, "ldmia%c.w %16-19r%21'!, %m"}, + 0xe8900000, 0xffd00000, "ldmia%c.w %16-19r%21'!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe9000000, 0xffd00000, "stmdb%c %16-19r%21'!, %m"}, + 0xe9000000, 0xffd00000, "stmdb%c %16-19r%21'!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe9100000, 0xffd00000, "ldmdb%c %16-19r%21'!, %m"}, + 0xe9100000, 0xffd00000, "ldmdb%c %16-19r%21'!, %m" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe9c00000, 0xffd000ff, "strd%c %12-15r, %8-11r, [%16-19r]"}, + 0xe9c00000, 0xffd000ff, "strd%c %12-15r, %8-11r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xe9d00000, 0xffd000ff, "ldrd%c %12-15r, %8-11r, [%16-19r]"}, + 0xe9d00000, 0xffd000ff, "ldrd%c %12-15r, %8-11r, [%16-19r]" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe9400000, 0xff500000, - "strd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L"}, + "strd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe9500000, 0xff500000, - "ldrd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L"}, + "ldrd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe8600000, 0xff700000, - "strd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L"}, + "strd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe8700000, 0xff700000, - "ldrd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L"}, + "ldrd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf8000000, 0xff100000, "str%w%c.w %12-15r, %a"}, + 0xf8000000, 0xff100000, "str%w%c.w %12-15r, %a" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf8100000, 0xfe100000, "ldr%w%c.w %12-15r, %a"}, + 0xf8100000, 0xfe100000, "ldr%w%c.w %12-15r, %a" }, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, + 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, + 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0008000, 0xf800d000, "b%22-25c.w %b%X"}, + 0xf0008000, 0xf800d000, "b%22-25c.w %b%X" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf0009000, 0xf800d000, "b%c.w %B%x"}, + 0xf0009000, 0xf800d000, "b%c.w %B%x" }, /* These have been 32-bit since the invention of Thumb. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0xf000c000, 0xf800d001, "blx%c %B%x"}, + 0xf000c000, 0xf800d001, "blx%c %B%x" }, {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), - 0xf000d000, 0xf800d000, "bl%c %B%x"}, + 0xf000d000, 0xf800d000, "bl%c %B%x" }, /* Fallback. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), @@ -3186,14 +3186,14 @@ static const struct opcode32 thumb32_opcodes[] = }; static const char *const arm_conditional[] = -{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "al", "", ""}; +{ "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "al", "", "" }; static const char *const arm_fp_const[] = -{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; +{ "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0" }; static const char *const arm_shift[] = -{"lsl", "lsr", "asr", "ror"}; +{ "lsl", "lsr", "asr", "ror" }; typedef struct { @@ -3206,7 +3206,7 @@ arm_regname; static const arm_regname regnames[] = { { "reg-names-raw", N_("Select raw register names"), - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" }}, { "reg-names-gcc", N_("Select register names used by GCC"), { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), @@ -3222,10 +3222,10 @@ static const arm_regname regnames[] = }; static const char *const iwmmxt_wwnames[] = -{"b", "h", "w", "d"}; +{ "b", "h", "w", "d" }; static const char *const iwmmxt_wwssnames[] = -{"b", "bus", "bc", "bss", +{ "b", "bus", "bc", "bss", "h", "hus", "hc", "hss", "w", "wus", "wc", "wss", "d", "dus", "dc", "dss" @@ -3874,8 +3874,7 @@ print_insn_coprocessor (bfd_vma pc, case '3': /* List */ func (stream, "{"); regno = (given >> 12) & 0x0000000f; - if (single) - { + if (single) { regno <<= 1; regno += (given >> 22) & 1; } else { @@ -4230,7 +4229,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else { func (stream, "d%d-d%d", rd, rd + n - 1); } - func (stream, "}, [%s", arm_regnames[rn]); + func (stream, " }, [%s", arm_regnames[rn]); if (align) { func (stream, " :%d", 32 << align); } @@ -4310,7 +4309,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", rd + i * stride, idx); } - func (stream, "}, [%s", arm_regnames[rn]); + func (stream, " }, [%s", arm_regnames[rn]); if (align) { func (stream, " :%d", align); } @@ -4351,7 +4350,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else { func (stream, "d%d[]-d%d[]", rd, rd + n - 1); } - func (stream, "}, [%s", arm_regnames[rn]); + func (stream, " }, [%s", arm_regnames[rn]); if (align) { align = (8 * (type + 1)) << size; diff --git a/libr/asm/arch/avr/assemble.c b/libr/asm/arch/avr/assemble.c index 3692f5aad1..5184dfc428 100644 --- a/libr/asm/arch/avr/assemble.c +++ b/libr/asm/arch/avr/assemble.c @@ -35,9 +35,9 @@ static int getnum(const char *s) { // radare tolower instruction in rasm, so we use 'x' instead of 'X' etc. specialregs RegsTable[REGS_TABLE] = { - {"-x", OPERAND_XP}, {"x", OPERAND_X}, {"x+", OPERAND_XP}, - {"-y", OPERAND_YP}, {"y", OPERAND_Y}, {"y+", OPERAND_YP}, - {"-z", OPERAND_ZP}, {"z", OPERAND_Z}, {"z+", OPERAND_ZP}, + { "-x", OPERAND_XP}, { "x", OPERAND_X}, { "x+", OPERAND_XP}, + { "-y", OPERAND_YP}, { "y", OPERAND_Y}, { "y+", OPERAND_YP}, + { "-z", OPERAND_ZP}, { "z", OPERAND_Z}, { "z+", OPERAND_ZP}, }; diff --git a/libr/asm/arch/avr/avr_instructionset.c b/libr/asm/arch/avr/avr_instructionset.c index 100aeea3c1..df136c7560 100644 --- a/libr/asm/arch/avr/avr_instructionset.c +++ b/libr/asm/arch/avr/avr_instructionset.c @@ -44,150 +44,150 @@ */ instructionInfo instructionSet[AVR_TOTAL_INSTRUCTIONS] = { - {"break", 0x9598, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"clc", 0x9488, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"clh", 0x94d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"cli", 0x94f8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"cln", 0x94a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"cls", 0x94c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"clt", 0x94e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"clv", 0x94b8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"clz", 0x9498, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"eicall", 0x9519, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"eijmp", 0x9419, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"elpm", 0x95d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"icall", 0x9509, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"ijmp", 0x9409, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"lpm", 0x95c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"nop", 0x0000, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"ret", 0x9508, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"reti", 0x9518, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sec", 0x9408, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"seh", 0x9458, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sei", 0x9478, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sen", 0x9428, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"ses", 0x9448, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"set", 0x9468, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sev", 0x9438, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sez", 0x9418, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"sleep", 0x9588, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"spm", 0x95e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"spm", 0x95f8, 1, {0x0000, 0x0000}, {OPERAND_ZP, OPERAND_NONE}}, - {"wdr", 0x95a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, - {"des", 0x940b, 1, {0x00f0, 0x0000}, {OPERAND_DES_ROUND, OPERAND_NONE}}, - {"asr", 0x9405, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"bclr", 0x9488, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}}, - {"brcc", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brcs", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"breq", 0xf001, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brge", 0xf404, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brhc", 0xf405, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brhs", 0xf005, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brid", 0xf407, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brie", 0xf007, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brlo", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brlt", 0xf004, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brmi", 0xf002, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brne", 0xf401, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brpl", 0xf402, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brsh", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brtc", 0xf406, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brts", 0xf006, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brvc", 0xf403, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"brvs", 0xf003, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, - {"bset", 0x9408, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}}, - {"call", 0x940e, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}}, - {"clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, - {"com", 0x9400, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"dec", 0x940a, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"inc", 0x9403, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"jmp", 0x940c, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}}, - {"lpm", 0x9004, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, - {"lpm", 0x9005, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, - {"lsl", 0x0c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, - {"lsr", 0x9406, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"neg", 0x9401, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"pop", 0x900f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"xch", 0x9204, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, - {"las", 0x9205, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, - {"lac", 0x9206, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, - {"lat", 0x9207, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, - {"push", 0x920f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"rcall", 0xd000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}}, - {"rjmp", 0xc000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}}, - {"rol", 0x1c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, - {"ror", 0x9407, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"ser", 0xef0f, 1, {0x00f0, 0x0000}, {OPERAND_REGISTER_STARTR16, OPERAND_NONE}}, - {"swap", 0x9402, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, - {"tst", 0x2000, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, + { "break", 0x9598, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "clc", 0x9488, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "clh", 0x94d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "cli", 0x94f8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "cln", 0x94a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "cls", 0x94c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "clt", 0x94e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "clv", 0x94b8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "clz", 0x9498, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "eicall", 0x9519, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "eijmp", 0x9419, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "elpm", 0x95d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "icall", 0x9509, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "ijmp", 0x9409, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "lpm", 0x95c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "nop", 0x0000, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "ret", 0x9508, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "reti", 0x9518, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sec", 0x9408, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "seh", 0x9458, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sei", 0x9478, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sen", 0x9428, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "ses", 0x9448, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "set", 0x9468, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sev", 0x9438, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sez", 0x9418, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "sleep", 0x9588, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "spm", 0x95e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "spm", 0x95f8, 1, {0x0000, 0x0000}, {OPERAND_ZP, OPERAND_NONE}}, + { "wdr", 0x95a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}}, + { "des", 0x940b, 1, {0x00f0, 0x0000}, {OPERAND_DES_ROUND, OPERAND_NONE}}, + { "asr", 0x9405, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "bclr", 0x9488, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}}, + { "brcc", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brcs", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "breq", 0xf001, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brge", 0xf404, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brhc", 0xf405, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brhs", 0xf005, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brid", 0xf407, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brie", 0xf007, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brlo", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brlt", 0xf004, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brmi", 0xf002, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brne", 0xf401, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brpl", 0xf402, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brsh", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brtc", 0xf406, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brts", 0xf006, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brvc", 0xf403, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "brvs", 0xf003, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}}, + { "bset", 0x9408, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}}, + { "call", 0x940e, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}}, + { "clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, + { "com", 0x9400, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "dec", 0x940a, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "inc", 0x9403, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "jmp", 0x940c, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}}, + { "lpm", 0x9004, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, + { "lpm", 0x9005, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, + { "lsl", 0x0c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, + { "lsr", 0x9406, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "neg", 0x9401, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "pop", 0x900f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "xch", 0x9204, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, + { "las", 0x9205, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, + { "lac", 0x9206, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, + { "lat", 0x9207, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, + { "push", 0x920f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "rcall", 0xd000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}}, + { "rjmp", 0xc000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}}, + { "rol", 0x1c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, + { "ror", 0x9407, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "ser", 0xef0f, 1, {0x00f0, 0x0000}, {OPERAND_REGISTER_STARTR16, OPERAND_NONE}}, + { "swap", 0x9402, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}}, + { "tst", 0x2000, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}}, - {"adc", 0x1c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"add", 0x0c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"adiw", 0x9600, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}}, - {"and", 0x2000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"andi", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"bld", 0xf800, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, - {"brbc", 0xf400, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}}, - {"brbs", 0xf000, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}}, - {"bst", 0xfa00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, - {"cbi", 0x9800, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, - {"cbr", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_COMPLEMENTED_DATA}}, - {"cp", 0x1400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"cpc", 0x0400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"cpi", 0x3000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"cpse", 0x1000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"elpm", 0x9006, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, - {"elpm", 0x9007, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, - {"eor", 0x2400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"fmul", 0x0308, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, - {"fmuls", 0x0380, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, - {"fmulsu", 0x0388, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, - {"in", 0xb000, 2, {0x01f0, 0x060f}, {OPERAND_REGISTER, OPERAND_DATA}}, - {"ld", 0x900c, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_X}}, - {"ld", 0x900d, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_XP}}, - {"ld", 0x900e, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MX}}, - {"ld", 0x8008, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Y}}, - {"ld", 0x9009, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_YP}}, - {"ld", 0x900a, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MY}}, - {"ld", 0x8000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, - {"ld", 0x9001, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, - {"ld", 0x9002, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MZ}}, - {"ldd", 0x8008, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_YPQ}}, - {"ldd", 0x8000, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_ZPQ}}, - {"ldi", 0xe000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"std", 0x8208, 2, {0x2c07, 0x01f0}, {OPERAND_YPQ, OPERAND_REGISTER}}, - {"std", 0x8200, 2, {0x2c07, 0x01f0}, {OPERAND_ZPQ, OPERAND_REGISTER}}, - {"lds", 0x9000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_LONG_ABSOLUTE_ADDRESS}}, - {"lds", 0xA000, 2, {0x00f0, 0x070f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"mov", 0x2c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"movw", 0x0100, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_EVEN_PAIR, OPERAND_REGISTER_EVEN_PAIR}}, - {"mul", 0x9c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"muls", 0x0200, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, - {"mulsu", 0x0300, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, - {"or", 0x2800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"ori", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"out", 0xb800, 2, {0x060f, 0x01f0}, {OPERAND_IO_REGISTER, OPERAND_REGISTER}}, - {"sbc", 0x0800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"sbci", 0x4000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"sbi", 0x9a00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, - {"sbic", 0x9900, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, - {"sbis", 0x9b00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, - {"sbiw", 0x9700, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}}, - {"sbr", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {"sbrc", 0xfc00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, - {"sbrs", 0xfe00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, - {"st", 0x920c, 2, {0x0000, 0x01f0}, {OPERAND_X, OPERAND_REGISTER}}, - {"st", 0x920d, 2, {0x0000, 0x01f0}, {OPERAND_XP, OPERAND_REGISTER}}, - {"st", 0x920e, 2, {0x0000, 0x01f0}, {OPERAND_MX, OPERAND_REGISTER}}, - {"st", 0x8208, 2, {0x0000, 0x01f0}, {OPERAND_Y, OPERAND_REGISTER}}, - {"st", 0x9209, 2, {0x0000, 0x01f0}, {OPERAND_YP, OPERAND_REGISTER}}, - {"st", 0x920a, 2, {0x0000, 0x01f0}, {OPERAND_MY, OPERAND_REGISTER}}, - {"st", 0x8200, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, - {"st", 0x9201, 2, {0x0000, 0x01f0}, {OPERAND_ZP, OPERAND_REGISTER}}, - {"st", 0x9202, 2, {0x0000, 0x01f0}, {OPERAND_MZ, OPERAND_REGISTER}}, - {"sts", 0x9200, 2, {0x0000, 0x01f0}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_REGISTER}}, - {"sts", 0xA800, 2, {0x00f0, 0x070f}, {OPERAND_DATA, OPERAND_REGISTER_STARTR16}}, // was {OPERAND_REGISTER_STARTR16, OPERAND_DATA}, bug? - {"sub", 0x1800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, - {"subi", 0x5000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, - {".word", 0x0000, 1, {0xFFFF, 0x0000}, {OPERAND_WORD_DATA, OPERAND_NONE}}, + { "adc", 0x1c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "add", 0x0c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "adiw", 0x9600, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}}, + { "and", 0x2000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "andi", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "bld", 0xf800, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, + { "brbc", 0xf400, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}}, + { "brbs", 0xf000, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}}, + { "bst", 0xfa00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, + { "cbi", 0x9800, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, + { "cbr", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_COMPLEMENTED_DATA}}, + { "cp", 0x1400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "cpc", 0x0400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "cpi", 0x3000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "cpse", 0x1000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "elpm", 0x9006, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, + { "elpm", 0x9007, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, + { "eor", 0x2400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "fmul", 0x0308, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, + { "fmuls", 0x0380, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, + { "fmulsu", 0x0388, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, + { "in", 0xb000, 2, {0x01f0, 0x060f}, {OPERAND_REGISTER, OPERAND_DATA}}, + { "ld", 0x900c, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_X}}, + { "ld", 0x900d, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_XP}}, + { "ld", 0x900e, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MX}}, + { "ld", 0x8008, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Y}}, + { "ld", 0x9009, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_YP}}, + { "ld", 0x900a, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MY}}, + { "ld", 0x8000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}}, + { "ld", 0x9001, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}}, + { "ld", 0x9002, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MZ}}, + { "ldd", 0x8008, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_YPQ}}, + { "ldd", 0x8000, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_ZPQ}}, + { "ldi", 0xe000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "std", 0x8208, 2, {0x2c07, 0x01f0}, {OPERAND_YPQ, OPERAND_REGISTER}}, + { "std", 0x8200, 2, {0x2c07, 0x01f0}, {OPERAND_ZPQ, OPERAND_REGISTER}}, + { "lds", 0x9000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_LONG_ABSOLUTE_ADDRESS}}, + { "lds", 0xA000, 2, {0x00f0, 0x070f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "mov", 0x2c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "movw", 0x0100, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_EVEN_PAIR, OPERAND_REGISTER_EVEN_PAIR}}, + { "mul", 0x9c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "muls", 0x0200, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, + { "mulsu", 0x0300, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}}, + { "or", 0x2800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "ori", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "out", 0xb800, 2, {0x060f, 0x01f0}, {OPERAND_IO_REGISTER, OPERAND_REGISTER}}, + { "sbc", 0x0800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "sbci", 0x4000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "sbi", 0x9a00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, + { "sbic", 0x9900, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, + { "sbis", 0x9b00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}}, + { "sbiw", 0x9700, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}}, + { "sbr", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { "sbrc", 0xfc00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, + { "sbrs", 0xfe00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}}, + { "st", 0x920c, 2, {0x0000, 0x01f0}, {OPERAND_X, OPERAND_REGISTER}}, + { "st", 0x920d, 2, {0x0000, 0x01f0}, {OPERAND_XP, OPERAND_REGISTER}}, + { "st", 0x920e, 2, {0x0000, 0x01f0}, {OPERAND_MX, OPERAND_REGISTER}}, + { "st", 0x8208, 2, {0x0000, 0x01f0}, {OPERAND_Y, OPERAND_REGISTER}}, + { "st", 0x9209, 2, {0x0000, 0x01f0}, {OPERAND_YP, OPERAND_REGISTER}}, + { "st", 0x920a, 2, {0x0000, 0x01f0}, {OPERAND_MY, OPERAND_REGISTER}}, + { "st", 0x8200, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}}, + { "st", 0x9201, 2, {0x0000, 0x01f0}, {OPERAND_ZP, OPERAND_REGISTER}}, + { "st", 0x9202, 2, {0x0000, 0x01f0}, {OPERAND_MZ, OPERAND_REGISTER}}, + { "sts", 0x9200, 2, {0x0000, 0x01f0}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_REGISTER}}, + { "sts", 0xA800, 2, {0x00f0, 0x070f}, {OPERAND_DATA, OPERAND_REGISTER_STARTR16}}, // was {OPERAND_REGISTER_STARTR16, OPERAND_DATA}, bug? + { "sub", 0x1800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}}, + { "subi", 0x5000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}}, + { ".word", 0x0000, 1, {0xFFFF, 0x0000}, {OPERAND_WORD_DATA, OPERAND_NONE}}, }; diff --git a/libr/asm/arch/cris/gnu/cris-opc.c b/libr/asm/arch/cris/gnu/cris-opc.c index 24a6784350..6756af11c8 100644 --- a/libr/asm/arch/cris/gnu/cris-opc.c +++ b/libr/asm/arch/cris/gnu/cris-opc.c @@ -31,64 +31,64 @@ const struct cris_spec_reg cris_spec_regs[] = { - {"bz", 0, 1, cris_ver_v32p, NULL}, - {"p0", 0, 1, 0, NULL}, - {"vr", 1, 1, 0, NULL}, - {"p1", 1, 1, 0, NULL}, - {"pid", 2, 1, cris_ver_v32p, NULL}, - {"p2", 2, 1, cris_ver_v32p, NULL}, - {"p2", 2, 1, cris_ver_warning, NULL}, - {"srs", 3, 1, cris_ver_v32p, NULL}, - {"p3", 3, 1, cris_ver_v32p, NULL}, - {"p3", 3, 1, cris_ver_warning, NULL}, - {"wz", 4, 2, cris_ver_v32p, NULL}, - {"p4", 4, 2, 0, NULL}, - {"ccr", 5, 2, cris_ver_v0_10, NULL}, - {"exs", 5, 4, cris_ver_v32p, NULL}, - {"p5", 5, 2, cris_ver_v0_10, NULL}, - {"p5", 5, 4, cris_ver_v32p, NULL}, - {"dcr0",6, 2, cris_ver_v0_3, NULL}, - {"eda", 6, 4, cris_ver_v32p, NULL}, - {"p6", 6, 2, cris_ver_v0_3, NULL}, - {"p6", 6, 4, cris_ver_v32p, NULL}, - {"dcr1/mof", 7, 4, cris_ver_v10p, - "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, - {"dcr1/mof", 7, 2, cris_ver_v0_3, - "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, - {"mof", 7, 4, cris_ver_v10p, NULL}, - {"dcr1",7, 2, cris_ver_v0_3, NULL}, - {"p7", 7, 4, cris_ver_v10p, NULL}, - {"p7", 7, 2, cris_ver_v0_3, NULL}, - {"dz", 8, 4, cris_ver_v32p, NULL}, - {"p8", 8, 4, 0, NULL}, - {"ibr", 9, 4, cris_ver_v0_10, NULL}, - {"ebp", 9, 4, cris_ver_v32p, NULL}, - {"p9", 9, 4, 0, NULL}, - {"irp", 10, 4, cris_ver_v0_10, NULL}, - {"erp", 10, 4, cris_ver_v32p, NULL}, - {"p10", 10, 4, 0, NULL}, - {"srp", 11, 4, 0, NULL}, - {"p11", 11, 4, 0, NULL}, + { "bz", 0, 1, cris_ver_v32p, NULL}, + { "p0", 0, 1, 0, NULL}, + { "vr", 1, 1, 0, NULL}, + { "p1", 1, 1, 0, NULL}, + { "pid", 2, 1, cris_ver_v32p, NULL}, + { "p2", 2, 1, cris_ver_v32p, NULL}, + { "p2", 2, 1, cris_ver_warning, NULL}, + { "srs", 3, 1, cris_ver_v32p, NULL}, + { "p3", 3, 1, cris_ver_v32p, NULL}, + { "p3", 3, 1, cris_ver_warning, NULL}, + { "wz", 4, 2, cris_ver_v32p, NULL}, + { "p4", 4, 2, 0, NULL}, + { "ccr", 5, 2, cris_ver_v0_10, NULL}, + { "exs", 5, 4, cris_ver_v32p, NULL}, + { "p5", 5, 2, cris_ver_v0_10, NULL}, + { "p5", 5, 4, cris_ver_v32p, NULL}, + { "dcr0",6, 2, cris_ver_v0_3, NULL}, + { "eda", 6, 4, cris_ver_v32p, NULL}, + { "p6", 6, 2, cris_ver_v0_3, NULL}, + { "p6", 6, 4, cris_ver_v32p, NULL}, + { "dcr1/mof", 7, 4, cris_ver_v10p, + "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes" }, + { "dcr1/mof", 7, 2, cris_ver_v0_3, + "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes" }, + { "mof", 7, 4, cris_ver_v10p, NULL}, + { "dcr1",7, 2, cris_ver_v0_3, NULL}, + { "p7", 7, 4, cris_ver_v10p, NULL}, + { "p7", 7, 2, cris_ver_v0_3, NULL}, + { "dz", 8, 4, cris_ver_v32p, NULL}, + { "p8", 8, 4, 0, NULL}, + { "ibr", 9, 4, cris_ver_v0_10, NULL}, + { "ebp", 9, 4, cris_ver_v32p, NULL}, + { "p9", 9, 4, 0, NULL}, + { "irp", 10, 4, cris_ver_v0_10, NULL}, + { "erp", 10, 4, cris_ver_v32p, NULL}, + { "p10", 10, 4, 0, NULL}, + { "srp", 11, 4, 0, NULL}, + { "p11", 11, 4, 0, NULL}, /* For disassembly use only. Accept at assembly with a warning. */ - {"bar/dtp0", 12, 4, cris_ver_warning, - "Ambiguous register `bar/dtp0' specified"}, - {"nrp", 12, 4, cris_ver_v32p, NULL}, - {"bar", 12, 4, cris_ver_v8_10, NULL}, - {"dtp0",12, 4, cris_ver_v0_3, NULL}, - {"p12", 12, 4, 0, NULL}, + { "bar/dtp0", 12, 4, cris_ver_warning, + "Ambiguous register `bar/dtp0' specified" }, + { "nrp", 12, 4, cris_ver_v32p, NULL}, + { "bar", 12, 4, cris_ver_v8_10, NULL}, + { "dtp0",12, 4, cris_ver_v0_3, NULL}, + { "p12", 12, 4, 0, NULL}, /* For disassembly use only. Accept at assembly with a warning. */ - {"dccr/dtp1",13, 4, cris_ver_warning, - "Ambiguous register `dccr/dtp1' specified"}, - {"ccs", 13, 4, cris_ver_v32p, NULL}, - {"dccr",13, 4, cris_ver_v8_10, NULL}, - {"dtp1",13, 4, cris_ver_v0_3, NULL}, - {"p13", 13, 4, 0, NULL}, - {"brp", 14, 4, cris_ver_v3_10, NULL}, - {"usp", 14, 4, cris_ver_v32p, NULL}, - {"p14", 14, 4, cris_ver_v3p, NULL}, - {"usp", 15, 4, cris_ver_v10, NULL}, - {"spc", 15, 4, cris_ver_v32p, NULL}, - {"p15", 15, 4, cris_ver_v10p, NULL}, + { "dccr/dtp1",13, 4, cris_ver_warning, + "Ambiguous register `dccr/dtp1' specified" }, + { "ccs", 13, 4, cris_ver_v32p, NULL}, + { "dccr",13, 4, cris_ver_v8_10, NULL}, + { "dtp1",13, 4, cris_ver_v0_3, NULL}, + { "p13", 13, 4, 0, NULL}, + { "brp", 14, 4, cris_ver_v3_10, NULL}, + { "usp", 14, 4, cris_ver_v32p, NULL}, + { "p14", 14, 4, cris_ver_v3p, NULL}, + { "usp", 15, 4, cris_ver_v10, NULL}, + { "spc", 15, 4, cris_ver_v32p, NULL}, + { "p15", 15, 4, cris_ver_v10p, NULL}, {NULL, 0, 0, cris_ver_version_all, NULL} }; @@ -97,22 +97,22 @@ cris_spec_regs[] = implementation. */ const struct cris_support_reg cris_support_regs[] = { - {"s0", 0}, - {"s1", 1}, - {"s2", 2}, - {"s3", 3}, - {"s4", 4}, - {"s5", 5}, - {"s6", 6}, - {"s7", 7}, - {"s8", 8}, - {"s9", 9}, - {"s10", 10}, - {"s11", 11}, - {"s12", 12}, - {"s13", 13}, - {"s14", 14}, - {"s15", 15}, + { "s0", 0}, + { "s1", 1}, + { "s2", 2}, + { "s3", 3}, + { "s4", 4}, + { "s5", 5}, + { "s6", 6}, + { "s7", 7}, + { "s8", 8}, + { "s9", 9}, + { "s10", 10}, + { "s11", 11}, + { "s12", 12}, + { "s13", 13}, + { "s14", 14}, + { "s15", 15}, {NULL, 0} }; @@ -194,163 +194,163 @@ const struct cris_support_reg cris_support_regs[] = const struct cris_opcode cris_opcodes[] = { - {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, + { "abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, cris_abs_op}, - {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, + { "add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, + { "add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, + { "add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, + { "add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, + { "add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, cris_ver_v32p, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, + { "addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, - {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, + { "addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, - {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, + { "addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, cris_ver_v32p, cris_addi_op}, - {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, + { "addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, cris_addi_op}, /* This collates after "addo", but we want to disassemble as "addoq", not "addo". */ - {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, + { "addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, + { "addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, cris_ver_v32p, cris_not_implemented_op}, /* This must be located after the insn above, lest we misinterpret "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a parser bug. */ - {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, + { "addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, + { "addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, cris_quick_mode_add_sub_op}, - {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, + { "adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, + { "adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, + { "adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, + { "adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, + { "addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, + { "addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, + { "addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, + { "addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, + { "and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, + { "and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, + { "and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, + { "and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, + { "andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, - {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, + { "asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, cris_asr_op}, - {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, + { "asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, cris_asrq_op}, - {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, + { "ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, /* FIXME: Should use branch #defines. */ - {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, + { "b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, cris_sixteen_bit_offset_branch_op}, - {"ba", + { "ba", BA_QUICK_OPCODE, 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, /* Needs to come after the usual "ba o", which might be relaxed to this one. */ - {"ba", BA_DWORD_OPCODE, + { "ba", BA_DWORD_OPCODE, 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, + { "bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, + { "basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"bcc", + { "bcc", BRANCH_QUICK_OPCODE+CC_CC*0x1000, 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bcs", + { "bcs", BRANCH_QUICK_OPCODE+CC_CS*0x1000, 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bdap", + { "bdap", BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED, cris_ver_v0_10, cris_bdap_prefix}, - {"bdap", + { "bdap", BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, cris_ver_v0_10, cris_quick_mode_bdap_prefix}, - {"beq", + { "beq", BRANCH_QUICK_OPCODE+CC_EQ*0x1000, 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, @@ -358,730 +358,730 @@ cris_opcodes[] = /* This is deliberately put before "bext" to trump it, even though not in alphabetical order, since we don't do excluding version checks for v0..v10. */ - {"bwf", + { "bwf", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v10, cris_eight_bit_offset_branch_op}, - {"bext", + { "bext", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v0_3, cris_eight_bit_offset_branch_op}, - {"bge", + { "bge", BRANCH_QUICK_OPCODE+CC_GE*0x1000, 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bgt", + { "bgt", BRANCH_QUICK_OPCODE+CC_GT*0x1000, 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bhi", + { "bhi", BRANCH_QUICK_OPCODE+CC_HI*0x1000, 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bhs", + { "bhs", BRANCH_QUICK_OPCODE+CC_HS*0x1000, 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, + { "biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, cris_ver_v0_10, cris_biap_prefix}, - {"ble", + { "ble", BRANCH_QUICK_OPCODE+CC_LE*0x1000, 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"blo", + { "blo", BRANCH_QUICK_OPCODE+CC_LO*0x1000, 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bls", + { "bls", BRANCH_QUICK_OPCODE+CC_LS*0x1000, 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"blt", + { "blt", BRANCH_QUICK_OPCODE+CC_LT*0x1000, 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bmi", + { "bmi", BRANCH_QUICK_OPCODE+CC_MI*0x1000, 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, + { "bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, cris_ver_sim_v0_10, cris_not_implemented_op}, - {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, + { "bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, cris_ver_sim_v0_10, cris_not_implemented_op}, - {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, + { "bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, cris_ver_sim_v0_10, cris_not_implemented_op}, - {"bne", + { "bne", BRANCH_QUICK_OPCODE+CC_NE*0x1000, 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, + { "bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, cris_two_operand_bound_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, + { "bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, cris_ver_v0_10, cris_two_operand_bound_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, + { "bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, cris_two_operand_bound_op}, - {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, + { "bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_two_operand_bound_op}, - {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, + { "bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_bound_op}, - {"bpl", + { "bpl", BRANCH_QUICK_OPCODE+CC_PL*0x1000, 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, + { "break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, cris_ver_v3p, cris_break_op}, - {"bsb", + { "bsb", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v32p, cris_eight_bit_offset_branch_op}, - {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, + { "bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, + { "bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, + { "bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, cris_ver_warning, cris_not_implemented_op}, - {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, + { "bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, cris_ver_warning, cris_not_implemented_op}, - {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, + { "bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, cris_ver_warning, cris_not_implemented_op}, - {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, + { "btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, cris_btst_nop_op}, - {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, + { "btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, cris_btst_nop_op}, - {"bvc", + { "bvc", BRANCH_QUICK_OPCODE+CC_VC*0x1000, 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"bvs", + { "bvs", BRANCH_QUICK_OPCODE+CC_VS*0x1000, 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, - {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, + { "clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, cris_reg_mode_clear_op}, - {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, + { "clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, cris_none_reg_mode_clear_test_op}, - {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, + { "clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_clear_test_op}, - {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, + { "clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, cris_clearf_di_op}, - {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, + { "cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, + { "cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, + { "cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, + { "cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, + { "cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, + { "cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, + { "cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, + { "cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, + { "di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, cris_clearf_di_op}, - {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, + { "dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, cris_ver_v0_10, cris_dip_prefix}, - {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, + { "div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, cris_not_implemented_op}, - {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, + { "dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, + { "ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, - {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, + { "fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, + { "fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, + { "ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, + { "ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, + { "halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, + { "jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, + { "jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, + { "jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, + { "jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, + { "jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, - {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, + { "jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, + { "jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, + { "jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, - {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, + { "jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, + { "jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, + { "jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, - {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, + { "jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, + { "jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, + { "jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, cris_reg_mode_jump_op}, - {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, + { "jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, cris_ver_v0_10, cris_none_reg_mode_jump_op}, - {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, + { "jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, + { "jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_jump_op}, - {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, + { "jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, - {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, + { "jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, + { "jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, - {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, + { "jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, + { "jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, - {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, + { "jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, cris_reg_mode_jump_op}, - {"jump", + { "jump", JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, cris_ver_v0_10, cris_none_reg_mode_jump_op}, - {"jump", + { "jump", JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_jump_op}, - {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, + { "jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"jump", + { "jump", JUMP_PC_INCR_OPCODE_V32, (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, - {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, + { "jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, cris_ver_v10, cris_none_reg_mode_jump_op}, - {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, + { "jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, cris_ver_v10, cris_none_reg_mode_jump_op}, - {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, + { "lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, + { "lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, - {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, + { "lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, cris_ver_v32p, cris_addi_op}, - {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, + { "lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, + { "lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, + { "lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, + { "lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, + { "lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, cris_ver_v3p, cris_not_implemented_op}, - {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, + { "mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, + { "move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, + { "move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, + { "move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, + { "move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, cris_move_to_preg_op}, - {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, + { "move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, cris_reg_mode_move_from_preg_op}, - {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, + { "move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, + { "move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"move", + { "move", MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS, "s,P", 0, SIZE_SPEC_REG, 0, cris_move_to_preg_op}, - {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, + { "move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, cris_ver_v0_10, cris_move_to_preg_op}, - {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, + { "move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, cris_none_reg_mode_move_from_preg_op}, - {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, + { "move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_move_from_preg_op}, - {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, + { "move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, + { "move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, + { "movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, cris_move_reg_to_mem_movem_op}, - {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, + { "movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, cris_ver_v0_10, cris_move_reg_to_mem_movem_op}, - {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, + { "movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, cris_move_mem_to_reg_movem_op}, - {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, + { "movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_move_mem_to_reg_movem_op}, - {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, + { "moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, - {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, + { "movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, + { "movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, + { "movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, + { "movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, + { "movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, + { "movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, + { "mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, cris_ver_v0_10, cris_dstep_logshift_mstep_neg_not_op}, - {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, + { "muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, cris_ver_v10p, cris_muls_op}, - {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, + { "mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, cris_ver_v10p, cris_mulu_op}, - {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, + { "neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, + { "nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, cris_ver_v0_10, cris_btst_nop_op}, - {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE, + { "nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE, cris_ver_v32p, cris_btst_nop_op}, - {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, + { "not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, - {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, + { "or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, + { "or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, + { "or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, + { "or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, + { "orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, - {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, + { "pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, + { "pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_move_from_preg_op}, - {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, + { "push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, + { "push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, cris_ver_v0_10, cris_move_to_preg_op}, - {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, + { "rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, - {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, + { "rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, - {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, + { "rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, + { "rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, + { "rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, - {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, + { "ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, - {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, + { "ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, - {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, + { "retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, - {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, + { "rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, - {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, + { "reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, - {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, + { "retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, - {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, + { "sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, - {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, + { "sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, - {"sa", + { "sa", 0x0530+CC_A*0x1000, 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"ssb", + { "ssb", 0x0530+CC_EXT*0x1000, 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v32p, cris_scc_op}, - {"scc", + { "scc", 0x0530+CC_CC*0x1000, 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"scs", + { "scs", 0x0530+CC_CS*0x1000, 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"seq", + { "seq", 0x0530+CC_EQ*0x1000, 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, + { "setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, - {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, + { "sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, /* Need to have "swf" in front of "sext" so it is the one displayed in disassembly. */ - {"swf", + { "swf", 0x0530+CC_EXT*0x1000, 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v10, cris_scc_op}, - {"sext", + { "sext", 0x0530+CC_EXT*0x1000, 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v0_3, cris_scc_op}, - {"sge", + { "sge", 0x0530+CC_GE*0x1000, 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"sgt", + { "sgt", 0x0530+CC_GT*0x1000, 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"shi", + { "shi", 0x0530+CC_HI*0x1000, 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"shs", + { "shs", 0x0530+CC_HS*0x1000, 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"sle", + { "sle", 0x0530+CC_LE*0x1000, 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"slo", + { "slo", 0x0530+CC_LO*0x1000, 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"sls", + { "sls", 0x0530+CC_LS*0x1000, 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"slt", + { "slt", 0x0530+CC_LT*0x1000, 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"smi", + { "smi", 0x0530+CC_MI*0x1000, 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"sne", + { "sne", 0x0530+CC_NE*0x1000, 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"spl", + { "spl", 0x0530+CC_PL*0x1000, 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, + { "sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, - {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, + { "sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, + { "sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, + { "sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, + { "subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, cris_quick_mode_add_sub_op}, - {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, + { "subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, + { "subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, + { "subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, + { "subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, + { "subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, + { "subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, + { "subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, - {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, + { "subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, - {"svc", + { "svc", 0x0530+CC_VC*0x1000, 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, - {"svs", + { "svs", 0x0530+CC_VS*0x1000, 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, @@ -1089,78 +1089,78 @@ cris_opcodes[] = /* The insn "swapn" is the same as "not" and will be disassembled as such, but the swap* family of mnmonics are generally v8-and-higher only, so count it in. */ - {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, + { "swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, + { "swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, + { "swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, + { "swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, + { "swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, + { "swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, + { "swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, + { "swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, + { "swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, + { "swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, + { "swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, + { "swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, + { "swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, + { "swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, + { "swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, - {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, + { "test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_test_op}, - {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, + { "test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, cris_none_reg_mode_clear_test_op}, - {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, + { "test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_clear_test_op}, - {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, + { "xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, cris_xor_op}, {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} @@ -1194,9 +1194,9 @@ cris_cc_strings[] = const struct cris_cond15 cris_cond15s[] = { /* FIXME: In what version did condition "ext" disappear? */ - {"ext", cris_ver_v0_3}, - {"wf", cris_ver_v10}, - {"sb", cris_ver_v32p}, + { "ext", cris_ver_v0_3}, + { "wf", cris_ver_v10}, + { "sb", cris_ver_v32p}, {NULL, 0} }; diff --git a/libr/asm/arch/hppa/gnu/hppa-dis.c b/libr/asm/arch/hppa/gnu/hppa-dis.c index 73667fc3f4..7423696360 100644 --- a/libr/asm/arch/hppa/gnu/hppa-dis.c +++ b/libr/asm/arch/hppa/gnu/hppa-dis.c @@ -112,11 +112,11 @@ static const char *const wide_add_cond_names[] = static const char *const logical_cond_names[] = { "", ",=", ",<", ",<=", 0, 0, 0, ",od", - ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"}; + ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev" }; static const char *const logical_cond_64_names[] = { ",*", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od", - ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"}; + ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev" }; static const char *const unit_cond_names[] = { "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc", @@ -139,15 +139,15 @@ static const char *const bb_cond_64_names[] = { ",*<", ",*>=" }; -static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"}; -static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"}; +static const char *const index_compl_names[] = { "", ",m", ",s", ",sm" }; +static const char *const short_ldst_compl_names[] = { "", ",ma", "", ",mb" }; static const char *const short_bytes_compl_names[] = { "", ",b,m", ",e", ",e,m" }; -static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; -static const char *const fcnv_fixed_names[] = {",w", ",dw", "", ",qw"}; -static const char *const fcnv_ufixed_names[] = {",uw", ",udw", "", ",uqw"}; +static const char *const float_format_names[] = { ",sgl", ",dbl", "", ",quad" }; +static const char *const fcnv_fixed_names[] = { ",w", ",dw", "", ",qw" }; +static const char *const fcnv_ufixed_names[] = { ",uw", ",udw", "", ",uqw" }; static const char *const float_comp_names[] = { ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>", @@ -155,10 +155,10 @@ static const char *const float_comp_names[] = ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<", ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true" }; -static const char *const signed_unsigned_names[] = {",u", ",s"}; -static const char *const mix_half_names[] = {",l", ",r"}; -static const char *const saturation_names[] = {",us", ",ss", 0, ""}; -static const char *const read_write_names[] = {",r", ",w"}; +static const char *const signed_unsigned_names[] = { ",u", ",s" }; +static const char *const mix_half_names[] = { ",l", ",r" }; +static const char *const saturation_names[] = { ",us", ",ss", 0, "" }; +static const char *const read_write_names[] = { ",r", ",w" }; static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" }; /* For a bunch of different instructions form an index into a diff --git a/libr/asm/arch/m68k/gnu/m68k-dis.c b/libr/asm/arch/m68k/gnu/m68k-dis.c index f3839e6dd9..73e35b872c 100644 --- a/libr/asm/arch/m68k/gnu/m68k-dis.c +++ b/libr/asm/arch/m68k/gnu/m68k-dis.c @@ -718,35 +718,35 @@ print_insn_arg (const char *d, struct regname { char * name; int value; }; static const struct regname names[] = { - {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, - {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, - {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, - {"%rgpiobar", 0x009}, {"%acr4",0x00c}, - {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f}, - {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, - {"%msp", 0x803}, {"%isp", 0x804}, - {"%pc", 0x80f}, + { "%sfc", 0x000}, { "%dfc", 0x001}, { "%cacr", 0x002}, + { "%tc", 0x003}, { "%itt0",0x004}, { "%itt1", 0x005}, + { "%dtt0",0x006}, { "%dtt1",0x007}, { "%buscr",0x008}, + { "%rgpiobar", 0x009}, { "%acr4",0x00c}, + { "%acr5",0x00d}, { "%acr6",0x00e}, { "%acr7", 0x00f}, + { "%usp", 0x800}, { "%vbr", 0x801}, { "%caar", 0x802}, + { "%msp", 0x803}, { "%isp", 0x804}, + { "%pc", 0x80f}, /* Reg c04 is sometimes called flashbar or rambar. Reg c05 is also sometimes called rambar. */ - {"%rambar0", 0xc04}, {"%rambar1", 0xc05}, + { "%rambar0", 0xc04}, { "%rambar1", 0xc05}, /* reg c0e is sometimes called mbar2 or secmbar. reg c0f is sometimes called mbar. */ - {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f}, + { "%mbar0", 0xc0e}, { "%mbar1", 0xc0f}, /* Should we be calling this psr like we do in case 'Y'? */ - {"%mmusr",0x805}, + { "%mmusr",0x805}, - {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}, + { "%urp", 0x806}, { "%srp", 0x807}, { "%pcr", 0x808}, /* Fido added these. */ - {"%cac", 0xffe}, {"%mbo", 0xfff} + { "%cac", 0xffe}, { "%mbo", 0xfff} }; /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */ static const struct regname names_v4e[] = { - {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005}, - {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008}, + { "%asid",0x003}, { "%acr0",0x004}, { "%acr1",0x005}, + { "%acr2",0x006}, { "%acr3",0x007}, { "%mmubar",0x008}, }; unsigned int arch_mask; diff --git a/libr/asm/arch/m68k/gnu/m68k-opc.c b/libr/asm/arch/m68k/gnu/m68k-opc.c index f9af1cf0a5..0e295e1247 100644 --- a/libr/asm/arch/m68k/gnu/m68k-opc.c +++ b/libr/asm/arch/m68k/gnu/m68k-opc.c @@ -34,1506 +34,1506 @@ const struct m68k_opcode m68k_opcodes[] = { -{"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, -{"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, +{ "abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, +{ "abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, -{"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, -{"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, +{ "addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, -{"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, -{"addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, -{"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, +{ "addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, +{ "addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, +{ "addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, +{ "addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, -{"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, -{"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, -{"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, +{ "addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, +{ "addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, +{ "addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, /* The add opcode can generate the adda, addi, and addq instructions. */ -{"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, -{"addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, -{"addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, -{"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, -{"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, -{"addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, -{"addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, -{"addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, -{"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, -{"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, -{"addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, -{"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, -{"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, -{"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, +{ "addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, +{ "addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, +{ "addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, +{ "addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, +{ "addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, +{ "addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, +{ "addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, +{ "addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, +{ "addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, +{ "addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, +{ "addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, +{ "addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, +{ "addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{ "addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, -{"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, -{"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, -{"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, -{"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, -{"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, -{"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, +{ "addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, +{ "addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, +{ "addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, +{ "addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, +{ "addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, +{ "addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, -{"andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, -{"andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, -{"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, -{"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, -{"andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, -{"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, -{"andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, -{"andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, -{"andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{ "andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, +{ "andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{ "andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{ "andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{ "andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, +{ "andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, +{ "andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{ "andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{ "andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, /* The and opcode can generate the andi instruction. */ -{"andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, -{"andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, -{"andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, -{"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, -{"andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, -{"andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, -{"andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, -{"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, -{"andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, -{"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, -{"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, -{"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, -{"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, -{"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, -{"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, -{"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, -{"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, +{ "andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, +{ "andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{ "andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, +{ "andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, +{ "andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{ "andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{ "andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, +{ "andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, +{ "andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, +{ "andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, +{ "andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, +{ "andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, +{ "and", 4, one(0001100), one(0177700), "#w$w", m68000up }, +{ "and", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{ "and", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{ "and", 2, one(0140100), one(0170700), ";wDd", m68000up }, +{ "and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, -{"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, -{"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, -{"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, -{"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, -{"aslw", 2, one(0160700), one(0177700), "~s", m68000up }, -{"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, -{"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, +{ "aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, +{ "aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, +{ "aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, +{ "aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, +{ "aslw", 2, one(0160700), one(0177700), "~s", m68000up }, +{ "asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, +{ "asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, -{"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, -{"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, -{"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, -{"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, -{"asrw", 2, one(0160300), one(0177700), "~s", m68000up }, -{"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, -{"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, +{ "asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, +{ "asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, +{ "asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, +{ "asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, +{ "asrw", 2, one(0160300), one(0177700), "~s", m68000up }, +{ "asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, +{ "asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, -{"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, -{"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, -{"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, -{"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, -{"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, -{"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, -{"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, -{"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, -{"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, -{"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, -{"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, -{"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, -{"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, -{"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, +{ "jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, -{"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, -{"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, -{"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, +{ "bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{ "bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, +{ "bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, -{"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, -{"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, -{"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, +{ "bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{ "bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, +{ "bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, -{"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, -{"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, +{ "bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{ "bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{ "bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{ "bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{ "bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{ "bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, +{ "bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{ "bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, -{"bgnd", 2, one(0045372), one(0177777), "", cpu32 | fido_a }, +{ "bgnd", 2, one(0045372), one(0177777), "", cpu32 | fido_a }, -{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, +{ "bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, -{"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, +{ "bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, -{"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, -{"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, -{"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, +{ "braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, +{ "bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, -{"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, -{"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, -{"bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, -{"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, +{ "bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{ "bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, +{ "bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, +{ "bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, -{"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, -{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, -{"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, +{ "bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, +{ "bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{ "bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, -{"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, -{"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, -{"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, +{ "btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, +{ "btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, +{ "btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, -{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, +{ "byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, -{"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, +{ "callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, -{"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, -{"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, -{"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, -{"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, +{ "cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{ "cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, +{ "cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{ "cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, -{"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, -{"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, -{"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{ "casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{ "casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{ "casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, -{"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"chkl", 2, one(0040400), one(0170700), ";lDd", m68020up }, -{"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, +{ "chkl", 2, one(0040400), one(0170700), ";lDd", m68020up }, +{ "chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, #define SCOPE_LINE (0x1 << 3) #define SCOPE_PAGE (0x2 << 3) #define SCOPE_ALL (0x3 << 3) -{"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, -{"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, -{"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, +{ "cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{ "cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, +{ "cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, -{"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, -{"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, -{"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, +{ "cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{ "cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, +{ "cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, #undef SCOPE_LINE #undef SCOPE_PAGE #undef SCOPE_ALL -{"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, -{"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, -{"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, +{ "clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, +{ "clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, +{ "clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, -{"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{ "cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, -{"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, +{ "cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"cmpib", 4, one(0006000), one(0177700), "#b$s", m68000 | m68010 }, -{"cmpib", 4, one(0006000), one(0177700), "#b@s", m68020up | cpu32 | fido_a }, -{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, -{"cmpiw", 4, one(0006100), one(0177700), "#w$s", m68000 | m68010 }, -{"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68020up | cpu32 | fido_a }, -{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, -{"cmpil", 6, one(0006200), one(0177700), "#l$s", m68000 | m68010 }, -{"cmpil", 6, one(0006200), one(0177700), "#l@s", m68020up | cpu32 | fido_a }, -{"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, +{ "cmpib", 4, one(0006000), one(0177700), "#b$s", m68000 | m68010 }, +{ "cmpib", 4, one(0006000), one(0177700), "#b@s", m68020up | cpu32 | fido_a }, +{ "cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, +{ "cmpiw", 4, one(0006100), one(0177700), "#w$s", m68000 | m68010 }, +{ "cmpiw", 4, one(0006100), one(0177700), "#w@s", m68020up | cpu32 | fido_a }, +{ "cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, +{ "cmpil", 6, one(0006200), one(0177700), "#l$s", m68000 | m68010 }, +{ "cmpil", 6, one(0006200), one(0177700), "#l@s", m68020up | cpu32 | fido_a }, +{ "cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, -{"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, +{ "cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, +{ "cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, +{ "cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ -{"cmpb", 4, one(0006000), one(0177700), "#b$s", m68000 | m68010 }, -{"cmpb", 4, one(0006000), one(0177700), "#b@s", m68020up | cpu32 | fido_a }, -{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, -{"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, -{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, -{"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpw", 4, one(0006100), one(0177700), "#w$s", m68000 | m68010 }, -{"cmpw", 4, one(0006100), one(0177700), "#w@s", m68020up | cpu32 | fido_a }, -{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, -{"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b | mcfisa_c }, -{"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"cmpl", 6, one(0006200), one(0177700), "#l$s", m68000 | m68010 }, -{"cmpl", 6, one(0006200), one(0177700), "#l@s", m68020up | cpu32 | fido_a }, -{"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, -{"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, -{"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{ "cmpb", 4, one(0006000), one(0177700), "#b$s", m68000 | m68010 }, +{ "cmpb", 4, one(0006000), one(0177700), "#b@s", m68020up | cpu32 | fido_a }, +{ "cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, +{ "cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, +{ "cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, +{ "cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, +{ "cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, +{ "cmpw", 4, one(0006100), one(0177700), "#w$s", m68000 | m68010 }, +{ "cmpw", 4, one(0006100), one(0177700), "#w@s", m68020up | cpu32 | fido_a }, +{ "cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, +{ "cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, +{ "cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b | mcfisa_c }, +{ "cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "cmpl", 6, one(0006200), one(0177700), "#l$s", m68000 | m68010 }, +{ "cmpl", 6, one(0006200), one(0177700), "#l@s", m68020up | cpu32 | fido_a }, +{ "cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, +{ "cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, +{ "cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, -{"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a}, -{"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a}, -{"cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a}, -{"cp1nop", 4, two (0177000,0), two (01777477,0170777), "jE", mcfisa_a}, +{ "cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a}, +{ "cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a}, +{ "cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a}, +{ "cp1nop", 4, two (0177000,0), two (01777477,0170777), "jE", mcfisa_a}, /* These all have 2 opcode words, but no fixed bits in the second word. We use a leading ' ' in the args string to indicate the extra opcode word. */ -{"cp0ldb", 6, one (0176000), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp1ldb", 6, one (0177000), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp0ldw", 6, one (0176100), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp1ldw", 6, one (0177100), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp0ldl", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp1ldl", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp0ld", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp1ld", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, -{"cp0stb", 6, one (0176400), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp1stb", 6, one (0177400), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp0stw", 6, one (0176500), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp1stw", 6, one (0177500), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp0stl", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp0ldb", 6, one (0176000), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp1ldb", 6, one (0177000), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp0ldw", 6, one (0176100), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp1ldw", 6, one (0177100), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp0ldl", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp1ldl", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp0ld", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp1ld", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{ "cp0stb", 6, one (0176400), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp1stb", 6, one (0177400), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp0stw", 6, one (0176500), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp1stw", 6, one (0177500), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp0stl", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{ "cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, -{"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, -{"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, -{"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, -{"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, -{"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, -{"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, -{"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, -{"dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, -{"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, -{"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, -{"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, -{"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, -{"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, -{"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, -{"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, -{"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, +{ "dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, +{ "dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, +{ "dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, +{ "dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, +{ "dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, +{ "dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, +{ "dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, +{ "dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, +{ "dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, +{ "dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, +{ "dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, +{ "dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, +{ "dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, +{ "dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, +{ "dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, +{ "dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, -{"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, +{ "divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, -{"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, -{"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, -{"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, +{ "divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, +{ "divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{ "divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, -{"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, -{"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{ "divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, +{ "divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, -{"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, +{ "divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, -{"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, -{"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, -{"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, +{ "divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, +{ "divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{ "divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, -{"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, -{"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{ "divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, +{ "divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, -{"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, -{"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, -{"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, -{"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, -{"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, -{"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, -{"eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, -{"eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, -{"eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{ "eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, +{ "eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{ "eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{ "eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{ "eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, +{ "eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, +{ "eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{ "eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{ "eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, /* The eor opcode can generate the eori instruction. */ -{"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, -{"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, -{"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, -{"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, -{"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, -{"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, -{"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, -{"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, -{"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, -{"eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, -{"eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, -{"eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, -{"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, +{ "eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, +{ "eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{ "eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, +{ "eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{ "eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{ "eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, +{ "eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, +{ "eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, +{ "eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{ "eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{ "eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{ "eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{ "eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, -{"exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, -{"exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, -{"exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, -{"exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, +{ "exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, +{ "exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, +{ "exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, +{ "exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, -{"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, -{"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, -{"extbl", 2, one(0044700), one(0177770), "Ds", m68020up | cpu32 | fido_a | mcfisa_a }, +{ "extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, +{ "extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, +{ "extbl", 2, one(0044700), one(0177770), "Ds", m68020up | cpu32 | fido_a | mcfisa_a }, -{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, +{ "ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, /* float stuff starts here */ -{"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, -{"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, +{ "fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, -{"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, -{"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, -{"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, -{"fdabss", 4, two(0xF000, 0x445C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, -{"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, -{"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, -{"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, -{"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, +{ "fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, +{ "fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, +{ "fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, +{ "fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, +{ "fdabss", 4, two(0xF000, 0x445C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, +{ "fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, +{ "fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, +{ "fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, +{ "fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, -{"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsaddd", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsaddd", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, /* This is the same as `fbf .+2'. */ -{"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat }, +{ "fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat }, -{"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, +{ "fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, -{"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, +{ "fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, -{"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, +{ "fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, -{"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{ "fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, -{"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, -{"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, -{"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, -{"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, +{ "fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, +{ "fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, +{ "fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, +{ "fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, +{ "fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, /* FIXME: the next two variants should not permit moving an address register to anything but the floating point instruction register. */ -{"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, -{"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, +{ "fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{ "fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, +{ "fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, /* Move the FP control registers. */ -{"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, -{"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, -{"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, -{"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, -{"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, -{"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, -{"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, -{"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, +{ "fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, +{ "fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, +{ "fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, +{ "fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, +{ "fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, +{ "fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, +{ "fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, +{ "fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, -{"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, -{"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, +{ "fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, -{"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{ "fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, +{ "fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, -{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, -{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, -{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, -{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, +{ "fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, +{ "fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, +{ "fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, +{ "fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, -{"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, -{"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, -{"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, -{"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, -{"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, -{"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, -{"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, -{"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, -{"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, -{"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, -{"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, -{"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{ "fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{ "fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{ "fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{ "fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{ "fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{ "fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{ "fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, -{"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +{ "fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{ "fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, /* FIXME: In the next instruction, we should only permit %dn if the target is a single register. We should only permit %an if the target is a single %fpiar. */ -{"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, +{ "fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, -{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, -{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, -{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, -{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, +{ "fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, +{ "fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, +{ "fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, +{ "fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, -{"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, -{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, -{"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, -{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, -{"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, -{"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, -{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, -{"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, -{"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, -{"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, -{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, -{"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, -{"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, -{"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, -{"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, +{ "fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{ "fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{ "fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{ "fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{ "fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{ "fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{ "fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{ "fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{ "fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, +{ "fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{ "fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{ "fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{ "fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{ "fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, +{ "fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +{ "fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, -{"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"frestore", 2, one(0xF140), one(0xF1C0), "Ids", mfloat }, -{"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat }, +{ "fsave", 2, one(0xF100), one(0xF1C0), "Id>s", mfloat }, +{ "fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat }, -{"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, /* $ is necessary to prevent the assembler from using PC-relative. If @ were used, "label: fseq label" could produce "ftrapeq", 2, because "label" became "pc@label". */ -{"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{ "fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, -{"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, -{"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, -{"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, -{"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, -{"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, -{"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, -{"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, +{ "fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, +{ "fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, +{ "fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, +{ "fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, +{ "fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, +{ "fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, +{ "fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, +{ "fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, -{"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat }, -{"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{ "fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdsubd", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, -{"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, -{"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, -{"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, +{ "fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{ "fdsubd", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{ "fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{ "fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{ "fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{ "fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{ "fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{ "fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{ "fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{ "fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{ "fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{ "fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, -{"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{ "ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{ "ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{ "ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, -{"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, -{"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat }, -{"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, -{"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, -{"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, -{"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, -{"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, -{"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, -{"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, -{"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, -{"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, -{"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, -{"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, +{ "ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, +{ "ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{ "ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat }, +{ "ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, +{ "ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{ "ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, +{ "ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{ "ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, +{ "ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, +{ "ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{ "ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, +{ "ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{ "ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, +{ "ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, -{"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, +{ "ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{ "ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{ "ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{ "ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{ "ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{ "ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{ "ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{ "ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{ "ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, -{"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, +{ "halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, -{"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, -{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b | mcfisa_c }, +{ "illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, +{ "intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b | mcfisa_c }, -{"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, +{ "jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, -{"jra", 2, one(0060000), one(0177400), "Bb", m68000up | mcfisa_a }, -{"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, +{ "jra", 2, one(0060000), one(0177400), "Bb", m68000up | mcfisa_a }, +{ "jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, -{"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, +{ "jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, -{"jbsr", 2, one(0060400), one(0177400), "Bs", m68000up | mcfisa_a }, -{"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, +{ "jbsr", 2, one(0060400), one(0177400), "Bs", m68000up | mcfisa_a }, +{ "jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, -{"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, +{ "lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, -{"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32 | fido_a | m68060 }, +{ "lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32 | fido_a | m68060 }, -{"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, -{"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, -{"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, -{"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, +{ "linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, +{ "linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, +{ "link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, +{ "link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, -{"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up }, -{"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up }, -{"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up }, -{"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up }, -{"lslw", 2, one(0161700), one(0177700), "~s", m68000up }, -{"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, -{"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, +{ "lslb", 2, one(0160410), one(0170770), "QdDs", m68000up }, +{ "lslb", 2, one(0160450), one(0170770), "DdDs", m68000up }, +{ "lslw", 2, one(0160510), one(0170770), "QdDs", m68000up }, +{ "lslw", 2, one(0160550), one(0170770), "DdDs", m68000up }, +{ "lslw", 2, one(0161700), one(0177700), "~s", m68000up }, +{ "lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, +{ "lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, -{"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up }, -{"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up }, -{"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up }, -{"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up }, -{"lsrw", 2, one(0161300), one(0177700), "~s", m68000up }, -{"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, -{"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, +{ "lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up }, +{ "lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up }, +{ "lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up }, +{ "lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up }, +{ "lsrw", 2, one(0161300), one(0177700), "~s", m68000up }, +{ "lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, +{ "lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, -{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, -{"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, -{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, -{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, -{"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, -{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac }, +{ "macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, +{ "macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, +{ "macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, +{ "macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, +{ "macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, +{ "macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac }, -{"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,,accX. */ -{"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ -{"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ -{"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ -{"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ -{"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ +{ "macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,,accX. */ +{ "macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ +{ "macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ +{ "macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ +{ "macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ +{ "macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ -{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfemac }, -{"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfemac }, -{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfemac }, -{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0910), "uMumiI", mcfemac }, -{"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0910), "uMumMh", mcfemac }, -{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f10), "uMum", mcfemac }, +{ "macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfemac }, +{ "macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfemac }, +{ "macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfemac }, +{ "macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0910), "uMumiI", mcfemac }, +{ "macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0910), "uMumMh", mcfemac }, +{ "macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f10), "uMum", mcfemac }, -{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, -{"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, -{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, -{"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0900), "RMRm", mcfmac }, +{ "macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, +{ "macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, +{ "macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, +{ "macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0900), "RMRm", mcfmac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, -{"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, -{"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, +{ "macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, +{ "macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, -{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfemac }, -{"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfemac }, -{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfemac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b10), "RMRmiI", mcfemac }, -{"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b10), "RMRmMh", mcfemac }, -{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0910), "RMRm", mcfemac }, +{ "macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfemac }, +{ "macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfemac }, +{ "macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b10), "RMRmiI", mcfemac }, +{ "macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b10), "RMRmMh", mcfemac }, +{ "macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0910), "RMRm", mcfemac }, /* NOTE: The mcf5200 family programmer's reference manual does not indicate the byte form of the movea instruction is invalid (as it @@ -1551,630 +1551,630 @@ const struct m68k_opcode m68k_opcodes[] = jtc@cygnus.com - 97/01/24. */ -{"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, +{ "moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, -{"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, +{ "movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, -{"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, -{"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, -{"movec", 4, one(0047172), one(0177777), "JjR1", m68010up }, -{"movec", 4, one(0047172), one(0177777), "#jR1", m68010up }, +{ "movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, +{ "movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, +{ "movec", 4, one(0047172), one(0177777), "JjR1", m68010up }, +{ "movec", 4, one(0047172), one(0177777), "#jR1", m68010up }, -{"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up }, -{"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up }, -{"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up }, -{"movemw", 4, one(0046200), one(0177700), "s", m68000up }, -{"moveml", 4, one(0046300), one(0177700), "s", m68000up }, +{ "movemw", 4, one(0046200), one(0177700), "s", m68000up }, +{ "moveml", 4, one(0046300), one(0177700), ",accX. */ -{"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ -{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ -{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ -{"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ -{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ +{ "msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,,accX. */ +{ "msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ +{ "msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ +{ "msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ +{ "msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ +{ "msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ -{"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, -{"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, -{"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, -{"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0900), "RMRm", mcfmac }, +{ "msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, +{ "msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, +{ "msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, +{ "msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0900), "RMRm", mcfmac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, -{"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, -{"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, -{"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, +{ "msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, -{"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a }, -{"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, -{"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a }, -{"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, +{ "mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a }, +{ "mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, +{ "mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a }, +{ "mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, -{"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a }, -{"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, -{"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a }, -{"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, +{ "muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a }, +{ "mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, +{ "mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a }, +{ "mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, -{"nbcd", 2, one(0044000), one(0177700), "$s", m68000up }, +{ "nbcd", 2, one(0044000), one(0177700), "$s", m68000up }, -{"negb", 2, one(0042000), one(0177700), "$s", m68000up }, -{"negw", 2, one(0042100), one(0177700), "$s", m68000up }, -{"negl", 2, one(0042200), one(0177700), "$s", m68000up }, -{"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a}, +{ "negb", 2, one(0042000), one(0177700), "$s", m68000up }, +{ "negw", 2, one(0042100), one(0177700), "$s", m68000up }, +{ "negl", 2, one(0042200), one(0177700), "$s", m68000up }, +{ "negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a}, -{"negxb", 2, one(0040000), one(0177700), "$s", m68000up }, -{"negxw", 2, one(0040100), one(0177700), "$s", m68000up }, -{"negxl", 2, one(0040200), one(0177700), "$s", m68000up }, -{"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a}, +{ "negxb", 2, one(0040000), one(0177700), "$s", m68000up }, +{ "negxw", 2, one(0040100), one(0177700), "$s", m68000up }, +{ "negxl", 2, one(0040200), one(0177700), "$s", m68000up }, +{ "negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a}, -{"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a}, +{ "nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a}, -{"notb", 2, one(0043000), one(0177700), "$s", m68000up }, -{"notw", 2, one(0043100), one(0177700), "$s", m68000up }, -{"notl", 2, one(0043200), one(0177700), "$s", m68000up }, -{"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a}, +{ "notb", 2, one(0043000), one(0177700), "$s", m68000up }, +{ "notw", 2, one(0043100), one(0177700), "$s", m68000up }, +{ "notl", 2, one(0043200), one(0177700), "$s", m68000up }, +{ "notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a}, -{"orib", 4, one(0000000), one(0177700), "#b$s", m68000up }, -{"orib", 4, one(0000074), one(0177777), "#bCs", m68000up }, -{"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up }, -{"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up }, -{"oril", 6, one(0000200), one(0177700), "#l$s", m68000up }, -{"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, -{"ori", 4, one(0000074), one(0177777), "#bCs", m68000up }, -{"ori", 4, one(0000100), one(0177700), "#w$s", m68000up }, -{"ori", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{ "orib", 4, one(0000000), one(0177700), "#b$s", m68000up }, +{ "orib", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{ "oriw", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{ "oriw", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{ "oril", 6, one(0000200), one(0177700), "#l$s", m68000up }, +{ "oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, +{ "ori", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{ "ori", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{ "ori", 4, one(0000174), one(0177777), "#wSs", m68000up }, /* The or opcode can generate the ori instruction. */ -{"orb", 4, one(0000000), one(0177700), "#b$s", m68000up }, -{"orb", 4, one(0000074), one(0177777), "#bCs", m68000up }, -{"orb", 2, one(0100000), one(0170700), ";bDd", m68000up }, -{"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up }, -{"orw", 4, one(0000100), one(0177700), "#w$s", m68000up }, -{"orw", 4, one(0000174), one(0177777), "#wSs", m68000up }, -{"orw", 2, one(0100100), one(0170700), ";wDd", m68000up }, -{"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up }, -{"orl", 6, one(0000200), one(0177700), "#l$s", m68000up }, -{"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, -{"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a }, -{"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a }, -{"or", 4, one(0000074), one(0177777), "#bCs", m68000up }, -{"or", 4, one(0000100), one(0177700), "#w$s", m68000up }, -{"or", 4, one(0000174), one(0177777), "#wSs", m68000up }, -{"or", 2, one(0100100), one(0170700), ";wDd", m68000up }, -{"or", 2, one(0100500), one(0170700), "Dd~s", m68000up }, +{ "orb", 4, one(0000000), one(0177700), "#b$s", m68000up }, +{ "orb", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{ "orb", 2, one(0100000), one(0170700), ";bDd", m68000up }, +{ "orb", 2, one(0100400), one(0170700), "Dd~s", m68000up }, +{ "orw", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{ "orw", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{ "orw", 2, one(0100100), one(0170700), ";wDd", m68000up }, +{ "orw", 2, one(0100500), one(0170700), "Dd~s", m68000up }, +{ "orl", 6, one(0000200), one(0177700), "#l$s", m68000up }, +{ "orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, +{ "orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a }, +{ "orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a }, +{ "or", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{ "or", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{ "or", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{ "or", 2, one(0100100), one(0170700), ";wDd", m68000up }, +{ "or", 2, one(0100500), one(0170700), "Dd~s", m68000up }, -{"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up }, -{"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up }, +{ "pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up }, +{ "pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up }, -{"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 }, -{"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 }, -{"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 }, -{"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 }, -{"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 }, -{"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 }, -{"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 }, -{"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 }, -{"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 }, -{"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 }, -{"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 }, -{"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 }, -{"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 }, -{"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 }, -{"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 }, -{"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 }, -{"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 }, -{"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 }, -{"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 }, -{"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 }, -{"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 }, -{"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 }, -{"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 }, -{"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 }, -{"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 }, -{"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 }, -{"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 }, -{"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 }, -{"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 }, -{"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 }, -{"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 }, -{"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 }, +{ "pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 }, +{ "pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 }, +{ "pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 }, +{ "pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 }, +{ "pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 }, +{ "pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 }, +{ "pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 }, +{ "pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 }, +{ "pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 }, +{ "pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 }, +{ "pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 }, +{ "pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 }, +{ "pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 }, +{ "pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 }, +{ "pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 }, +{ "pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 }, +{ "pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 }, +{ "pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 }, +{ "pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 }, +{ "pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 }, +{ "pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 }, +{ "pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 }, +{ "pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 }, +{ "pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 }, +{ "pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 }, +{ "pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 }, +{ "pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 }, +{ "pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 }, +{ "pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 }, +{ "pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 }, +{ "pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 }, +{ "pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 }, -{"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, +{ "pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a }, +{ "pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a }, -{"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up }, -{"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, +{ "pflusha", 2, one(0xf518), one(0xfff8), "", m68040up }, +{ "pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, -{"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, -{"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, -{"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, -{"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, -{"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, -{"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, -{"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up }, -{"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up }, +{ "pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, +{ "pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, +{ "pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, +{ "pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, +{ "pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, +{ "pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, +{ "pflush", 2, one(0xf508), one(0xfff8), "as", m68040up }, +{ "pflush", 2, one(0xf508), one(0xfff8), "As", m68040up }, -{"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up }, -{"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up }, -{"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up }, +{ "pflushan", 2, one(0xf510), one(0xfff8), "", m68040up }, +{ "pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up }, +{ "pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up }, -{"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, +{ "pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, -{"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, -{"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, -{"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, -{"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, -{"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, -{"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, +{ "pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, -{"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, -{"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, -{"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, -{"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, -{"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, -{"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, +{ "ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{ "ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{ "ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, +{ "ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{ "ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{ "ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, -{"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 }, -{"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 }, +{ "plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 }, +{ "plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 }, -{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, -{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, -{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, -{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, -{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, -{"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, -{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "*wX3", m68851 }, -{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "X3%s", m68851 }, -{"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, -{"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, +{ "pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, +{ "pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, +{ "pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, +{ "pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, +{ "pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, +{ "pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, +{ "pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "*wX3", m68851 }, +{ "pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "X3%s", m68851 }, +{ "pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, +{ "pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, -{"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, -{"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, -{"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, +{ "pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, +{ "pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, +{ "pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, -{"prestore", 2, one(0xf140), one(0xffc0), "s", m68851 }, +{ "psave", 2, one(0xf100), one(0xffc0), ">s", m68851 }, -{"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, -{"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, -{"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, -{"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, -{"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, -{"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, -{"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, -{"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, -{"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, -{"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, -{"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, -{"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, -{"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, -{"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, -{"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, -{"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, +{ "pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, +{ "pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, +{ "pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, +{ "pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, +{ "pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, +{ "psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, -{"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, -{"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, -{"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, -{"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, -{"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, -{"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, -{"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 }, +{ "ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, +{ "ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{ "ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{ "ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{ "ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{ "ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{ "ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 }, -{"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, -{"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, -{"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, -{"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, -{"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, -{"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, -{"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 }, +{ "ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, +{ "ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{ "ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{ "ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{ "ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{ "ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{ "ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 }, -{"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, -{"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, -{"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, -{"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, -{"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, -{"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, -{"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, -{"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, -{"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, -{"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, -{"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, -{"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, -{"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, +{ "ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, -{"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, -{"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, +{ "ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, -{"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, -{"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, -{"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, -{"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, +{ "ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, +{ "ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, +{ "ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, -{"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a }, +{ "pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a }, -{"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, -{"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, +{ "pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, +{ "pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, /* FIXME: don't allow Dw==Dx. */ -{"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, -{"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, +{ "remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, +{ "remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, -{"reset", 2, one(0047160), one(0177777), "", m68000up }, +{ "reset", 2, one(0047160), one(0177777), "", m68000up }, -{"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up }, -{"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up }, -{"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up }, -{"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up }, -{"rolw", 2, one(0163700), one(0177700), "~s", m68000up }, -{"roll", 2, one(0160630), one(0170770), "QdDs", m68000up }, -{"roll", 2, one(0160670), one(0170770), "DdDs", m68000up }, +{ "rolb", 2, one(0160430), one(0170770), "QdDs", m68000up }, +{ "rolb", 2, one(0160470), one(0170770), "DdDs", m68000up }, +{ "rolw", 2, one(0160530), one(0170770), "QdDs", m68000up }, +{ "rolw", 2, one(0160570), one(0170770), "DdDs", m68000up }, +{ "rolw", 2, one(0163700), one(0177700), "~s", m68000up }, +{ "roll", 2, one(0160630), one(0170770), "QdDs", m68000up }, +{ "roll", 2, one(0160670), one(0170770), "DdDs", m68000up }, -{"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up }, -{"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up }, -{"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up }, -{"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up }, -{"rorw", 2, one(0163300), one(0177700), "~s", m68000up }, -{"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up }, -{"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up }, +{ "rorb", 2, one(0160030), one(0170770), "QdDs", m68000up }, +{ "rorb", 2, one(0160070), one(0170770), "DdDs", m68000up }, +{ "rorw", 2, one(0160130), one(0170770), "QdDs", m68000up }, +{ "rorw", 2, one(0160170), one(0170770), "DdDs", m68000up }, +{ "rorw", 2, one(0163300), one(0177700), "~s", m68000up }, +{ "rorl", 2, one(0160230), one(0170770), "QdDs", m68000up }, +{ "rorl", 2, one(0160270), one(0170770), "DdDs", m68000up }, -{"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up }, -{"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up }, -{"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up }, -{"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up }, -{"roxlw", 2, one(0162700), one(0177700), "~s", m68000up }, -{"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up }, -{"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up }, +{ "roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up }, +{ "roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up }, +{ "roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up }, +{ "roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up }, +{ "roxlw", 2, one(0162700), one(0177700), "~s", m68000up }, +{ "roxll", 2, one(0160620), one(0170770), "QdDs", m68000up }, +{ "roxll", 2, one(0160660), one(0170770), "DdDs", m68000up }, -{"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up }, -{"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up }, -{"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up }, -{"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up }, -{"roxrw", 2, one(0162300), one(0177700), "~s", m68000up }, -{"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up }, -{"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up }, +{ "roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up }, +{ "roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up }, +{ "roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up }, +{ "roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up }, +{ "roxrw", 2, one(0162300), one(0177700), "~s", m68000up }, +{ "roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up }, +{ "roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up }, -{"rtd", 4, one(0047164), one(0177777), "#w", m68010up }, +{ "rtd", 4, one(0047164), one(0177777), "#w", m68010up }, -{"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a }, +{ "rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a }, -{"rtm", 2, one(0003300), one(0177760), "Rs", m68020 }, +{ "rtm", 2, one(0003300), one(0177760), "Rs", m68020 }, -{"rtr", 2, one(0047167), one(0177777), "", m68000up }, +{ "rtr", 2, one(0047167), one(0177777), "", m68000up }, -{"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, +{ "rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, -{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c }, +{ "satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c }, -{"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, -{"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, +{ "sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, +{ "sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, -{"stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c }, +{ "stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c }, /* Traps have to come before conditional sets, as they have a more specific opcode. */ -{"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"tpf", 2, one(0050774), one(0177777), "", mcfisa_a }, -{"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | fido_a | mcfisa_a }, -{"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "tpf", 2, one(0050774), one(0177777), "", mcfisa_a }, +{ "trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | fido_a | mcfisa_a }, +{ "trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 | fido_a }, +{ "trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 | fido_a }, -{"trapccw", 4, one(0052372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"tpfw", 4, one(0050772), one(0177777), "#w", mcfisa_a}, -{"trapfw", 4, one(0050772), one(0177777), "#w", m68020up | cpu32 | fido_a | mcfisa_a}, -{"trapgew", 4, one(0056372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"traphiw", 4, one(0051372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"traplew", 4, one(0057772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"traplsw", 4, one(0051772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapltw", 4, one(0056772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapnew", 4, one(0053372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapplw", 4, one(0055372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"traptw", 4, one(0050372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapccw", 4, one(0052372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapcsw", 4, one(0052772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapeqw", 4, one(0053772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "tpfw", 4, one(0050772), one(0177777), "#w", mcfisa_a}, +{ "trapfw", 4, one(0050772), one(0177777), "#w", m68020up | cpu32 | fido_a | mcfisa_a}, +{ "trapgew", 4, one(0056372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapgtw", 4, one(0057372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "traphiw", 4, one(0051372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "traplew", 4, one(0057772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "traplsw", 4, one(0051772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapltw", 4, one(0056772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapmiw", 4, one(0055772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapnew", 4, one(0053372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapplw", 4, one(0055372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "traptw", 4, one(0050372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapvcw", 4, one(0054372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{ "trapvsw", 4, one(0054772), one(0177777), "#w", m68020up | cpu32 | fido_a }, -{"trapccl", 6, one(0052373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapeql", 6, one(0053773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"tpfl", 6, one(0050773), one(0177777), "#l", mcfisa_a}, -{"trapfl", 6, one(0050773), one(0177777), "#l", m68020up | cpu32 | fido_a | mcfisa_a}, -{"trapgel", 6, one(0056373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"traphil", 6, one(0051373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"traplel", 6, one(0057773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"traplsl", 6, one(0051773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapltl", 6, one(0056773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapmil", 6, one(0055773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapnel", 6, one(0053373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trappll", 6, one(0055373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"traptl", 6, one(0050373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapccl", 6, one(0052373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapcsl", 6, one(0052773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapeql", 6, one(0053773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "tpfl", 6, one(0050773), one(0177777), "#l", mcfisa_a}, +{ "trapfl", 6, one(0050773), one(0177777), "#l", m68020up | cpu32 | fido_a | mcfisa_a}, +{ "trapgel", 6, one(0056373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapgtl", 6, one(0057373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "traphil", 6, one(0051373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "traplel", 6, one(0057773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "traplsl", 6, one(0051773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapltl", 6, one(0056773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapmil", 6, one(0055773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapnel", 6, one(0053373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trappll", 6, one(0055373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "traptl", 6, one(0050373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapvcl", 6, one(0054373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{ "trapvsl", 6, one(0054773), one(0177777), "#l", m68020up | cpu32 | fido_a }, -{"trapv", 2, one(0047166), one(0177777), "", m68000up }, +{ "trapv", 2, one(0047166), one(0177777), "", m68000up }, -{"scc", 2, one(0052300), one(0177700), "$s", m68000up }, -{"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a }, -{"scs", 2, one(0052700), one(0177700), "$s", m68000up }, -{"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a }, -{"seq", 2, one(0053700), one(0177700), "$s", m68000up }, -{"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a }, -{"sf", 2, one(0050700), one(0177700), "$s", m68000up }, -{"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a }, -{"sge", 2, one(0056300), one(0177700), "$s", m68000up }, -{"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a }, -{"sgt", 2, one(0057300), one(0177700), "$s", m68000up }, -{"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a }, -{"shi", 2, one(0051300), one(0177700), "$s", m68000up }, -{"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a }, -{"sle", 2, one(0057700), one(0177700), "$s", m68000up }, -{"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a }, -{"sls", 2, one(0051700), one(0177700), "$s", m68000up }, -{"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a }, -{"slt", 2, one(0056700), one(0177700), "$s", m68000up }, -{"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a }, -{"smi", 2, one(0055700), one(0177700), "$s", m68000up }, -{"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a }, -{"sne", 2, one(0053300), one(0177700), "$s", m68000up }, -{"sne", 2, one(0053300), one(0177770), "Ds", mcfisa_a }, -{"spl", 2, one(0055300), one(0177700), "$s", m68000up }, -{"spl", 2, one(0055300), one(0177770), "Ds", mcfisa_a }, -{"st", 2, one(0050300), one(0177700), "$s", m68000up }, -{"st", 2, one(0050300), one(0177770), "Ds", mcfisa_a }, -{"svc", 2, one(0054300), one(0177700), "$s", m68000up }, -{"svc", 2, one(0054300), one(0177770), "Ds", mcfisa_a }, -{"svs", 2, one(0054700), one(0177700), "$s", m68000up }, -{"svs", 2, one(0054700), one(0177770), "Ds", mcfisa_a }, +{ "scc", 2, one(0052300), one(0177700), "$s", m68000up }, +{ "scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a }, +{ "scs", 2, one(0052700), one(0177700), "$s", m68000up }, +{ "scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a }, +{ "seq", 2, one(0053700), one(0177700), "$s", m68000up }, +{ "seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a }, +{ "sf", 2, one(0050700), one(0177700), "$s", m68000up }, +{ "sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a }, +{ "sge", 2, one(0056300), one(0177700), "$s", m68000up }, +{ "sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a }, +{ "sgt", 2, one(0057300), one(0177700), "$s", m68000up }, +{ "sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a }, +{ "shi", 2, one(0051300), one(0177700), "$s", m68000up }, +{ "shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a }, +{ "sle", 2, one(0057700), one(0177700), "$s", m68000up }, +{ "sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a }, +{ "sls", 2, one(0051700), one(0177700), "$s", m68000up }, +{ "sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a }, +{ "slt", 2, one(0056700), one(0177700), "$s", m68000up }, +{ "slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a }, +{ "smi", 2, one(0055700), one(0177700), "$s", m68000up }, +{ "smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a }, +{ "sne", 2, one(0053300), one(0177700), "$s", m68000up }, +{ "sne", 2, one(0053300), one(0177770), "Ds", mcfisa_a }, +{ "spl", 2, one(0055300), one(0177700), "$s", m68000up }, +{ "spl", 2, one(0055300), one(0177770), "Ds", mcfisa_a }, +{ "st", 2, one(0050300), one(0177700), "$s", m68000up }, +{ "st", 2, one(0050300), one(0177770), "Ds", mcfisa_a }, +{ "svc", 2, one(0054300), one(0177700), "$s", m68000up }, +{ "svc", 2, one(0054300), one(0177770), "Ds", mcfisa_a }, +{ "svs", 2, one(0054700), one(0177700), "$s", m68000up }, +{ "svs", 2, one(0054700), one(0177770), "Ds", mcfisa_a }, -{"sleep", 2, one(0047170), one(0177777), "", fido_a }, +{ "sleep", 2, one(0047170), one(0177777), "", fido_a }, -{"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a }, +{ "stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a }, -{"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa}, +{ "strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa}, -{"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up }, +{ "subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "subaw", 2, one(0110300), one(0170700), "*wAd", m68000up }, -{"subib", 4, one(0002000), one(0177700), "#b$s", m68000up }, -{"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up }, -{"subil", 6, one(0002200), one(0177700), "#l$s", m68000up }, -{"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, +{ "subib", 4, one(0002000), one(0177700), "#b$s", m68000up }, +{ "subiw", 4, one(0002100), one(0177700), "#w$s", m68000up }, +{ "subil", 6, one(0002200), one(0177700), "#l$s", m68000up }, +{ "subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, -{"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, -{"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, -{"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, +{ "subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, +{ "subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, +{ "subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, /* The sub opcode can generate the suba, subi, and subq instructions. */ -{"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, -{"subb", 4, one(0002000), one(0177700), "#b$s", m68000up }, -{"subb", 2, one(0110000), one(0170700), ";bDd", m68000up }, -{"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up }, -{"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, -{"subw", 4, one(0002100), one(0177700), "#w$s", m68000up }, -{"subw", 2, one(0110300), one(0170700), "*wAd", m68000up }, -{"subw", 2, one(0110100), one(0170700), "*wDd", m68000up }, -{"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up }, -{"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, -{"subl", 6, one(0002200), one(0177700), "#l$s", m68000up }, -{"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, -{"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, -{"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a }, -{"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a }, +{ "subb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, +{ "subb", 4, one(0002000), one(0177700), "#b$s", m68000up }, +{ "subb", 2, one(0110000), one(0170700), ";bDd", m68000up }, +{ "subb", 2, one(0110400), one(0170700), "Dd~s", m68000up }, +{ "subw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, +{ "subw", 4, one(0002100), one(0177700), "#w$s", m68000up }, +{ "subw", 2, one(0110300), one(0170700), "*wAd", m68000up }, +{ "subw", 2, one(0110100), one(0170700), "*wDd", m68000up }, +{ "subw", 2, one(0110500), one(0170700), "Dd~s", m68000up }, +{ "subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, +{ "subl", 6, one(0002200), one(0177700), "#l$s", m68000up }, +{ "subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, +{ "subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{ "subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{ "subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a }, -{"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up }, -{"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up }, -{"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up }, -{"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up }, -{"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a }, -{"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up }, +{ "subxb", 2, one(0110400), one(0170770), "DsDd", m68000up }, +{ "subxb", 2, one(0110410), one(0170770), "-s-d", m68000up }, +{ "subxw", 2, one(0110500), one(0170770), "DsDd", m68000up }, +{ "subxw", 2, one(0110510), one(0170770), "-s-d", m68000up }, +{ "subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a }, +{ "subxl", 2, one(0110610), one(0170770), "-s-d", m68000up }, -{"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a }, +{ "swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a }, /* swbeg and swbegl are magic constants used on sysV68. The compiler generates them before a switch table. They tell the debugger and @@ -2182,10 +2182,10 @@ const struct m68k_opcode m68k_opcodes[] = number of elements in the table. swbeg means that the entries in the table are word (2 byte) sized, and swbegl means that the entries in the table are longword (4 byte) sized. */ -{"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, -{"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, +{ "swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, +{ "swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, -{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b | mcfisa_c}, +{ "tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b | mcfisa_c}, #define TBL1(name,insn_size,signed,round,size) \ {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ @@ -2199,30 +2199,30 @@ TBL("tblsnb", "tblsnw", "tblsnl", 1, 0), TBL("tblub", "tbluw", "tblul", 0, 1), TBL("tblunb", "tblunw", "tblunl", 0, 0), -{"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a }, +{ "trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a }, -{"trapx", 2, one(0047060), one(0177760), "Ts", fido_a }, +{ "trapx", 2, one(0047060), one(0177760), "Ts", fido_a }, -{"tstb", 2, one(0045000), one(0177700), ";b", m68020up | cpu32 | fido_a | mcfisa_a }, -{"tstb", 2, one(0045000), one(0177700), "$b", m68000up }, -{"tstw", 2, one(0045100), one(0177700), "*w", m68020up | cpu32 | fido_a | mcfisa_a }, -{"tstw", 2, one(0045100), one(0177700), "$w", m68000up }, -{"tstl", 2, one(0045200), one(0177700), "*l", m68020up | cpu32 | fido_a | mcfisa_a }, -{"tstl", 2, one(0045200), one(0177700), "$l", m68000up }, +{ "tstb", 2, one(0045000), one(0177700), ";b", m68020up | cpu32 | fido_a | mcfisa_a }, +{ "tstb", 2, one(0045000), one(0177700), "$b", m68000up }, +{ "tstw", 2, one(0045100), one(0177700), "*w", m68020up | cpu32 | fido_a | mcfisa_a }, +{ "tstw", 2, one(0045100), one(0177700), "$w", m68000up }, +{ "tstl", 2, one(0045200), one(0177700), "*l", m68020up | cpu32 | fido_a | mcfisa_a }, +{ "tstl", 2, one(0045200), one(0177700), "$l", m68000up }, -{"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a }, +{ "unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a }, -{"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up }, -{"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up }, +{ "unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up }, +{ "unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up }, -{"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a }, -{"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a }, -{"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a }, +{ "wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a }, +{ "wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a }, +{ "wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a }, -{"wdebugl", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, -{"wdebugl", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, -{"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, -{"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, +{ "wdebugl", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, +{ "wdebugl", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, +{ "wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, +{ "wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, }; const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; diff --git a/libr/asm/arch/mips/gnu/micromips-opc.c b/libr/asm/arch/mips/gnu/micromips-opc.c index e59b3e3d95..6864cbcbb8 100644 --- a/libr/asm/arch/mips/gnu/micromips-opc.c +++ b/libr/asm/arch/mips/gnu/micromips-opc.c @@ -294,1586 +294,1586 @@ const struct mips_opcode micromips_opcodes[] = them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 }, -{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, -{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 }, -{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 }, -{"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ -{"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ -{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, -{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, -{"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, -{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */ -{"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */ -{"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */ -{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 }, -{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */ -{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */ +{ "pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 }, +{ "pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, +{ "nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 }, +{ "nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 }, +{ "li", "t,j", 0x30000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ +{ "li", "t,i", 0x50000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ +{ "li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, +{ "move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, +{ "move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, +{ "move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */ +{ "move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */ +{ "move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */ +{ "b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 }, +{ "b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* beq 0, 0 */ +{ "b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 }, /* bgez 0 */ /* BC is next to B so that we easily find it when converting a normal branch to a compact one. */ -{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */ -{"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */ -{"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */ -{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, -{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, -{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, -{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, -{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ -{"addiu", "md,ms,mW", 0x6c01, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur1sp */ -{"addiu", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur2 */ -{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp */ -{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addius5 */ -{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, /* addiupc */ -{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, -{"addiur1sp", "md,mW", 0x6c01, 0xfc01, WR_1, RD_sp, I1, 0, 0 }, -{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, -{"addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1, 0, 0 }, -{"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, -{"addu", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ -{"addu", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */ -{"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, -{"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, -{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, -{"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, -{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, -{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, +{ "bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, 0 }, /* beqzc 0 */ +{ "bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, 0 }, /* bgezal 0 */ +{ "bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, 0 }, /* bgezals 0 */ +{ "abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, +{ "abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, +{ "aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, +{ "add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "addi", "t,r,j", 0x10000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addiu", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ +{ "addiu", "md,ms,mW", 0x6c01, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur1sp */ +{ "addiu", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur2 */ +{ "addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp */ +{ "addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addius5 */ +{ "addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, /* addiupc */ +{ "addiu", "t,r,j", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addiupc", "mb,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, +{ "addiur1sp", "md,mW", 0x6c01, 0xfc01, WR_1, RD_sp, I1, 0, 0 }, +{ "addiur2", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1, 0, 0 }, +{ "addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, +{ "addu", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ +{ "addu", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */ +{ "addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, +{ "and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, +{ "and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, +{ "andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, +{ "aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, /* b is at the top of the table. */ /* bal is at the top of the table. */ -{"bc1f", "p", 0x43800000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1f", "N,p", 0x43800000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"bc2f", "p", 0x42800000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 }, -{"bc2f", "N,p", 0x42800000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 }, -{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 }, -{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 }, -{"bc1t", "p", 0x43a00000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1t", "N,p", 0x43a00000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"bc2t", "p", 0x42a00000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 }, -{"bc2t", "N,p", 0x42a00000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 }, -{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 }, -{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 }, -{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, -{"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, -{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */ -{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */ -{"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, -{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bc1f", "p", 0x43800000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, +{ "bc1f", "N,p", 0x43800000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, +{ "bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "bc2f", "p", 0x42800000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 }, +{ "bc2f", "N,p", 0x42800000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 }, +{ "bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bc1t", "p", 0x43a00000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, +{ "bc1t", "N,p", 0x43a00000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, +{ "bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "bc2t", "p", 0x42a00000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 }, +{ "bc2t", "N,p", 0x42a00000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 }, +{ "bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 }, +{ "beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, +{ "beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, +{ "beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */ +{ "beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */ +{ "beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, +{ "beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, /* BEQZC is next to BEQ so that we easily find it when converting a normal branch to a compact one. */ -{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, -{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, -{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgez", "s,p", 0x40400000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgezal", "s,p", 0x40600000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 }, -{"bgezals", "s,p", 0x42600000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 }, -{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, -{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtz", "s,p", 0x40c00000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1, 0, 0 }, -{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, -{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1, 0, 0 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1, 0, 0 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"blez", "s,p", 0x40800000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1, 0, 0 }, -{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, -{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1, 0, 0 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1, 0, 0 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltz", "s,p", 0x40000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1, 0, 0 }, -{"bltzal", "s,p", 0x40200000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 }, -{"bltzals", "s,p", 0x42200000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 }, -{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 }, -{"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, -{"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, -{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, -{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */ -{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */ -{"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, -{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, +{ "beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 }, +{ "beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, +{ "bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgez", "s,p", 0x40400000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgezal", "s,p", 0x40600000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 }, +{ "bgezals", "s,p", 0x42600000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 }, +{ "bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtz", "s,p", 0x40c00000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1, 0, 0 }, +{ "ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, +{ "ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1, 0, 0 }, +{ "blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "blez", "s,p", 0x40800000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1, 0, 0 }, +{ "blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, +{ "blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltz", "s,p", 0x40000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltzal", "s,p", 0x40200000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 }, +{ "bltzals", "s,p", 0x42200000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 }, +{ "bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, +{ "bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */ +{ "bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */ +{ "bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, +{ "bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, /* BNEZC is next to BNE so that we easily find it when converting a normal branch to a compact one. */ -{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, -{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 }, -{"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 }, -{"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, -{"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, -{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, -{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_3, 0, I1, 0, 0 }, -{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, -{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, -{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, -{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, -{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, -{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1, 0, 0 }, -{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, -{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, -{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, -{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I1, 0, 0 }, -{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, -{"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, -{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, -{"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, -{"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, -{"deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"dext", "t,r,+A,+H", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dext", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextm */ -{"dext", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextu */ -{"dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 }, +{ "bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 }, +{ "bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 }, +{ "break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 }, +{ "break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 }, +{ "break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{ "break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 }, +{ "c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 }, +{ "c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 }, +{ "cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_3, 0, I1, 0, 0 }, +{ "cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, +{ "cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, +{ "cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, +{ "clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1, 0, 0 }, +{ "ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, +{ "ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, +{ "ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, +{ "cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.l.d", "T,S", 0x5400413b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "cvt.l.s", "T,S", 0x5400013b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.s.l", "T,S", 0x54005b7b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.s.d", "T,S", 0x54001b7b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.s.w", "T,S", 0x54003b7b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "cvt.s.pl", "T,S", 0x5400213b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I1, 0, 0 }, +{ "dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, +{ "dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, +{ "daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{ "dext", "t,r,+A,+H", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dext", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextm */ +{ "dext", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextu */ +{ "dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* For ddiv, see the comments about div. */ -{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, -{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 }, -{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, -{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, 0 }, +{ "ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, +{ "ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 }, +{ "ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, 0 }, /* For ddivu, see the comments about div. */ -{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, -{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 }, -{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 }, -{"di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 }, -{"di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dins", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsm */ -{"dins", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsu */ -{"dinsm", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dinsu", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, +{ "ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 }, +{ "ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 }, +{ "di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 }, +{ "di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 }, +{ "dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dins", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsm */ +{ "dins", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsu */ +{ "dinsm", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dinsu", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as though the first operand appeared twice (the first operand is both a source and a destination). To get the div machine instruction, you must use an explicit destination of $0. */ -{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 }, -{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, -{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 }, -{"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, +{ "div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 }, +{ "div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 }, +{ "div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, /* For divu, see the comments about div. */ -{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 }, -{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 }, -{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"dli", "t,j", 0x30000000, 0xfc1f0000, WR_1, 0, I3, 0, 0 }, /* addiu */ -{"dli", "t,i", 0x50000000, 0xfc1f0000, WR_1, 0, I3, 0, 0 }, /* ori */ -{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, -{"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_1|RD_C0, 0, I3, 0, 0 }, -{"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I3, 0, 0 }, -{"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, -{"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, -{"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, -{"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, -{"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, -{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, -{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, -{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, -{"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_1|RD_C2, 0, I3, 0, 0 }, -/*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_1|RD_C2, 0, I3, 0, 0 },*/ -{"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, -/*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ -{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, -{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, 0 }, -{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, 0 }, -{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 }, -{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 }, -{"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ -{"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0 */ -{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, -{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, -{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, 0 }, -{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, -{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, 0 }, -{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, -{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"drorv", "d,t,s", 0x580000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, -{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, -{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, -{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, -{"drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */ -{"dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ -{"dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ -{"dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ -{"dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ -{"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ -{"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 }, -{"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 }, -{"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 }, -{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, -{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, -{"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, -{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, -{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC, 0 }, -{"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, -{"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */ -{"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */ -{"jraddiusp", "mP", 0x4700, 0xffe0, NODS, WR_sp|RD_31|RD_sp|UBR, I1, 0, 0 }, +{ "divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, +{ "divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 }, +{ "divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 }, +{ "dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "dli", "t,j", 0x30000000, 0xfc1f0000, WR_1, 0, I3, 0, 0 }, /* addiu */ +{ "dli", "t,i", 0x50000000, 0xfc1f0000, WR_1, 0, I3, 0, 0 }, /* ori */ +{ "dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_1|RD_C0, 0, I3, 0, 0 }, +{ "dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I3, 0, 0 }, +{ "dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{ "dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{ "dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, +{ "dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, +{ "dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{ "dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{ "dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, +{ "dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 }, +{ "dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, +{ "dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 }, +{ "dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_1|RD_C2, 0, I3, 0, 0 }, +/*{ "dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_1|RD_C2, 0, I3, 0, 0 },*/ +{ "dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, +/*{ "dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/ +{ "dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 }, +{ "dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 }, +{ "dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ +{ "dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0 */ +{ "drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, +{ "drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 }, +{ "dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, 0 }, +{ "drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, +{ "drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "t,r,<", 0x580000c0, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "drorv", "d,t,s", 0x580000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dror32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, +{ "drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, +{ "drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "drotrv", "d,t,s", 0x580000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "drotr32", "t,r,<", 0x580000c8, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsbh", "t,r", 0x58007b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dshd", "t,r", 0x5800fb3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsllv", "d,t,s", 0x58000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsll32", "t,r,<", 0x58000008, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsll", "d,t,s", 0x58000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */ +{ "dsll", "t,r,>", 0x58000008, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ +{ "dsll", "t,r,<", 0x58000000, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsrav", "d,t,s", 0x58000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsra32", "t,r,<", 0x58000088, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsra", "d,t,s", 0x58000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ +{ "dsra", "t,r,>", 0x58000088, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ +{ "dsra", "t,r,<", 0x58000080, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsrlv", "d,t,s", 0x58000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsrl32", "t,r,<", 0x58000048, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsrl", "d,t,s", 0x58000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ +{ "dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ +{ "dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 }, +{ "ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 }, +{ "eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{ "eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 }, +{ "ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, +{ "floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, +{ "hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, +{ "ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, +{ "iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC, 0 }, +{ "jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, +{ "jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */ +{ "jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */ +{ "jraddiusp", "mP", 0x4700, 0xffe0, NODS, WR_sp|RD_31|RD_sp|UBR, I1, 0, 0 }, /* This macro is after the real instruction so that it only matches with -minsn32. */ -{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 }, -{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */ -{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */ -{"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */ -{"j", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jr */ +{ "jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 }, +{ "jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */ +{ "jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */ +{ "j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */ +{ "j", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jr */ /* SVR4 PIC code requires special handling for j, so it must be a macro. */ -{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, +{ "j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, /* This form of j is used by the disassembler and internally by the assembler, but will never match user input (because the line above will match first). */ -{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 }, +{ "j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 }, /* JRC is close to JR and J so that we easily find it when converting a normal jump to a compact one. */ -{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 }, +{ "jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 }, /* This macro is after the real instruction so that it only matches with -minsn32. */ -{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 }, -{"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, -{"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 }, -{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, -{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 }, -{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, -{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 }, -{"jalrs", "mj", 0x45e0, 0xffe0, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, -{"jalrs", "my,mj", 0x45e0, 0xffe0, RD_2|WR_31|UBD, BD16, I1, 0, 0 }, -{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, -{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 }, -{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, -{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 }, +{ "jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 }, +{ "jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, +{ "jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 }, +{ "jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, +{ "jalr", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 }, +{ "jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 }, +{ "jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 }, +{ "jalrs", "mj", 0x45e0, 0xffe0, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, +{ "jalrs", "my,mj", 0x45e0, 0xffe0, RD_2|WR_31|UBD, BD16, I1, 0, 0 }, +{ "jalrs", "s", 0x03e04f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, +{ "jalrs", "t,s", 0x00004f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 }, +{ "jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 }, +{ "jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 }, /* SVR4 PIC code requires special handling for jal, so it must be a macro. */ -{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, -{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, -{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, /* This form of jal is used by the disassembler and internally by the assembler, but will never match user input (because the line above will match first). */ -{"jal", "a", 0xf4000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, -{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1, 0, 0 }, -{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1, 0, 0 }, -{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1, 0, 0 }, -{"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 }, -{"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, -{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "a", 0xf4000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, +{ "jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1, 0, 0 }, +{ "jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1, 0, 0 }, +{ "jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1, 0, 0 }, +{ "jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 }, +{ "jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, +{ "la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ -{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, -{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, -{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, /* ldc1 */ -{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3|LM, 0, I3, 0, 0 }, -{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, -{"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{ "ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{ "ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, +{ "ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, /* ldc1 */ +{ "l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3|LM, 0, I3, 0, 0 }, +{ "ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{ "lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, /* li is at the start of the table. */ -{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 }, -{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, -{"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwsp */ -{"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwgp */ -{"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, -{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, -{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, /* lwc1 */ -{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* same */ -{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, 0 }, -{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS|LM, 0, I1, 0, 0 }, -{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS|LM, 0, I1, 0, 0 }, -{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, -{"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ -{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, 0 }, -{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, -{"madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, -{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, -{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, -{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, -{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, -{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, -{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 }, -{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 }, -{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, -{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, -{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, -{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, -{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, -{"mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, 0 }, -{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, 0 }, -{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_1|RD_HI, 0, 0, D32, 0 }, -{"mflo", "mj", 0x4640, 0xffe0, WR_1|RD_LO, 0, I1, 0, 0 }, -{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_1|RD_LO, 0, I1, 0, 0 }, -{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_1|RD_LO, 0, 0, D32, 0 }, -{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"movep", "mh,mm,mn", 0x8400, 0xfc01, WR_1|RD_2|RD_3|NODS, 0, I1, 0, 0 }, +{ "li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 }, +{ "luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{ "lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwsp */ +{ "lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwgp */ +{ "lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, +{ "lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, +{ "lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, +{ "lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, /* lwc1 */ +{ "l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* same */ +{ "lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, 0 }, +{ "lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS|LM, 0, I1, 0, 0 }, +{ "lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS|LM, 0, I1, 0, 0 }, +{ "lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, +{ "flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ +{ "flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, 0 }, +{ "madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, +{ "madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, +{ "madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, +{ "maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 }, +{ "mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 }, +{ "mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, +{ "mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I1, 0, 0 }, +{ "mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, +{ "mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, +{ "mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, +{ "mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 }, +{ "mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 }, +{ "mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, +{ "mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 }, +{ "mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, +{ "mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 }, +{ "mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, +{ "mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, 0 }, +{ "mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, 0 }, +{ "mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_1|RD_HI, 0, 0, D32, 0 }, +{ "mflo", "mj", 0x4640, 0xffe0, WR_1|RD_LO, 0, I1, 0, 0 }, +{ "mflo", "s", 0x00001d7c, 0xffe0ffff, WR_1|RD_LO, 0, I1, 0, 0 }, +{ "mflo", "s,7", 0x0000107c, 0xffe03fff, WR_1|RD_LO, 0, 0, D32, 0 }, +{ "mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "movep", "mh,mm,mn", 0x8400, 0xfc01, WR_1|RD_2|RD_3|NODS, 0, I1, 0, 0 }, /* This macro is after the real instruction so that it only matches with -minsn32. */ -{"movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1, 0, 0 }, -{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 }, -{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, -{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 }, -{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, -{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 }, -{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, -{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 }, -{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, -{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, -{"msub", "7,s,t", 0x00002abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, -{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, -{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, -{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, -{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, -{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, -{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, -{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, -{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, -{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, -{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, -{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, -{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, -{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, -{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, -{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, 0 }, -{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_1|WR_HI, 0, 0, D32, 0 }, -{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1|WR_LO, 0, I1, 0, 0 }, -{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_1|WR_LO, 0, 0, D32, 0 }, -{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 }, -{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 }, -{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 }, -{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 }, -{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, -{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 }, -{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, -{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ -{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ -{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, -{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, -{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, -{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1, 0, 0 }, +{ "movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 }, +{ "movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, +{ "movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 }, +{ "movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, +{ "movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 }, +{ "movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, +{ "movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 }, +{ "movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 }, +{ "movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, +{ "msub", "7,s,t", 0x00002abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, +{ "msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, +{ "msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, +{ "mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, +{ "mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, +{ "mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I1, 0, 0 }, +{ "mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, +{ "mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, +{ "mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, +{ "mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, +{ "mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 }, +{ "mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, +{ "mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 }, +{ "mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, +{ "mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 }, +{ "mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, +{ "mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, 0 }, +{ "mthi", "s,7", 0x0000207c, 0xffe03fff, RD_1|WR_HI, 0, 0, D32, 0 }, +{ "mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1|WR_LO, 0, I1, 0, 0 }, +{ "mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_1|WR_LO, 0, 0, D32, 0 }, +{ "mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, +{ "mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 }, +{ "mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 }, +{ "mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 }, +{ "mult", "7,s,t", 0x00000cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, +{ "multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 }, +{ "multu", "7,s,t", 0x00001cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, +{ "neg", "d,w", 0x00000190, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ +{ "negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ +{ "neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, +{ "nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, +{ "nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 }, +{ "nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, /* nop is at the start of the table. */ -{"not", "mf,mg", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* put not before nor */ -{"not", "d,v", 0x000002d0, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* nor d,s,0 */ -{"nor", "mf,mz,mg", 0x4400, 0xffc0, WR_1|RD_3, 0, I1, 0, 0 }, /* not */ -{"nor", "mf,mg,mz", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* not */ -{"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"or", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ -{"or", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */ -{"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, -{"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, -{"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ori", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ -{"ori", "t,r,i", 0x50000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "not", "mf,mg", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* put not before nor */ +{ "not", "d,v", 0x000002d0, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* nor d,s,0 */ +{ "nor", "mf,mz,mg", 0x4400, 0xffc0, WR_1|RD_3, 0, I1, 0, 0 }, /* not */ +{ "nor", "mf,mg,mz", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* not */ +{ "nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "or", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ +{ "or", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */ +{ "or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, +{ "or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, +{ "or", "d,v,t", 0x00000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ori", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */ +{ "ori", "t,r,i", 0x50000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, /* pref is at the start of the table. */ -{"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, -{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 }, -{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, WR_1, 0, I1, 0, 0 }, -{"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_1, 0, I1, 0, 0 }, -{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, -{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, -{"rorv", "d,t,s", 0x000000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, -{"rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, -{"rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"sb", "mq,mL(ml)", 0x8800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sb", "t,o(b)", 0x18000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, 0 }, -{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, +{ "rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 }, +{ "remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, +{ "remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 }, +{ "rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, WR_1, 0, I1, 0, 0 }, +{ "rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_1, 0, I1, 0, 0 }, +{ "rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, +{ "rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "t,r,<", 0x000000c0, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "rorv", "d,t,s", 0x000000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, +{ "rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, +{ "rotr", "t,r,<", 0x000000c0, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "rotrv", "d,t,s", 0x000000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "round.l.d", "T,S", 0x5400733b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "round.l.s", "T,S", 0x5400333b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "round.w.d", "T,S", 0x54007b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "round.w.s", "T,S", 0x54003b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "rsqrt.d", "T,S", 0x5400423b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "rsqrt.s", "T,S", 0x5400023b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "sb", "mq,mL(ml)", 0x8800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sb", "t,o(b)", 0x18000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ -{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sd", "t,o(b)", 0xd8000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 }, -{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, 0 }, -{"sdbbp", "+J", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, -{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, -{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, -{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, /* sdc1 */ -{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, RD_3|SM, 0, I3, 0, 0 }, -{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 }, -{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, -{"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, -{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, -{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, -{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, -{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, -{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, -{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sh", "mq,mH(ml)", 0xa800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sh", "t,o(b)", 0x38000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, -{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, -{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sll", "md,mc,mM", 0x2400, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, -{"sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ -{"sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, -{"slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"slti", "t,r,j", 0x90000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, -{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ -{"sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, -{"srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"srl", "md,mc,mM", 0x2401, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, -{"srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ -{"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "sd", "t,o(b)", 0xd8000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 }, +{ "sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, +{ "sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, 0 }, +{ "sdbbp", "+J", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{ "sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, +{ "sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, +{ "sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 }, +{ "sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "s.d", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, /* sdc1 */ +{ "s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "sdl", "t,~(b)", 0x6000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "sdm", "n,~(b)", 0x2000f000, 0xfc00f000, RD_3|SM, 0, I3, 0, 0 }, +{ "sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "sdp", "t,~(b)", 0x2000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "sdr", "t,~(b)", 0x6000d000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 }, +{ "seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, +{ "seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sh", "mq,mH(ml)", 0xa800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sh", "t,o(b)", 0x38000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sllv", "d,t,s", 0x00000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sll", "md,mc,mM", 0x2400, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sll", "d,w,s", 0x00000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ +{ "sll", "t,r,<", 0x00000000, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "slt", "d,v,t", 0x00000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "slti", "t,r,j", 0x90000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sltiu", "t,r,j", 0xb0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sltu", "d,v,t", 0x00000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sqrt.d", "T,S", 0x54004a3b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "sqrt.s", "T,S", 0x54000a3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "srav", "d,t,s", 0x00000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sra", "d,w,s", 0x00000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ +{ "sra", "t,r,<", 0x00000080, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "srlv", "d,t,s", 0x00000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "srl", "md,mc,mM", 0x2401, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, +{ "srl", "d,w,s", 0x00000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ +{ "srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* ssnop is at the start of the table. */ -{"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"subu", "md,me,ml", 0x0401, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 }, -{"sw", "mq,mJ(ml)", 0xe800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sw", "mp,mU(ms)", 0xc800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* swsp */ -{"sw", "t,o(b)", 0xf8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swc1", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "E,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"s.s", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ -{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swl", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"scache", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ -{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, RD_3|NODS, 0, I1, 0, 0 }, -{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, RD_3|SM|NODS, 0, I1, 0, 0 }, -{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swp", "t,~(b)", 0x20009000, 0xfc00f000, RD_1|RD_3|SM|NODS, 0, I1, 0, 0 }, -{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swr", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ -{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, -{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, -{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, -{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, -{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, -{"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 }, -{"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 }, -{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"syscall", "+J", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"teq", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"tgei", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tge", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, -{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, -{"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgwr", "", 0x0000317c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlti", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tlt", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tltu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"tnei", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, -{"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, -{"tne", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, -{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"wait", "+J", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 }, -{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_2, 0, I1, 0, 0 }, -{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, -{"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, -{"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, -{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, +{ "subu", "md,me,ml", 0x0401, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 }, +{ "sw", "mq,mJ(ml)", 0xe800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sw", "mp,mU(ms)", 0xc800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* swsp */ +{ "sw", "t,o(b)", 0xf8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swc1", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{ "swc1", "E,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{ "swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "swc2", "E,~(b)", 0x20008000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 }, +{ "swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "s.s", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ +{ "s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "swl", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "scache", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ +{ "scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swm", "mN,mJ(ms)", 0x4540, 0xffc0, RD_3|NODS, 0, I1, 0, 0 }, +{ "swm", "n,~(b)", 0x2000d000, 0xfc00f000, RD_3|SM|NODS, 0, I1, 0, 0 }, +{ "swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swp", "t,~(b)", 0x20009000, 0xfc00f000, RD_1|RD_3|SM|NODS, 0, I1, 0, 0 }, +{ "swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swr", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ +{ "invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{ "sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{ "sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{ "sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{ "sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{ "sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 }, +{ "sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{ "sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 }, +{ "synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 }, +{ "syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1, 0, 0 }, +{ "syscall", "+J", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{ "teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "teq", "s,t", 0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "teq", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* teqi */ +{ "teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "tgei", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "tge", "s,t", 0x0000023c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tge", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgei */ +{ "tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "tgeiu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tgeu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgeiu */ +{ "tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, +{ "tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, +{ "tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgwr", "", 0x0000317c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbp", "", 0x0000037c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlti", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tlt", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tlti */ +{ "tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "tltiu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tltu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tltiu */ +{ "tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "tnei", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, +{ "tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 }, +{ "tne", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tnei */ +{ "tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{ "trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, +{ "trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{ "wait", "+J", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 }, +{ "wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_2, 0, I1, 0, 0 }, +{ "wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, +{ "xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 }, +{ "xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 }, +{ "xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, /* microMIPS Enhanced VA Scheme */ -{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, -{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, -{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, -{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, -{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3|LM, 0, 0, EVA, 0 }, -{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, +{ "cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, +{ "prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3|LM, 0, 0, EVA, 0 }, +{ "prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, /* MIPS DSP ASE. */ -{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32, 0 }, -{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_1|RD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, -{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, -{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, -{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, -{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_1|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbra", "t,s", 0x0000d33c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_1, 0, 0, D32, 0 }, -{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_1, 0, 0, D32, 0 }, -{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_1, 0, 0, D32, 0 }, -{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_1, 0, 0, D32, 0 }, -{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, 0, D32, 0 }, -{"shilov", "7,s", 0x0000127c, 0xffe03fff, RD_2|MOD_a, 0, 0, D32, 0 }, -{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, -{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, +{ "absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32, 0 }, +{ "cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_1|RD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "insv", "t,s", 0x0000413c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, +{ "lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, +{ "lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, +{ "maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_1|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbra", "t,s", 0x0000d33c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_1, 0, 0, D32, 0 }, +{ "rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_1, 0, 0, D32, 0 }, +{ "repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_1, 0, 0, D32, 0 }, +{ "repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_1, 0, 0, D32, 0 }, +{ "replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, 0, D32, 0 }, +{ "shilov", "7,s", 0x0000127c, 0xffe03fff, RD_2|MOD_a, 0, 0, D32, 0 }, +{ "shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, +{ "wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, /* MIPS DSP ASE Rev2. */ -{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_1|RD_2, 0, 0, D33, 0 }, -{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, -{"balign", "t,s,2", 0x000008bc, 0xfc003fff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "append", "t,s,h", 0x00000215, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, +{ "balign", "t,s,2", 0x000008bc, 0xfc003fff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "prepend", "t,s,h", 0x00000255, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, /* MSA Extension. */ -{"sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"slli.b", "+d,+e,+!", 0x58700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.h", "+d,+e,+@", 0x58600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.w", "+d,+e,+x", 0x58400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.d", "+d,+e,+#", 0x58000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sra.b", "+d,+e,+h", 0x5880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.h", "+d,+e,+h", 0x58a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.w", "+d,+e,+h", 0x58c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.d", "+d,+e,+h", 0x58e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srai.b", "+d,+e,+!", 0x58f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.h", "+d,+e,+@", 0x58e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.w", "+d,+e,+x", 0x58c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.d", "+d,+e,+#", 0x58800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srl.b", "+d,+e,+h", 0x5900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.h", "+d,+e,+h", 0x5920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.w", "+d,+e,+h", 0x5940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.d", "+d,+e,+h", 0x5960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srli.b", "+d,+e,+!", 0x59700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.h", "+d,+e,+@", 0x59600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.w", "+d,+e,+x", 0x59400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.d", "+d,+e,+#", 0x59000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclr.b", "+d,+e,+h", 0x5980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.h", "+d,+e,+h", 0x59a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.w", "+d,+e,+h", 0x59c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.d", "+d,+e,+h", 0x59e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclri.b", "+d,+e,+!", 0x59f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.h", "+d,+e,+@", 0x59e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.w", "+d,+e,+x", 0x59c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.d", "+d,+e,+#", 0x59800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bset.b", "+d,+e,+h", 0x5a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.h", "+d,+e,+h", 0x5a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.w", "+d,+e,+h", 0x5a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.d", "+d,+e,+h", 0x5a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bseti.b", "+d,+e,+!", 0x5a700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.h", "+d,+e,+@", 0x5a600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.w", "+d,+e,+x", 0x5a400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.d", "+d,+e,+#", 0x5a000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bneg.b", "+d,+e,+h", 0x5a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.h", "+d,+e,+h", 0x5aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.w", "+d,+e,+h", 0x5ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.d", "+d,+e,+h", 0x5ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bnegi.b", "+d,+e,+!", 0x5af00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.h", "+d,+e,+@", 0x5ae00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.w", "+d,+e,+x", 0x5ac00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.d", "+d,+e,+#", 0x5a800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"binsl.b", "+d,+e,+h", 0x5b00001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.h", "+d,+e,+h", 0x5b20001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.w", "+d,+e,+h", 0x5b40001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.d", "+d,+e,+h", 0x5b60001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsli.b", "+d,+e,+!", 0x5b700012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.h", "+d,+e,+@", 0x5b600012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.w", "+d,+e,+x", 0x5b400012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.d", "+d,+e,+#", 0x5b000012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsr.b", "+d,+e,+h", 0x5b80001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.h", "+d,+e,+h", 0x5ba0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.w", "+d,+e,+h", 0x5bc0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.d", "+d,+e,+h", 0x5be0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsri.b", "+d,+e,+!", 0x5bf00012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.h", "+d,+e,+@", 0x5be00012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.w", "+d,+e,+x", 0x5bc00012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.d", "+d,+e,+#", 0x5b800012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"addv.b", "+d,+e,+h", 0x5800002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.h", "+d,+e,+h", 0x5820002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.w", "+d,+e,+h", 0x5840002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.d", "+d,+e,+h", 0x5860002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addvi.b", "+d,+e,+$", 0x58000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.h", "+d,+e,+$", 0x58200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.w", "+d,+e,+$", 0x58400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.d", "+d,+e,+$", 0x58600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subv.b", "+d,+e,+h", 0x5880002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.h", "+d,+e,+h", 0x58a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.w", "+d,+e,+h", 0x58c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.d", "+d,+e,+h", 0x58e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subvi.b", "+d,+e,+$", 0x58800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.h", "+d,+e,+$", 0x58a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.w", "+d,+e,+$", 0x58c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.d", "+d,+e,+$", 0x58e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_s.b", "+d,+e,+h", 0x5900002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.h", "+d,+e,+h", 0x5920002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.w", "+d,+e,+h", 0x5940002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.d", "+d,+e,+h", 0x5960002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maxi_s.b", "+d,+e,+%", 0x59000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.h", "+d,+e,+%", 0x59200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.w", "+d,+e,+%", 0x59400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.d", "+d,+e,+%", 0x59600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_u.b", "+d,+e,+h", 0x5980002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.h", "+d,+e,+h", 0x59a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.w", "+d,+e,+h", 0x59c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.d", "+d,+e,+h", 0x59e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maxi_u.b", "+d,+e,+$", 0x59800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.h", "+d,+e,+$", 0x59a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.w", "+d,+e,+$", 0x59c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.d", "+d,+e,+$", 0x59e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"min_s.b", "+d,+e,+h", 0x5a00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.h", "+d,+e,+h", 0x5a20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.w", "+d,+e,+h", 0x5a40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.d", "+d,+e,+h", 0x5a60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mini_s.b", "+d,+e,+%", 0x5a000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.h", "+d,+e,+%", 0x5a200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.w", "+d,+e,+%", 0x5a400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.d", "+d,+e,+%", 0x5a600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"min_u.b", "+d,+e,+h", 0x5a80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.h", "+d,+e,+h", 0x5aa0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.w", "+d,+e,+h", 0x5ac0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.d", "+d,+e,+h", 0x5ae0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mini_u.b", "+d,+e,+$", 0x5a800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.h", "+d,+e,+$", 0x5aa00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.w", "+d,+e,+$", 0x5ac00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.d", "+d,+e,+$", 0x5ae00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_a.b", "+d,+e,+h", 0x5b00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.h", "+d,+e,+h", 0x5b20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.w", "+d,+e,+h", 0x5b40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.d", "+d,+e,+h", 0x5b60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.b", "+d,+e,+h", 0x5b80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.h", "+d,+e,+h", 0x5ba0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.w", "+d,+e,+h", 0x5bc0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.d", "+d,+e,+h", 0x5be0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.b", "+d,+e,+h", 0x5800003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.h", "+d,+e,+h", 0x5820003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.w", "+d,+e,+h", 0x5840003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.d", "+d,+e,+h", 0x5860003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceqi.b", "+d,+e,+%", 0x58000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.h", "+d,+e,+%", 0x58200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.w", "+d,+e,+%", 0x58400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.d", "+d,+e,+%", 0x58600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clt_s.b", "+d,+e,+h", 0x5900003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.h", "+d,+e,+h", 0x5920003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.w", "+d,+e,+h", 0x5940003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.d", "+d,+e,+h", 0x5960003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clti_s.b", "+d,+e,+%", 0x59000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.h", "+d,+e,+%", 0x59200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.w", "+d,+e,+%", 0x59400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.d", "+d,+e,+%", 0x59600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clt_u.b", "+d,+e,+h", 0x5980003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.h", "+d,+e,+h", 0x59a0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.w", "+d,+e,+h", 0x59c0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.d", "+d,+e,+h", 0x59e0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clti_u.b", "+d,+e,+$", 0x59800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.h", "+d,+e,+$", 0x59a00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.w", "+d,+e,+$", 0x59c00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.d", "+d,+e,+$", 0x59e00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"cle_s.b", "+d,+e,+h", 0x5a00003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.h", "+d,+e,+h", 0x5a20003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.w", "+d,+e,+h", 0x5a40003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.d", "+d,+e,+h", 0x5a60003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clei_s.b", "+d,+e,+%", 0x5a000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.h", "+d,+e,+%", 0x5a200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.w", "+d,+e,+%", 0x5a400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.d", "+d,+e,+%", 0x5a600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"cle_u.b", "+d,+e,+h", 0x5a80003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.h", "+d,+e,+h", 0x5aa0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.w", "+d,+e,+h", 0x5ac0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.d", "+d,+e,+h", 0x5ae0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clei_u.b", "+d,+e,+$", 0x5a800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.d", "+d,+W(d)", 0x5800003f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"sat_s.b", "+d,+e,+!", 0x58700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.h", "+d,+e,+@", 0x58600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.w", "+d,+e,+x", 0x58400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.d", "+d,+e,+#", 0x58000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.b", "+d,+e,+!", 0x58f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.h", "+d,+e,+@", 0x58e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.w", "+d,+e,+x", 0x58c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.d", "+d,+e,+#", 0x58800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"add_a.b", "+d,+e,+h", 0x58000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.h", "+d,+e,+h", 0x58200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.w", "+d,+e,+h", 0x58400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.d", "+d,+e,+h", 0x58600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.b", "+d,+e,+h", 0x58800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.h", "+d,+e,+h", 0x58a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.w", "+d,+e,+h", 0x58c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.d", "+d,+e,+h", 0x58e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.b", "+d,+e,+h", 0x59000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.h", "+d,+e,+h", 0x59200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.w", "+d,+e,+h", 0x59400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.d", "+d,+e,+h", 0x59600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.b", "+d,+e,+h", 0x59800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.h", "+d,+e,+h", 0x59a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.w", "+d,+e,+h", 0x59c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.d", "+d,+e,+h", 0x59e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.b", "+d,+e,+h", 0x5a000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.h", "+d,+e,+h", 0x5a200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.w", "+d,+e,+h", 0x5a400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.d", "+d,+e,+h", 0x5a600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.b", "+d,+e,+h", 0x5a800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.h", "+d,+e,+h", 0x5aa00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.w", "+d,+e,+h", 0x5ac00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.d", "+d,+e,+h", 0x5ae00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.b", "+d,+e,+h", 0x5b000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.h", "+d,+e,+h", 0x5b200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.w", "+d,+e,+h", 0x5b400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.d", "+d,+e,+h", 0x5b600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.b", "+d,+e,+h", 0x5b800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.h", "+d,+e,+h", 0x5ba00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.w", "+d,+e,+h", 0x5bc00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.d", "+d,+e,+h", 0x5be00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.b", "+d,+e,+h", 0x58000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.h", "+d,+e,+h", 0x58200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.w", "+d,+e,+h", 0x58400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.d", "+d,+e,+h", 0x58600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.b", "+d,+e,+h", 0x58800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.h", "+d,+e,+h", 0x58a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.w", "+d,+e,+h", 0x58c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.d", "+d,+e,+h", 0x58e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.b", "+d,+e,+h", 0x59000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.h", "+d,+e,+h", 0x59200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.w", "+d,+e,+h", 0x59400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.d", "+d,+e,+h", 0x59600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.b", "+d,+e,+h", 0x59800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.h", "+d,+e,+h", 0x59a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.w", "+d,+e,+h", 0x59c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.d", "+d,+e,+h", 0x59e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.b", "+d,+e,+h", 0x5a000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.h", "+d,+e,+h", 0x5a200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.w", "+d,+e,+h", 0x5a400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.d", "+d,+e,+h", 0x5a600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.b", "+d,+e,+h", 0x5a800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.h", "+d,+e,+h", 0x5aa00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.w", "+d,+e,+h", 0x5ac00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.d", "+d,+e,+h", 0x5ae00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.b", "+d,+e,+h", 0x58000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.h", "+d,+e,+h", 0x58200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.w", "+d,+e,+h", 0x58400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.d", "+d,+e,+h", 0x58600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.b", "+d,+e,+h", 0x58800023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.h", "+d,+e,+h", 0x58a00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.w", "+d,+e,+h", 0x58c00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.d", "+d,+e,+h", 0x58e00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.b", "+d,+e,+h", 0x59000023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.h", "+d,+e,+h", 0x59200023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.w", "+d,+e,+h", 0x59400023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.d", "+d,+e,+h", 0x59600023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.b", "+d,+e,+h", 0x5a000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.h", "+d,+e,+h", 0x5a200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.w", "+d,+e,+h", 0x5a400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.d", "+d,+e,+h", 0x5a600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.b", "+d,+e,+h", 0x5a800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.h", "+d,+e,+h", 0x5aa00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.w", "+d,+e,+h", 0x5ac00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.d", "+d,+e,+h", 0x5ae00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.b", "+d,+e,+h", 0x5b000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.h", "+d,+e,+h", 0x5b200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.w", "+d,+e,+h", 0x5b400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.d", "+d,+e,+h", 0x5b600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.b", "+d,+e,+h", 0x5b800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.h", "+d,+e,+h", 0x5ba00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.w", "+d,+e,+h", 0x5bc00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.d", "+d,+e,+h", 0x5be00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.h", "+d,+e,+h", 0x58200033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.w", "+d,+e,+h", 0x58400033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.d", "+d,+e,+h", 0x58600033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.h", "+d,+e,+h", 0x58a00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.w", "+d,+e,+h", 0x58c00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.d", "+d,+e,+h", 0x58e00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.h", "+d,+e,+h", 0x59200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.w", "+d,+e,+h", 0x59400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.d", "+d,+e,+h", 0x59600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.h", "+d,+e,+h", 0x59a00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.w", "+d,+e,+h", 0x59c00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.d", "+d,+e,+h", 0x59e00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.h", "+d,+e,+h", 0x5a200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.w", "+d,+e,+h", 0x5a400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.d", "+d,+e,+h", 0x5a600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.h", "+d,+e,+h", 0x5aa00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.w", "+d,+e,+h", 0x5ac00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.d", "+d,+e,+h", 0x5ae00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.b", "+d,+e+*", 0x5800000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.h", "+d,+e+*", 0x5820000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.w", "+d,+e+*", 0x5840000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.d", "+d,+e+*", 0x5860000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sldi.b", "+d,+e+o", 0x58000016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.h", "+d,+e+u", 0x58200016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.w", "+d,+e+v", 0x58300016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.d", "+d,+e+w", 0x58380016, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"splat.b", "+d,+e+*", 0x5880000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.h", "+d,+e+*", 0x58a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.w", "+d,+e+*", 0x58c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.d", "+d,+e+*", 0x58e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splati.b", "+d,+e+o", 0x58400016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.h", "+d,+e+u", 0x58600016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.w", "+d,+e+v", 0x58700016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.d", "+d,+e+w", 0x58780016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pckev.b", "+d,+e,+h", 0x5900000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.h", "+d,+e,+h", 0x5920000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.w", "+d,+e,+h", 0x5940000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.d", "+d,+e,+h", 0x5960000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.b", "+d,+e,+h", 0x5980000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.h", "+d,+e,+h", 0x59a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.w", "+d,+e,+h", 0x59c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.d", "+d,+e,+h", 0x59e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.b", "+d,+e,+h", 0x5a00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.h", "+d,+e,+h", 0x5a20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.w", "+d,+e,+h", 0x5a40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.d", "+d,+e,+h", 0x5a60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.b", "+d,+e,+h", 0x5a80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.h", "+d,+e,+h", 0x5aa0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.w", "+d,+e,+h", 0x5ac0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.d", "+d,+e,+h", 0x5ae0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.b", "+d,+e,+h", 0x5b00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.h", "+d,+e,+h", 0x5b20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.w", "+d,+e,+h", 0x5b40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.d", "+d,+e,+h", 0x5b60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.b", "+d,+e,+h", 0x5b80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.h", "+d,+e,+h", 0x5ba0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.w", "+d,+e,+h", 0x5bc0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.d", "+d,+e,+h", 0x5be0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.b", "+d,+e,+h", 0x5800001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.h", "+d,+e,+h", 0x5820001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.w", "+d,+e,+h", 0x5840001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.d", "+d,+e,+h", 0x5860001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.b", "+d,+e,+h", 0x5880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.h", "+d,+e,+h", 0x58a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.w", "+d,+e,+h", 0x58c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.d", "+d,+e,+h", 0x58e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srari.b", "+d,+e,+!", 0x59700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.h", "+d,+e,+@", 0x59600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.w", "+d,+e,+x", 0x59400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.d", "+d,+e,+#", 0x59000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlr.b", "+d,+e,+h", 0x5900001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.h", "+d,+e,+h", 0x5920001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.w", "+d,+e,+h", 0x5940001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.d", "+d,+e,+h", 0x5960001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlri.b", "+d,+e,+!", 0x59f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.h", "+d,+e,+@", 0x59e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.w", "+d,+e,+x", 0x59c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.d", "+d,+e,+#", 0x59800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"hadd_s.h", "+d,+e,+h", 0x5a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_s.w", "+d,+e,+h", 0x5a40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_s.d", "+d,+e,+h", 0x5a60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.h", "+d,+e,+h", 0x5aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.w", "+d,+e,+h", 0x5ac0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.d", "+d,+e,+h", 0x5ae0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.h", "+d,+e,+h", 0x5b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.w", "+d,+e,+h", 0x5b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.d", "+d,+e,+h", 0x5b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.h", "+d,+e,+h", 0x5ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.w", "+d,+e,+h", 0x5bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.d", "+d,+e,+h", 0x5be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"and.v", "+d,+e,+h", 0x5800002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"andi.b", "+d,+e,+|", 0x58000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"or.v", "+d,+e,+h", 0x5820002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ori.b", "+d,+e,+|", 0x59000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nor.v", "+d,+e,+h", 0x5840002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"nori.b", "+d,+e,+|", 0x5a000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"xor.v", "+d,+e,+h", 0x5860002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"xori.b", "+d,+e,+|", 0x5b000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bmnz.v", "+d,+e,+h", 0x5880002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bmnzi.b", "+d,+e,+|", 0x58000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"bmz.v", "+d,+e,+h", 0x58a0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bmzi.b", "+d,+e,+|", 0x59000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"bsel.v", "+d,+e,+h", 0x58c0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bseli.b", "+d,+e,+|", 0x5a000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"shf.b", "+d,+e,+|", 0x58000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"shf.h", "+d,+e,+|", 0x59000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"shf.w", "+d,+e,+|", 0x5a000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnz.v", "+h,p", 0x81e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"fill.b", "+d,d", 0x5b00002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.h", "+d,d", 0x5b01002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.w", "+d,d", 0x5b02002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.d", "+d,d", 0x5b03002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"pcnt.b", "+d,+e", 0x5b04002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.h", "+d,+e", 0x5b05002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.w", "+d,+e", 0x5b06002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.d", "+d,+e", 0x5b07002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.b", "+d,+e", 0x5b08002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.h", "+d,+e", 0x5b09002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.w", "+d,+e", 0x5b0a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.d", "+d,+e", 0x5b0b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.b", "+d,+e", 0x5b0c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.h", "+d,+e", 0x5b0d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.w", "+d,+e", 0x5b0e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.d", "+d,+e", 0x5b0f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.b", "+k,+e+o", 0x58800016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.h", "+k,+e+u", 0x58a00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.w", "+k,+e+v", 0x58b00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.d", "+k,+e+w", 0x58b80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"copy_u.b", "+k,+e+o", 0x58c00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.h", "+k,+e+u", 0x58e00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.w", "+k,+e+v", 0x58f00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.d", "+k,+e+w", 0x58f80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"insert.b", "+d+o,d", 0x59000016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.h", "+d+u,d", 0x59200016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.w", "+d+v,d", 0x59300016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.d", "+d+w,d", 0x59380016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, -{"insve.b", "+d+o,+e+&", 0x59400016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.h", "+d+u,+e+&", 0x59600016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.w", "+d+v,+e+&", 0x59700016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.d", "+d+w,+e+&", 0x59780016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"bnz.b", "+h,p", 0x83800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.h", "+h,p", 0x83a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.w", "+h,p", 0x83c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.d", "+h,p", 0x83e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.b", "+h,p", 0x83000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.h", "+h,p", 0x83200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.w", "+h,p", 0x83400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.d", "+h,p", 0x83600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"fcaf.w", "+d,+e,+h", 0x58000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcaf.d", "+d,+e,+h", 0x58200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcun.w", "+d,+e,+h", 0x58400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcun.d", "+d,+e,+h", 0x58600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fceq.w", "+d,+e,+h", 0x58800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fceq.d", "+d,+e,+h", 0x58a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcueq.w", "+d,+e,+h", 0x58c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcueq.d", "+d,+e,+h", 0x58e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclt.w", "+d,+e,+h", 0x59000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclt.d", "+d,+e,+h", 0x59200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcult.w", "+d,+e,+h", 0x59400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcult.d", "+d,+e,+h", 0x59600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcle.w", "+d,+e,+h", 0x59800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcle.d", "+d,+e,+h", 0x59a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcule.w", "+d,+e,+h", 0x59c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcule.d", "+d,+e,+h", 0x59e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsaf.w", "+d,+e,+h", 0x5a000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsaf.d", "+d,+e,+h", 0x5a200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsun.w", "+d,+e,+h", 0x5a400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsun.d", "+d,+e,+h", 0x5a600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fseq.w", "+d,+e,+h", 0x5a800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fseq.d", "+d,+e,+h", 0x5aa00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsueq.w", "+d,+e,+h", 0x5ac00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsueq.d", "+d,+e,+h", 0x5ae00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fslt.w", "+d,+e,+h", 0x5b000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fslt.d", "+d,+e,+h", 0x5b200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsult.w", "+d,+e,+h", 0x5b400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsult.d", "+d,+e,+h", 0x5b600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsle.w", "+d,+e,+h", 0x5b800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsle.d", "+d,+e,+h", 0x5ba00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsule.w", "+d,+e,+h", 0x5bc00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsule.d", "+d,+e,+h", 0x5be00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fadd.w", "+d,+e,+h", 0x58000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fadd.d", "+d,+e,+h", 0x58200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsub.w", "+d,+e,+h", 0x58400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsub.d", "+d,+e,+h", 0x58600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmul.w", "+d,+e,+h", 0x58800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmul.d", "+d,+e,+h", 0x58a00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fdiv.w", "+d,+e,+h", 0x58c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fdiv.d", "+d,+e,+h", 0x58e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmadd.w", "+d,+e,+h", 0x59000036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmadd.d", "+d,+e,+h", 0x59200036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmsub.w", "+d,+e,+h", 0x59400036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmsub.d", "+d,+e,+h", 0x59600036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexp2.w", "+d,+e,+h", 0x59c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexp2.d", "+d,+e,+h", 0x59e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexdo.h", "+d,+e,+h", 0x5a000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexdo.w", "+d,+e,+h", 0x5a200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ftq.h", "+d,+e,+h", 0x5a800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ftq.w", "+d,+e,+h", 0x5aa00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin.w", "+d,+e,+h", 0x5b000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin.d", "+d,+e,+h", 0x5b200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin_a.w", "+d,+e,+h", 0x5b400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin_a.d", "+d,+e,+h", 0x5b600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax.w", "+d,+e,+h", 0x5b800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax.d", "+d,+e,+h", 0x5ba00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax_a.w", "+d,+e,+h", 0x5bc00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax_a.d", "+d,+e,+h", 0x5be00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcor.w", "+d,+e,+h", 0x5840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcor.d", "+d,+e,+h", 0x5860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcune.w", "+d,+e,+h", 0x5880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcune.d", "+d,+e,+h", 0x58a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcne.w", "+d,+e,+h", 0x58c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcne.d", "+d,+e,+h", 0x58e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mul_q.h", "+d,+e,+h", 0x5900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mul_q.w", "+d,+e,+h", 0x5920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"madd_q.h", "+d,+e,+h", 0x5940000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"madd_q.w", "+d,+e,+h", 0x5960000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msub_q.h", "+d,+e,+h", 0x5980000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msub_q.w", "+d,+e,+h", 0x59a0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsor.w", "+d,+e,+h", 0x5a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsor.d", "+d,+e,+h", 0x5a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsune.w", "+d,+e,+h", 0x5a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsune.d", "+d,+e,+h", 0x5aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsne.w", "+d,+e,+h", 0x5ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsne.d", "+d,+e,+h", 0x5ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulr_q.h", "+d,+e,+h", 0x5b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulr_q.w", "+d,+e,+h", 0x5b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddr_q.h", "+d,+e,+h", 0x5b40000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddr_q.w", "+d,+e,+h", 0x5b60000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubr_q.h", "+d,+e,+h", 0x5b80000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubr_q.w", "+d,+e,+h", 0x5ba0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclass.w", "+d,+e", 0x5b20002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fclass.d", "+d,+e", 0x5b21002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_s.w", "+d,+e", 0x5b22002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_s.d", "+d,+e", 0x5b23002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_u.w", "+d,+e", 0x5b24002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_u.d", "+d,+e", 0x5b25002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fsqrt.w", "+d,+e", 0x5b26002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fsqrt.d", "+d,+e", 0x5b27002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frsqrt.w", "+d,+e", 0x5b28002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frsqrt.d", "+d,+e", 0x5b29002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frcp.w", "+d,+e", 0x5b2a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frcp.d", "+d,+e", 0x5b2b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frint.w", "+d,+e", 0x5b2c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frint.d", "+d,+e", 0x5b2d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"flog2.w", "+d,+e", 0x5b2e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"flog2.d", "+d,+e", 0x5b2f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupl.w", "+d,+e", 0x5b30002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupl.d", "+d,+e", 0x5b31002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupr.w", "+d,+e", 0x5b32002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupr.d", "+d,+e", 0x5b33002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffql.w", "+d,+e", 0x5b34002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffql.d", "+d,+e", 0x5b35002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffqr.w", "+d,+e", 0x5b36002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffqr.d", "+d,+e", 0x5b37002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_s.w", "+d,+e", 0x5b38002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_s.d", "+d,+e", 0x5b39002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_u.w", "+d,+e", 0x5b3a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_u.d", "+d,+e", 0x5b3b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_s.w", "+d,+e", 0x5b3c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_s.d", "+d,+e", 0x5b3d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_u.w", "+d,+e", 0x5b3e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_u.d", "+d,+e", 0x5b3f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 }, -{"cfcmsa", "+k,+n", 0x587e0016, 0xffff003f, WR_1, 0, 0, MSA, 0 }, -{"move.v", "+d,+e", 0x58be0016, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 }, +{ "sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "slli.b", "+d,+e,+!", 0x58700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.h", "+d,+e,+@", 0x58600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.w", "+d,+e,+x", 0x58400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.d", "+d,+e,+#", 0x58000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sra.b", "+d,+e,+h", 0x5880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.h", "+d,+e,+h", 0x58a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.w", "+d,+e,+h", 0x58c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.d", "+d,+e,+h", 0x58e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srai.b", "+d,+e,+!", 0x58f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.h", "+d,+e,+@", 0x58e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.w", "+d,+e,+x", 0x58c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.d", "+d,+e,+#", 0x58800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srl.b", "+d,+e,+h", 0x5900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.h", "+d,+e,+h", 0x5920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.w", "+d,+e,+h", 0x5940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.d", "+d,+e,+h", 0x5960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srli.b", "+d,+e,+!", 0x59700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.h", "+d,+e,+@", 0x59600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.w", "+d,+e,+x", 0x59400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.d", "+d,+e,+#", 0x59000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclr.b", "+d,+e,+h", 0x5980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.h", "+d,+e,+h", 0x59a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.w", "+d,+e,+h", 0x59c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.d", "+d,+e,+h", 0x59e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclri.b", "+d,+e,+!", 0x59f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.h", "+d,+e,+@", 0x59e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.w", "+d,+e,+x", 0x59c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.d", "+d,+e,+#", 0x59800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bset.b", "+d,+e,+h", 0x5a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.h", "+d,+e,+h", 0x5a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.w", "+d,+e,+h", 0x5a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.d", "+d,+e,+h", 0x5a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bseti.b", "+d,+e,+!", 0x5a700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.h", "+d,+e,+@", 0x5a600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.w", "+d,+e,+x", 0x5a400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.d", "+d,+e,+#", 0x5a000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bneg.b", "+d,+e,+h", 0x5a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.h", "+d,+e,+h", 0x5aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.w", "+d,+e,+h", 0x5ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.d", "+d,+e,+h", 0x5ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bnegi.b", "+d,+e,+!", 0x5af00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.h", "+d,+e,+@", 0x5ae00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.w", "+d,+e,+x", 0x5ac00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.d", "+d,+e,+#", 0x5a800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "binsl.b", "+d,+e,+h", 0x5b00001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.h", "+d,+e,+h", 0x5b20001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.w", "+d,+e,+h", 0x5b40001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.d", "+d,+e,+h", 0x5b60001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsli.b", "+d,+e,+!", 0x5b700012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.h", "+d,+e,+@", 0x5b600012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.w", "+d,+e,+x", 0x5b400012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.d", "+d,+e,+#", 0x5b000012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsr.b", "+d,+e,+h", 0x5b80001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.h", "+d,+e,+h", 0x5ba0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.w", "+d,+e,+h", 0x5bc0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.d", "+d,+e,+h", 0x5be0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsri.b", "+d,+e,+!", 0x5bf00012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.h", "+d,+e,+@", 0x5be00012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.w", "+d,+e,+x", 0x5bc00012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.d", "+d,+e,+#", 0x5b800012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "addv.b", "+d,+e,+h", 0x5800002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.h", "+d,+e,+h", 0x5820002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.w", "+d,+e,+h", 0x5840002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.d", "+d,+e,+h", 0x5860002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addvi.b", "+d,+e,+$", 0x58000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.h", "+d,+e,+$", 0x58200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.w", "+d,+e,+$", 0x58400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.d", "+d,+e,+$", 0x58600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subv.b", "+d,+e,+h", 0x5880002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.h", "+d,+e,+h", 0x58a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.w", "+d,+e,+h", 0x58c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.d", "+d,+e,+h", 0x58e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subvi.b", "+d,+e,+$", 0x58800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.h", "+d,+e,+$", 0x58a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.w", "+d,+e,+$", 0x58c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.d", "+d,+e,+$", 0x58e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_s.b", "+d,+e,+h", 0x5900002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.h", "+d,+e,+h", 0x5920002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.w", "+d,+e,+h", 0x5940002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.d", "+d,+e,+h", 0x5960002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maxi_s.b", "+d,+e,+%", 0x59000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.h", "+d,+e,+%", 0x59200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.w", "+d,+e,+%", 0x59400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.d", "+d,+e,+%", 0x59600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_u.b", "+d,+e,+h", 0x5980002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.h", "+d,+e,+h", 0x59a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.w", "+d,+e,+h", 0x59c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.d", "+d,+e,+h", 0x59e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maxi_u.b", "+d,+e,+$", 0x59800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.h", "+d,+e,+$", 0x59a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.w", "+d,+e,+$", 0x59c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.d", "+d,+e,+$", 0x59e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "min_s.b", "+d,+e,+h", 0x5a00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.h", "+d,+e,+h", 0x5a20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.w", "+d,+e,+h", 0x5a40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.d", "+d,+e,+h", 0x5a60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mini_s.b", "+d,+e,+%", 0x5a000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.h", "+d,+e,+%", 0x5a200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.w", "+d,+e,+%", 0x5a400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.d", "+d,+e,+%", 0x5a600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "min_u.b", "+d,+e,+h", 0x5a80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.h", "+d,+e,+h", 0x5aa0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.w", "+d,+e,+h", 0x5ac0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.d", "+d,+e,+h", 0x5ae0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mini_u.b", "+d,+e,+$", 0x5a800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.h", "+d,+e,+$", 0x5aa00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.w", "+d,+e,+$", 0x5ac00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.d", "+d,+e,+$", 0x5ae00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_a.b", "+d,+e,+h", 0x5b00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.h", "+d,+e,+h", 0x5b20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.w", "+d,+e,+h", 0x5b40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.d", "+d,+e,+h", 0x5b60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.b", "+d,+e,+h", 0x5b80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.h", "+d,+e,+h", 0x5ba0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.w", "+d,+e,+h", 0x5bc0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.d", "+d,+e,+h", 0x5be0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.b", "+d,+e,+h", 0x5800003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.h", "+d,+e,+h", 0x5820003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.w", "+d,+e,+h", 0x5840003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.d", "+d,+e,+h", 0x5860003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceqi.b", "+d,+e,+%", 0x58000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.h", "+d,+e,+%", 0x58200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.w", "+d,+e,+%", 0x58400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.d", "+d,+e,+%", 0x58600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clt_s.b", "+d,+e,+h", 0x5900003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.h", "+d,+e,+h", 0x5920003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.w", "+d,+e,+h", 0x5940003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.d", "+d,+e,+h", 0x5960003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clti_s.b", "+d,+e,+%", 0x59000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.h", "+d,+e,+%", 0x59200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.w", "+d,+e,+%", 0x59400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.d", "+d,+e,+%", 0x59600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clt_u.b", "+d,+e,+h", 0x5980003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.h", "+d,+e,+h", 0x59a0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.w", "+d,+e,+h", 0x59c0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.d", "+d,+e,+h", 0x59e0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clti_u.b", "+d,+e,+$", 0x59800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.h", "+d,+e,+$", 0x59a00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.w", "+d,+e,+$", 0x59c00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.d", "+d,+e,+$", 0x59e00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "cle_s.b", "+d,+e,+h", 0x5a00003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.h", "+d,+e,+h", 0x5a20003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.w", "+d,+e,+h", 0x5a40003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.d", "+d,+e,+h", 0x5a60003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clei_s.b", "+d,+e,+%", 0x5a000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.h", "+d,+e,+%", 0x5a200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.w", "+d,+e,+%", 0x5a400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.d", "+d,+e,+%", 0x5a600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "cle_u.b", "+d,+e,+h", 0x5a80003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.h", "+d,+e,+h", 0x5aa0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.w", "+d,+e,+h", 0x5ac0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.d", "+d,+e,+h", 0x5ae0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clei_u.b", "+d,+e,+$", 0x5a800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.d", "+d,+W(d)", 0x5800003f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "sat_s.b", "+d,+e,+!", 0x58700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.h", "+d,+e,+@", 0x58600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.w", "+d,+e,+x", 0x58400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.d", "+d,+e,+#", 0x58000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.b", "+d,+e,+!", 0x58f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.h", "+d,+e,+@", 0x58e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.w", "+d,+e,+x", 0x58c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.d", "+d,+e,+#", 0x58800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "add_a.b", "+d,+e,+h", 0x58000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.h", "+d,+e,+h", 0x58200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.w", "+d,+e,+h", 0x58400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.d", "+d,+e,+h", 0x58600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.b", "+d,+e,+h", 0x58800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.h", "+d,+e,+h", 0x58a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.w", "+d,+e,+h", 0x58c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.d", "+d,+e,+h", 0x58e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.b", "+d,+e,+h", 0x59000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.h", "+d,+e,+h", 0x59200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.w", "+d,+e,+h", 0x59400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.d", "+d,+e,+h", 0x59600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.b", "+d,+e,+h", 0x59800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.h", "+d,+e,+h", 0x59a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.w", "+d,+e,+h", 0x59c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.d", "+d,+e,+h", 0x59e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.b", "+d,+e,+h", 0x5a000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.h", "+d,+e,+h", 0x5a200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.w", "+d,+e,+h", 0x5a400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.d", "+d,+e,+h", 0x5a600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.b", "+d,+e,+h", 0x5a800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.h", "+d,+e,+h", 0x5aa00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.w", "+d,+e,+h", 0x5ac00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.d", "+d,+e,+h", 0x5ae00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.b", "+d,+e,+h", 0x5b000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.h", "+d,+e,+h", 0x5b200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.w", "+d,+e,+h", 0x5b400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.d", "+d,+e,+h", 0x5b600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.b", "+d,+e,+h", 0x5b800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.h", "+d,+e,+h", 0x5ba00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.w", "+d,+e,+h", 0x5bc00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.d", "+d,+e,+h", 0x5be00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.b", "+d,+e,+h", 0x58000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.h", "+d,+e,+h", 0x58200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.w", "+d,+e,+h", 0x58400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.d", "+d,+e,+h", 0x58600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.b", "+d,+e,+h", 0x58800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.h", "+d,+e,+h", 0x58a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.w", "+d,+e,+h", 0x58c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.d", "+d,+e,+h", 0x58e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.b", "+d,+e,+h", 0x59000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.h", "+d,+e,+h", 0x59200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.w", "+d,+e,+h", 0x59400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.d", "+d,+e,+h", 0x59600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.b", "+d,+e,+h", 0x59800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.h", "+d,+e,+h", 0x59a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.w", "+d,+e,+h", 0x59c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.d", "+d,+e,+h", 0x59e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.b", "+d,+e,+h", 0x5a000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.h", "+d,+e,+h", 0x5a200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.w", "+d,+e,+h", 0x5a400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.d", "+d,+e,+h", 0x5a600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.b", "+d,+e,+h", 0x5a800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.h", "+d,+e,+h", 0x5aa00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.w", "+d,+e,+h", 0x5ac00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.d", "+d,+e,+h", 0x5ae00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.b", "+d,+e,+h", 0x58000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.h", "+d,+e,+h", 0x58200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.w", "+d,+e,+h", 0x58400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.d", "+d,+e,+h", 0x58600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.b", "+d,+e,+h", 0x58800023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.h", "+d,+e,+h", 0x58a00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.w", "+d,+e,+h", 0x58c00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.d", "+d,+e,+h", 0x58e00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.b", "+d,+e,+h", 0x59000023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.h", "+d,+e,+h", 0x59200023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.w", "+d,+e,+h", 0x59400023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.d", "+d,+e,+h", 0x59600023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.b", "+d,+e,+h", 0x5a000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.h", "+d,+e,+h", 0x5a200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.w", "+d,+e,+h", 0x5a400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.d", "+d,+e,+h", 0x5a600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.b", "+d,+e,+h", 0x5a800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.h", "+d,+e,+h", 0x5aa00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.w", "+d,+e,+h", 0x5ac00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.d", "+d,+e,+h", 0x5ae00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.b", "+d,+e,+h", 0x5b000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.h", "+d,+e,+h", 0x5b200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.w", "+d,+e,+h", 0x5b400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.d", "+d,+e,+h", 0x5b600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.b", "+d,+e,+h", 0x5b800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.h", "+d,+e,+h", 0x5ba00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.w", "+d,+e,+h", 0x5bc00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.d", "+d,+e,+h", 0x5be00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.h", "+d,+e,+h", 0x58200033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.w", "+d,+e,+h", 0x58400033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.d", "+d,+e,+h", 0x58600033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.h", "+d,+e,+h", 0x58a00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.w", "+d,+e,+h", 0x58c00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.d", "+d,+e,+h", 0x58e00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.h", "+d,+e,+h", 0x59200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.w", "+d,+e,+h", 0x59400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.d", "+d,+e,+h", 0x59600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.h", "+d,+e,+h", 0x59a00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.w", "+d,+e,+h", 0x59c00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.d", "+d,+e,+h", 0x59e00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.h", "+d,+e,+h", 0x5a200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.w", "+d,+e,+h", 0x5a400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.d", "+d,+e,+h", 0x5a600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.h", "+d,+e,+h", 0x5aa00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.w", "+d,+e,+h", 0x5ac00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.d", "+d,+e,+h", 0x5ae00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.b", "+d,+e+*", 0x5800000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.h", "+d,+e+*", 0x5820000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.w", "+d,+e+*", 0x5840000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.d", "+d,+e+*", 0x5860000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sldi.b", "+d,+e+o", 0x58000016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.h", "+d,+e+u", 0x58200016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.w", "+d,+e+v", 0x58300016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.d", "+d,+e+w", 0x58380016, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "splat.b", "+d,+e+*", 0x5880000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.h", "+d,+e+*", 0x58a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.w", "+d,+e+*", 0x58c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.d", "+d,+e+*", 0x58e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splati.b", "+d,+e+o", 0x58400016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.h", "+d,+e+u", 0x58600016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.w", "+d,+e+v", 0x58700016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.d", "+d,+e+w", 0x58780016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pckev.b", "+d,+e,+h", 0x5900000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.h", "+d,+e,+h", 0x5920000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.w", "+d,+e,+h", 0x5940000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.d", "+d,+e,+h", 0x5960000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.b", "+d,+e,+h", 0x5980000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.h", "+d,+e,+h", 0x59a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.w", "+d,+e,+h", 0x59c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.d", "+d,+e,+h", 0x59e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.b", "+d,+e,+h", 0x5a00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.h", "+d,+e,+h", 0x5a20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.w", "+d,+e,+h", 0x5a40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.d", "+d,+e,+h", 0x5a60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.b", "+d,+e,+h", 0x5a80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.h", "+d,+e,+h", 0x5aa0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.w", "+d,+e,+h", 0x5ac0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.d", "+d,+e,+h", 0x5ae0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.b", "+d,+e,+h", 0x5b00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.h", "+d,+e,+h", 0x5b20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.w", "+d,+e,+h", 0x5b40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.d", "+d,+e,+h", 0x5b60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.b", "+d,+e,+h", 0x5b80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.h", "+d,+e,+h", 0x5ba0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.w", "+d,+e,+h", 0x5bc0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.d", "+d,+e,+h", 0x5be0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.b", "+d,+e,+h", 0x5800001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.h", "+d,+e,+h", 0x5820001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.w", "+d,+e,+h", 0x5840001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.d", "+d,+e,+h", 0x5860001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.b", "+d,+e,+h", 0x5880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.h", "+d,+e,+h", 0x58a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.w", "+d,+e,+h", 0x58c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.d", "+d,+e,+h", 0x58e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srari.b", "+d,+e,+!", 0x59700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.h", "+d,+e,+@", 0x59600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.w", "+d,+e,+x", 0x59400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.d", "+d,+e,+#", 0x59000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlr.b", "+d,+e,+h", 0x5900001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.h", "+d,+e,+h", 0x5920001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.w", "+d,+e,+h", 0x5940001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.d", "+d,+e,+h", 0x5960001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlri.b", "+d,+e,+!", 0x59f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.h", "+d,+e,+@", 0x59e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.w", "+d,+e,+x", 0x59c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.d", "+d,+e,+#", 0x59800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "hadd_s.h", "+d,+e,+h", 0x5a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_s.w", "+d,+e,+h", 0x5a40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_s.d", "+d,+e,+h", 0x5a60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.h", "+d,+e,+h", 0x5aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.w", "+d,+e,+h", 0x5ac0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.d", "+d,+e,+h", 0x5ae0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.h", "+d,+e,+h", 0x5b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.w", "+d,+e,+h", 0x5b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.d", "+d,+e,+h", 0x5b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.h", "+d,+e,+h", 0x5ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.w", "+d,+e,+h", 0x5bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.d", "+d,+e,+h", 0x5be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "and.v", "+d,+e,+h", 0x5800002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "andi.b", "+d,+e,+|", 0x58000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "or.v", "+d,+e,+h", 0x5820002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ori.b", "+d,+e,+|", 0x59000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nor.v", "+d,+e,+h", 0x5840002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "nori.b", "+d,+e,+|", 0x5a000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "xor.v", "+d,+e,+h", 0x5860002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "xori.b", "+d,+e,+|", 0x5b000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bmnz.v", "+d,+e,+h", 0x5880002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bmnzi.b", "+d,+e,+|", 0x58000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "bmz.v", "+d,+e,+h", 0x58a0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bmzi.b", "+d,+e,+|", 0x59000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "bsel.v", "+d,+e,+h", 0x58c0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bseli.b", "+d,+e,+|", 0x5a000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.b", "+d,+e,+|", 0x58000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.h", "+d,+e,+|", 0x59000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.w", "+d,+e,+|", 0x5a000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnz.v", "+h,p", 0x81e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "fill.b", "+d,d", 0x5b00002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.h", "+d,d", 0x5b01002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.w", "+d,d", 0x5b02002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.d", "+d,d", 0x5b03002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "pcnt.b", "+d,+e", 0x5b04002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.h", "+d,+e", 0x5b05002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.w", "+d,+e", 0x5b06002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.d", "+d,+e", 0x5b07002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.b", "+d,+e", 0x5b08002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.h", "+d,+e", 0x5b09002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.w", "+d,+e", 0x5b0a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.d", "+d,+e", 0x5b0b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.b", "+d,+e", 0x5b0c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.h", "+d,+e", 0x5b0d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.w", "+d,+e", 0x5b0e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.d", "+d,+e", 0x5b0f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.b", "+k,+e+o", 0x58800016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.h", "+k,+e+u", 0x58a00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.w", "+k,+e+v", 0x58b00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.d", "+k,+e+w", 0x58b80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "copy_u.b", "+k,+e+o", 0x58c00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_u.h", "+k,+e+u", 0x58e00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_u.w", "+k,+e+v", 0x58f00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_u.d", "+k,+e+w", 0x58f80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "insert.b", "+d+o,d", 0x59000016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.h", "+d+u,d", 0x59200016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.w", "+d+v,d", 0x59300016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.d", "+d+w,d", 0x59380016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{ "insve.b", "+d+o,+e+&", 0x59400016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.h", "+d+u,+e+&", 0x59600016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.w", "+d+v,+e+&", 0x59700016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.d", "+d+w,+e+&", 0x59780016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "bnz.b", "+h,p", 0x83800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.h", "+h,p", 0x83a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.w", "+h,p", 0x83c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.d", "+h,p", 0x83e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.b", "+h,p", 0x83000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.h", "+h,p", 0x83200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.w", "+h,p", 0x83400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.d", "+h,p", 0x83600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "fcaf.w", "+d,+e,+h", 0x58000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcaf.d", "+d,+e,+h", 0x58200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcun.w", "+d,+e,+h", 0x58400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcun.d", "+d,+e,+h", 0x58600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fceq.w", "+d,+e,+h", 0x58800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fceq.d", "+d,+e,+h", 0x58a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcueq.w", "+d,+e,+h", 0x58c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcueq.d", "+d,+e,+h", 0x58e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclt.w", "+d,+e,+h", 0x59000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclt.d", "+d,+e,+h", 0x59200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcult.w", "+d,+e,+h", 0x59400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcult.d", "+d,+e,+h", 0x59600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcle.w", "+d,+e,+h", 0x59800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcle.d", "+d,+e,+h", 0x59a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcule.w", "+d,+e,+h", 0x59c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcule.d", "+d,+e,+h", 0x59e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsaf.w", "+d,+e,+h", 0x5a000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsaf.d", "+d,+e,+h", 0x5a200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsun.w", "+d,+e,+h", 0x5a400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsun.d", "+d,+e,+h", 0x5a600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fseq.w", "+d,+e,+h", 0x5a800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fseq.d", "+d,+e,+h", 0x5aa00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsueq.w", "+d,+e,+h", 0x5ac00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsueq.d", "+d,+e,+h", 0x5ae00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fslt.w", "+d,+e,+h", 0x5b000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fslt.d", "+d,+e,+h", 0x5b200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsult.w", "+d,+e,+h", 0x5b400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsult.d", "+d,+e,+h", 0x5b600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsle.w", "+d,+e,+h", 0x5b800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsle.d", "+d,+e,+h", 0x5ba00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsule.w", "+d,+e,+h", 0x5bc00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsule.d", "+d,+e,+h", 0x5be00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fadd.w", "+d,+e,+h", 0x58000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fadd.d", "+d,+e,+h", 0x58200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsub.w", "+d,+e,+h", 0x58400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsub.d", "+d,+e,+h", 0x58600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmul.w", "+d,+e,+h", 0x58800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmul.d", "+d,+e,+h", 0x58a00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fdiv.w", "+d,+e,+h", 0x58c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fdiv.d", "+d,+e,+h", 0x58e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmadd.w", "+d,+e,+h", 0x59000036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmadd.d", "+d,+e,+h", 0x59200036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmsub.w", "+d,+e,+h", 0x59400036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmsub.d", "+d,+e,+h", 0x59600036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexp2.w", "+d,+e,+h", 0x59c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexp2.d", "+d,+e,+h", 0x59e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexdo.h", "+d,+e,+h", 0x5a000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexdo.w", "+d,+e,+h", 0x5a200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ftq.h", "+d,+e,+h", 0x5a800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ftq.w", "+d,+e,+h", 0x5aa00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin.w", "+d,+e,+h", 0x5b000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin.d", "+d,+e,+h", 0x5b200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin_a.w", "+d,+e,+h", 0x5b400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin_a.d", "+d,+e,+h", 0x5b600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax.w", "+d,+e,+h", 0x5b800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax.d", "+d,+e,+h", 0x5ba00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax_a.w", "+d,+e,+h", 0x5bc00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax_a.d", "+d,+e,+h", 0x5be00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcor.w", "+d,+e,+h", 0x5840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcor.d", "+d,+e,+h", 0x5860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcune.w", "+d,+e,+h", 0x5880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcune.d", "+d,+e,+h", 0x58a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcne.w", "+d,+e,+h", 0x58c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcne.d", "+d,+e,+h", 0x58e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mul_q.h", "+d,+e,+h", 0x5900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mul_q.w", "+d,+e,+h", 0x5920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "madd_q.h", "+d,+e,+h", 0x5940000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "madd_q.w", "+d,+e,+h", 0x5960000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msub_q.h", "+d,+e,+h", 0x5980000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msub_q.w", "+d,+e,+h", 0x59a0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsor.w", "+d,+e,+h", 0x5a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsor.d", "+d,+e,+h", 0x5a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsune.w", "+d,+e,+h", 0x5a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsune.d", "+d,+e,+h", 0x5aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsne.w", "+d,+e,+h", 0x5ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsne.d", "+d,+e,+h", 0x5ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulr_q.h", "+d,+e,+h", 0x5b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulr_q.w", "+d,+e,+h", 0x5b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddr_q.h", "+d,+e,+h", 0x5b40000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddr_q.w", "+d,+e,+h", 0x5b60000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubr_q.h", "+d,+e,+h", 0x5b80000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubr_q.w", "+d,+e,+h", 0x5ba0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclass.w", "+d,+e", 0x5b20002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fclass.d", "+d,+e", 0x5b21002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_s.w", "+d,+e", 0x5b22002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_s.d", "+d,+e", 0x5b23002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_u.w", "+d,+e", 0x5b24002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_u.d", "+d,+e", 0x5b25002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fsqrt.w", "+d,+e", 0x5b26002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fsqrt.d", "+d,+e", 0x5b27002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frsqrt.w", "+d,+e", 0x5b28002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frsqrt.d", "+d,+e", 0x5b29002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frcp.w", "+d,+e", 0x5b2a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frcp.d", "+d,+e", 0x5b2b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frint.w", "+d,+e", 0x5b2c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frint.d", "+d,+e", 0x5b2d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "flog2.w", "+d,+e", 0x5b2e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "flog2.d", "+d,+e", 0x5b2f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupl.w", "+d,+e", 0x5b30002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupl.d", "+d,+e", 0x5b31002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupr.w", "+d,+e", 0x5b32002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupr.d", "+d,+e", 0x5b33002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffql.w", "+d,+e", 0x5b34002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffql.d", "+d,+e", 0x5b35002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffqr.w", "+d,+e", 0x5b36002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffqr.d", "+d,+e", 0x5b37002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_s.w", "+d,+e", 0x5b38002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_s.d", "+d,+e", 0x5b39002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_u.w", "+d,+e", 0x5b3a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_u.d", "+d,+e", 0x5b3b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_s.w", "+d,+e", 0x5b3c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_s.d", "+d,+e", 0x5b3d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_u.w", "+d,+e", 0x5b3e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_u.d", "+d,+e", 0x5b3f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 }, +{ "cfcmsa", "+k,+n", 0x587e0016, 0xffff003f, WR_1, 0, 0, MSA, 0 }, +{ "move.v", "+d,+e", 0x58be0016, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 }, }; const int bfd_micromips_num_opcodes = diff --git a/libr/asm/arch/mips/gnu/mips-opc.c b/libr/asm/arch/mips/gnu/mips-opc.c index 739630c712..c80ece8c3f 100644 --- a/libr/asm/arch/mips/gnu/mips-opc.c +++ b/libr/asm/arch/mips/gnu/mips-opc.c @@ -447,2977 +447,2977 @@ const struct mips_opcode mips_builtin_opcodes[] = them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"pref", "k,+j(b)", 0x7c000035, 0xfc00007f, RD_3, 0, I37, 0, 0 }, -{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3|LM, 0, I4_32|G3, 0, I37 }, -{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 }, -{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I4_33, 0, I37 }, -{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ -{"li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ -{"li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ -{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, -{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, -{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */ -{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */ -{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */ -{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */ -{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */ -{"bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/ -{"bc", "+'", 0xc8000000, 0xfc000000, NODS, 0, I37, 0, 0 }, -{"balc", "+'", 0xe8000000, 0xfc000000, WR_31|NODS, 0, I37, 0, 0 }, -{"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, -{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "pref", "k,+j(b)", 0x7c000035, 0xfc00007f, RD_3, 0, I37, 0, 0 }, +{ "pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3|LM, 0, I4_32|G3, 0, I37 }, +{ "pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 }, +{ "prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I4_33, 0, I37 }, +{ "nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ +{ "li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */ +{ "li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */ +{ "li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 }, +{ "move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 }, +{ "move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */ +{ "move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */ +{ "move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */ +{ "b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */ +{ "b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */ +{ "bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/ +{ "bc", "+'", 0xc8000000, 0xfc000000, NODS, 0, I37, 0, 0 }, +{ "balc", "+'", 0xe8000000, 0xfc000000, WR_31|NODS, 0, I37, 0, 0 }, +{ "lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, +{ "la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, /* Loongson specific instructions. Loongson gs464 (aka loongson3a) redefines the Coprocessor 2 instructions. Put them here so that disassembler will find them first. The assemblers uses a hash table based on the instruction name anyhow. */ -{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, -{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, -{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 }, -{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, -{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, -{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, -{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, -{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, -{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, -{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, -{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, -{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, -{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, -{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, -{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, -{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, -{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, -{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, -{"cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, -{"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, -{"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, -{"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{ "campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{ "campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{ "camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 }, +{ "ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{ "gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, +{ "gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 }, +{ "gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 }, +{ "gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 }, +{ "gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, +{ "gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, +{ "gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, +{ "cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{ "ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{ "dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{ "dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, /* R5900 VU0 Macromode instructions. */ -{"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vadd", "+5+K,+6+K,+7+K", 0x4a000028, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddi", "+5+K,+6+K,+y", 0x4a000022, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddq", "+5+K,+6+K,+q", 0x4a000020, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddw", "+5+K,+6+K,+7+N", 0x4a000003, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddx", "+5+K,+6+K,+7+N", 0x4a000000, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddy", "+5+K,+6+K,+7+N", 0x4a000001, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vaddz", "+5+K,+6+K,+7+N", 0x4a000002, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vadda", "+m+K,+7+K,+6+K", 0x4a0002bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vaddai", "+m+K,+6+K,+y", 0x4a00023e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vaddaq", "+m+K,+6+K,+q", 0x4a00023c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vaddaw", "+m+K,+6+K,+7+N", 0x4a00003f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vaddax", "+m+K,+6+K,+7+N", 0x4a00003c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vadday", "+m+K,+6+K,+7+N", 0x4a00003d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vaddaz", "+m+K,+6+K,+7+N", 0x4a00003e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vcallms", "+f", 0x4a000038, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"vcallmsr", "+9", 0x4a000039, 0xffff07ff, CP, 0, VU0, 0, 0 }, -{"vclipw.xyz", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vclipw", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vdiv", "+q,+6+L,+7+M", 0x4a0003bc, 0xfe0007ff, CP, 0, VU0, 0, 0 }, -{"vftoi0", "+7+K,+6+K", 0x4a00017c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vftoi4", "+7+K,+6+K", 0x4a00017d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vftoi12", "+7+K,+6+K", 0x4a00017e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vftoi15", "+7+K,+6+K", 0x4a00017f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"viadd", "+8,+9,+0", 0x4a000030, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"viaddi", "+0,+9,+g", 0x4a000032, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"viand", "+8,+9,+0", 0x4a000034, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"vilwr.w", "+0,(+9)", 0x4a2003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vilwr.x", "+0,(+9)", 0x4b0003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vilwr.y", "+0,(+9)", 0x4a8003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vilwr.z", "+0,(+9)", 0x4a4003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vior", "+8,+9,+0", 0x4a000035, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"viswr.w", "+0,(+9)", 0x4a2003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"viswr.x", "+0,(+9)", 0x4b0003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"viswr.y", "+0,(+9)", 0x4a8003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"viswr.z", "+0,(+9)", 0x4a4003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"visub", "+8,+9,+0", 0x4a000031, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"vitof0", "+7+K,+6+K", 0x4a00013c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vitof4", "+7+K,+6+K", 0x4a00013d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vitof12", "+7+K,+6+K", 0x4a00013e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vitof15", "+7+K,+6+K", 0x4a00013f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vlqd", "+7+K,(#-+9)", 0x4a00037e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vlqi", "+7+K,(+9#+)", 0x4a00037c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmadd", "+5+K,+6+K,+7+K", 0x4a000029, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddi", "+5+K,+6+K,+y", 0x4a000023, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddq", "+5+K,+6+K,+q", 0x4a000021, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddw", "+5+K,+6+K,+7+N", 0x4a00000b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddx", "+5+K,+6+K,+7+N", 0x4a000008, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddy", "+5+K,+6+K,+7+N", 0x4a000009, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaddz", "+5+K,+6+K,+7+N", 0x4a00000a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmadda", "+m+K,+6+K,+7+K", 0x4a0002bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmaddai", "+m+K,+6+K,+y", 0x4a00023f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmaddaq", "+m+K,+6+K,+q", 0x4a00023d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmaddaw", "+m+K,+6+K,+7+N", 0x4a0000bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmaddax", "+m+K,+6+K,+7+N", 0x4a0000bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmadday", "+m+K,+6+K,+7+N", 0x4a0000bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmaddaz", "+m+K,+6+K,+7+N", 0x4a0000be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmax", "+5+K,+6+K,+7+K", 0x4a00002b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaxi", "+5+K,+6+K,+y", 0x4a00001d, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaxw", "+5+K,+6+K,+7+N", 0x4a000013, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaxx", "+5+K,+6+K,+7+N", 0x4a000010, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaxy", "+5+K,+6+K,+7+N", 0x4a000011, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmaxz", "+5+K,+6+K,+7+N", 0x4a000012, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmfir", "+7+K,+9", 0x4a0003fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmini", "+5+K,+6+K,+7+K", 0x4a00002f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vminii", "+5+K,+6+K,+y", 0x4a00001f, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vminiw", "+5+K,+6+K,+7+N", 0x4a000017, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vminix", "+5+K,+6+K,+7+N", 0x4a000014, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vminiy", "+5+K,+6+K,+7+N", 0x4a000015, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vminiz", "+5+K,+6+K,+7+N", 0x4a000016, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmove", "+7+K,+6+K", 0x4a00033c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmr32", "+7+K,+6+K", 0x4a00033d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsub", "+5+K,+6+K,+7+K", 0x4a00002d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsubi", "+5+K,+6+K,+y", 0x4a000027, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsubq", "+5+K,+6+K,+q", 0x4a000025, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsubw", "+5+K,+6+K,+7+N", 0x4a00000f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsubx", "+5+K,+6+K,+7+N", 0x4a00000c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsuby", "+5+K,+6+K,+7+N", 0x4a00000d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsubz", "+5+K,+6+K,+7+N", 0x4a00000e, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmsuba", "+m+K,+7+K,+6+K", 0x4a0002fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubai", "+m+K,+6+K,+y", 0x4a00027f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubaq", "+m+K,+6+K,+q", 0x4a00027d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubaw", "+m+K,+6+K,+7+N", 0x4a0000ff, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubax", "+m+K,+6+K,+7+N", 0x4a0000fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubay", "+m+K,+6+K,+7+N", 0x4a0000fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmsubaz", "+m+K,+6+K,+7+N", 0x4a0000fe, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmtir", "+0,+6+L", 0x4a0003fc, 0xff8007ff, CP, 0, VU0, 0, 0 }, -{"vmul", "+5+K,+6+K,+7+K", 0x4a00002a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmuli", "+5+K,+6+K,+y", 0x4a00001e, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmulq", "+5+K,+6+K,+q", 0x4a00001c, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vmulw", "+5+K,+6+K,+7+N", 0x4a00001b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmulx", "+5+K,+6+K,+7+N", 0x4a000018, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmuly", "+5+K,+6+K,+7+N", 0x4a000019, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmulz", "+5+K,+6+K,+7+N", 0x4a00001a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vmula", "+m+K,+6+K,+7+K", 0x4a0002be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulai", "+m+K,+6+K,+y", 0x4a0001fe, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulaq", "+m+K,+6+K,+q", 0x4a0001fc, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulaw", "+m+K,+6+K,+7+N", 0x4a0001bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vnop", "", 0x4a0002ff, 0xffffffff, CP, 0, VU0, 0, 0 }, -{"vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, -{"vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"vopmsub", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, -{"vrget", "+7+K,+r", 0x4a00043d, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, -{"vrinit", "+r,+6+L", 0x4a00043e, 0xff9f07ff, CP, 0, VU0, 0, 0 }, -{"vrnext", "+7+K,+r", 0x4a00043c, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, -{"vrsqrt", "+q,+6+L,+7+M", 0x4a0003be, 0xfe0007ff, CP, 0, VU0, 0, 0 }, -{"vrxor", "+r,+6+L", 0x4a00043f, 0xff9f07ff, CP, 0, VU0, 0, 0 }, -{"vsqd", "+6+K,(#-+0)", 0x4a00037f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsqi", "+6+K,(+0#+)", 0x4a00037d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsqrt", "+q,+7+M", 0x4a2003bd, 0xfe60ffff, CP, 0, VU0, 0, 0 }, -{"vsub", "+5+K,+6+K,+7+K", 0x4a00002c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vsubi", "+5+K,+6+K,+y", 0x4a000026, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vsubq", "+5+K,+6+K,+q", 0x4a000024, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, -{"vsubw", "+5+K,+6+K,+7+N", 0x4a000007, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vsubx", "+5+K,+6+K,+7+N", 0x4a000004, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vsuby", "+5+K,+6+K,+7+N", 0x4a000005, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vsubz", "+5+K,+6+K,+7+N", 0x4a000006, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, -{"vsuba", "+m+K,+6+K,+7+K", 0x4a0002fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubai", "+m+K,+6+K,+y", 0x4a00027e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubaq", "+m+K,+6+K,+q", 0x4a00027c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubaw", "+m+K,+6+K,+7+N", 0x4a00007f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubax", "+m+K,+6+K,+7+N", 0x4a00007c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubay", "+m+K,+6+K,+7+N", 0x4a00007d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, -{"vwaitq", "", 0x4a0003bf, 0xffffffff, CP, 0, VU0, 0, 0 }, +{ "vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vadd", "+5+K,+6+K,+7+K", 0x4a000028, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddi", "+5+K,+6+K,+y", 0x4a000022, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddq", "+5+K,+6+K,+q", 0x4a000020, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddw", "+5+K,+6+K,+7+N", 0x4a000003, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddx", "+5+K,+6+K,+7+N", 0x4a000000, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddy", "+5+K,+6+K,+7+N", 0x4a000001, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vaddz", "+5+K,+6+K,+7+N", 0x4a000002, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vadda", "+m+K,+7+K,+6+K", 0x4a0002bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vaddai", "+m+K,+6+K,+y", 0x4a00023e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vaddaq", "+m+K,+6+K,+q", 0x4a00023c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vaddaw", "+m+K,+6+K,+7+N", 0x4a00003f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vaddax", "+m+K,+6+K,+7+N", 0x4a00003c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vadday", "+m+K,+6+K,+7+N", 0x4a00003d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vaddaz", "+m+K,+6+K,+7+N", 0x4a00003e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vcallms", "+f", 0x4a000038, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "vcallmsr", "+9", 0x4a000039, 0xffff07ff, CP, 0, VU0, 0, 0 }, +{ "vclipw.xyz", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vclipw", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vdiv", "+q,+6+L,+7+M", 0x4a0003bc, 0xfe0007ff, CP, 0, VU0, 0, 0 }, +{ "vftoi0", "+7+K,+6+K", 0x4a00017c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vftoi4", "+7+K,+6+K", 0x4a00017d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vftoi12", "+7+K,+6+K", 0x4a00017e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vftoi15", "+7+K,+6+K", 0x4a00017f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "viadd", "+8,+9,+0", 0x4a000030, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "viaddi", "+0,+9,+g", 0x4a000032, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "viand", "+8,+9,+0", 0x4a000034, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "vilwr.w", "+0,(+9)", 0x4a2003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vilwr.x", "+0,(+9)", 0x4b0003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vilwr.y", "+0,(+9)", 0x4a8003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vilwr.z", "+0,(+9)", 0x4a4003fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vior", "+8,+9,+0", 0x4a000035, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "viswr.w", "+0,(+9)", 0x4a2003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "viswr.x", "+0,(+9)", 0x4b0003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "viswr.y", "+0,(+9)", 0x4a8003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "viswr.z", "+0,(+9)", 0x4a4003ff, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "visub", "+8,+9,+0", 0x4a000031, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "vitof0", "+7+K,+6+K", 0x4a00013c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vitof4", "+7+K,+6+K", 0x4a00013d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vitof12", "+7+K,+6+K", 0x4a00013e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vitof15", "+7+K,+6+K", 0x4a00013f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vlqd", "+7+K,(#-+9)", 0x4a00037e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vlqi", "+7+K,(+9#+)", 0x4a00037c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmadd", "+5+K,+6+K,+7+K", 0x4a000029, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddi", "+5+K,+6+K,+y", 0x4a000023, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddq", "+5+K,+6+K,+q", 0x4a000021, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddw", "+5+K,+6+K,+7+N", 0x4a00000b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddx", "+5+K,+6+K,+7+N", 0x4a000008, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddy", "+5+K,+6+K,+7+N", 0x4a000009, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddz", "+5+K,+6+K,+7+N", 0x4a00000a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmadda", "+m+K,+6+K,+7+K", 0x4a0002bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddai", "+m+K,+6+K,+y", 0x4a00023f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddaq", "+m+K,+6+K,+q", 0x4a00023d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddaw", "+m+K,+6+K,+7+N", 0x4a0000bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddax", "+m+K,+6+K,+7+N", 0x4a0000bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmadday", "+m+K,+6+K,+7+N", 0x4a0000bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmaddaz", "+m+K,+6+K,+7+N", 0x4a0000be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmax", "+5+K,+6+K,+7+K", 0x4a00002b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaxi", "+5+K,+6+K,+y", 0x4a00001d, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaxw", "+5+K,+6+K,+7+N", 0x4a000013, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaxx", "+5+K,+6+K,+7+N", 0x4a000010, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaxy", "+5+K,+6+K,+7+N", 0x4a000011, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmaxz", "+5+K,+6+K,+7+N", 0x4a000012, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmfir", "+7+K,+9", 0x4a0003fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmini", "+5+K,+6+K,+7+K", 0x4a00002f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vminii", "+5+K,+6+K,+y", 0x4a00001f, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vminiw", "+5+K,+6+K,+7+N", 0x4a000017, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vminix", "+5+K,+6+K,+7+N", 0x4a000014, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vminiy", "+5+K,+6+K,+7+N", 0x4a000015, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vminiz", "+5+K,+6+K,+7+N", 0x4a000016, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmove", "+7+K,+6+K", 0x4a00033c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmr32", "+7+K,+6+K", 0x4a00033d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsub", "+5+K,+6+K,+7+K", 0x4a00002d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubi", "+5+K,+6+K,+y", 0x4a000027, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubq", "+5+K,+6+K,+q", 0x4a000025, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubw", "+5+K,+6+K,+7+N", 0x4a00000f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubx", "+5+K,+6+K,+7+N", 0x4a00000c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsuby", "+5+K,+6+K,+7+N", 0x4a00000d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubz", "+5+K,+6+K,+7+N", 0x4a00000e, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmsuba", "+m+K,+7+K,+6+K", 0x4a0002fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubai", "+m+K,+6+K,+y", 0x4a00027f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubaq", "+m+K,+6+K,+q", 0x4a00027d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubaw", "+m+K,+6+K,+7+N", 0x4a0000ff, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubax", "+m+K,+6+K,+7+N", 0x4a0000fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubay", "+m+K,+6+K,+7+N", 0x4a0000fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmsubaz", "+m+K,+6+K,+7+N", 0x4a0000fe, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmtir", "+0,+6+L", 0x4a0003fc, 0xff8007ff, CP, 0, VU0, 0, 0 }, +{ "vmul", "+5+K,+6+K,+7+K", 0x4a00002a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmuli", "+5+K,+6+K,+y", 0x4a00001e, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmulq", "+5+K,+6+K,+q", 0x4a00001c, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmulw", "+5+K,+6+K,+7+N", 0x4a00001b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmulx", "+5+K,+6+K,+7+N", 0x4a000018, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmuly", "+5+K,+6+K,+7+N", 0x4a000019, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmulz", "+5+K,+6+K,+7+N", 0x4a00001a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vmula", "+m+K,+6+K,+7+K", 0x4a0002be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulai", "+m+K,+6+K,+y", 0x4a0001fe, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulaq", "+m+K,+6+K,+q", 0x4a0001fc, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulaw", "+m+K,+6+K,+7+N", 0x4a0001bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vnop", "", 0x4a0002ff, 0xffffffff, CP, 0, VU0, 0, 0 }, +{ "vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 }, +{ "vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "vopmsub", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 }, +{ "vrget", "+7+K,+r", 0x4a00043d, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, +{ "vrinit", "+r,+6+L", 0x4a00043e, 0xff9f07ff, CP, 0, VU0, 0, 0 }, +{ "vrnext", "+7+K,+r", 0x4a00043c, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 }, +{ "vrsqrt", "+q,+6+L,+7+M", 0x4a0003be, 0xfe0007ff, CP, 0, VU0, 0, 0 }, +{ "vrxor", "+r,+6+L", 0x4a00043f, 0xff9f07ff, CP, 0, VU0, 0, 0 }, +{ "vsqd", "+6+K,(#-+0)", 0x4a00037f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsqi", "+6+K,(+0#+)", 0x4a00037d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsqrt", "+q,+7+M", 0x4a2003bd, 0xfe60ffff, CP, 0, VU0, 0, 0 }, +{ "vsub", "+5+K,+6+K,+7+K", 0x4a00002c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsubi", "+5+K,+6+K,+y", 0x4a000026, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsubq", "+5+K,+6+K,+q", 0x4a000024, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsubw", "+5+K,+6+K,+7+N", 0x4a000007, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsubx", "+5+K,+6+K,+7+N", 0x4a000004, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsuby", "+5+K,+6+K,+7+N", 0x4a000005, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsubz", "+5+K,+6+K,+7+N", 0x4a000006, 0xfe00003f, CP, VU0CH, VU0, 0, 0 }, +{ "vsuba", "+m+K,+6+K,+7+K", 0x4a0002fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubai", "+m+K,+6+K,+y", 0x4a00027e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubaq", "+m+K,+6+K,+q", 0x4a00027c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubaw", "+m+K,+6+K,+7+N", 0x4a00007f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubax", "+m+K,+6+K,+7+N", 0x4a00007c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubay", "+m+K,+6+K,+7+N", 0x4a00007d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, +{ "vwaitq", "", 0x4a0003bf, 0xffffffff, CP, 0, VU0, 0, 0 }, -{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, -{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, -{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, -{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, -{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, -{"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, -{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, -{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, I37 }, -{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"addiu", "s,+R,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, -{"addiupc", "s,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, -{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, -{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, -{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, -{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, SB1, MX, 0 }, -{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, 0, MX, 0 }, -{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, -{"and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, -{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, -{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, +{ "abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, +{ "abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "abs.ps", "D,V", 0x45600005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, +{ "aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, +{ "aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, +{ "add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, +{ "add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, +{ "add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "adda.s", "S,T", 0x46000018, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, I37 }, +{ "addiu", "t,r,j", 0x24000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addiu", "s,+R,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, +{ "addiupc", "s,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 }, +{ "addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, +{ "addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, +{ "alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, +{ "alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, SB1, MX, 0 }, +{ "alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, 0, MX, 0 }, +{ "and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "andi", "t,r,i", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, +{ "aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, +{ "baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, /* b is at the top of the table. */ /* bal is at the top of the table. */ -{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, -{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit032 */ -{"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, -{"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, -{"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit132 */ -{"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, +{ "bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, +{ "bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit032 */ +{ "bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, +{ "bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, +{ "bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit132 */ +{ "bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bc0[tf]l? are at the bottom of the table. */ -{"bc1any2f", "N,p", 0x45200000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, -{"bc1any2t", "N,p", 0x45210000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, -{"bc1any4f", "N,p", 0x45400000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, -{"bc1any4t", "N,p", 0x45410000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, -{"bc1eqz", "T,p", 0x45200000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, -{"bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, -{"bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, -{"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, -{"bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, -{"bc1nez", "T,p", 0x45a00000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, -{"bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, -{"bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, -{"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, -{"bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, +{ "bc1any2f", "N,p", 0x45200000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, +{ "bc1any2t", "N,p", 0x45210000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, +{ "bc1any4f", "N,p", 0x45400000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, +{ "bc1any4t", "N,p", 0x45410000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, +{ "bc1eqz", "T,p", 0x45200000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, +{ "bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, +{ "bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, +{ "bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, +{ "bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, +{ "bc1nez", "T,p", 0x45a00000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, +{ "bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, +{ "bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, +{ "bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, +{ "bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, /* bc2* are at the bottom of the table. */ /* bc3* are at the bottom of the table. */ -{"beqz", "s,p", 0x10000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"beq", "s,t,p", 0x10000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, -{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, -{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgez", "s,p", 0x04010000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, -{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, -{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, -{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"blez", "s,p", 0x18000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, -{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"bltz", "s,p", 0x04000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, -{"nal", "", 0x04100000, 0xffffffff, WR_31|CBD, 0, I1, 0, 0 }, /* bltzal 0,.+4 */ -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, -{"bnez", "s,p", 0x14000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, -{"bne", "s,t,p", 0x14000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, -{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, -{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, -{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, -{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, -{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, -{"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, -{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, -{"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, -{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, -{"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, -{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, -{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, -{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, -{"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, -{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.nge.ps", "M,S,T", 0x46c0007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngl.ps", "M,S,T", 0x46c0007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ngle.d", "M,S,T", 0x46200079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngle.ps", "M,S,T", 0x46c00079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngle.s", "M,S,T", 0x46000079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngt.ps", "M,S,T", 0x46c0007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ole.ps", "M,S,T", 0x46c00076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.olt.ps", "M,S,T", 0x46c00074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.seq.ps", "M,S,T", 0x46c0007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ueq.ps", "M,S,T", 0x46c00073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ule.ps", "M,S,T", 0x46c00077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ult.ps", "M,S,T", 0x46c00075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, -{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, -{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "beqz", "s,p", 0x10000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "beq", "s,t,p", 0x10000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, +{ "beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, +{ "beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, +{ "bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgez", "s,p", 0x04010000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, +{ "bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, +{ "bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bgtz", "s,p", 0x1c000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, +{ "ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "blez", "s,p", 0x18000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, +{ "blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "bltz", "s,p", 0x04000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, +{ "nal", "", 0x04100000, 0xffffffff, WR_31|CBD, 0, I1, 0, 0 }, /* bltzal 0,.+4 */ +{ "bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, +{ "bnez", "s,p", 0x14000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, +{ "bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{ "bne", "s,t,p", 0x14000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, +{ "bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, +{ "bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, +{ "break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 }, +{ "break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, +{ "break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 }, +{ "c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, +{ "c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, +{ "c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, +{ "c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, +{ "c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, +{ "c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, +{ "c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, +{ "c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, +{ "c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, +{ "c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, +{ "c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, +{ "c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, +{ "c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, +{ "c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{ "c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{ "c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{ "c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{ "c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{ "cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.nge.ps", "M,S,T", 0x46c0007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngl.ps", "M,S,T", 0x46c0007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ngle.d", "M,S,T", 0x46200079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngle.ps", "M,S,T", 0x46c00079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngle.s", "M,S,T", 0x46000079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngt.ps", "M,S,T", 0x46c0007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ole.ps", "M,S,T", 0x46c00076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.olt.ps", "M,S,T", 0x46c00074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.seq.ps", "M,S,T", 0x46c0007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ueq.ps", "M,S,T", 0x46c00073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ule.ps", "M,S,T", 0x46c00077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ult.ps", "M,S,T", 0x46c00075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, +{ "cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, +{ "cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, /* CW4010 instructions which are aliases for the cache instruction. */ -{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1, 0, 0 }, -{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 }, -{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, -{"wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 }, -{"cache", "k,+j(b)", 0x7c000025, 0xfc00007f, RD_3, 0, I37, 0, 0 }, -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, I37 }, -{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0 }, -{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, -{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, +{ "flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1, 0, 0 }, +{ "flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 }, +{ "flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, +{ "wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 }, +{ "cache", "k,+j(b)", 0x7c000025, 0xfc00007f, RD_3, 0, I37, 0, 0 }, +{ "cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, I37 }, +{ "cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0 }, +{ "ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, +{ "ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, /* cfc0 is at the bottom of the table. */ -{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 }, -{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 }, +{ "cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 }, +{ "cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 }, /* cfc2 is at the bottom of the table. */ /* cfc3 is at the bottom of the table. */ -{"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, -{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, -{"cftc2", "d,E", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ -{"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"clo", "d,s", 0x00000051, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, -{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, -{"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, -{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +{ "cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, +{ "cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 }, +{ "cftc2", "d,E", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ +{ "cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "clo", "d,s", 0x00000051, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, +{ "clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +{ "clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, +{ "clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, /* ctc0 is at the bottom of the table. */ -{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, -{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, +{ "ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, +{ "ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, /* ctc2 is at the bottom of the table. */ /* ctc3 is at the bottom of the table. */ -{"cttc1", "t,G", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, -{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, -{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, -{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"cvt.s.pl", "D,S", 0x46c00028, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, -{"cvt.s.pu", "D,S", 0x46c00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, -{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, -{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, EE }, -{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, -{"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, I37 }, -{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, -{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, -{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 }, -{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, -{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, -{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, -{"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, -{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, -{"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, -{"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, +{ "cttc1", "t,G", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, +{ "cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, +{ "cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, +{ "cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, +{ "cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, +{ "cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "cvt.s.pl", "D,S", 0x46c00028, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, +{ "cvt.s.pu", "D,S", 0x46c00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 }, +{ "cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, +{ "cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, EE }, +{ "cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, +{ "cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, I37 }, +{ "cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, +{ "dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, +{ "dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 }, +{ "daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, +{ "daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, +{ "dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, +{ "dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, +{ "dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, +{ "dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, +{ "dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, /* dctr and dctw are used on the r5000. */ -{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, -{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, -{"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, -{"dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, -{"dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */ -{"dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */ -{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, -{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, +{ "dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, +{ "deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, +{ "dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */ +{ "dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */ +{ "dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* For ddiv, see the comments about div. */ -{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, -{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{ "ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, /* For ddivu, see the comments about div. */ -{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, -{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, -{"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, -{"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, -{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, -{"dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */ -{"dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */ -{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, -{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{ "ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, +{ "di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, +{ "di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, +{ "dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */ +{ "dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */ +{ "dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as though the first operand appeared twice (the first operand is both a source and a destination). To get the div machine instruction, you must use an explicit destination of $0. */ -{"mod", "d,v,t", 0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"modu", "d,v,t", 0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"div", "d,v,t", 0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, -{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, -{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, I37 }, -{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, I37 }, -{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, -{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, -{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, -{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, +{ "mod", "d,v,t", 0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "modu", "d,v,t", 0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "div", "d,v,t", 0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, +{ "div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, +{ "div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, I37 }, +{ "div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, I37 }, +{ "div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, +{ "div1", "z,t", 0x7000001a, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, +{ "div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, +{ "div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, /* For divu, see the comments about div. */ -{"divu", "d,v,t", 0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, -{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, -{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, I37 }, -{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, I37 }, -{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, -{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, -{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"dli", "t,j", 0x24000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* addiu */ -{"dli", "t,i", 0x34000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* ori */ -{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, -{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, -{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO, 0, N411, 0, 0 }, -{"dmfc0", "t,G", 0x40200000, 0xffe007ff, WR_1|RD_C0|LC, 0, I3, 0, EE }, -{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, -{"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, -{"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, -{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, -{"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, -{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I64, 0, 0 }, -{"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, -{"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, -{"dmfc1", "t,S", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF }, -{"dmfc1", "t,G", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF }, -{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, -{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, +{ "divu", "d,v,t", 0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, +{ "divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, +{ "divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, I37 }, +{ "divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, I37 }, +{ "divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, +{ "divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, +{ "dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "dli", "t,j", 0x24000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* addiu */ +{ "dli", "t,i", 0x34000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* ori */ +{ "dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmacc", "d,s,t", 0x00000029, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 }, +{ "dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO, 0, N411, 0, 0 }, +{ "dmfc0", "t,G", 0x40200000, 0xffe007ff, WR_1|RD_C0|LC, 0, I3, 0, EE }, +{ "dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, +{ "dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, +{ "dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, +{ "dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, +{ "dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, +{ "dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I64, 0, 0 }, +{ "dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, +{ "dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, +{ "dmfc1", "t,S", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF }, +{ "dmfc1", "t,G", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF }, +{ "dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, +{ "dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF }, /* dmfc2 is at the bottom of the table. */ /* dmtc2 is at the bottom of the table. */ /* dmfc3 is at the bottom of the table. */ /* dmtc3 is at the bottom of the table. */ -{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, -{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, -{"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, -{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ -{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0*/ -{"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, -{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, -{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, -{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 }, -{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, -{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, -{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I65, 0, 0 }, -{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, -{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65, 0, 0 }, -{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65, 0, 0 }, -{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65, 0, 0 }, -{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65, 0, 0 }, -{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I65, 0, 0 }, -{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, I65, 0, 0 }, -{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, -{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, -{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */ -{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ -{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ -{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ -{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ -{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ -{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, -{"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 }, -{"dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, -{"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 }, -{"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 }, -{"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, -{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, -{"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, -{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 }, -{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, -{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 }, -{"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, -{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, -{"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */ -{"exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, -{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, -{"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 }, -{"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, -{"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, -{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, -{"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, -{"jr", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ -{"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, +{ "dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, +{ "dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, +{ "dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, +{ "dneg", "d,w", 0x0000002e, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ +{ "dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0*/ +{ "dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{ "drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{ "dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{ "dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 }, +{ "drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, +{ "drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, +{ "drorv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I65, 0, 0 }, +{ "dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 }, +{ "drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65, 0, 0 }, +{ "drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65, 0, 0 }, +{ "drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65, 0, 0 }, +{ "drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65, 0, 0 }, +{ "drotrv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I65, 0, 0 }, +{ "drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dshd", "d,w", 0x7c000164, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 }, +{ "dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */ +{ "dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */ +{ "dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */ +{ "dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */ +{ "dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */ +{ "dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */ +{ "dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{ "dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 }, +{ "dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{ "dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, +{ "ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 }, +{ "ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 }, +{ "ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, +{ "emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, +{ "emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, +{ "eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 }, +{ "evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, +{ "evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{ "evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, +{ "ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, +{ "exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */ +{ "exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, +{ "floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, +{ "hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 }, +{ "hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, +{ "hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, +{ "ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, +{ "iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, +{ "jr", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ +{ "jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, /* MIPS R6 jic appears before beqzc and jialc appears before bnezc */ /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with the same hazard barrier effect. */ -{"jr.hb", "s", 0x00000409, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr.hb $0 */ -{"jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, I37 }, -{"j", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ -{"j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, /* jr */ +{ "jr.hb", "s", 0x00000409, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr.hb $0 */ +{ "jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, I37 }, +{ "j", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ +{ "j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, /* jr */ /* SVR4 PIC code requires special handling for j, so it must be a macro. */ -{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, +{ "j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, /* This form of j is used by the disassembler and internally by the assembler, but will never match user input (because the line above will match first). */ -{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 }, -{"jalr", "s", 0x0000f809, 0xfc1fffff, RD_1|WR_31|UBD, 0, I1, 0, 0 }, -{"jalr", "d,s", 0x00000009, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I1, 0, 0 }, +{ "j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 }, +{ "jalr", "s", 0x0000f809, 0xfc1fffff, RD_1|WR_31|UBD, 0, I1, 0, 0 }, +{ "jalr", "d,s", 0x00000009, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I1, 0, 0 }, /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr with the same hazard barrier effect. */ -{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, RD_1|WR_31|UBD, 0, I32, 0, 0 }, -{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I32, 0, 0 }, +{ "jalr.hb", "s", 0x0000fc09, 0xfc1fffff, RD_1|WR_31|UBD, 0, I32, 0, 0 }, +{ "jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I32, 0, 0 }, /* SVR4 PIC code requires special handling for jal, so it must be a macro. */ -{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, -{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, -{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 }, +{ "jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 }, /* This form of jal is used by the disassembler and internally by the assembler, but will never match user input (because the line above will match first). */ -{"jal", "a", 0x0c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, +{ "jal", "a", 0x0c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, // I don't know why the args definition causes wrong decoding, so I modifiy it. -//{"jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 }, -{"jalx", "a", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 }, -{"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, -{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, -{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, -{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, -{"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, -{"lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, -{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, -{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D64, 0}, -{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, -{"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, -{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, -{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, -{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ldpc", "s,-B", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, +//{ "jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 }, +{ "jalx", "a", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 }, +{ "laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{ "laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{ "lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{ "law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{ "lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{ "lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, +{ "lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{ "ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D64, 0}, +{ "lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{ "lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, +{ "lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{ "lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, +{ "lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ldpc", "s,-B", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ -{"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, -{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, -{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, -{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ -{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, -{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, -{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I4_33, 0, I37 }, -{"lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, +{ "ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, +{ "ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, +{ "ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, +{ "ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, +{ "l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ +{ "l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, +{ "ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, +{ "ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, +{ "ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I4_33, 0, I37 }, +{ "lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, /* li is at the start of the table. */ -{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, -{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, -{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"ll", "t,+j(b)", 0x7c000036, 0xfc00007f, WR_1|RD_3|LM, 0, I37, 0, 0 }, -{"ll", "t,o(b)", 0xc0000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, EE|I37 }, -{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE }, -{"lld", "t,+j(b)", 0x7c000037, 0xfc00007f, WR_1|RD_3|LM, 0, I69, 0, 0 }, -{"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, EE|I69 }, -{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, -{"lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, -{"lldp", "t,d,A(b)", 0, (int) M_LLDP_AB, INSN_MACRO, 0, I69, 0, 0 }, -{"llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, -{"llwp", "t,d,A(b)", 0, (int) M_LLWP_AB, INSN_MACRO, 0, I37, 0, 0 }, -{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3|LM, 0, MMI, 0, 0 }, -{"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, -{"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, -{"lqc2", "+7,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, -{"lui", "t,u", 0x3c000000, 0xffe00000, WR_1, 0, I1, 0, 0 }, -{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I5_33|N55, 0, I37}, -{"lwpc", "s,-A", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 }, -{"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, -{"lw", "s,-a(+R)", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 }, -{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, -{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, -{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ -{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ -{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwl */ -{"lwr", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, -{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"flush", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ -{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwr */ -{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP, 0, 0, MT32, 0 }, -{"lwupc", "s,-A", 0xec100000, 0xfc180000, WR_1, RD_pc, I69, 0, 0 }, -{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, -{"lwu" , "s,-a(+R)", 0xec100000, 0xfc180000, WR_1, RD_pc, I69, 0, 0 }, -{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S, 0, I4_33, 0, I37 }, -{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, SMT, 0 }, -{"macc", "d,s,t", 0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"macc", "d,s,t", 0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"macchius", "d,s,t", 0x00000668, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, -{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, -{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, -{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, -{"madd.d", "D,S,T", 0x46200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"madd.d", "D,S,T", 0x72200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, -{"madd.s", "D,S,T", 0x46000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"madd.s", "D,S,T", 0x72000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, -{"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"madd", "d,s,t", 0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, -{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, N411, 0, 0 }, -{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"mfbpc", "t", 0x4000c000, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfdab", "t", 0x4000c004, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfdabm", "t", 0x4000c005, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfdvb", "t", 0x4000c006, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfdvbm", "t", 0x4000c007, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfiab", "t", 0x4000c002, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfiabm", "t", 0x4000c003, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, -{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, -{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, -{"mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftc0", "d,+t", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, -{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, -{"mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, -{"mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, -{"mftc2", "d,E", 0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mftdsp", "d", 0x41100021, 0xffff07ff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"mftgpr", "d,t", 0x41000020, 0xffe007ff, WR_1|RD_2|TRAP, 0, 0, MT32, 0 }, -{"mfthc1", "d,T", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, -{"mfthc1", "d,E", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, -{"mfthc2", "d,E", 0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mfthi", "d", 0x41010021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mfthi", "d,*", 0x41010021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftlo", "d", 0x41000021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftlo", "d,*", 0x41000021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, WR_1|TRAP, 0, 0, MT32, 0 }, -{"mfc0", "t,G", 0x40000000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, 0 }, -{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, WR_1|RD_C0|LC, 0, I32, 0, 0 }, -{"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT, 0 }, -{"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT, 0 }, -{"mfhc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, XPA, 0 }, -{"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, XPA, 0 }, -{"mfhgc0", "t,G", 0x40600400, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, XPAVZ, 0 }, -{"mfhgc0", "t,G,H", 0x40600400, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, XPAVZ, 0 }, -{"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 }, -{"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 }, -{"mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 }, +{ "li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, +{ "li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, +{ "li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "ll", "t,+j(b)", 0x7c000036, 0xfc00007f, WR_1|RD_3|LM, 0, I37, 0, 0 }, +{ "ll", "t,o(b)", 0xc0000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, EE|I37 }, +{ "ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE }, +{ "lld", "t,+j(b)", 0x7c000037, 0xfc00007f, WR_1|RD_3|LM, 0, I69, 0, 0 }, +{ "lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, EE|I69 }, +{ "lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, +{ "lldp", "t,d,s", 0x7c000077, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 }, +{ "lldp", "t,d,A(b)", 0, (int) M_LLDP_AB, INSN_MACRO, 0, I69, 0, 0 }, +{ "llwp", "t,d,s", 0x7c000076, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 }, +{ "llwp", "t,d,A(b)", 0, (int) M_LLWP_AB, INSN_MACRO, 0, I37, 0, 0 }, +{ "lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3|LM, 0, MMI, 0, 0 }, +{ "lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, +{ "lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, +{ "lqc2", "+7,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, +{ "lui", "t,u", 0x3c000000, 0xffe00000, WR_1, 0, I1, 0, 0 }, +{ "luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I5_33|N55, 0, I37}, +{ "lwpc", "s,-A", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 }, +{ "lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{ "lw", "s,-a(+R)", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 }, +{ "lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, +{ "lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, +{ "lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ +{ "l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, +{ "lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, +{ "lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ +{ "lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwl */ +{ "lwr", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, +{ "lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "flush", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ +{ "flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwr */ +{ "fork", "d,s,t", 0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP, 0, 0, MT32, 0 }, +{ "lwupc", "s,-A", 0xec100000, 0xfc180000, WR_1, RD_pc, I69, 0, 0 }, +{ "lwu", "t,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{ "lwu" , "s,-a(+R)", 0xec100000, 0xfc180000, WR_1, RD_pc, I69, 0, 0 }, +{ "lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, +{ "lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S, 0, I4_33, 0, I37 }, +{ "lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, SMT, 0 }, +{ "macc", "d,s,t", 0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "macc", "d,s,t", 0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "maccs", "d,s,t", 0x00000428, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "macchi", "d,s,t", 0x00000228, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "macchi", "d,s,t", 0x00000358, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "macchis", "d,s,t", 0x00000628, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "macchiu", "d,s,t", 0x00000268, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "macchiu", "d,s,t", 0x00000359, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "macchius", "d,s,t", 0x00000668, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "maccu", "d,s,t", 0x00000068, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "maccu", "d,s,t", 0x00000159, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "maccus", "d,s,t", 0x00000468, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, +{ "mad", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, +{ "madu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, +{ "madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, +{ "madd.d", "D,S,T", 0x46200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "madd.d", "D,S,T", 0x72200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, +{ "madd.s", "D,S,T", 0x46000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "madd.s", "D,S,T", 0x72000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, +{ "madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{ "madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, +{ "madd.ps", "D,S,T", 0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{ "madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, +{ "madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "madd", "7,s,t", 0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "madd", "d,s,t", 0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "madd1", "s,t", 0x70000020, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "madd1", "d,s,t", 0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "maddp", "s,t", 0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, +{ "maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{ "maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, +{ "maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "maddu", "7,s,t", 0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maddu", "d,s,t", 0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "maddu1", "d,s,t", 0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "madd16", "s,t", 0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, N411, 0, 0 }, +{ "max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{ "max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "mfbpc", "t", 0x4000c000, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfdab", "t", 0x4000c004, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfdabm", "t", 0x4000c005, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfdvb", "t", 0x4000c006, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfdvbm", "t", 0x4000c007, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfiab", "t", 0x4000c002, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfiabm", "t", 0x4000c003, 0xffe0ffff, WR_1|RD_C0|LC, 0, EE, 0, 0 }, +{ "mfpc", "t,P", 0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, +{ "mfps", "t,P", 0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, +{ "mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mftc0", "d,+t", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, +{ "mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, +{ "mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, +{ "mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, +{ "mftc2", "d,E", 0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "mftdsp", "d", 0x41100021, 0xffff07ff, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "mftgpr", "d,t", 0x41000020, 0xffe007ff, WR_1|RD_2|TRAP, 0, 0, MT32, 0 }, +{ "mfthc1", "d,T", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, +{ "mfthc1", "d,E", 0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0, 0, MT32, 0 }, +{ "mfthc2", "d,E", 0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "mfthi", "d", 0x41010021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mfthi", "d,*", 0x41010021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mftlo", "d", 0x41000021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mftlo", "d,*", 0x41000021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, +{ "mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, WR_1|TRAP, 0, 0, MT32, 0 }, +{ "mfc0", "t,G", 0x40000000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, 0 }, +{ "mfc0", "t,G,H", 0x40000000, 0xffe007f8, WR_1|RD_C0|LC, 0, I32, 0, 0 }, +{ "mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT, 0 }, +{ "mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT, 0 }, +{ "mfhc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, XPA, 0 }, +{ "mfhc0", "t,G,H", 0x40400000, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, XPA, 0 }, +{ "mfhgc0", "t,G", 0x40600400, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, XPAVZ, 0 }, +{ "mfhgc0", "t,G,H", 0x40600400, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, XPAVZ, 0 }, +{ "mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 }, +{ "mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S, 0, I1, 0, 0 }, +{ "mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 }, +{ "mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I33, 0, 0 }, /* mfc2 is at the bottom of the table. */ /* mfhc2 is at the bottom of the table. */ /* mfc3 is at the bottom of the table. */ -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LC, 0, N5, 0, 0 }, -{"mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, I37 }, -{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_1|RD_HI, 0, 0, D32, 0 }, -{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_1|RD_HI, 0, EE, 0, 0 }, -{"mflo", "d", 0x00000012, 0xffff07ff, WR_1|RD_LO, 0, I1, 0, I37 }, -{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, -{"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, -{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, -{"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, -{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"min.s", "D,S,T", 0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, -{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, -{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, -{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, -{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, -{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 }, -{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, -{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, -{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, -{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, -{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, -{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, -{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, -{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, -{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, -{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, -{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LC, 0, N5, 0, 0 }, +{ "mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, I37 }, +{ "mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_1|RD_HI, 0, 0, D32, 0 }, +{ "mfhi1", "d", 0x70000010, 0xffff07ff, WR_1|RD_HI, 0, EE, 0, 0 }, +{ "mflo", "d", 0x00000012, 0xffff07ff, WR_1|RD_LO, 0, I1, 0, I37 }, +{ "mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, +{ "mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, +{ "mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, +{ "mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, +{ "mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, +{ "min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "min.s", "D,S,T", 0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{ "min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "mov.d", "D,S", 0x46200006, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, +{ "mov.s", "D,S", 0x46000006, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "mov.ps", "D,S", 0x45600006, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, +{ "movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, +{ "movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, +{ "movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, +{ "movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, +{ "movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, +{ "movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, +{ "movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, +{ "movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 }, +{ "ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, +{ "movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, +{ "movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, +{ "movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, +{ "movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, +{ "movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, +{ "movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, +{ "movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, +{ "movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, +{ "movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, +{ "ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, +{ "movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, +{ "movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, +{ "movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "msac", "d,s,t", 0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "msacu", "d,s,t", 0x000001d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "msachi", "d,s,t", 0x000003d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, /* move is at the top of the table. */ -{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, -{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, -{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, -{"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, -{"msub.s", "D,S,T", 0x46000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"msub.s", "D,S,T", 0x72000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, -{"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, -{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, -{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"mtbpc", "t", 0x4080c000, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtdab", "t", 0x4080c004, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtdabm", "t", 0x4080c005, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtdvb", "t", 0x4080c006, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtdvbm", "t", 0x4080c007, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtiab", "t", 0x4080c002, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtiabm", "t", 0x4080c003, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, -{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 }, -{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 }, -{"mtc0", "t,G", 0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I1, 0, 0 }, -{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I32, 0, 0 }, -{"mtgc0", "t,G", 0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT, 0 }, -{"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT, 0 }, -{"mthc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, XPA, 0 }, -{"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, XPA, 0 }, -{"mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, XPAVZ, 0 }, -{"mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, XPAVZ, 0 }, -{"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, -{"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, -{"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, +{ "msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, +{ "msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, +{ "msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, +{ "msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, +{ "msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, +{ "msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, +{ "msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, +{ "msub.s", "D,S,T", 0x46000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "msub.s", "D,S,T", 0x72000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, +{ "msub.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{ "msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, +{ "msub.ps", "D,S,T", 0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "msub", "s,t", 0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{ "msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, +{ "msub", "7,s,t", 0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{ "msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, +{ "msubu", "7,s,t", 0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "mtbpc", "t", 0x4080c000, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtdab", "t", 0x4080c004, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtdabm", "t", 0x4080c005, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtdvb", "t", 0x4080c006, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtdvbm", "t", 0x4080c007, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtiab", "t", 0x4080c002, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtiabm", "t", 0x4080c003, 0xffe0ffff, RD_1|WR_C0|CM, 0, EE, 0, 0 }, +{ "mtpc", "t,P", 0x4080c801, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 }, +{ "mtps", "t,P", 0x4080c800, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 }, +{ "mtc0", "t,G", 0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I1, 0, 0 }, +{ "mtc0", "t,G,H", 0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I32, 0, 0 }, +{ "mtgc0", "t,G", 0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT, 0 }, +{ "mtgc0", "t,G,H", 0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT, 0 }, +{ "mthc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, XPA, 0 }, +{ "mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, XPA, 0 }, +{ "mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, XPAVZ, 0 }, +{ "mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, XPAVZ, 0 }, +{ "mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, +{ "mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S, 0, I1, 0, 0 }, +{ "mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, +{ "mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I33, 0, 0 }, /* mtc2 is at the bottom of the table. */ /* mthc2 is at the bottom of the table. */ /* mtc3 is at the bottom of the table. */ -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|CM, 0, N5, 0, 0 }, -{"mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, I37 }, -{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_1|WR_HI, 0, 0, D32, 0 }, -{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_1|WR_HI, 0, EE, 0, 0 }, -{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_1|WR_LO, 0, I1, 0, I37 }, -{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, -{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, -{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, -{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -{"mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, -{"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 }, -{"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, -{"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, -{"mttc0", "t,G", 0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, -{"mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, -{"mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, -{"mttc2", "t,g", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, 0, 0, MT32, 0 }, -{"mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, 0, 0, MT32, 0 }, -{"mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, -{"mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, -{"mtthc2", "t,g", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, -{"mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttlo", "t,&", 0x41800021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, -{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, RD_1|TRAP, 0, 0, MT32, 0 }, -{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, -{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"muh", "d,v,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"muhu", "d,v,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"mul", "d,v,t", 0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I32|P3|N55, 0, I37}, -{"mul", "d,s,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N54, 0, 0 }, -{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, I37 }, -{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, I37 }, -{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, -{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"mull.ob", "S,Q", 0x48000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, -{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, I37 }, -{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, I37 }, -{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, I37 }, -{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, I37 }, -{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, -{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"muls.ob", "S,Q", 0x48000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, -{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, -{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, -{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, -{"mult", "d,s,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, -{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, -{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, -{"multu", "d,s,t", 0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, -{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, -{"mulu", "d,v,t", 0x00000099, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, -{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, -{"neg", "d,w", 0x00000022, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ -{"negu", "d,w", 0x00000023, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ -{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, -{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, -{"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, -{"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, -{"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, -{"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, -{"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, -{"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|CM, 0, N5, 0, 0 }, +{ "mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, I37 }, +{ "mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_1|WR_HI, 0, 0, D32, 0 }, +{ "mthi1", "s", 0x70000011, 0xfc1fffff, RD_1|WR_HI, 0, EE, 0, 0 }, +{ "mtlo", "s", 0x00000013, 0xfc1fffff, RD_1|WR_LO, 0, I1, 0, I37 }, +{ "mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, +{ "mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, +{ "mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, +{ "mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, +{ "mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{ "mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, +{ "mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 }, +{ "mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, +{ "mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, +{ "mttc0", "t,G", 0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, +{ "mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 }, +{ "mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, +{ "mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 }, +{ "mttc2", "t,g", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, 0, 0, MT32, 0 }, +{ "mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, 0, 0, MT32, 0 }, +{ "mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, +{ "mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 }, +{ "mtthc2", "t,g", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, +{ "mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mttlo", "t,&", 0x41800021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 }, +{ "mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, RD_1|TRAP, 0, 0, MT32, 0 }, +{ "mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, +{ "mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "muh", "d,v,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "muhu", "d,v,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "mul", "d,v,t", 0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I32|P3|N55, 0, I37}, +{ "mul", "d,s,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N54, 0, 0 }, +{ "mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, I37 }, +{ "mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, I37 }, +{ "mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "mula.ob", "S,Q", 0x48000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, +{ "mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "mulhi", "d,s,t", 0x00000258, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "mull.ob", "S,Q", 0x48000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, +{ "mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, I37 }, +{ "mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, I37 }, +{ "mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, I37 }, +{ "mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, I37 }, +{ "mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, +{ "muls", "d,s,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "muls.ob", "S,Q", 0x48000032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, +{ "muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, +{ "mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "mult", "s,t", 0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, +{ "mult", "7,s,t", 0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, +{ "mult", "d,s,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "mult1", "s,t", 0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "multp", "s,t", 0x00000459, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, +{ "multu", "s,t", 0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, +{ "multu", "7,s,t", 0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, +{ "multu", "d,s,t", 0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, +{ "multu1", "s,t", 0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, +{ "mulu", "d,v,t", 0x00000099, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{ "mulu", "d,s,t", 0x00000059, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, +{ "neg", "d,w", 0x00000022, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ +{ "negu", "d,w", 0x00000023, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ +{ "neg.d", "D,V", 0x46200007, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, +{ "neg.s", "D,V", 0x46000007, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{ "neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "neg.ps", "D,V", 0x45600007, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, +{ "nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, +{ "nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, +{ "nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, +{ "nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, +{ "nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, +{ "nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{ "nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, +{ "nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, +{ "nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, +{ "nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, /* nop is at the start of the table. */ -{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"nor", "D,S,T", 0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 },/*nor d,s,0*/ -{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"or", "D,S,T", 0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"pabsdiff.ob", "X,Y,Q", 0x78000009, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, -{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, 0, 0 }, -{"pause", "", 0x00000140, 0xffffffff, TRAP, 0, I33, 0, 0 }, -{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, -{"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"paddsw", "d,s,t", 0x70000408, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddub", "d,s,t", 0x70000628, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"padduh", "d,s,t", 0x70000528, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"padduw", "d,s,t", 0x70000428, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"padsbh", "d,s,t", 0x70000128, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pand", "d,s,t", 0x70000489, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pceqb", "d,s,t", 0x700002a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pceqh", "d,s,t", 0x700001a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pceqw", "d,s,t", 0x700000a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pcgtb", "d,s,t", 0x70000288, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pcgth", "d,s,t", 0x70000188, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pcgtw", "d,s,t", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pcpyld", "d,s,t", 0x70000389, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pcpyud", "d,s,t", 0x700003a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, -{"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, -{"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, -{"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pexew", "d,t", 0x70000789, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pext5", "d,t", 0x70000788, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pextlb", "d,s,t", 0x70000688, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pextlh", "d,s,t", 0x70000588, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pextlw", "d,s,t", 0x70000488, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pextub", "d,s,t", 0x700006a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pextuh", "d,s,t", 0x700005a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pextuw", "d,s,t", 0x700004a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"pickf.ob", "D,S,Q", 0x48000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"pickt.ob", "D,S,Q", 0x48000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, -{"pmaddw", "d,s,t", 0x70000009, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, -{"pmaxh", "d,s,t", 0x700001c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pmaxw", "d,s,t", 0x700000c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pmfhi", "d", 0x70000209, 0xffff07ff, WR_1|RD_HI, 0, MMI, 0, 0 }, -{"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, -{"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, -{"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, -{"pmfhl.slw", "d", 0x700000b0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, -{"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, -{"pmflo", "d", 0x70000249, 0xffff07ff, WR_1|RD_LO, 0, MMI, 0, 0 }, -{"pminh", "d,s,t", 0x700001e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pminw", "d,s,t", 0x700000e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pmsubh", "d,s,t", 0x70000509, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, -{"pmsubw", "d,s,t", 0x70000109, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, -{"pmthi", "s", 0x70000229, 0xfc1fffff, RD_1|WR_HI, 0, MMI, 0, 0 }, -{"pmthl.lw", "s", 0x70000031, 0xfc1fffff, RD_1|MOD_HILO, 0, MMI, 0, 0 }, -{"pmtlo", "s", 0x70000269, 0xfc1fffff, RD_1|WR_LO, 0, MMI, 0, 0 }, -{"pmulth", "d,s,t", 0x70000709, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"pmultuw", "d,s,t", 0x70000329, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"pmultw", "d,s,t", 0x70000309, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, -{"pnor", "d,s,t", 0x700004e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"por", "d,s,t", 0x700004a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"ppacb", "d,s,t", 0x700006c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"ppach", "d,s,t", 0x700005c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"ppacw", "d,s,t", 0x700004c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubsw", "d,s,t", 0x70000448, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubub", "d,s,t", 0x70000668, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubuh", "d,s,t", 0x70000568, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "nor", "D,S,T", 0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "nor", "D,S,T", 0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "not", "d,v", 0x00000027, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 },/*nor d,s,0*/ +{ "or", "d,v,t", 0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "or", "D,S,T", 0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "or", "D,S,T", 0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "ori", "t,r,i", 0x34000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "pabsdiff.ob", "X,Y,Q", 0x78000009, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, +{ "pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, 0, 0 }, +{ "pause", "", 0x00000140, 0xffffffff, TRAP, 0, I33, 0, 0 }, +{ "pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, +{ "pabsh", "d,t", 0x70000168, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pabsw", "d,t", 0x70000068, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "paddsw", "d,s,t", 0x70000408, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddub", "d,s,t", 0x70000628, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "padduh", "d,s,t", 0x70000528, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "padduw", "d,s,t", 0x70000428, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "padsbh", "d,s,t", 0x70000128, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pand", "d,s,t", 0x70000489, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pceqb", "d,s,t", 0x700002a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pceqh", "d,s,t", 0x700001a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pceqw", "d,s,t", 0x700000a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pcgtb", "d,s,t", 0x70000288, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pcgth", "d,s,t", 0x70000188, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pcgtw", "d,s,t", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pcpyld", "d,s,t", 0x70000389, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pcpyud", "d,s,t", 0x700003a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, +{ "pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, +{ "pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, MMI, 0, 0 }, +{ "pexch", "d,t", 0x700006a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pexeh", "d,t", 0x70000689, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pexew", "d,t", 0x70000789, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pext5", "d,t", 0x70000788, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pextlb", "d,s,t", 0x70000688, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pextlh", "d,s,t", 0x70000588, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pextlw", "d,s,t", 0x70000488, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pextub", "d,s,t", 0x700006a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pextuh", "d,s,t", 0x700005a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pextuw", "d,s,t", 0x700004a8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "pickf.ob", "D,S,Q", 0x48000002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "pickt.ob", "D,S,Q", 0x48000003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, +{ "pmaddw", "d,s,t", 0x70000009, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, +{ "pmaxh", "d,s,t", 0x700001c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pmaxw", "d,s,t", 0x700000c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pmfhi", "d", 0x70000209, 0xffff07ff, WR_1|RD_HI, 0, MMI, 0, 0 }, +{ "pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, +{ "pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, +{ "pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, +{ "pmfhl.slw", "d", 0x700000b0, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, +{ "pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_1|RD_HILO, 0, MMI, 0, 0 }, +{ "pmflo", "d", 0x70000249, 0xffff07ff, WR_1|RD_LO, 0, MMI, 0, 0 }, +{ "pminh", "d,s,t", 0x700001e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pminw", "d,s,t", 0x700000e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pmsubh", "d,s,t", 0x70000509, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, +{ "pmsubw", "d,s,t", 0x70000109, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, +{ "pmthi", "s", 0x70000229, 0xfc1fffff, RD_1|WR_HI, 0, MMI, 0, 0 }, +{ "pmthl.lw", "s", 0x70000031, 0xfc1fffff, RD_1|MOD_HILO, 0, MMI, 0, 0 }, +{ "pmtlo", "s", 0x70000269, 0xfc1fffff, RD_1|WR_LO, 0, MMI, 0, 0 }, +{ "pmulth", "d,s,t", 0x70000709, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "pmultuw", "d,s,t", 0x70000329, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "pmultw", "d,s,t", 0x70000309, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, +{ "pnor", "d,s,t", 0x700004e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "por", "d,s,t", 0x700004a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "ppacb", "d,s,t", 0x700006c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "ppach", "d,s,t", 0x700005c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "ppacw", "d,s,t", 0x700004c8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "prevh", "d,t", 0x700006c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubsw", "d,s,t", 0x70000448, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubub", "d,s,t", 0x70000668, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubuh", "d,s,t", 0x70000568, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, /* pref and prefx are at the start of the table. */ -{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, -{"pperm", "s,t", 0x70000481, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, -{"qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"qmac.00", "s,t", 0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmac.01", "s,t", 0x70000452, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmac.02", "s,t", 0x70000492, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmac.03", "s,t", 0x700004d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmacs.00", "s,t", 0x70000012, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmacs.01", "s,t", 0x70000052, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmacs.02", "s,t", 0x70000092, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, -{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, -{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, -{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, -{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, -{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, -{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, -{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, -{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, -{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, -{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, -{"recip.ps", "D,S", 0x46c00015, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, -{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, -{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, -{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, -{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, -{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, -{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, -{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, -{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, -{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, I37 }, -{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, I37 }, -{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, -{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 }, -{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 }, -{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, -{"rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 }, -{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, +{ "pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{ "pperm", "s,t", 0x70000481, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, +{ "qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "qmac.00", "s,t", 0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmac.01", "s,t", 0x70000452, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmac.02", "s,t", 0x70000492, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmac.03", "s,t", 0x700004d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmacs.00", "s,t", 0x70000012, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmacs.01", "s,t", 0x70000052, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmacs.02", "s,t", 0x70000092, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, +{ "rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, +{ "rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, +{ "rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, +{ "racl.ob", "X", 0x7800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, +{ "racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, +{ "racl.qh", "X", 0x7820003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, +{ "racm.ob", "X", 0x7900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, SB1, MX, 0 }, +{ "racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1|FP_D, RD_MACC, N54, 0, 0 }, +{ "racm.qh", "X", 0x7920003f, 0xfffff83f, WR_1|FP_D, RD_MACC, 0, MX, 0 }, +{ "recip.d", "D,S", 0x46200015, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, +{ "recip.ps", "D,S", 0x46c00015, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, +{ "recip.s", "D,S", 0x46000015, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, +{ "recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, +{ "recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, +{ "recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, +{ "recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, +{ "recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, +{ "recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, +{ "rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, +{ "rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, I37 }, +{ "rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, I37 }, +{ "remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, +{ "remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 }, +{ "remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 }, +{ "rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, +{ "rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 }, +{ "rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, /* rfe is moved below as it now conflicts with tlbgp */ -{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, -{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, -{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, -{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, -{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, -{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, -{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, -{"rsqrt.ps", "D,S", 0x46c00016, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, -{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, -{"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, -{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, -{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, -{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, -{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, -{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, -{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, -{"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, N54, 0, 0 }, -{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, -{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, -{"saa", "t,(b)", 0x70000018, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, -{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, -{"saad", "t,(b)", 0x70000019, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, -{"sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, -{"sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE|I37 }, -{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE }, -{"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, -{"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 }, -{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, -{"scdp", "t,d,s", 0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I69, 0, 0 }, -{"scdp", "t,d,A(b)", 0, (int) M_SCDP_AB, INSN_MACRO, 0, I69, 0, 0 }, -{"scwp", "t,d,s", 0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I37, 0, 0 }, -{"scwp", "t,d,A(b)", 0, (int) M_SCWP_AB, INSN_MACRO, 0, I37, 0, 0 }, +{ "rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, +{ "rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, +{ "rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 }, +{ "rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, +{ "rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, +{ "rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, +{ "rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, +{ "rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, +{ "rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, +{ "rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, +{ "round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, +{ "round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, +{ "rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_1|RD_2|FP_D, 0, I4_33, 0, 0 }, +{ "rsqrt.ps", "D,S", 0x46c00016, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, +{ "rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_1|RD_2|FP_S, 0, I4_33, 0, 0 }, +{ "rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{ "rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, M3D, 0 }, +{ "rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, +{ "rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_1|RD_2|FP_S, 0, 0, M3D, 0 }, +{ "rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, +{ "rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, +{ "rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, +{ "rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, SB1, MX, 0 }, +{ "rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, N54, 0, 0 }, +{ "rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, +{ "saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, +{ "saa", "t,(b)", 0x70000018, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, +{ "saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP, 0, 0 }, +{ "saad", "t,(b)", 0x70000019, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, +{ "sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, +{ "sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE|I37 }, +{ "sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE }, +{ "scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, +{ "scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 }, +{ "scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, +{ "scdp", "t,d,s", 0x7c000067, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I69, 0, 0 }, +{ "scdp", "t,d,A(b)", 0, (int) M_SCDP_AB, INSN_MACRO, 0, I69, 0, 0 }, +{ "scwp", "t,d,s", 0x7c000066, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, I37, 0, 0 }, +{ "scwp", "t,d,A(b)", 0, (int) M_SCWP_AB, INSN_MACRO, 0, I37, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ -{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2, 0, 0 }, -{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2, 0, 0 }, -{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2, 0, 0 }, -{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, I37, 0, 0 }, -{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, I37 }, -{"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I37, 0, 0 }, -{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, I37 }, -{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, -{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, -{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -{"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, -{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, -{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, -{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, I37 }, -{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, -{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, -{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, -{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, -{"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, -{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, -{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"seq", "S,T", 0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, -{"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, -{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, -{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, -{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, -{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sh", "t,o(b)", 0xa4000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"sigrie", "u", 0x04170000, 0xffff0000, TRAP, 0, I37, 0, 0 }, -{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, -{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, -{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, -{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, -{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ -{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, -{"sll", "D,S,T", 0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, -{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, -{"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, -{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, -{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"sq", "t,o(b)", 0x7c000000, 0xfc000000, RD_1|RD_3|SM, 0, MMI, 0, 0 }, -{"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, -{"sqc2", "+7,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, EE, 0, 0 }, -{"sqc2", "+7,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, -{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_1|RD_2|FP_D, 0, I2, 0, SF }, -{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, -{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, -{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ -{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, -{"sra", "D,S,T", 0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ -{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, -{"srl", "D,S,T", 0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, +{ "sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2, 0, 0 }, +{ "sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2, 0, 0 }, +{ "sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2, 0, 0 }, +{ "sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{ "sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, I37 }, +{ "sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I37, 0, 0 }, +{ "sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, I37 }, +{ "sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, +{ "sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, +{ "sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, +{ "sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, +{ "sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, +{ "sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{ "s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, +{ "s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, +{ "sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, +{ "sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, +{ "sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, I37 }, +{ "seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, +{ "seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, +{ "selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, +{ "selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, +{ "seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 }, +{ "seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "seq", "S,T", 0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sh", "t,o(b)", 0xa4000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "sigrie", "u", 0x04170000, 0xffff0000, TRAP, 0, I37, 0, 0 }, +{ "sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sleu", "S,T", 0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* sllv */ +{ "sll", "d,w,<", 0x00000000, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sll", "D,S,T", 0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "sll", "D,S,T", 0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "slt", "S,T", 0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "slti", "t,r,j", 0x28000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sltu", "S,T", 0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1, 0, 0 }, +{ "sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, +{ "sq", "t,o(b)", 0x7c000000, 0xfc000000, RD_1|RD_3|SM, 0, MMI, 0, 0 }, +{ "sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, +{ "sqc2", "+7,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, EE, 0, 0 }, +{ "sqc2", "+7,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, +{ "sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_1|RD_2|FP_D, 0, I2, 0, SF }, +{ "sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 }, +{ "sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 }, +{ "srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srav */ +{ "sra", "d,w,<", 0x00000003, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sra", "D,S,T", 0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "sra", "D,S,T", 0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, /* srlv */ +{ "srl", "d,w,<", 0x00000002, 0xffe0003f, WR_1|RD_2, 0, I1, 0, 0 }, +{ "srl", "D,S,T", 0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "srl", "D,S,T", 0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, /* ssnop is at the start of the table. */ -{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, -{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, -{"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, -{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, -{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, -{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, -{"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, -{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, -{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, -{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, -{"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ -{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, -{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ -{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swl */ -{"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, -{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ -{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swr */ -{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I4_33, 0, I37 }, -{"synciobdma", "", 0x0000008f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, -{"syncs", "", 0x0000018f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, -{"syncw", "", 0x0000010f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, -{"syncws", "", 0x0000014f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, -{"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, -{"sync_mb", "", 0x0000040f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, -{"sync_release", "", 0x0000048f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, -{"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, -{"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, -{"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1, 0, 0 }, -{"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32, 0, 0 }, -{"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2, 0, 0 }, -{"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2, 0, 0 }, -{"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, -{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, -{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, -{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, -{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, -{"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, -{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, -{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, -{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, -{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1, 0, SF }, -{"trunc.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, -{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, -{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, -{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, I69 }, -{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, I37 }, -{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, -{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, -{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, -{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, SB1, MX, 0 }, -{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, N54, 0, 0 }, -{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_1|FP_D, WR_MACC, 0, MX, 0 }, -{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, -{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, -{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32, 0, 0 }, -{"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55, 0, 0 }, -{"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1, 0, 0 }, -{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_2, 0, I33, 0, 0 }, -{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, -{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"yield", "s", 0x7c000009, 0xfc1fffff, RD_1|NODS, 0, 0, MT32, 0 }, -{"yield", "d,s", 0x7c000009, 0xfc1f07ff, WR_1|RD_2|NODS, 0, 0, MT32, 0 }, -{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, -{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, +{ "standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, +{ "sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, +{ "sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, +{ "sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{ "sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, +{ "sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "suba.s", "S,T", 0x46000019, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, +{ "subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 }, +{ "suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, +{ "suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, +{ "sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, +{ "sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{ "swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{ "swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{ "swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{ "swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ +{ "s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, +{ "swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, +{ "swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ +{ "scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swl */ +{ "swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, +{ "swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ +{ "invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swr */ +{ "swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I4_33, 0, I37 }, +{ "synciobdma", "", 0x0000008f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, +{ "syncs", "", 0x0000018f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, +{ "syncw", "", 0x0000010f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, +{ "syncws", "", 0x0000014f, 0xffffffff, NODS, INSN2_ALIAS, IOCT, 0, 0 }, +{ "sync_acquire", "", 0x0000044f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, +{ "sync_mb", "", 0x0000040f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, +{ "sync_release", "", 0x0000048f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, +{ "sync_rmb", "", 0x000004cf, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, +{ "sync_wmb", "", 0x0000010f, 0xffffffff, NODS, INSN2_ALIAS, I33, 0, 0 }, +{ "sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1, 0, 0 }, +{ "sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32, 0, 0 }, +{ "sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2, 0, 0 }, +{ "sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2, 0, 0 }, +{ "synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, +{ "syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, +{ "syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, +{ "teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ +{ "teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ +{ "tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ +{ "tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, +{ "tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 }, +{ "tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1, 0, 0 }, +{ "tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, +{ "tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ +{ "tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ +{ "tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, +{ "tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, +{ "tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ +{ "tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, +{ "trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, +{ "trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, +{ "trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, +{ "trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, +{ "trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1, 0, SF }, +{ "trunc.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, EE, 0, 0 }, +{ "trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, +{ "trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, +{ "trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, +{ "uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, I69 }, +{ "ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, I37 }, +{ "v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, +{ "wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, SB1, MX, 0 }, +{ "wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1|FP_D, WR_MACC, N54, 0, 0 }, +{ "wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_1|FP_D, WR_MACC, 0, MX, 0 }, +{ "wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, +{ "wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, +{ "wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, +{ "wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32, 0, 0 }, +{ "wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55, 0, 0 }, +{ "waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1, 0, 0 }, +{ "wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_2, 0, I33, 0, 0 }, +{ "wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, +{ "xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{ "xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "xor", "D,S,T", 0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{ "xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, +{ "xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, +{ "xori", "t,r,i", 0x38000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{ "yield", "s", 0x7c000009, 0xfc1fffff, RD_1|NODS, 0, 0, MT32, 0 }, +{ "yield", "d,s", 0x7c000009, 0xfc1f07ff, WR_1|RD_2|NODS, 0, 0, MT32, 0 }, +{ "zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, +{ "zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, /* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the mfhc0 and mthc0 XPA instructions, so they have been placed here to allow the XPA instructions to take precedence. */ -{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ -{"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, -{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, -{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, -{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, -{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, -{"ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, -{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, -{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, -{"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 }, -{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, -{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 }, -{"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, -{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, -{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, -{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, -{"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 }, -{"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, -{"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, -{"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, -{"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, -{"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, -{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, +{ "bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, +{ "bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, +{ "bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, +{ "cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, +{ "cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, +{ "ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, +{ "ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, +{ "ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, +{ "dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 }, +{ "dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, +{ "dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 }, +{ "dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, +{ "dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, +{ "dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, +{ "mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, +{ "mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{ "mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 }, +{ "mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{ "qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, +{ "qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, +{ "qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, +{ "qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, +{ "qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, +{ "qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X instructions, so they are here for the latters to take precedence. */ -{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{ "mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, /* Conflicts with the 4650's "mul" instruction. Nobody's using the 4010 any more, so move this insn out of the way. If the object format gave us more info, we could do this right. */ -{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_1|RD_2, 0, L1, 0, 0 }, +{ "addciu", "t,r,j", 0x70000000, 0xfc000000, WR_1|RD_2, 0, L1, 0, 0 }, /* MIPS DSP ASE */ -{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, -{"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 }, -{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, -{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, -{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, -{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D64, 0 }, -{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D64, 0 }, -{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, -{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, -{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_1|RD_2, 0, 0, D64, 0 }, -{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D64, 0 }, -{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, 0, D64, 0 }, -{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D64, 0 }, -{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, -{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, -{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, -{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, +{ "bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 }, +{ "bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, +{ "cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, +{ "cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, +{ "dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D64, 0 }, +{ "dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D64, 0 }, +{ "dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D64, 0 }, +{ "dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_1|RD_a, 0, 0, D64, 0 }, +{ "dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D64, 0 }, +{ "dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, 0, D64, 0 }, +{ "dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D64, 0 }, +{ "extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_1|RD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_1|RD_3|RD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, +{ "extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_1|RD_a, 0, 0, D32, 0 }, +{ "insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, /* lbux, ldx, lhx and lwx are the basic instruction section. */ -{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, -{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, -{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, -{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, -{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, -{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, -{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, -{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, -{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, -{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_1, 0, 0, D32, 0 }, -{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_1, 0, 0, D32, 0 }, -{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_1, 0, 0, D64, 0 }, -{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_1, 0, 0, D32, 0 }, -{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, -{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_1, 0, 0, D32, 0 }, -{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, -{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, 0, D32, 0 }, -{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D32, 0 }, -{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, -{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, -{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, -{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, -{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, +{ "maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_1|MOD_a|DSP_VOLA, 0, 0, D32, 0 }, +{ "muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, +{ "muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, +{ "muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, +{ "muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, +{ "mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D32, 0 }, +{ "mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D64, 0 }, +{ "mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, +{ "mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D64, 0 }, +{ "packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_1, 0, 0, D32, 0 }, +{ "rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_1, 0, 0, D32, 0 }, +{ "repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_1, 0, 0, D64, 0 }, +{ "repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_1, 0, 0, D32, 0 }, +{ "repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, +{ "repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_1, 0, 0, D32, 0 }, +{ "repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_1, 0, 0, D64, 0 }, +{ "replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, 0, D32, 0 }, +{ "shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, RD_2|MOD_a, 0, 0, D32, 0 }, +{ "shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_1|RD_2, 0, 0, D64, 0 }, +{ "shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{ "shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, +{ "subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{ "wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, +{ "wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_1|DSP_VOLA, 0, 0, D32, 0 }, /* MIPS DSP ASE Rev2 */ -{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_1|RD_2, 0, 0, D33, 0 }, -{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"append", "t,s,h", 0x7c000031, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, -{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, -{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, -{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_1|RD_2, 0, 0, D33, 0 }, -{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, -{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, -{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "append", "t,s,h", 0x7c000031, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33, 0 }, +{ "balign", "t,s,2", 0x7c000431, 0xfc00e7ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, 0, D33, 0 }, +{ "mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "prepend", "t,s,h", 0x7c000071, 0xfc0007ff, MOD_1|RD_2, 0, 0, D33, 0 }, +{ "shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_1|RD_2, 0, 0, D33, 0 }, +{ "shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +{ "dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, +{ "dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ -{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{ "bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, /* ST Microelectronics Loongson-2E and -2F. */ -{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, -{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, -{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, -{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"packushb", "D,S,T", 0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddb", "D,S,T", 0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddh", "D,S,T", 0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddw", "D,S,T", 0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddd", "D,S,T", 0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddsb", "D,S,T", 0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddsh", "D,S,T", 0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"paddush", "D,S,T", 0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pandn", "D,S,T", 0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pavgb", "D,S,T", 0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pavgh", "D,S,T", 0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pminub", "D,S,T", 0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmovmskb", "D,S", 0x46a00005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, -{"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmullh", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"biadd", "D,S", 0x46800005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, -{"pshufh", "D,S,T", 0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psllh", "D,S,T", 0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psllw", "D,S,T", 0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psrah", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psraw", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psrlh", "D,S,T", 0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psrlw", "D,S,T", 0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, -{"psubb", "D,S,T", 0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubh", "D,S,T", 0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubw", "D,S,T", 0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubd", "D,S,T", 0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubsb", "D,S,T", 0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubsh", "D,S,T", 0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"psubush", "D,S,T", 0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, -{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, -{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, +{ "mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, +{ "dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, +{ "gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 }, +{ "packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "packsswh", "D,S,T", 0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "packushb", "D,S,T", 0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "packushb", "D,S,T", 0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddb", "D,S,T", 0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddb", "D,S,T", 0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddb", "d,s,t", 0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddh", "D,S,T", 0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddh", "d,s,t", 0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddh", "D,S,T", 0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddw", "D,S,T", 0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddw", "D,S,T", 0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddw", "d,s,t", 0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddd", "D,S,T", 0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddd", "D,S,T", 0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddsb", "D,S,T", 0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddsb", "D,S,T", 0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddsb", "d,s,t", 0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddsh", "D,S,T", 0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddsh", "D,S,T", 0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddsh", "d,s,t", 0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "paddusb", "D,S,T", 0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "paddush", "D,S,T", 0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "paddush", "D,S,T", 0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pandn", "D,S,T", 0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pandn", "D,S,T", 0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pavgb", "D,S,T", 0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pavgb", "D,S,T", 0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pavgh", "D,S,T", 0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pavgh", "D,S,T", 0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pextrh", "D,S,T", 0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pminsh", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pminsh", "D,S,T", 0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pminub", "D,S,T", 0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pminub", "D,S,T", 0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmovmskb", "D,S", 0x46a00005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, +{ "pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, +{ "pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmullh", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "pasubub", "D,S,T", 0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "biadd", "D,S", 0x46800005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, +{ "biadd", "D,S", 0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D, 0, 0, LMMI, 0 }, +{ "pshufh", "D,S,T", 0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "pshufh", "D,S,T", 0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psllh", "D,S,T", 0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psllh", "D,S,T", 0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psllw", "D,S,T", 0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psllw", "D,S,T", 0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psrah", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psrah", "D,S,T", 0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psraw", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psraw", "D,S,T", 0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psrlh", "D,S,T", 0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psrlw", "D,S,T", 0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_1|RD_2, 0, MMI, 0, 0 }, +{ "psubb", "D,S,T", 0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubb", "D,S,T", 0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubb", "d,s,t", 0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubh", "D,S,T", 0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubh", "D,S,T", 0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubh", "d,s,t", 0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubw", "D,S,T", 0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubw", "D,S,T", 0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubw", "d,s,t", 0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubd", "D,S,T", 0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubd", "D,S,T", 0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubsb", "D,S,T", 0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubsb", "D,S,T", 0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubsb", "d,s,t", 0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubsh", "D,S,T", 0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubsh", "D,S,T", 0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubsh", "d,s,t", 0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, +{ "psubusb", "D,S,T", 0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "psubush", "D,S,T", 0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "psubush", "D,S,T", 0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, +{ "punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 }, +{ "sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, +{ "sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, LMMI, 0 }, /* MIPS Enhanced VA Scheme */ -{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"llwpe", "t,d,s", 0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 }, -{"llwpe", "t,d,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 }, -{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, -{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, -{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, -{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, -{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, -{"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"scwpe", "t,d,s", 0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 }, -{"scwpe", "t,d,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 }, -{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, -{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, -{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, -{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, -{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, -{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, -{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3|LM, 0, 0, EVA, 0 }, -{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "llwpe", "t,d,s", 0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 }, +{ "llwpe", "t,d,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 }, +{ "lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, +{ "lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, +{ "lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{ "lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, +{ "lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{ "sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "scwpe", "t,d,s", 0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 }, +{ "scwpe", "t,d,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 }, +{ "she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, +{ "swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{ "swle", "t,+j(b)", 0x7c000021, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, +{ "swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{ "swre", "t,+j(b)", 0x7c000022, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, +{ "swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{ "cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, +{ "cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, +{ "prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3|LM, 0, 0, EVA, 0 }, +{ "prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, /* MSA Extension. */ -{"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"slli.b", "+d,+e,+!", 0x78700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.h", "+d,+e,+@", 0x78600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.w", "+d,+e,+x", 0x78400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"slli.d", "+d,+e,+#", 0x78000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sra.b", "+d,+e,+h", 0x7880000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.h", "+d,+e,+h", 0x78a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.w", "+d,+e,+h", 0x78c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sra.d", "+d,+e,+h", 0x78e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srai.b", "+d,+e,+!", 0x78f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.h", "+d,+e,+@", 0x78e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.w", "+d,+e,+x", 0x78c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srai.d", "+d,+e,+#", 0x78800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srl.b", "+d,+e,+h", 0x7900000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.h", "+d,+e,+h", 0x7920000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.w", "+d,+e,+h", 0x7940000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srl.d", "+d,+e,+h", 0x7960000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srli.b", "+d,+e,+!", 0x79700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.h", "+d,+e,+@", 0x79600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.w", "+d,+e,+x", 0x79400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srli.d", "+d,+e,+#", 0x79000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclr.b", "+d,+e,+h", 0x7980000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.h", "+d,+e,+h", 0x79a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.w", "+d,+e,+h", 0x79c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclr.d", "+d,+e,+h", 0x79e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bclri.b", "+d,+e,+!", 0x79f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.h", "+d,+e,+@", 0x79e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.w", "+d,+e,+x", 0x79c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bclri.d", "+d,+e,+#", 0x79800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bset.b", "+d,+e,+h", 0x7a00000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.h", "+d,+e,+h", 0x7a20000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.w", "+d,+e,+h", 0x7a40000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bset.d", "+d,+e,+h", 0x7a60000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bseti.b", "+d,+e,+!", 0x7a700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.h", "+d,+e,+@", 0x7a600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.w", "+d,+e,+x", 0x7a400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bseti.d", "+d,+e,+#", 0x7a000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bneg.b", "+d,+e,+h", 0x7a80000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.h", "+d,+e,+h", 0x7aa0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.w", "+d,+e,+h", 0x7ac0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bneg.d", "+d,+e,+h", 0x7ae0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bnegi.b", "+d,+e,+!", 0x7af00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.h", "+d,+e,+@", 0x7ae00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.w", "+d,+e,+x", 0x7ac00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnegi.d", "+d,+e,+#", 0x7a800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"binsl.b", "+d,+e,+h", 0x7b00000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.h", "+d,+e,+h", 0x7b20000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.w", "+d,+e,+h", 0x7b40000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsl.d", "+d,+e,+h", 0x7b60000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsli.b", "+d,+e,+!", 0x7b700009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.h", "+d,+e,+@", 0x7b600009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.w", "+d,+e,+x", 0x7b400009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsli.d", "+d,+e,+#", 0x7b000009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsr.b", "+d,+e,+h", 0x7b80000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.h", "+d,+e,+h", 0x7ba0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.w", "+d,+e,+h", 0x7bc0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsr.d", "+d,+e,+h", 0x7be0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"binsri.b", "+d,+e,+!", 0x7bf00009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.h", "+d,+e,+@", 0x7be00009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.w", "+d,+e,+x", 0x7bc00009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"binsri.d", "+d,+e,+#", 0x7b800009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"addv.b", "+d,+e,+h", 0x7800000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.h", "+d,+e,+h", 0x7820000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.w", "+d,+e,+h", 0x7840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addv.d", "+d,+e,+h", 0x7860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"addvi.b", "+d,+e,+$", 0x78000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.h", "+d,+e,+$", 0x78200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.w", "+d,+e,+$", 0x78400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"addvi.d", "+d,+e,+$", 0x78600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subv.b", "+d,+e,+h", 0x7880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.h", "+d,+e,+h", 0x78a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.w", "+d,+e,+h", 0x78c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subv.d", "+d,+e,+h", 0x78e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subvi.b", "+d,+e,+$", 0x78800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.h", "+d,+e,+$", 0x78a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.w", "+d,+e,+$", 0x78c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"subvi.d", "+d,+e,+$", 0x78e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_s.b", "+d,+e,+h", 0x7900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.h", "+d,+e,+h", 0x7920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.w", "+d,+e,+h", 0x7940000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_s.d", "+d,+e,+h", 0x7960000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maxi_s.b", "+d,+e,+%", 0x79000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.h", "+d,+e,+%", 0x79200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.w", "+d,+e,+%", 0x79400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_s.d", "+d,+e,+%", 0x79600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_u.b", "+d,+e,+h", 0x7980000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.h", "+d,+e,+h", 0x79a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.w", "+d,+e,+h", 0x79c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_u.d", "+d,+e,+h", 0x79e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maxi_u.b", "+d,+e,+$", 0x79800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.h", "+d,+e,+$", 0x79a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.w", "+d,+e,+$", 0x79c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"maxi_u.d", "+d,+e,+$", 0x79e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"min_s.b", "+d,+e,+h", 0x7a00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.h", "+d,+e,+h", 0x7a20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.w", "+d,+e,+h", 0x7a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_s.d", "+d,+e,+h", 0x7a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mini_s.b", "+d,+e,+%", 0x7a000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.h", "+d,+e,+%", 0x7a200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.w", "+d,+e,+%", 0x7a400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_s.d", "+d,+e,+%", 0x7a600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"min_u.b", "+d,+e,+h", 0x7a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.h", "+d,+e,+h", 0x7aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.w", "+d,+e,+h", 0x7ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_u.d", "+d,+e,+h", 0x7ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mini_u.b", "+d,+e,+$", 0x7a800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.h", "+d,+e,+$", 0x7aa00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.w", "+d,+e,+$", 0x7ac00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"mini_u.d", "+d,+e,+$", 0x7ae00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"max_a.b", "+d,+e,+h", 0x7b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.h", "+d,+e,+h", 0x7b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.w", "+d,+e,+h", 0x7b40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"max_a.d", "+d,+e,+h", 0x7b60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.b", "+d,+e,+h", 0x7b80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.h", "+d,+e,+h", 0x7ba0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.w", "+d,+e,+h", 0x7bc0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"min_a.d", "+d,+e,+h", 0x7be0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.b", "+d,+e,+h", 0x7800000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.h", "+d,+e,+h", 0x7820000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.w", "+d,+e,+h", 0x7840000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceq.d", "+d,+e,+h", 0x7860000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ceqi.b", "+d,+e,+%", 0x78000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.h", "+d,+e,+%", 0x78200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.w", "+d,+e,+%", 0x78400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ceqi.d", "+d,+e,+%", 0x78600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clt_s.b", "+d,+e,+h", 0x7900000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.h", "+d,+e,+h", 0x7920000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.w", "+d,+e,+h", 0x7940000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_s.d", "+d,+e,+h", 0x7960000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clti_s.b", "+d,+e,+%", 0x79000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.h", "+d,+e,+%", 0x79200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.w", "+d,+e,+%", 0x79400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_s.d", "+d,+e,+%", 0x79600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clt_u.b", "+d,+e,+h", 0x7980000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.h", "+d,+e,+h", 0x79a0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.w", "+d,+e,+h", 0x79c0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clt_u.d", "+d,+e,+h", 0x79e0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clti_u.b", "+d,+e,+$", 0x79800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.h", "+d,+e,+$", 0x79a00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.w", "+d,+e,+$", 0x79c00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clti_u.d", "+d,+e,+$", 0x79e00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"cle_s.b", "+d,+e,+h", 0x7a00000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.h", "+d,+e,+h", 0x7a20000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.w", "+d,+e,+h", 0x7a40000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_s.d", "+d,+e,+h", 0x7a60000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clei_s.b", "+d,+e,+%", 0x7a000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.h", "+d,+e,+%", 0x7a200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.w", "+d,+e,+%", 0x7a400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_s.d", "+d,+e,+%", 0x7a600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"cle_u.b", "+d,+e,+h", 0x7a80000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.h", "+d,+e,+h", 0x7aa0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.w", "+d,+e,+h", 0x7ac0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"cle_u.d", "+d,+e,+h", 0x7ae0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"clei_u.b", "+d,+e,+$", 0x7a800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.h", "+d,+e,+$", 0x7aa00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.w", "+d,+e,+$", 0x7ac00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"clei_u.d", "+d,+e,+$", 0x7ae00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ld.b", "+d,+T(d)", 0x78000020, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.h", "+d,+U(d)", 0x78000021, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.w", "+d,+V(d)", 0x78000022, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"ld.d", "+d,+W(d)", 0x78000023, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, -{"st.b", "+d,+T(d)", 0x78000024, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.h", "+d,+U(d)", 0x78000025, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.w", "+d,+V(d)", 0x78000026, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"st.d", "+d,+W(d)", 0x78000027, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, -{"sat_s.b", "+d,+e,+!", 0x7870000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.h", "+d,+e,+@", 0x7860000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.w", "+d,+e,+x", 0x7840000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_s.d", "+d,+e,+#", 0x7800000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.b", "+d,+e,+!", 0x78f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.h", "+d,+e,+@", 0x78e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.w", "+d,+e,+x", 0x78c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"sat_u.d", "+d,+e,+#", 0x7880000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"add_a.b", "+d,+e,+h", 0x78000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.h", "+d,+e,+h", 0x78200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.w", "+d,+e,+h", 0x78400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"add_a.d", "+d,+e,+h", 0x78600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.b", "+d,+e,+h", 0x78800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.h", "+d,+e,+h", 0x78a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.w", "+d,+e,+h", 0x78c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_a.d", "+d,+e,+h", 0x78e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.b", "+d,+e,+h", 0x79000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.h", "+d,+e,+h", 0x79200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.w", "+d,+e,+h", 0x79400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_s.d", "+d,+e,+h", 0x79600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.b", "+d,+e,+h", 0x79800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.h", "+d,+e,+h", 0x79a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.w", "+d,+e,+h", 0x79c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"adds_u.d", "+d,+e,+h", 0x79e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.b", "+d,+e,+h", 0x7a000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.h", "+d,+e,+h", 0x7a200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.w", "+d,+e,+h", 0x7a400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_s.d", "+d,+e,+h", 0x7a600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.b", "+d,+e,+h", 0x7a800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.h", "+d,+e,+h", 0x7aa00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.w", "+d,+e,+h", 0x7ac00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ave_u.d", "+d,+e,+h", 0x7ae00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.b", "+d,+e,+h", 0x7b000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.h", "+d,+e,+h", 0x7b200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.w", "+d,+e,+h", 0x7b400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_s.d", "+d,+e,+h", 0x7b600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.b", "+d,+e,+h", 0x7b800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.h", "+d,+e,+h", 0x7ba00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.w", "+d,+e,+h", 0x7bc00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"aver_u.d", "+d,+e,+h", 0x7be00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.b", "+d,+e,+h", 0x78000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.h", "+d,+e,+h", 0x78200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.w", "+d,+e,+h", 0x78400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_s.d", "+d,+e,+h", 0x78600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.b", "+d,+e,+h", 0x78800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.h", "+d,+e,+h", 0x78a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.w", "+d,+e,+h", 0x78c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subs_u.d", "+d,+e,+h", 0x78e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.b", "+d,+e,+h", 0x79000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.h", "+d,+e,+h", 0x79200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.w", "+d,+e,+h", 0x79400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsus_u.d", "+d,+e,+h", 0x79600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.b", "+d,+e,+h", 0x79800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.h", "+d,+e,+h", 0x79a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.w", "+d,+e,+h", 0x79c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"subsuu_s.d", "+d,+e,+h", 0x79e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.b", "+d,+e,+h", 0x7a000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.h", "+d,+e,+h", 0x7a200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.w", "+d,+e,+h", 0x7a400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_s.d", "+d,+e,+h", 0x7a600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.b", "+d,+e,+h", 0x7a800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.h", "+d,+e,+h", 0x7aa00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.w", "+d,+e,+h", 0x7ac00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"asub_u.d", "+d,+e,+h", 0x7ae00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.b", "+d,+e,+h", 0x78000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.h", "+d,+e,+h", 0x78200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.w", "+d,+e,+h", 0x78400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulv.d", "+d,+e,+h", 0x78600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.b", "+d,+e,+h", 0x78800012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.h", "+d,+e,+h", 0x78a00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.w", "+d,+e,+h", 0x78c00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddv.d", "+d,+e,+h", 0x78e00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.b", "+d,+e,+h", 0x79000012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.h", "+d,+e,+h", 0x79200012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.w", "+d,+e,+h", 0x79400012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubv.d", "+d,+e,+h", 0x79600012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.b", "+d,+e,+h", 0x7a000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.h", "+d,+e,+h", 0x7a200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.w", "+d,+e,+h", 0x7a400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_s.d", "+d,+e,+h", 0x7a600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.b", "+d,+e,+h", 0x7a800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.h", "+d,+e,+h", 0x7aa00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.w", "+d,+e,+h", 0x7ac00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"div_u.d", "+d,+e,+h", 0x7ae00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.b", "+d,+e,+h", 0x7b000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.h", "+d,+e,+h", 0x7b200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.w", "+d,+e,+h", 0x7b400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_s.d", "+d,+e,+h", 0x7b600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.b", "+d,+e,+h", 0x7b800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.h", "+d,+e,+h", 0x7ba00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.w", "+d,+e,+h", 0x7bc00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mod_u.d", "+d,+e,+h", 0x7be00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.h", "+d,+e,+h", 0x78200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.w", "+d,+e,+h", 0x78400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_s.d", "+d,+e,+h", 0x78600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.h", "+d,+e,+h", 0x78a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.w", "+d,+e,+h", 0x78c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dotp_u.d", "+d,+e,+h", 0x78e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.h", "+d,+e,+h", 0x79200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.w", "+d,+e,+h", 0x79400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_s.d", "+d,+e,+h", 0x79600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.h", "+d,+e,+h", 0x79a00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.w", "+d,+e,+h", 0x79c00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpadd_u.d", "+d,+e,+h", 0x79e00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.h", "+d,+e,+h", 0x7a200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.w", "+d,+e,+h", 0x7a400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_s.d", "+d,+e,+h", 0x7a600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.h", "+d,+e,+h", 0x7aa00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.w", "+d,+e,+h", 0x7ac00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"dpsub_u.d", "+d,+e,+h", 0x7ae00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.b", "+d,+e+*", 0x78000014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.h", "+d,+e+*", 0x78200014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.w", "+d,+e+*", 0x78400014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sld.d", "+d,+e+*", 0x78600014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"splat.b", "+d,+e+*", 0x78800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.h", "+d,+e+*", 0x78a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.w", "+d,+e+*", 0x78c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splat.d", "+d,+e+*", 0x78e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splati.b", "+d,+e+o", 0x78400019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.h", "+d,+e+u", 0x78600019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.w", "+d,+e+v", 0x78700019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.d", "+d,+e+w", 0x78780019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pckev.b", "+d,+e,+h", 0x79000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.h", "+d,+e,+h", 0x79200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.w", "+d,+e,+h", 0x79400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckev.d", "+d,+e,+h", 0x79600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.b", "+d,+e,+h", 0x79800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.h", "+d,+e,+h", 0x79a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.w", "+d,+e,+h", 0x79c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"pckod.d", "+d,+e,+h", 0x79e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.b", "+d,+e,+h", 0x7a000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.h", "+d,+e,+h", 0x7a200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.w", "+d,+e,+h", 0x7a400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvl.d", "+d,+e,+h", 0x7a600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.b", "+d,+e,+h", 0x7a800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.h", "+d,+e,+h", 0x7aa00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.w", "+d,+e,+h", 0x7ac00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvr.d", "+d,+e,+h", 0x7ae00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.b", "+d,+e,+h", 0x7b000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.h", "+d,+e,+h", 0x7b200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.w", "+d,+e,+h", 0x7b400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvev.d", "+d,+e,+h", 0x7b600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.b", "+d,+e,+h", 0x7b800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.h", "+d,+e,+h", 0x7ba00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.w", "+d,+e,+h", 0x7bc00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ilvod.d", "+d,+e,+h", 0x7be00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.b", "+d,+e,+h", 0x78000015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.h", "+d,+e,+h", 0x78200015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.w", "+d,+e,+h", 0x78400015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"vshf.d", "+d,+e,+h", 0x78600015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.b", "+d,+e,+h", 0x78800015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.h", "+d,+e,+h", 0x78a00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.w", "+d,+e,+h", 0x78c00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srar.d", "+d,+e,+h", 0x78e00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srari.b", "+d,+e,+!", 0x7970000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.h", "+d,+e,+@", 0x7960000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.w", "+d,+e,+x", 0x7940000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srari.d", "+d,+e,+#", 0x7900000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlr.b", "+d,+e,+h", 0x79000015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.h", "+d,+e,+h", 0x79200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.w", "+d,+e,+h", 0x79400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlr.d", "+d,+e,+h", 0x79600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"srlri.b", "+d,+e,+!", 0x79f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.h", "+d,+e,+@", 0x79e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.w", "+d,+e,+x", 0x79c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"srlri.d", "+d,+e,+#", 0x7980000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"hadd_s.h", "+d,+e,+h", 0x7a200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_s.w", "+d,+e,+h", 0x7a400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_s.d", "+d,+e,+h", 0x7a600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.h", "+d,+e,+h", 0x7aa00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.w", "+d,+e,+h", 0x7ac00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hadd_u.d", "+d,+e,+h", 0x7ae00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.h", "+d,+e,+h", 0x7b200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.w", "+d,+e,+h", 0x7b400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_s.d", "+d,+e,+h", 0x7b600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.h", "+d,+e,+h", 0x7ba00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.w", "+d,+e,+h", 0x7bc00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"hsub_u.d", "+d,+e,+h", 0x7be00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"and.v", "+d,+e,+h", 0x7800001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"andi.b", "+d,+e,+|", 0x78000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"or.v", "+d,+e,+h", 0x7820001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ori.b", "+d,+e,+|", 0x79000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nor.v", "+d,+e,+h", 0x7840001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"nori.b", "+d,+e,+|", 0x7a000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"xor.v", "+d,+e,+h", 0x7860001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"xori.b", "+d,+e,+|", 0x7b000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bmnz.v", "+d,+e,+h", 0x7880001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bmnzi.b", "+d,+e,+|", 0x78000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"bmz.v", "+d,+e,+h", 0x78a0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bmzi.b", "+d,+e,+|", 0x79000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"bsel.v", "+d,+e,+h", 0x78c0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"bseli.b", "+d,+e,+|", 0x7a000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"shf.b", "+d,+e,+|", 0x78000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"shf.h", "+d,+e,+|", 0x79000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"shf.w", "+d,+e,+|", 0x7a000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"bnz.v", "+h,p", 0x45e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.v", "+h,p", 0x45600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.b", "+k,+e+o", 0x78800019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.h", "+k,+e+u", 0x78a00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.w", "+k,+e+v", 0x78b00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"copy_u.b", "+k,+e+o", 0x78c00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"insert.b", "+d+o,d", 0x79000019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.h", "+d+u,d", 0x79200019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.w", "+d+v,d", 0x79300019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.d", "+d+w,d", 0x79380019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, -{"insve.b", "+d+o,+e+&", 0x79400019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.h", "+d+u,+e+&", 0x79600019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.w", "+d+v,+e+&", 0x79700019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.d", "+d+w,+e+&", 0x79780019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"bnz.b", "+h,p", 0x47800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.h", "+h,p", 0x47a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.w", "+h,p", 0x47c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bnz.d", "+h,p", 0x47e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.b", "+h,p", 0x47000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.h", "+h,p", 0x47200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.w", "+h,p", 0x47400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"bz.d", "+h,p", 0x47600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -{"ldi.b", "+d,+^", 0x7b000007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.h", "+d,+^", 0x7b200007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.w", "+d,+^", 0x7b400007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"ldi.d", "+d,+^", 0x7b600007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, -{"fcaf.w", "+d,+e,+h", 0x7800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcaf.d", "+d,+e,+h", 0x7820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcun.w", "+d,+e,+h", 0x7840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcun.d", "+d,+e,+h", 0x7860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fceq.w", "+d,+e,+h", 0x7880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fceq.d", "+d,+e,+h", 0x78a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcueq.w", "+d,+e,+h", 0x78c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcueq.d", "+d,+e,+h", 0x78e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclt.w", "+d,+e,+h", 0x7900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclt.d", "+d,+e,+h", 0x7920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcult.w", "+d,+e,+h", 0x7940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcult.d", "+d,+e,+h", 0x7960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcle.w", "+d,+e,+h", 0x7980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcle.d", "+d,+e,+h", 0x79a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcule.w", "+d,+e,+h", 0x79c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcule.d", "+d,+e,+h", 0x79e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsaf.w", "+d,+e,+h", 0x7a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsaf.d", "+d,+e,+h", 0x7a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsun.w", "+d,+e,+h", 0x7a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsun.d", "+d,+e,+h", 0x7a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fseq.w", "+d,+e,+h", 0x7a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fseq.d", "+d,+e,+h", 0x7aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsueq.w", "+d,+e,+h", 0x7ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsueq.d", "+d,+e,+h", 0x7ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fslt.w", "+d,+e,+h", 0x7b00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fslt.d", "+d,+e,+h", 0x7b20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsult.w", "+d,+e,+h", 0x7b40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsult.d", "+d,+e,+h", 0x7b60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsle.w", "+d,+e,+h", 0x7b80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsle.d", "+d,+e,+h", 0x7ba0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsule.w", "+d,+e,+h", 0x7bc0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsule.d", "+d,+e,+h", 0x7be0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fadd.w", "+d,+e,+h", 0x7800001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fadd.d", "+d,+e,+h", 0x7820001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsub.w", "+d,+e,+h", 0x7840001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsub.d", "+d,+e,+h", 0x7860001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmul.w", "+d,+e,+h", 0x7880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmul.d", "+d,+e,+h", 0x78a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fdiv.w", "+d,+e,+h", 0x78c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fdiv.d", "+d,+e,+h", 0x78e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmadd.w", "+d,+e,+h", 0x7900001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmadd.d", "+d,+e,+h", 0x7920001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmsub.w", "+d,+e,+h", 0x7940001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmsub.d", "+d,+e,+h", 0x7960001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexp2.w", "+d,+e,+h", 0x79c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexp2.d", "+d,+e,+h", 0x79e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexdo.h", "+d,+e,+h", 0x7a00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fexdo.w", "+d,+e,+h", 0x7a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ftq.h", "+d,+e,+h", 0x7a80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"ftq.w", "+d,+e,+h", 0x7aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin.w", "+d,+e,+h", 0x7b00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin.d", "+d,+e,+h", 0x7b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin_a.w", "+d,+e,+h", 0x7b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmin_a.d", "+d,+e,+h", 0x7b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax.w", "+d,+e,+h", 0x7b80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax.d", "+d,+e,+h", 0x7ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax_a.w", "+d,+e,+h", 0x7bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fmax_a.d", "+d,+e,+h", 0x7be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcor.w", "+d,+e,+h", 0x7840001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcor.d", "+d,+e,+h", 0x7860001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcune.w", "+d,+e,+h", 0x7880001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcune.d", "+d,+e,+h", 0x78a0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcne.w", "+d,+e,+h", 0x78c0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fcne.d", "+d,+e,+h", 0x78e0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mul_q.h", "+d,+e,+h", 0x7900001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mul_q.w", "+d,+e,+h", 0x7920001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"madd_q.h", "+d,+e,+h", 0x7940001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"madd_q.w", "+d,+e,+h", 0x7960001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msub_q.h", "+d,+e,+h", 0x7980001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msub_q.w", "+d,+e,+h", 0x79a0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsor.w", "+d,+e,+h", 0x7a40001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsor.d", "+d,+e,+h", 0x7a60001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsune.w", "+d,+e,+h", 0x7a80001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsune.d", "+d,+e,+h", 0x7aa0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsne.w", "+d,+e,+h", 0x7ac0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fsne.d", "+d,+e,+h", 0x7ae0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulr_q.h", "+d,+e,+h", 0x7b00001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"mulr_q.w", "+d,+e,+h", 0x7b20001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddr_q.h", "+d,+e,+h", 0x7b40001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"maddr_q.w", "+d,+e,+h", 0x7b60001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubr_q.h", "+d,+e,+h", 0x7b80001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"msubr_q.w", "+d,+e,+h", 0x7ba0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_s.w", "+d,+e", 0x7b22001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_s.d", "+d,+e", 0x7b23001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_u.w", "+d,+e", 0x7b24001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftrunc_u.d", "+d,+e", 0x7b25001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"ctcmsa", "+l,d", 0x783e0019, 0xffff003f, RD_2|CM, 0, 0, MSA, 0 }, -{"cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|CM, 0, 0, MSA, 0 }, -{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, -{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, +{ "sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "slli.b", "+d,+e,+!", 0x78700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.h", "+d,+e,+@", 0x78600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.w", "+d,+e,+x", 0x78400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "slli.d", "+d,+e,+#", 0x78000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sra.b", "+d,+e,+h", 0x7880000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.h", "+d,+e,+h", 0x78a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.w", "+d,+e,+h", 0x78c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sra.d", "+d,+e,+h", 0x78e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srai.b", "+d,+e,+!", 0x78f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.h", "+d,+e,+@", 0x78e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.w", "+d,+e,+x", 0x78c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srai.d", "+d,+e,+#", 0x78800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srl.b", "+d,+e,+h", 0x7900000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.h", "+d,+e,+h", 0x7920000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.w", "+d,+e,+h", 0x7940000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srl.d", "+d,+e,+h", 0x7960000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srli.b", "+d,+e,+!", 0x79700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.h", "+d,+e,+@", 0x79600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.w", "+d,+e,+x", 0x79400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srli.d", "+d,+e,+#", 0x79000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclr.b", "+d,+e,+h", 0x7980000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.h", "+d,+e,+h", 0x79a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.w", "+d,+e,+h", 0x79c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclr.d", "+d,+e,+h", 0x79e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bclri.b", "+d,+e,+!", 0x79f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.h", "+d,+e,+@", 0x79e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.w", "+d,+e,+x", 0x79c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bclri.d", "+d,+e,+#", 0x79800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bset.b", "+d,+e,+h", 0x7a00000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.h", "+d,+e,+h", 0x7a20000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.w", "+d,+e,+h", 0x7a40000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bset.d", "+d,+e,+h", 0x7a60000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bseti.b", "+d,+e,+!", 0x7a700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.h", "+d,+e,+@", 0x7a600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.w", "+d,+e,+x", 0x7a400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bseti.d", "+d,+e,+#", 0x7a000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bneg.b", "+d,+e,+h", 0x7a80000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.h", "+d,+e,+h", 0x7aa0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.w", "+d,+e,+h", 0x7ac0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bneg.d", "+d,+e,+h", 0x7ae0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bnegi.b", "+d,+e,+!", 0x7af00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.h", "+d,+e,+@", 0x7ae00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.w", "+d,+e,+x", 0x7ac00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnegi.d", "+d,+e,+#", 0x7a800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "binsl.b", "+d,+e,+h", 0x7b00000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.h", "+d,+e,+h", 0x7b20000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.w", "+d,+e,+h", 0x7b40000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsl.d", "+d,+e,+h", 0x7b60000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsli.b", "+d,+e,+!", 0x7b700009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.h", "+d,+e,+@", 0x7b600009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.w", "+d,+e,+x", 0x7b400009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsli.d", "+d,+e,+#", 0x7b000009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsr.b", "+d,+e,+h", 0x7b80000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.h", "+d,+e,+h", 0x7ba0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.w", "+d,+e,+h", 0x7bc0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsr.d", "+d,+e,+h", 0x7be0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "binsri.b", "+d,+e,+!", 0x7bf00009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.h", "+d,+e,+@", 0x7be00009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.w", "+d,+e,+x", 0x7bc00009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "binsri.d", "+d,+e,+#", 0x7b800009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "addv.b", "+d,+e,+h", 0x7800000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.h", "+d,+e,+h", 0x7820000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.w", "+d,+e,+h", 0x7840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addv.d", "+d,+e,+h", 0x7860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "addvi.b", "+d,+e,+$", 0x78000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.h", "+d,+e,+$", 0x78200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.w", "+d,+e,+$", 0x78400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "addvi.d", "+d,+e,+$", 0x78600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subv.b", "+d,+e,+h", 0x7880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.h", "+d,+e,+h", 0x78a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.w", "+d,+e,+h", 0x78c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subv.d", "+d,+e,+h", 0x78e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subvi.b", "+d,+e,+$", 0x78800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.h", "+d,+e,+$", 0x78a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.w", "+d,+e,+$", 0x78c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "subvi.d", "+d,+e,+$", 0x78e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_s.b", "+d,+e,+h", 0x7900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.h", "+d,+e,+h", 0x7920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.w", "+d,+e,+h", 0x7940000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_s.d", "+d,+e,+h", 0x7960000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maxi_s.b", "+d,+e,+%", 0x79000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.h", "+d,+e,+%", 0x79200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.w", "+d,+e,+%", 0x79400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_s.d", "+d,+e,+%", 0x79600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_u.b", "+d,+e,+h", 0x7980000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.h", "+d,+e,+h", 0x79a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.w", "+d,+e,+h", 0x79c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_u.d", "+d,+e,+h", 0x79e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maxi_u.b", "+d,+e,+$", 0x79800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.h", "+d,+e,+$", 0x79a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.w", "+d,+e,+$", 0x79c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "maxi_u.d", "+d,+e,+$", 0x79e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "min_s.b", "+d,+e,+h", 0x7a00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.h", "+d,+e,+h", 0x7a20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.w", "+d,+e,+h", 0x7a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_s.d", "+d,+e,+h", 0x7a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mini_s.b", "+d,+e,+%", 0x7a000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.h", "+d,+e,+%", 0x7a200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.w", "+d,+e,+%", 0x7a400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_s.d", "+d,+e,+%", 0x7a600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "min_u.b", "+d,+e,+h", 0x7a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.h", "+d,+e,+h", 0x7aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.w", "+d,+e,+h", 0x7ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_u.d", "+d,+e,+h", 0x7ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mini_u.b", "+d,+e,+$", 0x7a800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.h", "+d,+e,+$", 0x7aa00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.w", "+d,+e,+$", 0x7ac00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "mini_u.d", "+d,+e,+$", 0x7ae00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "max_a.b", "+d,+e,+h", 0x7b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.h", "+d,+e,+h", 0x7b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.w", "+d,+e,+h", 0x7b40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "max_a.d", "+d,+e,+h", 0x7b60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.b", "+d,+e,+h", 0x7b80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.h", "+d,+e,+h", 0x7ba0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.w", "+d,+e,+h", 0x7bc0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "min_a.d", "+d,+e,+h", 0x7be0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.b", "+d,+e,+h", 0x7800000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.h", "+d,+e,+h", 0x7820000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.w", "+d,+e,+h", 0x7840000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceq.d", "+d,+e,+h", 0x7860000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ceqi.b", "+d,+e,+%", 0x78000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.h", "+d,+e,+%", 0x78200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.w", "+d,+e,+%", 0x78400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ceqi.d", "+d,+e,+%", 0x78600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clt_s.b", "+d,+e,+h", 0x7900000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.h", "+d,+e,+h", 0x7920000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.w", "+d,+e,+h", 0x7940000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_s.d", "+d,+e,+h", 0x7960000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clti_s.b", "+d,+e,+%", 0x79000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.h", "+d,+e,+%", 0x79200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.w", "+d,+e,+%", 0x79400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_s.d", "+d,+e,+%", 0x79600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clt_u.b", "+d,+e,+h", 0x7980000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.h", "+d,+e,+h", 0x79a0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.w", "+d,+e,+h", 0x79c0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clt_u.d", "+d,+e,+h", 0x79e0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clti_u.b", "+d,+e,+$", 0x79800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.h", "+d,+e,+$", 0x79a00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.w", "+d,+e,+$", 0x79c00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clti_u.d", "+d,+e,+$", 0x79e00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "cle_s.b", "+d,+e,+h", 0x7a00000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.h", "+d,+e,+h", 0x7a20000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.w", "+d,+e,+h", 0x7a40000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_s.d", "+d,+e,+h", 0x7a60000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clei_s.b", "+d,+e,+%", 0x7a000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.h", "+d,+e,+%", 0x7a200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.w", "+d,+e,+%", 0x7a400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_s.d", "+d,+e,+%", 0x7a600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "cle_u.b", "+d,+e,+h", 0x7a80000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.h", "+d,+e,+h", 0x7aa0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.w", "+d,+e,+h", 0x7ac0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "cle_u.d", "+d,+e,+h", 0x7ae0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "clei_u.b", "+d,+e,+$", 0x7a800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.h", "+d,+e,+$", 0x7aa00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.w", "+d,+e,+$", 0x7ac00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "clei_u.d", "+d,+e,+$", 0x7ae00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ld.b", "+d,+T(d)", 0x78000020, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.h", "+d,+U(d)", 0x78000021, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.w", "+d,+V(d)", 0x78000022, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "ld.d", "+d,+W(d)", 0x78000023, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{ "st.b", "+d,+T(d)", 0x78000024, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.h", "+d,+U(d)", 0x78000025, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.w", "+d,+V(d)", 0x78000026, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "st.d", "+d,+W(d)", 0x78000027, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{ "sat_s.b", "+d,+e,+!", 0x7870000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.h", "+d,+e,+@", 0x7860000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.w", "+d,+e,+x", 0x7840000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_s.d", "+d,+e,+#", 0x7800000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.b", "+d,+e,+!", 0x78f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.h", "+d,+e,+@", 0x78e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.w", "+d,+e,+x", 0x78c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "sat_u.d", "+d,+e,+#", 0x7880000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "add_a.b", "+d,+e,+h", 0x78000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.h", "+d,+e,+h", 0x78200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.w", "+d,+e,+h", 0x78400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "add_a.d", "+d,+e,+h", 0x78600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.b", "+d,+e,+h", 0x78800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.h", "+d,+e,+h", 0x78a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.w", "+d,+e,+h", 0x78c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_a.d", "+d,+e,+h", 0x78e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.b", "+d,+e,+h", 0x79000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.h", "+d,+e,+h", 0x79200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.w", "+d,+e,+h", 0x79400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_s.d", "+d,+e,+h", 0x79600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.b", "+d,+e,+h", 0x79800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.h", "+d,+e,+h", 0x79a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.w", "+d,+e,+h", 0x79c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "adds_u.d", "+d,+e,+h", 0x79e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.b", "+d,+e,+h", 0x7a000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.h", "+d,+e,+h", 0x7a200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.w", "+d,+e,+h", 0x7a400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_s.d", "+d,+e,+h", 0x7a600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.b", "+d,+e,+h", 0x7a800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.h", "+d,+e,+h", 0x7aa00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.w", "+d,+e,+h", 0x7ac00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ave_u.d", "+d,+e,+h", 0x7ae00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.b", "+d,+e,+h", 0x7b000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.h", "+d,+e,+h", 0x7b200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.w", "+d,+e,+h", 0x7b400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_s.d", "+d,+e,+h", 0x7b600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.b", "+d,+e,+h", 0x7b800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.h", "+d,+e,+h", 0x7ba00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.w", "+d,+e,+h", 0x7bc00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "aver_u.d", "+d,+e,+h", 0x7be00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.b", "+d,+e,+h", 0x78000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.h", "+d,+e,+h", 0x78200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.w", "+d,+e,+h", 0x78400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_s.d", "+d,+e,+h", 0x78600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.b", "+d,+e,+h", 0x78800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.h", "+d,+e,+h", 0x78a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.w", "+d,+e,+h", 0x78c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subs_u.d", "+d,+e,+h", 0x78e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.b", "+d,+e,+h", 0x79000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.h", "+d,+e,+h", 0x79200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.w", "+d,+e,+h", 0x79400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsus_u.d", "+d,+e,+h", 0x79600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.b", "+d,+e,+h", 0x79800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.h", "+d,+e,+h", 0x79a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.w", "+d,+e,+h", 0x79c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "subsuu_s.d", "+d,+e,+h", 0x79e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.b", "+d,+e,+h", 0x7a000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.h", "+d,+e,+h", 0x7a200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.w", "+d,+e,+h", 0x7a400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_s.d", "+d,+e,+h", 0x7a600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.b", "+d,+e,+h", 0x7a800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.h", "+d,+e,+h", 0x7aa00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.w", "+d,+e,+h", 0x7ac00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "asub_u.d", "+d,+e,+h", 0x7ae00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.b", "+d,+e,+h", 0x78000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.h", "+d,+e,+h", 0x78200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.w", "+d,+e,+h", 0x78400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulv.d", "+d,+e,+h", 0x78600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.b", "+d,+e,+h", 0x78800012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.h", "+d,+e,+h", 0x78a00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.w", "+d,+e,+h", 0x78c00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddv.d", "+d,+e,+h", 0x78e00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.b", "+d,+e,+h", 0x79000012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.h", "+d,+e,+h", 0x79200012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.w", "+d,+e,+h", 0x79400012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubv.d", "+d,+e,+h", 0x79600012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.b", "+d,+e,+h", 0x7a000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.h", "+d,+e,+h", 0x7a200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.w", "+d,+e,+h", 0x7a400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_s.d", "+d,+e,+h", 0x7a600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.b", "+d,+e,+h", 0x7a800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.h", "+d,+e,+h", 0x7aa00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.w", "+d,+e,+h", 0x7ac00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "div_u.d", "+d,+e,+h", 0x7ae00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.b", "+d,+e,+h", 0x7b000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.h", "+d,+e,+h", 0x7b200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.w", "+d,+e,+h", 0x7b400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_s.d", "+d,+e,+h", 0x7b600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.b", "+d,+e,+h", 0x7b800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.h", "+d,+e,+h", 0x7ba00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.w", "+d,+e,+h", 0x7bc00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mod_u.d", "+d,+e,+h", 0x7be00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.h", "+d,+e,+h", 0x78200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.w", "+d,+e,+h", 0x78400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_s.d", "+d,+e,+h", 0x78600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.h", "+d,+e,+h", 0x78a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.w", "+d,+e,+h", 0x78c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dotp_u.d", "+d,+e,+h", 0x78e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.h", "+d,+e,+h", 0x79200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.w", "+d,+e,+h", 0x79400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_s.d", "+d,+e,+h", 0x79600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.h", "+d,+e,+h", 0x79a00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.w", "+d,+e,+h", 0x79c00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpadd_u.d", "+d,+e,+h", 0x79e00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.h", "+d,+e,+h", 0x7a200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.w", "+d,+e,+h", 0x7a400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_s.d", "+d,+e,+h", 0x7a600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.h", "+d,+e,+h", 0x7aa00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.w", "+d,+e,+h", 0x7ac00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "dpsub_u.d", "+d,+e,+h", 0x7ae00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.b", "+d,+e+*", 0x78000014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.h", "+d,+e+*", 0x78200014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.w", "+d,+e+*", 0x78400014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sld.d", "+d,+e+*", 0x78600014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "splat.b", "+d,+e+*", 0x78800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.h", "+d,+e+*", 0x78a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.w", "+d,+e+*", 0x78c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splat.d", "+d,+e+*", 0x78e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "splati.b", "+d,+e+o", 0x78400019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.h", "+d,+e+u", 0x78600019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.w", "+d,+e+v", 0x78700019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "splati.d", "+d,+e+w", 0x78780019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pckev.b", "+d,+e,+h", 0x79000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.h", "+d,+e,+h", 0x79200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.w", "+d,+e,+h", 0x79400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckev.d", "+d,+e,+h", 0x79600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.b", "+d,+e,+h", 0x79800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.h", "+d,+e,+h", 0x79a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.w", "+d,+e,+h", 0x79c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "pckod.d", "+d,+e,+h", 0x79e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.b", "+d,+e,+h", 0x7a000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.h", "+d,+e,+h", 0x7a200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.w", "+d,+e,+h", 0x7a400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvl.d", "+d,+e,+h", 0x7a600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.b", "+d,+e,+h", 0x7a800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.h", "+d,+e,+h", 0x7aa00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.w", "+d,+e,+h", 0x7ac00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvr.d", "+d,+e,+h", 0x7ae00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.b", "+d,+e,+h", 0x7b000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.h", "+d,+e,+h", 0x7b200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.w", "+d,+e,+h", 0x7b400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvev.d", "+d,+e,+h", 0x7b600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.b", "+d,+e,+h", 0x7b800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.h", "+d,+e,+h", 0x7ba00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.w", "+d,+e,+h", 0x7bc00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ilvod.d", "+d,+e,+h", 0x7be00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.b", "+d,+e,+h", 0x78000015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.h", "+d,+e,+h", 0x78200015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.w", "+d,+e,+h", 0x78400015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "vshf.d", "+d,+e,+h", 0x78600015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.b", "+d,+e,+h", 0x78800015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.h", "+d,+e,+h", 0x78a00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.w", "+d,+e,+h", 0x78c00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srar.d", "+d,+e,+h", 0x78e00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srari.b", "+d,+e,+!", 0x7970000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.h", "+d,+e,+@", 0x7960000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.w", "+d,+e,+x", 0x7940000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srari.d", "+d,+e,+#", 0x7900000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlr.b", "+d,+e,+h", 0x79000015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.h", "+d,+e,+h", 0x79200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.w", "+d,+e,+h", 0x79400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlr.d", "+d,+e,+h", 0x79600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "srlri.b", "+d,+e,+!", 0x79f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.h", "+d,+e,+@", 0x79e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.w", "+d,+e,+x", 0x79c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "srlri.d", "+d,+e,+#", 0x7980000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "hadd_s.h", "+d,+e,+h", 0x7a200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_s.w", "+d,+e,+h", 0x7a400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_s.d", "+d,+e,+h", 0x7a600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.h", "+d,+e,+h", 0x7aa00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.w", "+d,+e,+h", 0x7ac00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hadd_u.d", "+d,+e,+h", 0x7ae00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.h", "+d,+e,+h", 0x7b200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.w", "+d,+e,+h", 0x7b400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_s.d", "+d,+e,+h", 0x7b600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.h", "+d,+e,+h", 0x7ba00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.w", "+d,+e,+h", 0x7bc00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "hsub_u.d", "+d,+e,+h", 0x7be00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "and.v", "+d,+e,+h", 0x7800001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "andi.b", "+d,+e,+|", 0x78000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "or.v", "+d,+e,+h", 0x7820001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ori.b", "+d,+e,+|", 0x79000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nor.v", "+d,+e,+h", 0x7840001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "nori.b", "+d,+e,+|", 0x7a000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "xor.v", "+d,+e,+h", 0x7860001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "xori.b", "+d,+e,+|", 0x7b000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bmnz.v", "+d,+e,+h", 0x7880001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bmnzi.b", "+d,+e,+|", 0x78000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "bmz.v", "+d,+e,+h", 0x78a0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bmzi.b", "+d,+e,+|", 0x79000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "bsel.v", "+d,+e,+h", 0x78c0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "bseli.b", "+d,+e,+|", 0x7a000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.b", "+d,+e,+|", 0x78000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.h", "+d,+e,+|", 0x79000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "shf.w", "+d,+e,+|", 0x7a000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "bnz.v", "+h,p", 0x45e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.v", "+h,p", 0x45600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.b", "+k,+e+o", 0x78800019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.h", "+k,+e+u", 0x78a00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.w", "+k,+e+v", 0x78b00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_s.d", "+k,+e+w", 0x78b80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "copy_u.b", "+k,+e+o", 0x78c00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_u.h", "+k,+e+u", 0x78e00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{ "insert.b", "+d+o,d", 0x79000019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.h", "+d+u,d", 0x79200019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.w", "+d+v,d", 0x79300019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insert.d", "+d+w,d", 0x79380019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{ "insve.b", "+d+o,+e+&", 0x79400019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.h", "+d+u,+e+&", 0x79600019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.w", "+d+v,+e+&", 0x79700019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "insve.d", "+d+w,+e+&", 0x79780019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{ "bnz.b", "+h,p", 0x47800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.h", "+h,p", 0x47a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.w", "+h,p", 0x47c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bnz.d", "+h,p", 0x47e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.b", "+h,p", 0x47000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.h", "+h,p", 0x47200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.w", "+h,p", 0x47400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "bz.d", "+h,p", 0x47600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{ "ldi.b", "+d,+^", 0x7b000007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.h", "+d,+^", 0x7b200007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.w", "+d,+^", 0x7b400007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "ldi.d", "+d,+^", 0x7b600007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{ "fcaf.w", "+d,+e,+h", 0x7800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcaf.d", "+d,+e,+h", 0x7820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcun.w", "+d,+e,+h", 0x7840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcun.d", "+d,+e,+h", 0x7860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fceq.w", "+d,+e,+h", 0x7880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fceq.d", "+d,+e,+h", 0x78a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcueq.w", "+d,+e,+h", 0x78c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcueq.d", "+d,+e,+h", 0x78e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclt.w", "+d,+e,+h", 0x7900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclt.d", "+d,+e,+h", 0x7920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcult.w", "+d,+e,+h", 0x7940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcult.d", "+d,+e,+h", 0x7960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcle.w", "+d,+e,+h", 0x7980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcle.d", "+d,+e,+h", 0x79a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcule.w", "+d,+e,+h", 0x79c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcule.d", "+d,+e,+h", 0x79e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsaf.w", "+d,+e,+h", 0x7a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsaf.d", "+d,+e,+h", 0x7a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsun.w", "+d,+e,+h", 0x7a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsun.d", "+d,+e,+h", 0x7a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fseq.w", "+d,+e,+h", 0x7a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fseq.d", "+d,+e,+h", 0x7aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsueq.w", "+d,+e,+h", 0x7ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsueq.d", "+d,+e,+h", 0x7ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fslt.w", "+d,+e,+h", 0x7b00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fslt.d", "+d,+e,+h", 0x7b20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsult.w", "+d,+e,+h", 0x7b40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsult.d", "+d,+e,+h", 0x7b60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsle.w", "+d,+e,+h", 0x7b80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsle.d", "+d,+e,+h", 0x7ba0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsule.w", "+d,+e,+h", 0x7bc0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsule.d", "+d,+e,+h", 0x7be0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fadd.w", "+d,+e,+h", 0x7800001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fadd.d", "+d,+e,+h", 0x7820001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsub.w", "+d,+e,+h", 0x7840001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsub.d", "+d,+e,+h", 0x7860001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmul.w", "+d,+e,+h", 0x7880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmul.d", "+d,+e,+h", 0x78a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fdiv.w", "+d,+e,+h", 0x78c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fdiv.d", "+d,+e,+h", 0x78e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmadd.w", "+d,+e,+h", 0x7900001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmadd.d", "+d,+e,+h", 0x7920001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmsub.w", "+d,+e,+h", 0x7940001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmsub.d", "+d,+e,+h", 0x7960001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexp2.w", "+d,+e,+h", 0x79c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexp2.d", "+d,+e,+h", 0x79e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexdo.h", "+d,+e,+h", 0x7a00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fexdo.w", "+d,+e,+h", 0x7a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ftq.h", "+d,+e,+h", 0x7a80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "ftq.w", "+d,+e,+h", 0x7aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin.w", "+d,+e,+h", 0x7b00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin.d", "+d,+e,+h", 0x7b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin_a.w", "+d,+e,+h", 0x7b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmin_a.d", "+d,+e,+h", 0x7b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax.w", "+d,+e,+h", 0x7b80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax.d", "+d,+e,+h", 0x7ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax_a.w", "+d,+e,+h", 0x7bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fmax_a.d", "+d,+e,+h", 0x7be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcor.w", "+d,+e,+h", 0x7840001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcor.d", "+d,+e,+h", 0x7860001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcune.w", "+d,+e,+h", 0x7880001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcune.d", "+d,+e,+h", 0x78a0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcne.w", "+d,+e,+h", 0x78c0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fcne.d", "+d,+e,+h", 0x78e0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mul_q.h", "+d,+e,+h", 0x7900001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mul_q.w", "+d,+e,+h", 0x7920001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "madd_q.h", "+d,+e,+h", 0x7940001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "madd_q.w", "+d,+e,+h", 0x7960001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msub_q.h", "+d,+e,+h", 0x7980001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msub_q.w", "+d,+e,+h", 0x79a0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsor.w", "+d,+e,+h", 0x7a40001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsor.d", "+d,+e,+h", 0x7a60001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsune.w", "+d,+e,+h", 0x7a80001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsune.d", "+d,+e,+h", 0x7aa0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsne.w", "+d,+e,+h", 0x7ac0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fsne.d", "+d,+e,+h", 0x7ae0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulr_q.h", "+d,+e,+h", 0x7b00001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "mulr_q.w", "+d,+e,+h", 0x7b20001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddr_q.h", "+d,+e,+h", 0x7b40001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "maddr_q.w", "+d,+e,+h", 0x7b60001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubr_q.h", "+d,+e,+h", 0x7b80001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "msubr_q.w", "+d,+e,+h", 0x7ba0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{ "fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_s.w", "+d,+e", 0x7b22001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_s.d", "+d,+e", 0x7b23001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_u.w", "+d,+e", 0x7b24001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftrunc_u.d", "+d,+e", 0x7b25001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "ctcmsa", "+l,d", 0x783e0019, 0xffff003f, RD_2|CM, 0, 0, MSA, 0 }, +{ "cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|CM, 0, 0, MSA, 0 }, +{ "move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{ "lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, +{ "dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, /* interAptiv MR2 instruction extensions. */ -{"restore", "-m", 0x7000001f, 0xfc00603f, WR_31|NODS, MOD_SP, IAMR2, 0, 0 }, -{"save", "-m", 0x7000201f, 0xfc00603f, NODS, RD_31|MOD_SP, IAMR2, 0, 0 }, +{ "restore", "-m", 0x7000001f, 0xfc00603f, WR_31|NODS, MOD_SP, IAMR2, 0, 0 }, +{ "save", "-m", 0x7000201f, 0xfc00603f, NODS, RD_31|MOD_SP, IAMR2, 0, 0 }, /* User Defined Instruction. */ -{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{ "udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, /* MIPS r6. */ -{"aui", "t,s,u", 0x3c000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, -{"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 }, -{"daui", "t,-s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, -{"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, -{"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, +{ "aui", "t,s,u", 0x3c000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, +{ "auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 }, +{ "daui", "t,-s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, +{ "dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, +{ "dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, -{"align", "d,s,t,+I", 0x7c000220, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, -{"dalign", "d,s,t,+O", 0x7c000224, 0xfc00063f, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, -{"bitswap", "d,t", 0x7c000020, 0xffe007ff, WR_1|RD_2, 0, I37, 0, 0 }, -{"dbitswap", "d,t", 0x7c000024, 0xffe007ff, WR_1|RD_2, 0, I69, 0, 0 }, +{ "align", "d,s,t,+I", 0x7c000220, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{ "dalign", "d,s,t,+O", 0x7c000224, 0xfc00063f, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{ "bitswap", "d,t", 0x7c000020, 0xffe007ff, WR_1|RD_2, 0, I37, 0, 0 }, +{ "dbitswap", "d,t", 0x7c000024, 0xffe007ff, WR_1|RD_2, 0, I69, 0, 0 }, -{"bovc", "s,-w,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"bovc", "t,-x,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, -{"beqzalc", "-t,p", 0x20000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"beqc", "-s,-u,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"beqc", "t,-y,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, -{"bnvc", "s,-w,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"bnvc", "t,-x,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, -{"bnezalc", "-t,p", 0x60000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"bnec", "-s,-u,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"bnec", "t,-y,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{ "bovc", "s,-w,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "bovc", "t,-x,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{ "beqzalc", "-t,p", 0x20000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "beqc", "-s,-u,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "beqc", "t,-y,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{ "bnvc", "s,-w,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "bnvc", "t,-x,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{ "bnezalc", "-t,p", 0x60000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "bnec", "-s,-u,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "bnec", "t,-y,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, -{"blezc", "-t,p", 0x58000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, -{"bgezc", "+;,p", 0x58000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, -{"bgec", "-s,-v,p", 0x58000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"bgtzc", "-t,p", 0x5c000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, -{"bltzc", "+;,p", 0x5c000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, -{"bltc", "-s,-v,p", 0x5c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"blezalc", "-t,p", 0x18000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"bgezalc", "+;,p", 0x18000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"bgeuc", "-s,-v,p", 0x18000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"bgtzalc", "-t,p", 0x1c000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"bltzalc", "+;,p", 0x1c000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, -{"bltuc", "-s,-v,p", 0x1c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "blezc", "-t,p", 0x58000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, +{ "bgezc", "+;,p", 0x58000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{ "bgec", "-s,-v,p", 0x58000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "bgtzc", "-t,p", 0x5c000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, +{ "bltzc", "+;,p", 0x5c000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{ "bltc", "-s,-v,p", 0x5c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "blezalc", "-t,p", 0x18000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "bgezalc", "+;,p", 0x18000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "bgeuc", "-s,-v,p", 0x18000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{ "bgtzalc", "-t,p", 0x1c000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "bltzalc", "+;,p", 0x1c000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{ "bltuc", "-s,-v,p", 0x1c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, -{"beqzc", "-s,+\"", 0xd8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, -{"jrc", "t", 0xd8000000, 0xffe0ffff, RD_1|NODS, INSN2_ALIAS, I37, 0, 0 }, -{"jic", "t,j", 0xd8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, +{ "beqzc", "-s,+\"", 0xd8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{ "jrc", "t", 0xd8000000, 0xffe0ffff, RD_1|NODS, INSN2_ALIAS, I37, 0, 0 }, +{ "jic", "t,j", 0xd8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, -{"bnezc", "-s,+\"", 0xf8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, -{"jalrc", "t", 0xf8000000, 0xffe0ffff, RD_1|NODS, 0, I37, 0, 0 }, -{"jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, +{ "bnezc", "-s,+\"", 0xf8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{ "jalrc", "t", 0xf8000000, 0xffe0ffff, RD_1|NODS, 0, I37, 0, 0 }, +{ "jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, -{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"msubf.s", "D,S,T", 0x46000019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"maddf.d", "D,S,T", 0x46200018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"msubf.d", "D,S,T", 0x46200019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "maddf.s", "D,S,T", 0x46000018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "msubf.s", "D,S,T", 0x46000019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "maddf.d", "D,S,T", 0x46200018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "msubf.d", "D,S,T", 0x46200019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"rint.s", "D,S", 0x4600001a, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, -{"rint.d", "D,S", 0x4620001a, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, -{"class.s", "D,S", 0x4600001b, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, -{"class.d", "D,S", 0x4620001b, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, -{"min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "rint.s", "D,S", 0x4600001a, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, +{ "rint.d", "D,S", 0x4620001a, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, +{ "class.s", "D,S", 0x4600001b, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, +{ "class.d", "D,S", 0x4620001b, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, +{ "min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"sel.s", "D,S,T", 0x46000010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"sel.d", "D,S,T", 0x46200010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"selnez", "d,s,t", 0x00000037, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, -{"selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"seleqz", "d,s,t", 0x00000035, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, -{"seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, -{"seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "sel.s", "D,S,T", 0x46000010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "sel.d", "D,S,T", 0x46200010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "selnez", "d,s,t", 0x00000037, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{ "selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{ "seleqz", "d,s,t", 0x00000035, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{ "seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{ "seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, -{"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 }, +{ "aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 }, /* MIPS cyclic redundancy check (CRC) ASE. */ -{"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32w", "t,s,-d", 0x7c00008f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32d", "t,s,-d", 0x7c0000cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, -{"crc32cb", "t,s,-d", 0x7c00010f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32ch", "t,s,-d", 0x7c00014f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, -{"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, +{ "crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32w", "t,s,-d", 0x7c00008f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32d", "t,s,-d", 0x7c0000cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, +{ "crc32cb", "t,s,-d", 0x7c00010f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32ch", "t,s,-d", 0x7c00014f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, +{ "crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, /* MIPS Global INValidate (GINV) ASE. */ -{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, -{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, +{ "ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, +{ "ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the disassembler recognizes more specific versions first. */ -{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, -{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, +{ "c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, +{ "cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{ "cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, /* RFE conflicts with the new Virt spec instruction tlbgp. */ -{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, +{ "rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, }; #define MIPS_NUM_OPCODES \ diff --git a/libr/asm/arch/mips/gnu/mips16-opc.c b/libr/asm/arch/mips/gnu/mips16-opc.c index a89e960f22..95f88652ef 100644 --- a/libr/asm/arch/mips/gnu/mips16-opc.c +++ b/libr/asm/arch/mips/gnu/mips16-opc.c @@ -214,272 +214,272 @@ decode_mips16_operand (char type, bfd_boolean extended_p) const struct mips_opcode mips16_opcodes[] = { /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */ -{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, -{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, -{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, -{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, -{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, -{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, -{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, -{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, -{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, -{"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, -{"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 }, -{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, -{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, -{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, -{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, -{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, -{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, -{"addu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, -{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, -{"addu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, -{"addu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 }, -{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"andi", "x,u", 0xf0006860, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, -{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 }, -{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 }, -{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 }, -{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, -{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, -{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, -{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, -{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, -{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, -{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 }, -{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 }, -{"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 }, -{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 }, -{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 }, -{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 }, -{"cache", "T,9(x)", 0xf000d0a0, 0xfe00f8e0, RD_3, 0, 0, E2, 0 }, -{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, -{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, -{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, -{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, -{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, -{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, -{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, -{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, -{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, -{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, -{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, -{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, -{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, -{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, -{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, -{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, -{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"di", "", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, -{"di", ".", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, -{"di", "y", 0xf002670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 }, -{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, -{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, -{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, -{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, -{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, -{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, -{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, -{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, -{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 }, -{"ehb", "", 0xf0c03010, 0xffffffff, 0, 0, 0, E2, 0 }, -{"ei", "", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, -{"ei", ".", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, -{"ei", "y", 0xf003670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 }, -{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 }, -{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 }, -{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 }, -{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 }, -{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 }, -{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 }, -{"ext", "y,x,b,d", 0xf0203008, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 }, -{"ins", "y,.,b,c", 0xf0003004, 0xf820ff1f, WR_1, 0, 0, E2, 0 }, -{"ins", "y,x,b,c", 0xf0203004, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 }, -{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, -{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, -{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, -{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, -{"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, -{"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, -{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, -{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, -{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, -{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, +{ "nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */ +{ "la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, +{ "abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, +{ "addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, +{ "addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, +{ "addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, +{ "addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, +{ "addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, +{ "addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, +{ "addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, +{ "addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 }, +{ "addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, +{ "addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, +{ "addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, +{ "addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, +{ "addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, +{ "addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, +{ "addu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, +{ "addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, +{ "addu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, +{ "addu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 }, +{ "and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "andi", "x,u", 0xf0006860, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, +{ "b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 }, +{ "beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 }, +{ "beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 }, +{ "bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, +{ "bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, +{ "ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, +{ "blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, +{ "bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 }, +{ "bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 }, +{ "break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 }, +{ "break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 }, +{ "bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 }, +{ "btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 }, +{ "cache", "T,9(x)", 0xf000d0a0, 0xfe00f8e0, RD_3, 0, 0, E2, 0 }, +{ "cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, +{ "cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, +{ "daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, +{ "daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, +{ "daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, +{ "daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, +{ "daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, +{ "daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, +{ "daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, +{ "daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, +{ "daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, +{ "daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, +{ "daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, +{ "daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, +{ "daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, +{ "ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "di", "", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, +{ "di", ".", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, +{ "di", "y", 0xf002670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 }, +{ "div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, +{ "dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, +{ "dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, +{ "dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, +{ "dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, +{ "dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, +{ "dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{ "dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, +{ "dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, +{ "dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 }, +{ "ehb", "", 0xf0c03010, 0xffffffff, 0, 0, 0, E2, 0 }, +{ "ei", "", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, +{ "ei", ".", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 }, +{ "ei", "y", 0xf003670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 }, +{ "exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{ "exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{ "exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 }, +{ "exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{ "entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 }, +{ "entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 }, +{ "ext", "y,x,b,d", 0xf0203008, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 }, +{ "ins", "y,.,b,c", 0xf0003004, 0xf820ff1f, WR_1, 0, 0, E2, 0 }, +{ "ins", "y,x,b,c", 0xf0203004, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 }, +{ "jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, +{ "jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, +{ "jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, +{ "jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, +{ "jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, +{ "jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, +{ "jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, +{ "jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, +{ "j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, +{ "j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, /* MIPS16e compact jumps. We keep them near the ordinary jumps so that we easily find them when converting a normal jump to a compact one. */ -{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 }, -{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 }, -{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 }, -{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 }, -{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lb", "x,V(G)", 0xf0009060, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lbu", "x,V(G)", 0xf00090a0, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, -{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, -{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, -{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 }, -{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lh", "x,V(G)", 0xf0009040, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lhu", "x,V(G)", 0xf0009080, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"li", "x,U", 0x6800, 0xf800, WR_1, SH, 0, E2, 0 }, -{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 }, -{"li", "x,U", 0xf0006800, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, -{"ll", "x,9(r)", 0xf00090c0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lui", "x,u", 0xf0006820, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, -{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, -{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, -{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 }, -{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, -{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, -{"lw", "x,V(S)", 0xf0009000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, -{"lw", "x,V(G)", 0xf0009020, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lwl", "x,9(r)", 0xf00090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lwr", "x,9(r)", 0xf01090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, -{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, -{"mfc0", "y,N", 0xf0006700, 0xffffff00, WR_1|RD_C0, 0, 0, E2, 0 }, -{"mfc0", "y,N,O", 0xf0006700, 0xff1fff00, WR_1|RD_C0, 0, 0, E2, 0 }, -{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 }, -{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 }, -{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, -{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, -{"movn", "x,.,w", 0xf000300a, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, -{"movn", "x,r,w", 0xf020300a, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, -{"movtn", "x,.", 0xf000301a, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, -{"movtn", "x,r", 0xf020301a, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, -{"movtz", "x,.", 0xf0003016, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, -{"movtz", "x,r", 0xf0203016, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, -{"movz", "x,.,w", 0xf0003006, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, -{"movz", "x,r,w", 0xf0203006, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, -{"mtc0", "y,N", 0xf0016700, 0xffffff00, RD_1|WR_C0, 0, 0, E2, 0 }, -{"mtc0", "y,N,O", 0xf0016700, 0xff1fff00, RD_1|WR_C0, 0, 0, E2, 0 }, -{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, -{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, -{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, -{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"ori", "x,u", 0xf0006840, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, -{"pause", "", 0xf1403018, 0xffffffff, 0, 0, 0, E2, 0 }, -{"pref", "T,9(x)", 0xf000d080, 0xfe00f8e0, RD_3, 0, 0, E2, 0 }, -{"rdhwr", "y,Q", 0xf000300c, 0xffe0ff1f, WR_1, 0, 0, E2, 0 }, -{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, -{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, -{"sb", "x,V(G)", 0xf000d060, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"sc", "x,9(r)", 0xf000d0c0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, -{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 }, -{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, -{"sh", "x,V(G)", 0xf000d040, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, SH, 0, E2, 0 }, -{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"sll", "x,w,<", 0xf0003000, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 }, -{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, -{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, -{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, SH, 0, E2, 0 }, -{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"srl", "x,w,<", 0xf0003002, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 }, -{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, -{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, -{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, -{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, SH|RD_SP, 0, E2, 0 }, -{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 }, -{"sw", "x,V(S)", 0xf000d000, 0xf800f8e0, RD_1, RD_SP, 0, E2, 0 }, -{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 }, -{"sw", "x,V(G)", 0xf000d020, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"swl", "x,9(r)", 0xf000d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"swr", "x,9(r)", 0xf010d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, -{"sync_acquire", "", 0xf4403014, 0xffffffff, 0, AL, 0, E2, 0 }, -{"sync_mb", "", 0xf4003014, 0xffffffff, 0, AL, 0, E2, 0 }, -{"sync_release", "", 0xf4803014, 0xffffffff, 0, AL, 0, E2, 0 }, -{"sync_rmb", "", 0xf4c03014, 0xffffffff, 0, AL, 0, E2, 0 }, -{"sync_wmb", "", 0xf1003014, 0xffffffff, 0, AL, 0, E2, 0 }, -{"sync", "", 0xf0003014, 0xffffffff, 0, 0, 0, E2, 0 }, -{"sync", ">", 0xf0003014, 0xf83fffff, 0, 0, 0, E2, 0 }, -{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, -{"xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, +{ "jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 }, +{ "jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 }, +{ "jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 }, +{ "jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 }, +{ "lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, +{ "lb", "x,V(G)", 0xf0009060, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, +{ "lbu", "x,V(G)", 0xf00090a0, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, +{ "ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 }, +{ "ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, +{ "ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 }, +{ "lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, +{ "lh", "x,V(G)", 0xf0009040, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, +{ "lhu", "x,V(G)", 0xf0009080, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "li", "x,U", 0x6800, 0xf800, WR_1, SH, 0, E2, 0 }, +{ "li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 }, +{ "li", "x,U", 0xf0006800, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, +{ "ll", "x,9(r)", 0xf00090c0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lui", "x,u", 0xf0006820, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, +{ "lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, +{ "lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 }, +{ "lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 }, +{ "lw", "x,V(S)", 0x9000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 }, +{ "lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, +{ "lw", "x,V(S)", 0xf0009000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 }, +{ "lw", "x,V(G)", 0xf0009020, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lwl", "x,9(r)", 0xf00090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lwr", "x,9(r)", 0xf01090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 }, +{ "lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, +{ "mfc0", "y,N", 0xf0006700, 0xffffff00, WR_1|RD_C0, 0, 0, E2, 0 }, +{ "mfc0", "y,N,O", 0xf0006700, 0xff1fff00, WR_1|RD_C0, 0, 0, E2, 0 }, +{ "mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 }, +{ "mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 }, +{ "move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, +{ "move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, +{ "movn", "x,.,w", 0xf000300a, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, +{ "movn", "x,r,w", 0xf020300a, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, +{ "movtn", "x,.", 0xf000301a, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, +{ "movtn", "x,r", 0xf020301a, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, +{ "movtz", "x,.", 0xf0003016, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, +{ "movtz", "x,r", 0xf0203016, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 }, +{ "movz", "x,.,w", 0xf0003006, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, +{ "movz", "x,r,w", 0xf0203006, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 }, +{ "mtc0", "y,N", 0xf0016700, 0xffffff00, RD_1|WR_C0, 0, 0, E2, 0 }, +{ "mtc0", "y,N,O", 0xf0016700, 0xff1fff00, RD_1|WR_C0, 0, 0, E2, 0 }, +{ "mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, +{ "mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, +{ "not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, +{ "or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "ori", "x,u", 0xf0006840, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, +{ "pause", "", 0xf1403018, 0xffffffff, 0, 0, 0, E2, 0 }, +{ "pref", "T,9(x)", 0xf000d080, 0xfe00f8e0, RD_3, 0, 0, E2, 0 }, +{ "rdhwr", "y,Q", 0xf000300c, 0xffe0ff1f, WR_1, 0, 0, E2, 0 }, +{ "rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, +{ "remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, +{ "sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, +{ "sb", "x,V(G)", 0xf000d060, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "sc", "x,9(r)", 0xf000d0c0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, +{ "sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 }, +{ "sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 }, +{ "sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, +{ "sh", "x,V(G)", 0xf000d040, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, SH, 0, E2, 0 }, +{ "sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sll", "x,w,<", 0xf0003000, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 }, +{ "sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, +{ "slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, +{ "sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, +{ "srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, +{ "sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, SH, 0, E2, 0 }, +{ "srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, +{ "srl", "x,w,<", 0xf0003002, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 }, +{ "srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, +{ "subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, +{ "subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, +{ "sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, +{ "sw", "x,V(S)", 0xd000, 0xf800, RD_1, SH|RD_SP, 0, E2, 0 }, +{ "sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 }, +{ "sw", "x,V(S)", 0xf000d000, 0xf800f8e0, RD_1, RD_SP, 0, E2, 0 }, +{ "sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 }, +{ "sw", "x,V(G)", 0xf000d020, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "swl", "x,9(r)", 0xf000d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "swr", "x,9(r)", 0xf010d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 }, +{ "sync_acquire", "", 0xf4403014, 0xffffffff, 0, AL, 0, E2, 0 }, +{ "sync_mb", "", 0xf4003014, 0xffffffff, 0, AL, 0, E2, 0 }, +{ "sync_release", "", 0xf4803014, 0xffffffff, 0, AL, 0, E2, 0 }, +{ "sync_rmb", "", 0xf4c03014, 0xffffffff, 0, AL, 0, E2, 0 }, +{ "sync_wmb", "", 0xf1003014, 0xffffffff, 0, AL, 0, E2, 0 }, +{ "sync", "", 0xf0003014, 0xffffffff, 0, 0, 0, E2, 0 }, +{ "sync", ">", 0xf0003014, 0xf83fffff, 0, 0, 0, E2, 0 }, +{ "xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{ "xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, /* MIPS16e additions; see above for compact jumps. */ -{"restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 }, -{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 }, -{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }, -{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 }, -{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, -{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, -{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, -{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 }, -{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 }, -{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 }, +{ "restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 }, +{ "save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 }, +{ "sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }, +{ "sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 }, +{ "seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{ "seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{ "sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, +{ "zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{ "zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{ "zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 }, /* MIPS16e2 MT ASE instructions. */ -{"dmt", "", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"dmt", ".", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"dmt", "y", 0xf0226701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, -{"dvpe", "", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"dvpe", ".", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"dvpe", "y", 0xf0226700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, -{"emt", "", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"emt", ".", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"emt", "y", 0xf0236701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, -{"evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, -{"evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, +{ "dmt", "", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "dmt", ".", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "dmt", "y", 0xf0226701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, +{ "dvpe", "", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "dvpe", ".", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "dvpe", "y", 0xf0226700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, +{ "emt", "", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "emt", ".", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "emt", "y", 0xf0236701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, +{ "evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, +{ "evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, /* interAptiv MR2 instruction extensions. */ -{"copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, -{"ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, +{ "copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, +{ "ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, /* Place asmacro at the bottom so that it catches any implementation specific macros that didn't match anything. */ -{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 }, +{ "asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 }, /* Place EXTEND last so that it catches any prefix that didn't match anything. */ -{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 }, +{ "extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 }, }; const int bfd_mips16_num_opcodes = diff --git a/libr/asm/arch/nios/gnu/nios2-opc.c b/libr/asm/arch/nios/gnu/nios2-opc.c index 83cf1898af..10a498541d 100644 --- a/libr/asm/arch/nios/gnu/nios2-opc.c +++ b/libr/asm/arch/nios/gnu/nios2-opc.c @@ -28,136 +28,136 @@ const struct nios2_reg nios2_builtin_regs[] = { /* Standard register names. */ - {"zero", 0}, - {"at", 1}, /* assembler temporary */ - {"r2", 2}, - {"r3", 3}, - {"r4", 4}, - {"r5", 5}, - {"r6", 6}, - {"r7", 7}, - {"r8", 8}, - {"r9", 9}, - {"r10", 10}, - {"r11", 11}, - {"r12", 12}, - {"r13", 13}, - {"r14", 14}, - {"r15", 15}, - {"r16", 16}, - {"r17", 17}, - {"r18", 18}, - {"r19", 19}, - {"r20", 20}, - {"r21", 21}, - {"r22", 22}, - {"r23", 23}, - {"et", 24}, - {"bt", 25}, - {"gp", 26}, /* global pointer */ - {"sp", 27}, /* stack pointer */ - {"fp", 28}, /* frame pointer */ - {"ea", 29}, /* exception return address */ - {"ba", 30}, /* breakpoint return address */ - {"ra", 31}, /* return address */ + { "zero", 0}, + { "at", 1}, /* assembler temporary */ + { "r2", 2}, + { "r3", 3}, + { "r4", 4}, + { "r5", 5}, + { "r6", 6}, + { "r7", 7}, + { "r8", 8}, + { "r9", 9}, + { "r10", 10}, + { "r11", 11}, + { "r12", 12}, + { "r13", 13}, + { "r14", 14}, + { "r15", 15}, + { "r16", 16}, + { "r17", 17}, + { "r18", 18}, + { "r19", 19}, + { "r20", 20}, + { "r21", 21}, + { "r22", 22}, + { "r23", 23}, + { "et", 24}, + { "bt", 25}, + { "gp", 26}, /* global pointer */ + { "sp", 27}, /* stack pointer */ + { "fp", 28}, /* frame pointer */ + { "ea", 29}, /* exception return address */ + { "ba", 30}, /* breakpoint return address */ + { "ra", 31}, /* return address */ /* Alternative names for special registers. */ - {"r0", 0}, - {"r1", 1}, - {"r24", 24}, - {"r25", 25}, - {"r26", 26}, - {"r27", 27}, - {"r28", 28}, - {"r29", 29}, - {"r30", 30}, - {"sstatus", 30}, - {"r31", 31}, + { "r0", 0}, + { "r1", 1}, + { "r24", 24}, + { "r25", 25}, + { "r26", 26}, + { "r27", 27}, + { "r28", 28}, + { "r29", 29}, + { "r30", 30}, + { "sstatus", 30}, + { "r31", 31}, /* Control register names. */ - {"status", 0}, - {"estatus", 1}, - {"bstatus", 2}, - {"ienable", 3}, - {"ipending", 4}, - {"cpuid", 5}, - {"ctl6", 6}, - {"exception", 7}, - {"pteaddr", 8}, - {"tlbacc", 9}, - {"tlbmisc", 10}, - {"eccinj", 11}, - {"badaddr", 12}, - {"config", 13}, - {"mpubase", 14}, - {"mpuacc", 15}, - {"ctl16", 16}, - {"ctl17", 17}, - {"ctl18", 18}, - {"ctl19", 19}, - {"ctl20", 20}, - {"ctl21", 21}, - {"ctl22", 22}, - {"ctl23", 23}, - {"ctl24", 24}, - {"ctl25", 25}, - {"ctl26", 26}, - {"ctl27", 27}, - {"ctl28", 28}, - {"ctl29", 29}, - {"ctl30", 30}, - {"ctl31", 31}, + { "status", 0}, + { "estatus", 1}, + { "bstatus", 2}, + { "ienable", 3}, + { "ipending", 4}, + { "cpuid", 5}, + { "ctl6", 6}, + { "exception", 7}, + { "pteaddr", 8}, + { "tlbacc", 9}, + { "tlbmisc", 10}, + { "eccinj", 11}, + { "badaddr", 12}, + { "config", 13}, + { "mpubase", 14}, + { "mpuacc", 15}, + { "ctl16", 16}, + { "ctl17", 17}, + { "ctl18", 18}, + { "ctl19", 19}, + { "ctl20", 20}, + { "ctl21", 21}, + { "ctl22", 22}, + { "ctl23", 23}, + { "ctl24", 24}, + { "ctl25", 25}, + { "ctl26", 26}, + { "ctl27", 27}, + { "ctl28", 28}, + { "ctl29", 29}, + { "ctl30", 30}, + { "ctl31", 31}, /* Alternative names for special control registers. */ - {"ctl0", 0}, - {"ctl1", 1}, - {"ctl2", 2}, - {"ctl3", 3}, - {"ctl4", 4}, - {"ctl5", 5}, - {"ctl7", 7}, - {"ctl8", 8}, - {"ctl9", 9}, - {"ctl10", 10}, - {"ctl11", 11}, - {"ctl12", 12}, - {"ctl13", 13}, - {"ctl14", 14}, - {"ctl15", 15}, + { "ctl0", 0}, + { "ctl1", 1}, + { "ctl2", 2}, + { "ctl3", 3}, + { "ctl4", 4}, + { "ctl5", 5}, + { "ctl7", 7}, + { "ctl8", 8}, + { "ctl9", 9}, + { "ctl10", 10}, + { "ctl11", 11}, + { "ctl12", 12}, + { "ctl13", 13}, + { "ctl14", 14}, + { "ctl15", 15}, /* Coprocessor register names. */ - {"c0", 0}, - {"c1", 1}, - {"c2", 2}, - {"c3", 3}, - {"c4", 4}, - {"c5", 5}, - {"c6", 6}, - {"c7", 7}, - {"c8", 8}, - {"c9", 9}, - {"c10", 10}, - {"c11", 11}, - {"c12", 12}, - {"c13", 13}, - {"c14", 14}, - {"c15", 15}, - {"c16", 16}, - {"c17", 17}, - {"c18", 18}, - {"c19", 19}, - {"c20", 20}, - {"c21", 21}, - {"c22", 22}, - {"c23", 23}, - {"c24", 24}, - {"c25", 25}, - {"c26", 26}, - {"c27", 27}, - {"c28", 28}, - {"c29", 29}, - {"c30", 30}, - {"c31", 31}, + { "c0", 0}, + { "c1", 1}, + { "c2", 2}, + { "c3", 3}, + { "c4", 4}, + { "c5", 5}, + { "c6", 6}, + { "c7", 7}, + { "c8", 8}, + { "c9", 9}, + { "c10", 10}, + { "c11", 11}, + { "c12", 12}, + { "c13", 13}, + { "c14", 14}, + { "c15", 15}, + { "c16", 16}, + { "c17", 17}, + { "c18", 18}, + { "c19", 19}, + { "c20", 20}, + { "c21", 21}, + { "c22", 22}, + { "c23", 23}, + { "c24", 24}, + { "c25", 25}, + { "c26", 26}, + { "c27", 27}, + { "c28", 28}, + { "c29", 29}, + { "c30", 30}, + { "c31", 31}, }; #define NIOS2_NUM_REGS \ @@ -176,230 +176,230 @@ const struct nios2_opcode nios2_builtin_opcodes[] = { /* { name, args, args_test, num_args, match, mask, pinfo, overflow_msg } */ - {"add", "d,s,t", "d,s,t,E", 3, + { "add", "d,s,t", "d,s,t,E", 3, OP_MATCH_ADD, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"addi", "t,s,i", "t,s,i,E", 3, + { "addi", "t,s,i", "t,s,i,E", 3, OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_ADDI, signed_immed16_overflow}, - {"subi", "t,s,i", "t,s,i,E", 3, + { "subi", "t,s,i", "t,s,i,E", 3, OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow}, - {"and", "d,s,t", "d,s,t,E", 3, + { "and", "d,s,t", "d,s,t,E", 3, OP_MATCH_AND, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"andhi", "t,s,u", "t,s,u,E", 3, + { "andhi", "t,s,u", "t,s,u,E", 3, OP_MATCH_ANDHI, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"andi", "t,s,u", "t,s,u,E", 3, + { "andi", "t,s,u", "t,s,u,E", 3, OP_MATCH_ANDI, OP_MASK_IOP, NIOS2_INSN_ANDI, unsigned_immed16_overflow}, - {"beq", "s,t,o", "s,t,o,E", 3, + { "beq", "s,t,o", "s,t,o,E", 3, OP_MATCH_BEQ, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bge", "s,t,o", "s,t,o,E", 3, + { "bge", "s,t,o", "s,t,o,E", 3, OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bgeu", "s,t,o", "s,t,o,E", 3, + { "bgeu", "s,t,o", "s,t,o,E", 3, OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bgt", "s,t,o", "s,t,o,E", 3, + { "bgt", "s,t,o", "s,t,o,E", 3, OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bgtu", "s,t,o", "s,t,o,E", 3, + { "bgtu", "s,t,o", "s,t,o,E", 3, OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"ble", "s,t,o", "s,t,o,E", 3, + { "ble", "s,t,o", "s,t,o,E", 3, OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bleu", "s,t,o", "s,t,o,E", 3, + { "bleu", "s,t,o", "s,t,o,E", 3, OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"blt", "s,t,o", "s,t,o,E", 3, + { "blt", "s,t,o", "s,t,o,E", 3, OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bltu", "s,t,o", "s,t,o,E", 3, + { "bltu", "s,t,o", "s,t,o,E", 3, OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"bne", "s,t,o", "s,t,o,E", 3, + { "bne", "s,t,o", "s,t,o,E", 3, OP_MATCH_BNE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow}, - {"br", "o", "o,E", 1, + { "br", "o", "o,E", 1, OP_MATCH_BR, OP_MASK_IOP, NIOS2_INSN_UBRANCH, branch_target_overflow}, - {"break", "b", "b,E", 1, + { "break", "b", "b,E", 1, OP_MATCH_BREAK, OP_MASK_BREAK, 0, no_overflow}, - {"bret", "", "E", 0, + { "bret", "", "E", 0, OP_MATCH_BRET, OP_MASK, 0, no_overflow}, - {"flushd", "i(s)", "i(s)E", 2, + { "flushd", "i(s)", "i(s)E", 2, OP_MATCH_FLUSHD, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"flushda", "i(s)", "i(s)E", 2, + { "flushda", "i(s)", "i(s)E", 2, OP_MATCH_FLUSHDA, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"flushi", "s", "s,E", 1, + { "flushi", "s", "s,E", 1, OP_MATCH_FLUSHI, OP_MASK_FLUSHI, 0, no_overflow}, - {"flushp", "", "E", 0, + { "flushp", "", "E", 0, OP_MATCH_FLUSHP, OP_MASK, 0, no_overflow}, - {"initd", "i(s)", "i(s)E", 2, + { "initd", "i(s)", "i(s)E", 2, OP_MATCH_INITD, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"initda", "i(s)", "i(s)E", 2, + { "initda", "i(s)", "i(s)E", 2, OP_MATCH_INITDA, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"initi", "s", "s,E", 1, + { "initi", "s", "s,E", 1, OP_MATCH_INITI, OP_MASK_INITI, 0, no_overflow}, - {"call", "m", "m,E", 1, + { "call", "m", "m,E", 1, OP_MATCH_CALL, OP_MASK_IOP, NIOS2_INSN_CALL, call_target_overflow}, - {"callr", "s", "s,E", 1, + { "callr", "s", "s,E", 1, OP_MATCH_CALLR, OP_MASK_CALLR, 0, no_overflow}, - {"cmpeq", "d,s,t", "d,s,t,E", 3, + { "cmpeq", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPEQ, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmpeqi", "t,s,i", "t,s,i,E", 3, + { "cmpeqi", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPEQI, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"cmpge", "d,s,t", "d,s,t,E", 3, + { "cmpge", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmpgei", "t,s,i", "t,s,i,E", 3, + { "cmpgei", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPGEI, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"cmpgeu", "d,s,t", "d,s,t,E", 3, + { "cmpgeu", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmpgeui", "t,s,u", "t,s,u,E", 3, + { "cmpgeui", "t,s,u", "t,s,u,E", 3, OP_MATCH_CMPGEUI, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"cmpgt", "d,s,t", "d,s,t,E", 3, + { "cmpgt", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow}, - {"cmpgti", "t,s,i", "t,s,i,E", 3, + { "cmpgti", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPGEI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow}, - {"cmpgtu", "d,s,t", "d,s,t,E", 3, + { "cmpgtu", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow}, - {"cmpgtui", "t,s,u", "t,s,u,E", 3, + { "cmpgtui", "t,s,u", "t,s,u,E", 3, OP_MATCH_CMPGEUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow}, - {"cmple", "d,s,t", "d,s,t,E", 3, + { "cmple", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow}, - {"cmplei", "t,s,i", "t,s,i,E", 3, + { "cmplei", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPLTI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow}, - {"cmpleu", "d,s,t", "d,s,t,E", 3, + { "cmpleu", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow}, - {"cmpleui", "t,s,u", "t,s,u,E", 3, + { "cmpleui", "t,s,u", "t,s,u,E", 3, OP_MATCH_CMPLTUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow}, - {"cmplt", "d,s,t", "d,s,t,E", 3, + { "cmplt", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmplti", "t,s,i", "t,s,i,E", 3, + { "cmplti", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPLTI, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"cmpltu", "d,s,t", "d,s,t,E", 3, + { "cmpltu", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmpltui", "t,s,u", "t,s,u,E", 3, + { "cmpltui", "t,s,u", "t,s,u,E", 3, OP_MATCH_CMPLTUI, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"cmpne", "d,s,t", "d,s,t,E", 3, + { "cmpne", "d,s,t", "d,s,t,E", 3, OP_MATCH_CMPNE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"cmpnei", "t,s,i", "t,s,i,E", 3, + { "cmpnei", "t,s,i", "t,s,i,E", 3, OP_MATCH_CMPNEI, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"div", "d,s,t", "d,s,t,E", 3, + { "div", "d,s,t", "d,s,t,E", 3, OP_MATCH_DIV, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"divu", "d,s,t", "d,s,t,E", 3, + { "divu", "d,s,t", "d,s,t,E", 3, OP_MATCH_DIVU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"jmp", "s", "s,E", 1, + { "jmp", "s", "s,E", 1, OP_MATCH_JMP, OP_MASK_JMP, 0, no_overflow}, - {"jmpi", "m", "m,E", 1, + { "jmpi", "m", "m,E", 1, OP_MATCH_JMPI, OP_MASK_IOP, 0, no_overflow}, - {"ldb", "t,i(s)", "t,i(s)E", 3, + { "ldb", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDB, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldbio", "t,i(s)", "t,i(s)E", 3, + { "ldbio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDBIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldbu", "t,i(s)", "t,i(s)E", 3, + { "ldbu", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDBU, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldbuio", "t,i(s)", "t,i(s)E", 3, + { "ldbuio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDBUIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldh", "t,i(s)", "t,i(s)E", 3, + { "ldh", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDH, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldhio", "t,i(s)", "t,i(s)E", 3, + { "ldhio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDHIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldhu", "t,i(s)", "t,i(s)E", 3, + { "ldhu", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDHU, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldhuio", "t,i(s)", "t,i(s)E", 3, + { "ldhuio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDHUIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldl", "t,i(s)", "t,i(s)E", 3, + { "ldl", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDL, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldw", "t,i(s)", "t,i(s)E", 3, + { "ldw", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDW, OP_MASK_IOP, 0, address_offset_overflow}, - {"ldwio", "t,i(s)", "t,i(s)E", 3, + { "ldwio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_LDWIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"mov", "d,s", "d,s,E", 2, + { "mov", "d,s", "d,s,E", 2, OP_MATCH_ADD, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, NIOS2_INSN_MACRO_MOV, no_overflow}, - {"movhi", "t,u", "t,u,E", 2, + { "movhi", "t,u", "t,u,E", 2, OP_MATCH_ORHI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, - {"movui", "t,u", "t,u,E", 2, + { "movui", "t,u", "t,u,E", 2, OP_MATCH_ORI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, - {"movi", "t,i", "t,i,E", 2, + { "movi", "t,i", "t,i,E", 2, OP_MATCH_ADDI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow}, /* movia expands to two instructions so there is no mask or match */ - {"movia", "t,o", "t,o,E", 2, + { "movia", "t,o", "t,o,E", 2, OP_MATCH_ORHI, OP_MASK_IOP, NIOS2_INSN_MACRO_MOVIA, no_overflow}, - {"mul", "d,s,t", "d,s,t,E", 3, + { "mul", "d,s,t", "d,s,t,E", 3, OP_MATCH_MUL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"muli", "t,s,i", "t,s,i,E", 3, + { "muli", "t,s,i", "t,s,i,E", 3, OP_MATCH_MULI, OP_MASK_IOP, 0, signed_immed16_overflow}, - {"mulxss", "d,s,t", "d,s,t,E", 3, + { "mulxss", "d,s,t", "d,s,t,E", 3, OP_MATCH_MULXSS, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"mulxsu", "d,s,t", "d,s,t,E", 3, + { "mulxsu", "d,s,t", "d,s,t,E", 3, OP_MATCH_MULXSU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"mulxuu", "d,s,t", "d,s,t,E", 3, + { "mulxuu", "d,s,t", "d,s,t,E", 3, OP_MATCH_MULXUU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"nextpc", "d", "d,E", 1, + { "nextpc", "d", "d,E", 1, OP_MATCH_NEXTPC, OP_MASK_NEXTPC, 0, no_overflow}, - {"nop", "", "E", 0, + { "nop", "", "E", 0, OP_MATCH_ADD, OP_MASK, NIOS2_INSN_MACRO_MOV, no_overflow}, - {"nor", "d,s,t", "d,s,t,E", 3, + { "nor", "d,s,t", "d,s,t,E", 3, OP_MATCH_NOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"or", "d,s,t", "d,s,t,E", 3, + { "or", "d,s,t", "d,s,t,E", 3, OP_MATCH_OR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"orhi", "t,s,u", "t,s,u,E", 3, + { "orhi", "t,s,u", "t,s,u,E", 3, OP_MATCH_ORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"ori", "t,s,u", "t,s,u,E", 3, + { "ori", "t,s,u", "t,s,u,E", 3, OP_MATCH_ORI, OP_MASK_IOP, NIOS2_INSN_ORI, unsigned_immed16_overflow}, - {"rdctl", "d,c", "d,c,E", 2, + { "rdctl", "d,c", "d,c,E", 2, OP_MATCH_RDCTL, OP_MASK_RDCTL, 0, no_overflow}, - {"rdprs", "t,s,i", "t,s,i,E", 3, + { "rdprs", "t,s,i", "t,s,i,E", 3, OP_MATCH_RDPRS, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"ret", "", "E", 0, + { "ret", "", "E", 0, OP_MATCH_RET, OP_MASK, 0, no_overflow}, - {"rol", "d,s,t", "d,s,t,E", 3, + { "rol", "d,s,t", "d,s,t,E", 3, OP_MATCH_ROL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"roli", "d,s,j", "d,s,j,E", 3, + { "roli", "d,s,j", "d,s,j,E", 3, OP_MATCH_ROLI, OP_MASK_ROLI, 0, unsigned_immed5_overflow}, - {"ror", "d,s,t", "d,s,t,E", 3, + { "ror", "d,s,t", "d,s,t,E", 3, OP_MATCH_ROR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"sll", "d,s,t", "d,s,t,E", 3, + { "sll", "d,s,t", "d,s,t,E", 3, OP_MATCH_SLL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"slli", "d,s,j", "d,s,j,E", 3, + { "slli", "d,s,j", "d,s,j,E", 3, OP_MATCH_SLLI, OP_MASK_SLLI, 0, unsigned_immed5_overflow}, - {"sra", "d,s,t", "d,s,t,E", 3, + { "sra", "d,s,t", "d,s,t,E", 3, OP_MATCH_SRA, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"srai", "d,s,j", "d,s,j,E", 3, + { "srai", "d,s,j", "d,s,j,E", 3, OP_MATCH_SRAI, OP_MASK_SRAI, 0, unsigned_immed5_overflow}, - {"srl", "d,s,t", "d,s,t,E", 3, + { "srl", "d,s,t", "d,s,t,E", 3, OP_MATCH_SRL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"srli", "d,s,j", "d,s,j,E", 3, + { "srli", "d,s,j", "d,s,j,E", 3, OP_MATCH_SRLI, OP_MASK_SRLI, 0, unsigned_immed5_overflow}, - {"stb", "t,i(s)", "t,i(s)E", 3, + { "stb", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STB, OP_MASK_IOP, 0, address_offset_overflow}, - {"stbio", "t,i(s)", "t,i(s)E", 3, + { "stbio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STBIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"stc", "t,i(s)", "t,i(s)E", 3, + { "stc", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STC, OP_MASK_IOP, 0, address_offset_overflow}, - {"sth", "t,i(s)", "t,i(s)E", 3, + { "sth", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STH, OP_MASK_IOP, 0, address_offset_overflow}, - {"sthio", "t,i(s)", "t,i(s)E", 3, + { "sthio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STHIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"stw", "t,i(s)", "t,i(s)E", 3, + { "stw", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STW, OP_MASK_IOP, 0, address_offset_overflow}, - {"stwio", "t,i(s)", "t,i(s)E", 3, + { "stwio", "t,i(s)", "t,i(s)E", 3, OP_MATCH_STWIO, OP_MASK_IOP, 0, address_offset_overflow}, - {"sub", "d,s,t", "d,s,t,E", 3, + { "sub", "d,s,t", "d,s,t,E", 3, OP_MATCH_SUB, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"sync", "", "E", 0, + { "sync", "", "E", 0, OP_MATCH_SYNC, OP_MASK_SYNC, 0, no_overflow}, - {"trap", "b", "b,E", 1, + { "trap", "b", "b,E", 1, OP_MATCH_TRAP, OP_MASK_TRAP, 0, no_overflow}, - {"eret", "", "E", 0, + { "eret", "", "E", 0, OP_MATCH_ERET, OP_MASK, 0, no_overflow}, - {"custom", "l,d,s,t", "l,d,s,t,E", 4, + { "custom", "l,d,s,t", "l,d,s,t,E", 4, OP_MATCH_CUSTOM, OP_MASK_ROP, 0, custom_opcode_overflow}, - {"wrctl", "c,s", "c,s,E", 2, + { "wrctl", "c,s", "c,s,E", 2, OP_MATCH_WRCTL, OP_MASK_WRCTL, 0, no_overflow}, - {"wrprs", "d,s", "d,s,E", 2, + { "wrprs", "d,s", "d,s,E", 2, OP_MATCH_WRPRS, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, 0, no_overflow}, - {"xor", "d,s,t", "d,s,t,E", 3, + { "xor", "d,s,t", "d,s,t,E", 3, OP_MATCH_XOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow}, - {"xorhi", "t,s,u", "t,s,u,E", 3, + { "xorhi", "t,s,u", "t,s,u,E", 3, OP_MATCH_XORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow}, - {"xori", "t,s,u", "t,s,u,E", 3, + { "xori", "t,s,u", "t,s,u,E", 3, OP_MATCH_XORI, OP_MASK_IOP, NIOS2_INSN_XORI, unsigned_immed16_overflow} }; diff --git a/libr/asm/arch/pic/pic_midrange.c b/libr/asm/arch/pic/pic_midrange.c index 412dfe0678..ba608bde84 100644 --- a/libr/asm/arch/pic/pic_midrange.c +++ b/libr/asm/arch/pic/pic_midrange.c @@ -3,58 +3,58 @@ #include "pic_midrange.h" static const PicMidrangeOpInfo pic_midrange_op_info[PIC_MIDRANGE_OPCODE_INVALID] = { - {"nop", PIC_MIDRANGE_OP_ARGS_NONE}, - {"return", PIC_MIDRANGE_OP_ARGS_NONE}, - {"retfie", PIC_MIDRANGE_OP_ARGS_NONE}, - {"option", PIC_MIDRANGE_OP_ARGS_NONE}, - {"sleep", PIC_MIDRANGE_OP_ARGS_NONE}, - {"clrwdt", PIC_MIDRANGE_OP_ARGS_NONE}, - {"tris", PIC_MIDRANGE_OP_ARGS_2F}, - {"movwf", PIC_MIDRANGE_OP_ARGS_7F}, - {"clr", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"subwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"decf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"iorwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"andwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"xorwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"addwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"movf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"comf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"incf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"decfsz", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"rrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"rlf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"swapf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"incfsz", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"bcf", PIC_MIDRANGE_OP_ARGS_3B_7F}, - {"bsf", PIC_MIDRANGE_OP_ARGS_3B_7F}, - {"btfsc", PIC_MIDRANGE_OP_ARGS_3B_7F}, - {"btfss", PIC_MIDRANGE_OP_ARGS_3B_7F}, - {"call", PIC_MIDRANGE_OP_ARGS_11K}, - {"goto", PIC_MIDRANGE_OP_ARGS_11K}, - {"movlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"retlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"iorlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"andlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"xorlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"sublw", PIC_MIDRANGE_OP_ARGS_8K}, - {"addlw", PIC_MIDRANGE_OP_ARGS_8K}, - {"reset", PIC_MIDRANGE_OP_ARGS_NONE}, - {"callw", PIC_MIDRANGE_OP_ARGS_NONE}, - {"brw", PIC_MIDRANGE_OP_ARGS_NONE}, - {"moviw", PIC_MIDRANGE_OP_ARGS_1N_2M}, - {"movwi", PIC_MIDRANGE_OP_ARGS_1N_2M}, - {"movlb", PIC_MIDRANGE_OP_ARGS_4K}, - {"lslf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"lsrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"asrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"subwfb", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"addwfc", PIC_MIDRANGE_OP_ARGS_1D_7F}, - {"addfsr", PIC_MIDRANGE_OP_ARGS_1N_6K}, - {"movlp", PIC_MIDRANGE_OP_ARGS_7F}, - {"bra", PIC_MIDRANGE_OP_ARGS_9K}, - {"moviw", PIC_MIDRANGE_OP_ARGS_1N_6K}, - {"movwi", PIC_MIDRANGE_OP_ARGS_1N_6K} + { "nop", PIC_MIDRANGE_OP_ARGS_NONE}, + { "return", PIC_MIDRANGE_OP_ARGS_NONE}, + { "retfie", PIC_MIDRANGE_OP_ARGS_NONE}, + { "option", PIC_MIDRANGE_OP_ARGS_NONE}, + { "sleep", PIC_MIDRANGE_OP_ARGS_NONE}, + { "clrwdt", PIC_MIDRANGE_OP_ARGS_NONE}, + { "tris", PIC_MIDRANGE_OP_ARGS_2F}, + { "movwf", PIC_MIDRANGE_OP_ARGS_7F}, + { "clr", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "subwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "decf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "iorwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "andwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "xorwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "addwf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "movf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "comf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "incf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "decfsz", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "rrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "rlf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "swapf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "incfsz", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "bcf", PIC_MIDRANGE_OP_ARGS_3B_7F}, + { "bsf", PIC_MIDRANGE_OP_ARGS_3B_7F}, + { "btfsc", PIC_MIDRANGE_OP_ARGS_3B_7F}, + { "btfss", PIC_MIDRANGE_OP_ARGS_3B_7F}, + { "call", PIC_MIDRANGE_OP_ARGS_11K}, + { "goto", PIC_MIDRANGE_OP_ARGS_11K}, + { "movlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "retlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "iorlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "andlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "xorlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "sublw", PIC_MIDRANGE_OP_ARGS_8K}, + { "addlw", PIC_MIDRANGE_OP_ARGS_8K}, + { "reset", PIC_MIDRANGE_OP_ARGS_NONE}, + { "callw", PIC_MIDRANGE_OP_ARGS_NONE}, + { "brw", PIC_MIDRANGE_OP_ARGS_NONE}, + { "moviw", PIC_MIDRANGE_OP_ARGS_1N_2M}, + { "movwi", PIC_MIDRANGE_OP_ARGS_1N_2M}, + { "movlb", PIC_MIDRANGE_OP_ARGS_4K}, + { "lslf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "lsrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "asrf", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "subwfb", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "addwfc", PIC_MIDRANGE_OP_ARGS_1D_7F}, + { "addfsr", PIC_MIDRANGE_OP_ARGS_1N_6K}, + { "movlp", PIC_MIDRANGE_OP_ARGS_7F}, + { "bra", PIC_MIDRANGE_OP_ARGS_9K}, + { "moviw", PIC_MIDRANGE_OP_ARGS_1N_6K}, + { "movwi", PIC_MIDRANGE_OP_ARGS_1N_6K} }; static const char *PicMidrangeFsrOps[] = { diff --git a/libr/asm/arch/pic/pic_pic18.c b/libr/asm/arch/pic/pic_pic18.c index b5537c40ea..64abdc2f98 100644 --- a/libr/asm/arch/pic/pic_pic18.c +++ b/libr/asm/arch/pic/pic_pic18.c @@ -21,7 +21,7 @@ #define S_T 11 #define LFSR_T 12 -static char *fsr[] = {"fsr0", "fsr1", "fsr2", "reserved"}; +static char *fsr[] = { "fsr0", "fsr1", "fsr2", "reserved" }; static struct { ut16 opmin; diff --git a/libr/asm/arch/ppc/gnu/ppc-dis.c b/libr/asm/arch/ppc/gnu/ppc-dis.c index afa70ebce5..116ad6ad22 100644 --- a/libr/asm/arch/ppc/gnu/ppc-dis.c +++ b/libr/asm/arch/ppc/gnu/ppc-dis.c @@ -361,7 +361,7 @@ print_insn_powerpc (bfd_vma memaddr, if (operand->bitm == 7) { (*info->fprintf_func) (info->stream, "cr%ld", value); } else { - static const char *cbnames[4] = {"lt", "gt", "eq", "so"}; + static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; int cr; int cc; diff --git a/libr/asm/arch/ppc/gnu/ppc-opc.c b/libr/asm/arch/ppc/gnu/ppc-opc.c index 5d385d038c..a8067f2338 100644 --- a/libr/asm/arch/ppc/gnu/ppc-opc.c +++ b/libr/asm/arch/ppc/gnu/ppc-opc.c @@ -1895,3252 +1895,3252 @@ extract_xb6s (unsigned long insn, constrained otherwise by disassembler operation. */ const struct powerpc_opcode powerpc_opcodes[] = { -{"attn", X(0,256), X_MASK, POWER4, {0}}, -{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}}, -{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}}, -{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}}, -{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}}, -{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}}, -{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}}, -{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}}, -{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}}, -{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}}, -{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}}, -{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}}, -{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}}, -{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}}, -{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}}, -{"tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}}, - -{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}}, -{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}}, -{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}}, -{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}}, -{"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}}, -{"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}}, - -{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, -{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, -{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, -{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, -{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, -{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}}, -{"ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, -{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, -{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, -{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, -{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, -{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, -{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, -{"ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, -{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, -{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, -{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, -{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}}, -{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}}, -{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, -{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}}, -{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}}, -{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, -{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}}, -{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}}, -{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}}, -{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}}, -{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}}, -{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}}, -{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}}, -{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}}, -{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}}, -{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}}, -{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}}, -{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}}, -{"evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}}, -{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}}, -{"evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}}, -{"evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}}, -{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}}, -{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}}, -{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}}, -{"brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}}, -{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}}, -{"evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}}, -{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}}, -{"get", APU(4, 268,0), APU_RA_MASK, PPC405, {RT, FSL}}, -{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, -{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, -{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, -{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}}, -{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, -{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}}, -{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, {RT, FSL}}, -{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}}, -{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}}, -{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, {RT, FSL}}, -{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}}, -{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, {RT, FSL}}, -{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}}, -{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}}, -{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}}, -{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}}, -{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}}, -{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}}, -{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}}, -{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}}, -{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}}, -{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}}, -{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}}, -{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}}, -{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}}, -{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}}, -{"put", APU(4, 332,0), APU_RT_MASK, PPC405, {RA, FSL}}, -{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}}, -{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}}, -{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, {RA, FSL}}, -{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}}, -{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}}, -{"efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}}, -{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}}, -{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}}, -{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}}, -{"efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}}, -{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}}, -{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}}, -{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}}, -{"efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}}, -{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}}, -{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}}, -{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}}, -{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}}, -{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, {RA, FSL}}, -{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}}, -{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}}, -{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}}, -{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}}, -{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}}, -{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}}, -{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}}, -{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}}, -{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}}, -{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, {RA, FSL}}, -{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}}, -{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}}, -{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, -{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}}, -{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, -{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, -{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, -{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, -{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}}, -{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}}, -{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}}, -{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}}, -{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}}, -{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}}, -{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}}, -{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}}, -{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}}, -{"evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}}, -{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}}, -{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}}, -{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}}, -{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}}, -{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, -{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, -{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}}, -{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}}, -{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}}, -{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}}, -{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, -{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, {URT, URA, URB}}, -{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, {URT, URA, URB}}, -{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, -{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}}, - -{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}}, -{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}}, - -{"subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}}, -{"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}}, - -{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}}, - -{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}}, -{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}}, -{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}}, -{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}}, - -{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}}, -{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}}, -{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}}, -{"cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}}, - -{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}}, -{"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}}, -{"cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}}, -{"cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}}, - -{"addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}}, -{"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}}, -{"subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}}, - -{"addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}}, -{"ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}}, -{"subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}}, - -{"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}}, -{"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}}, -{"addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}}, -{"cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}}, -{"subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}}, -{"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}}, - -{"lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}}, -{"liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}}, -{"addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}}, -{"cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}}, -{"subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}}, - -{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, -{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, -{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}}, -{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}}, -{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, -{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, -{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}}, -{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}}, -{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, -{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, -{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}}, -{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}}, -{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, -{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, -{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}}, -{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}}, -{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, -{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, -{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}}, -{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, -{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, -{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}}, -{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, -{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, -{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}}, -{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, -{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, -{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}}, - -{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, -{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, -{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, -{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, - -{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, -{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, -{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, -{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, -{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, -{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, -{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, -{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, -{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, -{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, -{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, -{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, - -{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, - -{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, -{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, -{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, -{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, -{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, -{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, -{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, -{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, -{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, -{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, -{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, -{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, -{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, -{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, -{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, -{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, - -{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, -{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, -{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, -{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, -{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, -{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, -{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, - -{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, -{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, -{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, -{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, -{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, -{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, -{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, -{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, -{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, -{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, -{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, -{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, -{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, -{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, -{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, -{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, - -{"bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}}, -{"bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}}, -{"bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}}, -{"bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}}, -{"bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}}, -{"bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}}, -{"bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}}, -{"bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}}, -{"bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}}, -{"bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}}, -{"bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}}, -{"bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}}, - -{"svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, -{"svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, -{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}}, -{"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}}, -{"svcla", SC(17,1,1), SC_MASK, POWER, {SV}}, - -{"b", B(18,0,0), B_MASK, COM, {LI}}, -{"bl", B(18,0,1), B_MASK, COM, {LI}}, -{"ba", B(18,1,0), B_MASK, COM, {LIA}}, -{"bla", B(18,1,1), B_MASK, COM, {LIA}}, - -{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, - -{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, -{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, -{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, -{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, -{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, -{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, -{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}}, -{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, -{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}}, -{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, -{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, -{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, -{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, -{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, -{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, -{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, -{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, - -{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, -{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, - -{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}}, -{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}}, -{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}}, -{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}}, -{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}}, -{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}}, -{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}}, -{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}}, -{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}}, -{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}}, -{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}}, -{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}}, - -{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, -{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}}, -{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, -{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}}, - -{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}}, -{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}}, - -{"rfid", XL(19,18), 0xffffffff, PPC64, {0}}, - -{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}}, -{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}}, -{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}}, - -{"rfdi", XL(19,39), 0xffffffff, E500MC, {0}}, -{"rfi", XL(19,50), 0xffffffff, COM, {0}}, -{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}}, - -{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}}, - -{"rfgi", XL(19,102), 0xffffffff, E500MC, {0}}, - -{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}}, - -{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}}, -{"ics", XL(19,150), 0xffffffff, PWRCOM, {0}}, - -{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}}, -{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}}, - -{"dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}}, - -{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}}, - -{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}}, - -{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}}, - -{"crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}}, -{"creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}}, - -{"doze", XL(19,402), 0xffffffff, POWER6, {0}}, - -{"crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}}, - -{"nap", XL(19,434), 0xffffffff, POWER6, {0}}, - -{"crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}}, -{"cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}}, - -{"sleep", XL(19,466), 0xffffffff, POWER6, {0}}, -{"rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}}, - -{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}}, -{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}}, - -{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, -{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, -{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, -{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, -{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, - -{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}}, -{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}}, -{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}}, -{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}}, -{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}}, -{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}}, -{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, -{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}}, -{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}}, -{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}}, -{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}}, - -{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, -{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, -{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}}, -{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, -{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}}, - -{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}}, -{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}}, - -{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, -{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, - -{"rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, -{"rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, - -{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}}, -{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}}, -{"rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, -{"rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, -{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}}, -{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}}, -{"rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, -{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, - -{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}}, -{"be", B(22,0,0), B_MASK, BOOKE64, {LI}}, -{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}}, -{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}}, -{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}}, -{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}}, - -{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}}, -{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, -{"rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, -{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}}, -{"rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, -{"rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, - -{"nop", OP(24), 0xffffffff, PPCCOM, {0}}, -{"ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}}, -{"andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}}, - -{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}}, -{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}}, -{"rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, -{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}}, -{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}}, -{"rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, - -{"rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, -{"rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, - -{"rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, -{"rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, - -{"rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, -{"rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, - -{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}}, -{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, -{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}}, -{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, - -{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, -{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, - -{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, -{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, -{"cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}}, -{"cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, - -{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}}, -{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}}, -{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}}, -{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}}, -{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}}, -{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}}, -{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}}, -{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}}, -{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}}, -{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}}, -{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}}, -{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}}, -{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}}, -{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}}, -{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}}, -{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}}, -{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}}, -{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}}, -{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}}, -{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}}, -{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}}, -{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}}, -{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}}, -{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}}, -{"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}}, -{"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}}, - -{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}}, -{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}}, -{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "attn", X(0,256), X_MASK, POWER4, {0}}, +{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}}, +{ "tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}}, + +{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}}, +{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}}, +{ "twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}}, +{ "ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}}, + +{ "ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, +{ "vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, +{ "vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, +{ "vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, +{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}}, +{ "ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, +{ "ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, +{ "ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, +{ "ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, +{ "ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, +{ "ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, +{ "ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, +{ "ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, +{ "ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, +{ "vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, +{ "vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, +{ "vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, +{ "vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, +{ "vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}}, +{ "vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}}, +{ "vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}}, +{ "vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}}, +{ "vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}}, +{ "vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}}, +{ "vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}}, +{ "evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}}, +{ "vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}}, +{ "vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}}, +{ "evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}}, +{ "vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}}, +{ "evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}}, +{ "evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}}, +{ "vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}}, +{ "evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}}, +{ "vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}}, +{ "brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}}, +{ "evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}}, +{ "evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}}, +{ "get", APU(4, 268,0), APU_RA_MASK, PPC405, {RT, FSL}}, +{ "eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, +{ "evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, +{ "evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, +{ "evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}}, +{ "evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, +{ "evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}}, +{ "evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "cget", APU(4, 284,0), APU_RA_MASK, PPC405, {RT, FSL}}, +{ "vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}}, +{ "vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}}, +{ "nget", APU(4, 300,0), APU_RA_MASK, PPC405, {RT, FSL}}, +{ "evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}}, +{ "ncget", APU(4, 316,0), APU_RA_MASK, PPC405, {RT, FSL}}, +{ "evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}}, +{ "vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}}, +{ "evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}}, +{ "vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}}, +{ "evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}}, +{ "evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}}, +{ "put", APU(4, 332,0), APU_RT_MASK, PPC405, {RA, FSL}}, +{ "evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}}, +{ "evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}}, +{ "cput", APU(4, 348,0), APU_RT_MASK, PPC405, {RA, FSL}}, +{ "efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}}, +{ "vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}}, +{ "efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}}, +{ "vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}}, +{ "efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}}, +{ "efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}}, +{ "efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}}, +{ "efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}}, +{ "efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}}, +{ "efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}}, +{ "efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}}, +{ "efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}}, +{ "efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}}, +{ "efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}}, +{ "efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}}, +{ "nput", APU(4, 364,0), APU_RT_MASK, PPC405, {RA, FSL}}, +{ "efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}}, +{ "efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}}, +{ "efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}}, +{ "efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}}, +{ "efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}}, +{ "efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}}, +{ "ncput", APU(4, 380,0), APU_RT_MASK, PPC405, {RA, FSL}}, +{ "efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}}, +{ "efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}}, +{ "evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, +{ "vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}}, +{ "evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, +{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, +{ "mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, +{ "evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, +{ "vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}}, +{ "vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}}, +{ "mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}}, +{ "maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}}, +{ "vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}}, +{ "maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}}, +{ "evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}}, +{ "evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}}, +{ "evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}}, +{ "evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}}, +{ "vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}}, +{ "evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}}, +{ "evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}}, +{ "evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}}, +{ "machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, +{ "evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, +{ "evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}}, +{ "nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}}, +{ "vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi8fcm", APU(4, 771,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}}, +{ "vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi9fcm", APU(4, 804,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi10fcm", APU(4, 835,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi11fcm", APU(4, 867,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi12fcm", APU(4, 899,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi13fcm", APU(4, 931,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi14fcm", APU(4, 963,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}}, +{ "maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, +{ "udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, {URT, URA, URB}}, +{ "udi15fcm", APU(4, 995,1), APU_MASK, PPC440, {URT, URA, URB}}, +{ "maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, +{ "dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}}, + +{ "mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}}, +{ "muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}}, + +{ "subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}}, +{ "sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}}, + +{ "dozi", OP(9), OP_MASK, M601, {RT, RA, SI}}, + +{ "bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}}, +{ "bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}}, +{ "bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}}, +{ "bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}}, + +{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}}, +{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}}, +{ "cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}}, +{ "cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}}, + +{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}}, +{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}}, +{ "cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}}, +{ "cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}}, + +{ "addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}}, +{ "ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}}, +{ "subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}}, + +{ "addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}}, +{ "ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}}, +{ "subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}}, + +{ "li", OP(14), DRA_MASK, PPCCOM, {RT, SI}}, +{ "lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}}, +{ "addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}}, +{ "cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}}, +{ "subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}}, +{ "la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}}, + +{ "lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}}, +{ "liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}}, +{ "addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}}, +{ "cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}}, +{ "subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}}, + +{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, +{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, +{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}}, +{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}}, +{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, +{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, +{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}}, +{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}}, +{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, +{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, +{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}}, +{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}}, +{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, +{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, +{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}}, +{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}}, +{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, +{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, +{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}}, +{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, +{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, +{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}}, +{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, +{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, +{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}}, +{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, +{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, +{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}}, + +{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, +{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, +{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, +{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, + +{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, +{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, +{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, +{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, +{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, +{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, +{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, +{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, +{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, +{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, +{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, +{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, + +{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, + +{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, +{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, +{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, +{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, +{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, +{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, +{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, +{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, +{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, +{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, +{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, +{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, +{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, +{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, +{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, +{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, + +{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, +{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, +{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, +{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, +{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, +{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, +{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, + +{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, +{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, +{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, +{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, +{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, +{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, +{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, +{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, +{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, +{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, +{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, +{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, +{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, +{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, +{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, +{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, + +{ "bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}}, +{ "bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}}, +{ "bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}}, +{ "bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}}, +{ "bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}}, +{ "bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}}, +{ "bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}}, +{ "bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}}, +{ "bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}}, +{ "bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}}, +{ "bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}}, +{ "bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}}, + +{ "svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, +{ "svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, +{ "sc", SC(17,1,0), SC_MASK, PPC, {LEV}}, +{ "svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}}, +{ "svcla", SC(17,1,1), SC_MASK, POWER, {SV}}, + +{ "b", B(18,0,0), B_MASK, COM, {LI}}, +{ "bl", B(18,0,1), B_MASK, COM, {LI}}, +{ "ba", B(18,1,0), B_MASK, COM, {LIA}}, +{ "bla", B(18,1,1), B_MASK, COM, {LIA}}, + +{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, + +{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, +{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}}, +{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, +{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}}, +{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, +{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, + +{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, +{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, + +{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}}, +{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}}, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}}, +{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}}, +{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}}, +{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}}, +{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}}, +{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}}, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}}, +{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}}, +{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}}, +{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}}, + +{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, +{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}}, +{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, +{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}}, + +{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}}, +{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}}, + +{ "rfid", XL(19,18), 0xffffffff, PPC64, {0}}, + +{ "crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}}, +{ "crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}}, +{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}}, + +{ "rfdi", XL(19,39), 0xffffffff, E500MC, {0}}, +{ "rfi", XL(19,50), 0xffffffff, COM, {0}}, +{ "rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}}, + +{ "rfsvc", XL(19,82), 0xffffffff, POWER, {0}}, + +{ "rfgi", XL(19,102), 0xffffffff, E500MC, {0}}, + +{ "crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}}, + +{ "isync", XL(19,150), 0xffffffff, PPCCOM, {0}}, +{ "ics", XL(19,150), 0xffffffff, PWRCOM, {0}}, + +{ "crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}}, +{ "crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}}, + +{ "dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}}, + +{ "crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}}, + +{ "crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}}, + +{ "hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}}, + +{ "crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}}, +{ "creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}}, + +{ "doze", XL(19,402), 0xffffffff, POWER6, {0}}, + +{ "crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}}, + +{ "nap", XL(19,434), 0xffffffff, POWER6, {0}}, + +{ "crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}}, +{ "cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}}, + +{ "sleep", XL(19,466), 0xffffffff, POWER6, {0}}, +{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}}, + +{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}}, +{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}}, + +{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, +{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, +{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, +{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, + +{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}}, +{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}}, +{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}}, +{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}}, +{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}}, +{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}}, +{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, +{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}}, +{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}}, +{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}}, +{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}}, + +{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, +{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, +{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}}, +{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, +{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}}, + +{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}}, +{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}}, + +{ "rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, +{ "rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, + +{ "rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, +{ "rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, + +{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}}, +{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}}, +{ "rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, +{ "rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, +{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}}, +{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}}, +{ "rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, +{ "rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, + +{ "rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}}, +{ "be", B(22,0,0), B_MASK, BOOKE64, {LI}}, +{ "bel", B(22,0,1), B_MASK, BOOKE64, {LI}}, +{ "rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}}, +{ "bea", B(22,1,0), B_MASK, BOOKE64, {LIA}}, +{ "bela", B(22,1,1), B_MASK, BOOKE64, {LIA}}, + +{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}}, +{ "rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, +{ "rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, +{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}}, +{ "rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, +{ "rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, + +{ "nop", OP(24), 0xffffffff, PPCCOM, {0}}, +{ "ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}}, +{ "andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}}, + +{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}}, +{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}}, +{ "rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, +{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}}, +{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}}, +{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, + +{ "rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, +{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, + +{ "rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, +{ "rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, + +{ "rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, +{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, + +{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}}, +{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, +{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}}, +{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, + +{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, +{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, + +{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, +{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, +{ "cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}}, +{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, + +{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}}, +{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}}, +{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}}, +{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}}, +{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}}, +{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}}, +{ "tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}}, +{ "t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}}, + +{ "lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lbfcmx", APU(31,7,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}}, -{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}}, +{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}}, +{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}}, -{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}}, -{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}}, -{"isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}}, +{ "isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}}, -{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}}, -{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}}, -{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}}, - -{"lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}}, +{ "mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}}, +{ "mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}}, +{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}}, + +{ "lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}}, -{"ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}}, +{ "ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}}, -{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}}, +{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}}, -{"lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}}, -{"lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}}, +{ "lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}}, -{"slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}}, -{"slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}}, -{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}}, -{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}}, -{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}}, -{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}}, +{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}}, +{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}}, +{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}}, +{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}}, -{"sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}}, -{"sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}}, +{ "sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}}, +{ "sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}}, -{"and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}}, -{"and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}}, +{ "and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}}, +{ "and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}}, -{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}}, -{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}}, +{ "maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}}, +{ "maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}}, -{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}}, +{ "ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}}, -{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}}, +{ "icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}}, -{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}}, +{ "lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}}, -{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, -{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, -{"cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}}, -{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, +{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, +{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, +{ "cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}}, +{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, -{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}}, -{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}}, -{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lhfcmx", APU(31,39,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}}, +{ "iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}}, -{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}}, -{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}}, +{ "iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}}, -{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}}, +{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}}, -{"subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}}, -{"sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}}, -{"subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}}, -{"sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}}, +{ "subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}}, +{ "subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}}, -{"ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}}, +{ "ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}}, -{"dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}}, +{ "dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}}, -{"lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}}, -{"lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}}, +{ "lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}}, -{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}}, -{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}}, +{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}}, +{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}}, -{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}}, -{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}}, +{ "andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}}, +{ "andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}}, -{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}}, +{ "dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}}, -{"wait", X(31,62), 0xffffffff, E500MC, {0}}, +{ "wait", X(31,62), 0xffffffff, E500MC, {0}}, -{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}}, +{ "lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}}, -{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}}, +{ "dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}}, -{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}}, -{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}}, -{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}}, -{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}}, -{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}}, -{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}}, -{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}}, -{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}}, -{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}}, -{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}}, -{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}}, -{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}}, -{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}}, -{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}}, -{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}}, +{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}}, +{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}}, +{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}}, +{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}}, +{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}}, +{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}}, +{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}}, +{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}}, +{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}}, +{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}}, +{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}}, +{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}}, +{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}}, +{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}}, +{ "td", X(31,68), X_MASK, PPC64, {TO, RA, RB}}, -{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "lwfcmx", APU(31,71,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}}, -{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}}, -{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}}, -{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}}, +{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}}, +{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}}, -{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}}, +{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}}, -{"mfmsr", X(31,83), XRARB_MASK, COM, {RT}}, +{ "mfmsr", X(31,83), XRARB_MASK, COM, {RT}}, -{"ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}}, +{ "ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}}, -{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}}, -{"dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}}, +{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}}, +{ "dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}}, -{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}}, +{ "lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}}, -{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}}, +{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}}, -{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}}, +{ "lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}}, -{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}}, -{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}}, +{ "lqfcmx", APU(31,103,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}}, -{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}}, +{ "neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}}, +{ "neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}}, -{"mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}}, -{"mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}}, +{ "mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}}, +{ "mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}}, -{"mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}}, +{ "mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}}, -{"clf", X(31,118), XTO_MASK, POWER, {RA, RB}}, +{ "clf", X(31,118), XTO_MASK, POWER, {RA, RB}}, -{"lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}}, +{ "lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}}, -{"popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}}, +{ "popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}}, -{"not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}}, -{"nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}}, -{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}}, -{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}}, +{ "not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}}, +{ "nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}}, +{ "not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}}, +{ "nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}}, -{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}}, +{ "lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}}, -{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}}, +{ "dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}}, -{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}}, +{ "wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}}, -{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}}, +{ "dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}}, -{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}}, -{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}}, +{ "stbfcmx", APU(31,135,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}}, +{ "dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}}, -{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}}, -{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}}, -{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}}, +{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}}, +{ "mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}}, +{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}}, -{"mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}}, +{ "mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}}, -{"stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}}, +{ "stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}}, -{"stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}}, +{ "stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}}, -{"stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}}, -{"stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}}, +{ "stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}}, +{ "stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}}, -{"slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}}, -{"slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}}, +{ "slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}}, +{ "slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}}, -{"sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}}, -{"sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}}, +{ "sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}}, +{ "sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}}, -{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}}, +{ "prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}}, -{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}}, +{ "stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}}, -{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}}, +{ "stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}}, -{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}}, +{ "wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}}, -{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}}, +{ "dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}}, -{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}}, -{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}}, +{ "sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}}, +{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}}, -{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}}, +{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}}, -{"stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}}, +{ "stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}}, -{"stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}}, -{"stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}}, +{ "stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}}, +{ "stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}}, -{"sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}}, -{"sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}}, +{ "sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}}, +{ "sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}}, -{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}}, +{ "prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}}, -{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}}, +{ "stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}}, -{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}}, -{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}}, +{ "stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}}, +{ "msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}}, -{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}}, +{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}}, -{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}}, +{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}}, -{"stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}}, +{ "stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}}, -{"sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}}, -{"sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}}, +{ "sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}}, +{ "sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}}, -{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}}, -{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}}, +{ "sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}}, +{ "sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}}, -{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}}, +{ "stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}}, -{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}}, +{ "icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}}, -{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}}, -{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}}, +{ "stqfcmx", APU(31,231,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}}, -{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}}, -{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}}, -{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}}, +{ "msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}}, +{ "icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}}, +{ "mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}}, +{ "mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}}, -{"dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}}, +{ "dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}}, -{"stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}}, +{ "stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}}, -{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}}, -{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}}, +{ "slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}}, +{ "slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}}, -{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}}, +{ "dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}}, -{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}}, +{ "stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}}, -{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}}, +{ "dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}}, -{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}}, +{ "mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}}, -{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}}, +{ "icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}}, -{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}}, -{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}}, +{ "ldfcmx", APU(31,263,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}}, +{ "doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}}, -{"add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"ehpriv", X(31,270), 0xffffffff, E500MC, {0}}, +{ "ehpriv", X(31,270), 0xffffffff, E500MC, {0}}, -{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}}, +{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}}, -{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}}, +{ "mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}}, -{"lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}}, -{"lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}}, +{ "lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}}, +{ "lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}}, -{"dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}}, - -{"lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}}, - -{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}}, -{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}}, - -{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}}, - -{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}}, - -{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}}, - -{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}}, -{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}}, - -{"eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}}, - -{"lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}}, - -{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}}, -{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}}, - -{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}}, - -{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}}, - -{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}}, -{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}}, -{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}}, -{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}}, -{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}}, -{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}}, -{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}}, -{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}}, -{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}}, -{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}}, -{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}}, -{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}}, -{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}}, -{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}}, -{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}}, -{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}}, -{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}}, -{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}}, -{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}}, -{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}}, -{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}}, -{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}}, -{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}}, -{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}}, -{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}}, -{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}}, -{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}}, -{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}}, -{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}}, -{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}}, -{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}}, -{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}}, -{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}}, -{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}}, -{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}}, - -{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}}, -{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}}, - -{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}}, - -{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}}, -{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}}, -{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}}, -{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}}, -{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}}, -{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}}, -{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}}, -{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}}, -{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}}, -{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}}, -{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}}, -{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}}, -{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}}, -{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}}, -{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}}, -{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}}, -{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}}, -{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}}, -{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}}, -{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}}, -{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}}, -{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}}, -{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}}, -{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}}, -{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}}, -{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}}, -{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}}, -{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}}, -{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}}, -{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}}, -{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}}, -{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}}, -{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}}, -{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}}, -{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}}, -{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}}, -{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}}, -{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}}, -{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}}, -{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}}, -{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}}, -{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}}, -{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}}, -{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}}, -{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}}, -{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, -{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, -{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}}, -{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}}, -{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}}, -{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}}, -{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}}, -{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}}, -{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}}, -{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}}, -{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}}, -{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}}, -{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}}, -{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}}, -{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}}, -{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}}, -{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}}, -{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}}, -{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}}, -{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}}, -{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}}, -{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}}, -{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}}, -{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}}, -{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}}, -{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}}, -{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}}, -{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}}, -{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}}, -{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}}, -{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}}, -{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}}, -{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}}, -{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}}, -{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}}, -{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}}, -{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}}, -{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}}, -{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}}, -{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}}, -{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}}, -{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}}, -{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}}, -{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}}, -{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}}, -{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, -{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}}, -{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, -{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}}, -{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}}, -{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, -{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, -{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}}, -{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}}, -{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}}, -{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}}, -{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}}, -{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}}, -{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}}, -{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}}, -{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}}, -{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}}, -{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}}, -{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}}, -{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}}, -{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}}, -{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}}, -{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}}, -{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}}, -{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}}, -{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}}, -{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}}, -{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}}, -{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}}, -{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}}, -{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}}, -{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}}, -{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}}, -{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}}, -{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}}, -{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}}, -{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}}, -{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}}, -{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}}, -{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}}, -{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}}, -{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}}, -{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}}, -{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}}, -{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}}, -{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}}, -{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}}, -{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}}, -{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}}, -{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}}, -{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}}, -{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}}, -{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}}, -{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}}, -{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}}, -{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}}, -{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}}, -{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}}, -{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}}, -{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}}, -{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}}, -{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}}, -{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}}, -{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}}, -{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}}, -{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}}, -{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}}, -{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}}, -{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}}, -{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}}, -{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}}, -{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}}, -{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}}, -{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}}, -{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}}, -{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}}, -{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}}, -{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}}, -{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}}, -{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}}, -{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}}, -{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}}, -{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}}, -{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}}, -{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}}, -{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}}, -{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}}, -{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}}, -{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}}, -{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}}, -{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}}, -{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}}, -{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}}, -{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}}, -{"mfspr", X(31,339), X_MASK, COM, {RT, SPR}}, - -{"lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}}, - -{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, - -{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}}, - -{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}}, - -{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}}, - -{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}}, -{"abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}}, - -{"divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}}, -{"divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}}, - -{"tlbia", X(31,370), 0xffffffff, PPC, {0}}, - -{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}}, -{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}}, -{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}}, - -{"lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}}, - -{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, - -{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}}, - -{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}}, - -{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}}, - -{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}}, -{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}}, - -{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, - -{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, - -{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}}, - -{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}}, - -{"sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}}, - -{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}}, -{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}}, - -{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}}, - -{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}}, - -{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}}, - -{"ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}}, - -{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}}, - -{"mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}}, - -{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}}, -{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}}, -{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}}, -{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}}, - -{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}}, - -{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}}, -{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}}, -{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}}, -{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}}, -{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}}, -{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}}, -{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}}, -{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}}, -{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}}, -{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}}, -{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}}, -{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}}, -{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}}, -{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}}, -{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}}, -{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}}, -{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}}, -{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}}, -{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}}, -{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}}, -{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}}, -{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}}, -{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}}, -{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}}, -{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}}, -{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}}, -{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}}, -{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}}, -{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}}, -{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}}, -{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}}, -{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}}, -{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}}, -{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}}, -{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}}, - -{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}}, - -{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}}, - -{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}}, - -{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}}, - -{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}}, -{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}}, - -{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}}, - -{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}}, -{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}}, -{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}}, -{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}}, -{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}}, -{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}}, -{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}}, -{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}}, -{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}}, -{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}}, -{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}}, -{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}}, -{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}}, -{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}}, -{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}}, -{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}}, -{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}}, -{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}}, -{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}}, -{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}}, -{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}}, -{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}}, -{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}}, -{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}}, -{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}}, -{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}}, -{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}}, -{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}}, -{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}}, -{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}}, -{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}}, -{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}}, -{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}}, -{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}}, -{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}}, -{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}}, -{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}}, -{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}}, -{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}}, -{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}}, -{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}}, -{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}}, -{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}}, -{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}}, -{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}}, -{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}}, -{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}}, -{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}}, -{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}}, -{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}}, -{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}}, -{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}}, -{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}}, -{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}}, -{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}}, -{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}}, -{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}}, -{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}}, -{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}}, -{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}}, -{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}}, -{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}}, -{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}}, -{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}}, -{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}}, -{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}}, -{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}}, -{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}}, -{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}}, -{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}}, -{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}}, -{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}}, -{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}}, -{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}}, -{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}}, -{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}}, -{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}}, -{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}}, -{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}}, -{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}}, -{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}}, -{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}}, -{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}}, -{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}}, -{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}}, -{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}}, -{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}}, -{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, -{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}}, -{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, -{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}}, -{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}}, -{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, -{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, -{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}}, -{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}}, -{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}}, -{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}}, -{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}}, -{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}}, -{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}}, -{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}}, -{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}}, -{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}}, -{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}}, -{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}}, -{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}}, -{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}}, -{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}}, -{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}}, -{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}}, -{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}}, -{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}}, -{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}}, -{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}}, -{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}}, -{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}}, -{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}}, -{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}}, -{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}}, -{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}}, -{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}}, -{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}}, -{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}}, -{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}}, -{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}}, -{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}}, -{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}}, -{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}}, -{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}}, -{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}}, -{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}}, -{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}}, -{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}}, -{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}}, -{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}}, -{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}}, -{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}}, -{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}}, -{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}}, -{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}}, -{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}}, -{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}}, -{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}}, -{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}}, -{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}}, -{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}}, -{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}}, -{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}}, -{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}}, -{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}}, -{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}}, -{"mtspr", X(31,467), X_MASK, COM, {SPR, RS}}, - -{"dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}}, - -{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}}, -{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}}, - -{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}}, - -{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}}, - -{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}}, - -{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}}, - -{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}}, - -{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}}, -{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}}, -{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}}, - -{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}}, - -{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}}, - -{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}}, -{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}}, - -{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}}, - -{"slbia", X(31,498), 0xffffffff, PPC64, {0}}, +{ "dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}}, + +{ "lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}}, + +{ "eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}}, +{ "eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}}, + +{ "dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}}, + +{ "lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}}, + +{ "mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}}, + +{ "tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}}, +{ "tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}}, + +{ "eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}}, + +{ "lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}}, + +{ "xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}}, +{ "xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}}, + +{ "lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}}, + +{ "dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}}, + +{ "mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}}, +{ "mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}}, +{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}}, +{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}}, +{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}}, +{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}}, +{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}}, +{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}}, +{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}}, +{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}}, +{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}}, +{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}}, +{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}}, +{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}}, +{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}}, +{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}}, +{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}}, +{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}}, +{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}}, +{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}}, +{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}}, +{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}}, +{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}}, +{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}}, +{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}}, +{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}}, +{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}}, +{ "mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}}, + +{ "div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}}, +{ "div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}}, + +{ "mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}}, + +{ "mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}}, +{ "mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}}, +{ "mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}}, +{ "mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}}, +{ "mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}}, +{ "mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}}, +{ "mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}}, +{ "mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}}, +{ "mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}}, +{ "mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}}, +{ "mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}}, +{ "mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}}, +{ "mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}}, +{ "mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}}, +{ "mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}}, +{ "mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}}, +{ "mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}}, +{ "mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}}, +{ "mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}}, +{ "mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}}, +{ "mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}}, +{ "mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}}, +{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}}, +{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}}, +{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}}, +{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}}, +{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}}, +{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}}, +{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}}, +{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}}, +{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}}, +{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}}, +{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}}, +{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}}, +{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}}, +{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}}, +{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}}, +{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}}, +{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}}, +{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}}, +{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, +{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, +{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}}, +{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}}, +{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}}, +{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}}, +{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}}, +{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}}, +{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}}, +{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}}, +{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}}, +{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}}, +{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}}, +{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}}, +{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}}, +{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}}, +{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}}, +{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}}, +{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}}, +{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}}, +{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}}, +{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}}, +{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}}, +{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}}, +{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}}, +{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}}, +{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}}, +{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}}, +{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}}, +{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}}, +{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, +{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}}, +{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, +{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}}, +{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}}, +{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, +{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, +{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}}, +{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}}, +{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}}, +{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}}, +{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}}, +{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}}, +{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}}, +{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}}, +{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}}, +{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}}, +{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}}, +{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}}, +{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}}, +{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}}, +{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}}, +{ "mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}}, +{ "mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}}, +{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}}, +{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}}, +{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}}, +{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}}, +{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}}, +{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}}, +{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}}, +{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}}, +{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}}, +{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}}, +{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}}, +{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}}, +{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}}, +{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}}, +{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}}, +{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}}, +{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}}, +{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}}, +{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}}, +{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}}, +{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}}, +{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}}, +{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}}, +{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}}, +{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}}, +{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}}, +{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}}, +{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}}, +{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}}, +{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}}, +{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}}, +{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}}, +{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}}, +{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}}, +{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}}, +{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}}, +{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}}, +{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}}, +{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}}, +{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}}, +{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}}, +{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}}, +{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}}, +{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}}, +{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}}, +{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}}, +{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}}, +{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}}, +{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}}, +{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}}, +{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}}, +{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}}, +{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}}, +{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}}, +{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}}, +{ "mfspr", X(31,339), X_MASK, COM, {RT, SPR}}, + +{ "lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}}, + +{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, + +{ "lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}}, + +{ "lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}}, + +{ "lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}}, + +{ "abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}}, +{ "abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}}, + +{ "divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}}, +{ "divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}}, + +{ "tlbia", X(31,370), 0xffffffff, PPC, {0}}, + +{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}}, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}}, +{ "mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}}, + +{ "lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}}, + +{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, + +{ "lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}}, + +{ "lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}}, + +{ "mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}}, + +{ "dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}}, +{ "stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}}, + +{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, + +{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, + +{ "dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}}, + +{ "slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}}, + +{ "sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}}, + +{ "orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}}, +{ "orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}}, + +{ "sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}}, + +{ "mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}}, + +{ "slbie", X(31,434), XRTRA_MASK, PPC64, {RB}}, + +{ "ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}}, + +{ "sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}}, + +{ "mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}}, + +{ "mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}}, +{ "or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}}, +{ "mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}}, +{ "or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}}, + +{ "sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}}, + +{ "mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}}, +{ "mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}}, +{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}}, +{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}}, +{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}}, +{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}}, +{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}}, +{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}}, +{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}}, +{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}}, +{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}}, +{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}}, +{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}}, +{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}}, +{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}}, +{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}}, +{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}}, +{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}}, +{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}}, +{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}}, +{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}}, +{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}}, +{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}}, +{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}}, +{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}}, +{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}}, +{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}}, +{ "mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}}, + +{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}}, + +{ "subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}}, + +{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}}, + +{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}}, + +{ "divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}}, + +{ "mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}}, + +{ "mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}}, +{ "mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}}, +{ "mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}}, +{ "mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}}, +{ "mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}}, +{ "mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}}, +{ "mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}}, +{ "mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}}, +{ "mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}}, +{ "mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}}, +{ "mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}}, +{ "mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}}, +{ "mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}}, +{ "mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}}, +{ "mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}}, +{ "mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}}, +{ "mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}}, +{ "mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}}, +{ "mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}}, +{ "mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}}, +{ "mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}}, +{ "mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}}, +{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}}, +{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}}, +{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}}, +{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}}, +{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}}, +{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}}, +{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}}, +{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}}, +{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}}, +{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}}, +{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}}, +{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}}, +{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}}, +{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}}, +{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}}, +{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}}, +{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}}, +{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}}, +{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}}, +{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}}, +{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}}, +{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}}, +{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}}, +{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}}, +{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}}, +{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}}, +{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}}, +{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}}, +{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}}, +{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}}, +{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}}, +{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}}, +{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}}, +{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}}, +{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}}, +{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}}, +{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}}, +{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}}, +{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}}, +{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}}, +{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}}, +{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}}, +{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}}, +{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}}, +{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}}, +{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, +{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}}, +{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, +{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}}, +{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}}, +{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, +{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, +{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}}, +{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}}, +{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}}, +{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}}, +{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}}, +{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}}, +{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}}, +{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}}, +{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}}, +{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}}, +{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}}, +{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}}, +{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}}, +{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}}, +{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}}, +{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}}, +{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}}, +{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}}, +{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}}, +{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}}, +{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}}, +{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}}, +{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}}, +{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}}, +{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}}, +{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}}, +{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}}, +{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}}, +{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}}, +{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}}, +{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}}, +{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}}, +{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}}, +{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}}, +{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}}, +{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}}, +{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}}, +{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}}, +{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}}, +{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}}, +{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}}, +{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}}, +{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}}, +{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}}, +{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}}, +{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}}, +{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}}, +{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}}, +{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}}, +{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}}, +{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}}, +{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}}, +{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}}, +{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}}, +{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}}, +{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}}, +{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}}, +{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}}, +{ "mtspr", X(31,467), X_MASK, COM, {SPR, RS}}, + +{ "dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}}, + +{ "nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}}, +{ "nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}}, + +{ "dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}}, + +{ "dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}}, + +{ "dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}}, + +{ "icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}}, + +{ "stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}}, + +{ "nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}}, +{ "subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}}, +{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}}, + +{ "divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}}, + +{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}}, + +{ "divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}}, + +{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}}, + +{ "slbia", X(31,498), 0xffffffff, PPC64, {0}}, -{"cli", X(31,502), XRB_MASK, POWER, {RT, RA}}, +{ "cli", X(31,502), XRB_MASK, POWER, {RT, RA}}, -{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}}, +{ "cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}}, -{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}}, +{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}}, -{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}}, +{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}}, -{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}}, +{ "lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}}, -{"bblels", X(31,518), X_MASK, PPCBRLK, {0}}, +{ "bblels", X(31,518), X_MASK, PPCBRLK, {0}}, -{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}}, -{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}}, +{ "lbfcmux", APU(31,519,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}}, -{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}}, +{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}}, +{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}}, -{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"clcs", X(31,531), XRB_MASK, M601, {RT, RA}}, +{ "clcs", X(31,531), XRB_MASK, M601, {RT, RA}}, -{"ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}}, +{ "ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}}, -{"lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}}, -{"lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}}, +{ "lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}}, -{"lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}}, -{"lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}}, +{ "lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}}, -{"lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}}, +{ "lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}}, -{"srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}}, -{"srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}}, -{"rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}}, -{"rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}}, +{ "rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}}, +{ "rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}}, -{"srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}}, -{"srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}}, +{ "srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}}, +{ "srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}}, -{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}}, -{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}}, +{ "maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}}, +{ "maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}}, -{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}}, +{ "lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}}, -{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}}, +{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}}, -{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}}, +{ "lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}}, -{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}}, +{ "bbelr", X(31,550), X_MASK, PPCBRLK, {0}}, -{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}}, -{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}}, +{ "lhfcmux", APU(31,551,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}}, -{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}}, -{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}}, -{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}}, +{ "subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}}, +{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}}, -{"tlbsync", X(31,566), 0xffffffff, PPC, {0}}, +{ "tlbsync", X(31,566), 0xffffffff, PPC, {0}}, -{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}}, +{ "lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}}, -{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}}, +{ "lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}}, -{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}}, +{ "lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}}, -{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}}, +{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}}, -{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}}, -{"lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}}, +{ "lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}}, +{ "lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}}, -{"msync", X(31,598), 0xffffffff, BOOKE, {0}}, -{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}}, -{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}}, -{"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}}, -{"dcs", X(31,598), 0xffffffff, PWRCOM, {0}}, +{ "msync", X(31,598), 0xffffffff, BOOKE, {0}}, +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}}, +{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}}, +{ "sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}}, +{ "dcs", X(31,598), 0xffffffff, PWRCOM, {0}}, -{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}}, +{ "lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}}, -{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}}, -{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}}, -{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}}, +{ "lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}}, +{ "lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}}, +{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}}, -{"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}}, +{ "lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}}, -{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lqfcmux", APU(31,615,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}}, -{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}}, +{ "nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}}, +{ "nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}}, -{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}}, -{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}}, +{ "mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}}, +{ "mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}}, -{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}}, -{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}}, +{ "dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}}, -{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}}, +{ "lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}}, -{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}}, +{ "lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}}, -{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}}, +{ "stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}}, -{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}}, -{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}}, +{ "stbfcmux", APU(31,647,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}}, +{ "mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}}, -{"stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}}, +{ "stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}}, -{"stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}}, -{"stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}}, +{ "stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}}, +{ "stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}}, -{"stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}}, -{"stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}}, +{ "stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}}, +{ "stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}}, -{"stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}}, +{ "stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}}, -{"srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}}, -{"srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}}, +{ "srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}}, +{ "srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}}, -{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}}, -{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}}, +{ "sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}}, +{ "sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}}, -{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}}, +{ "stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}}, -{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}}, +{ "sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}}, -{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}}, -{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}}, +{ "sthfcmux", APU(31,679,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}}, +{ "stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}}, -{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}}, -{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}}, +{ "sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}}, +{ "sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}}, -{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}}, +{ "stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}}, -{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}}, +{ "stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}}, -{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}}, -{"stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}}, +{ "stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}}, +{ "stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}}, -{"stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}}, +{ "stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}}, -{"srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}}, -{"srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}}, +{ "srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}}, +{ "srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}}, -{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}}, -{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}}, +{ "sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}}, +{ "sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}}, -{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}}, -{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}}, -{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}}, +{ "stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}}, +{ "stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}}, +{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}}, -{"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}}, +{ "stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}}, -{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stqfcmux", APU(31,743,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}}, -{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}}, -{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}}, -{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}}, +{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}}, +{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}}, +{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}}, -{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}}, -{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}}, +{ "dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}}, +{ "dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}}, -{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}}, +{ "stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}}, -{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}}, -{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}}, +{ "srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}}, +{ "srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}}, -{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}}, +{ "dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}}, -{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}}, +{ "stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}}, -{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}}, -{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}}, +{ "ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}}, -{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}}, +{ "dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}}, +{ "dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}}, -{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, -{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, +{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, +{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, -{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}}, -{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}}, -{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}}, -{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}}, -{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}}, -{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}}, +{ "tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}}, +{ "tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}}, +{ "tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}}, +{ "tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}}, +{ "tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}}, +{ "tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}}, -{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}}, +{ "lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}}, -{"lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}}, +{ "lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}}, -{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}}, -{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}}, +{ "lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}}, +{ "lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}}, -{"sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}}, -{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}}, -{"sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}}, +{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}}, +{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}}, -{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}}, -{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}}, +{ "srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}}, +{ "srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}}, -{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}}, +{ "lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}}, -{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}}, +{ "lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}}, -{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}}, +{ "rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}}, -{"lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}}, +{ "lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}}, -{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}}, +{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}}, -{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}}, +{ "lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}}, -{"srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}}, -{"srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}}, -{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}}, -{"srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}}, +{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}}, +{ "srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}}, +{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}}, +{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}}, -{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}}, -{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}}, +{ "sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}}, +{ "sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}}, -{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}}, -{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}}, -{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}}, +{ "divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}}, +{ "divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}}, +{ "lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}}, -{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}}, +{ "lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}}, -{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}}, +{ "slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}}, -{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}}, +{ "lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}}, -{"mbar", X(31,854), X_MASK, BOOKE, {MO}}, -{"eieio", X(31,854), 0xffffffff, PPC, {0}}, +{ "mbar", X(31,854), X_MASK, BOOKE, {MO}}, +{ "eieio", X(31,854), 0xffffffff, PPC, {0}}, -{"lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}}, +{ "lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}}, -{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}}, -{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}}, +{ "abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}}, +{ "abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}}, -{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}}, -{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}}, +{ "divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}}, +{ "divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}}, -{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}}, +{ "lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}}, -{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}}, +{ "ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}}, -{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}}, -{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}}, +{ "stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}}, +{ "stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}}, -{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, +{ "subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, -{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, +{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, -{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, -{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, -{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}}, -{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}}, -{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}}, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}}, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}}, +{ "slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}}, -{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}}, +{ "stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}}, -{"sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}}, +{ "sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}}, -{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}}, -{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}}, +{ "stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}}, +{ "stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}}, -{"sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}}, -{"sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}}, +{ "sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}}, +{ "sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}}, -{"srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}}, -{"srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}}, +{ "srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}}, +{ "srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}}, -{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}}, -{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}}, -{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}}, -{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}}, +{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}}, +{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}}, +{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}}, +{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}}, -{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}}, +{ "stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}}, -{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}}, +{ "stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}}, -{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}}, +{ "stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}}, -{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}}, -{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}}, -{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, +{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}}, +{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}}, +{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, -{"sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}}, +{ "sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}}, -{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}}, +{ "stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}}, -{"sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}}, -{"sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}}, +{ "sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}}, +{ "sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}}, -{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}}, -{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}}, +{ "extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}}, +{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}}, -{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}}, +{ "stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}}, -{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}}, +{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}}, -{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}}, +{ "subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}}, -{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}}, +{ "addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}}, -{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}}, -{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}}, -{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}}, +{ "stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}}, -{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}}, -{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}}, -{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, -{"tlbld", X(31,978), XRTRA_MASK, PPC, {RB}}, +{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}}, +{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}}, +{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, +{ "tlbld", X(31,978), XRTRA_MASK, PPC, {RB}}, -{"stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}}, +{ "stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}}, -{"icbi", X(31,982), XRT_MASK, PPC, {RA, RB}}, +{ "icbi", X(31,982), XRT_MASK, PPC, {RA, RB}}, -{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}}, +{ "stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}}, -{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}}, -{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}}, +{ "extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}}, +{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}}, -{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}}, -{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}}, +{ "icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}}, +{ "stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}}, -{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}}, +{ "icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}}, -{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}}, +{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}}, -{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}}, -{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}}, -{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}}, +{ "nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}}, +{ "subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}}, +{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}}, -{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}}, -{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}}, +{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}}, -{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}}, +{ "addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}}, -{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}}, -{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}}, +{ "divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}}, +{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}}, -{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}}, +{ "stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}}, -{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}}, +{ "tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}}, -{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}}, +{ "stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}}, -{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, -{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, +{ "dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, +{ "dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, -{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}}, -{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}}, +{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}}, +{ "dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}}, -{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}}, -{"dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}}, +{ "dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}}, +{ "dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}}, -{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}}, -{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}}, -{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}}, +{ "cctpl", 0x7c210b78, 0xffffffff, CELL, {0}}, +{ "cctpm", 0x7c421378, 0xffffffff, CELL, {0}}, +{ "cctph", 0x7c631b78, 0xffffffff, CELL, {0}}, -{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, -{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, -{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}}, +{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, +{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}}, -{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}}, -{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}}, -{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}}, -{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}}, +{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}}, +{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}}, +{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}}, +{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}}, -{"lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}}, -{"l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}}, +{ "lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}}, +{ "l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}}, -{"lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}}, -{"lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}}, +{ "lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}}, +{ "lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}}, -{"lbz", OP(34), OP_MASK, COM, {RT, D, RA0}}, +{ "lbz", OP(34), OP_MASK, COM, {RT, D, RA0}}, -{"lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}}, +{ "lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}}, -{"stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}}, -{"st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}}, +{ "stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}}, +{ "st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}}, -{"stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}}, -{"stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}}, +{ "stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}}, +{ "stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}}, -{"stb", OP(38), OP_MASK, COM, {RS, D, RA0}}, +{ "stb", OP(38), OP_MASK, COM, {RS, D, RA0}}, -{"stbu", OP(39), OP_MASK, COM, {RS, D, RAS}}, +{ "stbu", OP(39), OP_MASK, COM, {RS, D, RAS}}, -{"lhz", OP(40), OP_MASK, COM, {RT, D, RA0}}, +{ "lhz", OP(40), OP_MASK, COM, {RT, D, RA0}}, -{"lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}}, +{ "lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}}, -{"lha", OP(42), OP_MASK, COM, {RT, D, RA0}}, +{ "lha", OP(42), OP_MASK, COM, {RT, D, RA0}}, -{"lhau", OP(43), OP_MASK, COM, {RT, D, RAL}}, +{ "lhau", OP(43), OP_MASK, COM, {RT, D, RAL}}, -{"sth", OP(44), OP_MASK, COM, {RS, D, RA0}}, +{ "sth", OP(44), OP_MASK, COM, {RS, D, RA0}}, -{"sthu", OP(45), OP_MASK, COM, {RS, D, RAS}}, +{ "sthu", OP(45), OP_MASK, COM, {RS, D, RAS}}, -{"lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}}, -{"lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}}, +{ "lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}}, +{ "lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}}, -{"stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}}, -{"stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}}, +{ "stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}}, +{ "stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}}, -{"lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}}, +{ "lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}}, -{"lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}}, +{ "lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}}, -{"lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}}, +{ "lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}}, -{"lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}}, +{ "lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}}, -{"stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}}, +{ "stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}}, -{"stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}}, +{ "stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}}, -{"stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}}, +{ "stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}}, -{"stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}}, +{ "stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}}, -{"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}}, +{ "lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}}, -{"lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}}, +{ "lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}}, -{"psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, +{ "psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, -{"lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}}, +{ "lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}}, -{"psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, +{ "psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, -{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}}, +{ "lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}}, -{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}}, -{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}}, -{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}}, -{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}}, -{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}}, -{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}}, -{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}}, -{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}}, -{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}}, -{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}}, -{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}}, -{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}}, -{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}}, -{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}}, +{ "lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}}, +{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}}, +{ "lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}}, +{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}}, +{ "lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}}, +{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}}, +{ "lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}}, +{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}}, +{ "stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}}, +{ "stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}}, +{ "sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}}, +{ "sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}}, +{ "stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}}, +{ "stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}}, -{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}}, -{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}}, -{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}}, +{ "ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}}, +{ "ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}}, +{ "lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}}, -{"dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, -{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, +{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, +{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, -{"fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, +{ "fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, -{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}}, -{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}}, +{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}}, +{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}}, -{"fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, -{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, +{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, +{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, -{"fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}}, -{"fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}}, +{ "fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}}, +{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}}, -{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, -{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, +{ "frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, +{ "frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, -{"fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, -{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, +{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, +{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, -{"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}}, -{"dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}}, -{"dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}}, -{"dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}}, +{ "dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}}, +{ "dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}}, -{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}}, -{"dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}}, -{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}}, -{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}}, -{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, -{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, +{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, +{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, -{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}}, -{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}}, -{"dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}}, -{"dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}}, -{"drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}}, -{"drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}}, +{ "drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}}, +{ "drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}}, -{"denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}}, -{"denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}}, +{ "denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}}, +{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}}, -{"diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}}, +{ "stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}}, -{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, +{ "psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, -{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, -{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, -{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}}, -{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}}, -{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, +{ "xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, +{ "xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, +{ "xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}}, +{ "xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}}, +{ "xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, -{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, +{ "psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, -{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}}, +{ "stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}}, -{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}}, +{ "stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}}, -{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}}, -{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}}, -{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}}, -{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}}, -{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}}, -{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}}, -{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}}, -{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}}, -{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}}, -{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}}, -{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}}, -{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}}, +{ "lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}}, +{ "ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}}, +{ "lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}}, +{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}}, +{ "lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}}, +{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}}, +{ "stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}}, +{ "stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}}, +{ "stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}}, +{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}}, +{ "stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}}, +{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}}, -{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}}, -{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}}, -{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}}, +{ "std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}}, +{ "stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}}, +{ "stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}}, -{"fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, +{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, -{"daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}}, -{"frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}}, +{ "frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}}, +{ "frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}}, -{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}}, -{"fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}}, -{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}}, -{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}}, +{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}}, +{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}}, +{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}}, +{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}}, -{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}}, -{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}}, -{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}}, -{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}}, +{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}}, +{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}}, +{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}}, +{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}}, -{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, -{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, +{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, +{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, -{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, -{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, +{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, +{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, -{"fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, +{ "fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, -{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, -{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, +{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, +{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, -{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, -{"fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, -{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, -{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, +{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, +{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, +{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, +{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, -{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, -{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, +{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, +{ "frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, -{"fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, -{"fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, +{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, +{ "fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, -{"fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, +{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, -{"dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, +{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, -{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}}, -{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}}, +{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}}, +{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}}, -{"fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}}, -{"fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}}, +{ "fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}}, +{ "fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}}, -{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, +{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, -{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, -{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, +{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, +{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, -{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}}, -{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}}, +{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}}, +{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}}, -{"fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}}, -{"fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}}, +{ "fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}}, +{ "fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}}, -{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, +{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, -{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}}, -{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, -{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, +{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, +{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, -{"fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}}, -{"fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}}, +{ "fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}}, +{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}}, -{"dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}}, -{"dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}}, -{"dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}}, +{ "dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}}, +{ "dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}}, -{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, +{ "drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, -{"dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}}, -{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}}, -{"fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}}, -{"fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}}, +{ "fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}}, +{ "fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}}, -{"dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}}, -{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}}, -{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, -{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, +{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, +{ "ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, -{"dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}}, -{"dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}}, -{"frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}}, -{"frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}}, -{"friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}}, -{"friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}}, -{"frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}}, -{"frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}}, -{"frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}}, -{"frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}}, +{ "friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}}, +{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}}, +{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}}, -{"dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}}, -{"mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}}, +{ "mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}}, +{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}}, -{"dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}}, -{"dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}}, +{ "dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}}, -{"mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, -{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, +{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, +{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, -{"drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}}, -{"drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}}, +{ "drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}}, +{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}}, -{"dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}}, -{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}}, +{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}}, +{ "dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}}, -{"fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}}, -{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}}, -{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}}, -{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}}, -{"denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}}, -{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}}, +{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}}, +{ "denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}}, -{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}}, -{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}}, +{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}}, -{"diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, -{"diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, +{ "diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, }; @@ -5160,45 +5160,45 @@ const int powerpc_num_opcodes = support extracting the whole word (32 bits in this case). */ const struct powerpc_macro powerpc_macros[] = { -{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, -{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, -{"extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)"}, -{"extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)"}, -{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, -{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, -{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, -{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, -{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, -{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, -{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, -{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, -{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, -{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, -{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, -{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, +{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, +{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, +{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, +{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, +{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, +{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, +{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, +{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, +{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, +{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, +{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, +{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, +{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, +{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, +{ "clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, +{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, -{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, -{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, -{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, -{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, -{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, -{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, -{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, -{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, -{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, -{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, -{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, -{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, -{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, -{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, -{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, -{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, -{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, -{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, -{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, -{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, +{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, +{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, +{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, +{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, +{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, +{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, +{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, +{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, +{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, +{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, +{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, +{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, +{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, +{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, +{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, +{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, +{ "clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, +{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, }; const int powerpc_num_macros = diff --git a/libr/asm/arch/ppc/libps/libps.c b/libr/asm/arch/ppc/libps/libps.c index 5dea4321cd..e9f3a48d98 100644 --- a/libr/asm/arch/ppc/libps/libps.c +++ b/libr/asm/arch/ppc/libps/libps.c @@ -21,76 +21,76 @@ ps_operand_t ps_operands_array[] = { ps_opcode_t ps_opcodes_array[] = { - { psq_lx, "psq_lx", OPM (4, 6), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load Indexed"}, - { psq_stx, "psq_stx", OPM (4, 7), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store Indexed"}, - { psq_lux, "psq_lux", OPM (4, 38), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load with update Indexed"}, - { psq_stux, "psq_stux", OPM (4, 39), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store with update Indexed"}, + { psq_lx, "psq_lx", OPM (4, 6), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load Indexed" }, + { psq_stx, "psq_stx", OPM (4, 7), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store Indexed" }, + { psq_lux, "psq_lux", OPM (4, 38), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load with update Indexed" }, + { psq_stux, "psq_stux", OPM (4, 39), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store with update Indexed" }, - { psq_l, "psq_l", OP (56), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load"}, - { psq_lu, "psq_lu", OP (57), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load with Update"}, - { psq_st, "psq_st", OP (60), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store"}, - { psq_stu, "psq_stu", OP (61), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store with update"}, + { psq_l, "psq_l", OP (56), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load" }, + { psq_lu, "psq_lu", OP (57), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load with Update" }, + { psq_st, "psq_st", OP (60), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store" }, + { psq_stu, "psq_stu", OP (61), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store with update" }, - { ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"}, - { ps_div_dot, "ps_div.", OPSC (4, 18, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"}, - { ps_sub, "ps_sub", OPSC (4, 20, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"}, - { ps_sub_dot, "ps_sub.", OPSC (4, 20, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"}, - { ps_add, "ps_add", OPSC (4, 21, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Add"}, - { ps_add_dot, "ps_add.", OPSC (4, 21, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Add"}, - { ps_sel, "ps_sel", OPSC (4, 23, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select"}, - { ps_sel_dot, "ps_sel.", OPSC (4, 23, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select"}, - { ps_res, "ps_res", OPSC (4, 24, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate"}, - { ps_res_dot, "ps_res.", OPSC (4, 24, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate"}, - { ps_mul, "ps_mul", OPSC (4, 25, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply"}, - { ps_mul_dot, "ps_mul.", OPSC (4, 25, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply"}, - { ps_rsqrte, "ps_rsqrte", OPSC (4, 26, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate"}, - { ps_rsqrte_dot, "ps_rsqrte.", OPSC (4, 26, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate"}, - { ps_msub, "ps_msub", OPSC (4, 28, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract"}, - { ps_msub_dot, "ps_msub.", OPSC (4, 28, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract"}, - { ps_madd, "ps_madd", OPSC (4, 29, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add"}, - { ps_madd_dot, "ps_madd.", OPSC (4, 29, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add"}, - { ps_nmsub, "ps_nmsub", OPSC (4, 30, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract"}, - { ps_nmsub_dot, "ps_nmsub.", OPSC (4, 30, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract"}, - { ps_nmadd, "ps_nmadd", OPSC (4, 31, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add"}, - { ps_nmadd_dot, "ps_nmadd.", OPSC (4, 31, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add"}, + { ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide" }, + { ps_div_dot, "ps_div.", OPSC (4, 18, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide" }, + { ps_sub, "ps_sub", OPSC (4, 20, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract" }, + { ps_sub_dot, "ps_sub.", OPSC (4, 20, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract" }, + { ps_add, "ps_add", OPSC (4, 21, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Add" }, + { ps_add_dot, "ps_add.", OPSC (4, 21, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Add" }, + { ps_sel, "ps_sel", OPSC (4, 23, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select" }, + { ps_sel_dot, "ps_sel.", OPSC (4, 23, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select" }, + { ps_res, "ps_res", OPSC (4, 24, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate" }, + { ps_res_dot, "ps_res.", OPSC (4, 24, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate" }, + { ps_mul, "ps_mul", OPSC (4, 25, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply" }, + { ps_mul_dot, "ps_mul.", OPSC (4, 25, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply" }, + { ps_rsqrte, "ps_rsqrte", OPSC (4, 26, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate" }, + { ps_rsqrte_dot, "ps_rsqrte.", OPSC (4, 26, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate" }, + { ps_msub, "ps_msub", OPSC (4, 28, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract" }, + { ps_msub_dot, "ps_msub.", OPSC (4, 28, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract" }, + { ps_madd, "ps_madd", OPSC (4, 29, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add" }, + { ps_madd_dot, "ps_madd.", OPSC (4, 29, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add" }, + { ps_nmsub, "ps_nmsub", OPSC (4, 30, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract" }, + { ps_nmsub_dot, "ps_nmsub.", OPSC (4, 30, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract" }, + { ps_nmadd, "ps_nmadd", OPSC (4, 31, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add" }, + { ps_nmadd_dot, "ps_nmadd.", OPSC (4, 31, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add" }, - { ps_neg, "ps_neg", OPLC (4, 40, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negate"}, - { ps_neg_dot, "ps_neg.", OPLC (4, 40, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negate"}, - { ps_mr, "ps_mr", OPLC (4, 72, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Move Register"}, - { ps_mr_dot, "ps_mr.", OPLC (4, 72, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Move Register"}, - { ps_nabs, "ps_nabs", OPLC (4, 136, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value"}, - { ps_nabs_dot, "ps_nabs.", OPLC (4, 136, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value"}, - { ps_abs, "ps_abs", OPLC (4, 264, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Absolute Value"}, - { ps_abs_dot, "ps_abs.", OPLC (4, 264, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Absolute Value"}, + { ps_neg, "ps_neg", OPLC (4, 40, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negate" }, + { ps_neg_dot, "ps_neg.", OPLC (4, 40, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negate" }, + { ps_mr, "ps_mr", OPLC (4, 72, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Move Register" }, + { ps_mr_dot, "ps_mr.", OPLC (4, 72, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Move Register" }, + { ps_nabs, "ps_nabs", OPLC (4, 136, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value" }, + { ps_nabs_dot, "ps_nabs.", OPLC (4, 136, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value" }, + { ps_abs, "ps_abs", OPLC (4, 264, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Absolute Value" }, + { ps_abs_dot, "ps_abs.", OPLC (4, 264, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Absolute Value" }, - { ps_sum0, "ps_sum0", OPSC (4, 10, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high"}, - { ps_sum0_dot, "ps_sum0.", OPSC (4, 10, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high"}, - { ps_sum1, "ps_sum1", OPSC (4, 11, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low"}, - { ps_sum1_dot, "ps_sum1.", OPSC (4, 11, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low"}, - { ps_muls0, "ps_muls0", OPSC (4, 12, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high"}, - { ps_muls0_dot, "ps_muls0.", OPSC (4, 12, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high"}, - { ps_muls1, "ps_muls1", OPSC (4, 13, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low"}, - { ps_muls1_dot, "ps_muls1.", OPSC (4, 13, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low"}, - { ps_madds0, "ps_madds0", OPSC (4, 14, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high"}, - { ps_madds0_dot, "ps_madds0.", OPSC (4, 14, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high"}, - { ps_madds1, "ps_madds1", OPSC (4, 15, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low"}, - { ps_madds1_dot, "ps_madds1.", OPSC (4, 15, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low"}, + { ps_sum0, "ps_sum0", OPSC (4, 10, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high" }, + { ps_sum0_dot, "ps_sum0.", OPSC (4, 10, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high" }, + { ps_sum1, "ps_sum1", OPSC (4, 11, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low" }, + { ps_sum1_dot, "ps_sum1.", OPSC (4, 11, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low" }, + { ps_muls0, "ps_muls0", OPSC (4, 12, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high" }, + { ps_muls0_dot, "ps_muls0.", OPSC (4, 12, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high" }, + { ps_muls1, "ps_muls1", OPSC (4, 13, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low" }, + { ps_muls1_dot, "ps_muls1.", OPSC (4, 13, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low" }, + { ps_madds0, "ps_madds0", OPSC (4, 14, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high" }, + { ps_madds0_dot, "ps_madds0.", OPSC (4, 14, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high" }, + { ps_madds1, "ps_madds1", OPSC (4, 15, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low" }, + { ps_madds1_dot, "ps_madds1.", OPSC (4, 15, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low" }, - { ps_cmpu0, "ps_cmpu0", OPL (4, 0), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered High"}, - { ps_cmpo0, "ps_cmpo0", OPL (4, 32), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered High"}, - { ps_cmpu1, "ps_cmpu1", OPL (4, 64), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered Low"}, - { ps_cmpo1, "ps_cmpo1", OPL (4, 96), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered Low"}, + { ps_cmpu0, "ps_cmpu0", OPL (4, 0), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered High" }, + { ps_cmpo0, "ps_cmpo0", OPL (4, 32), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered High" }, + { ps_cmpu1, "ps_cmpu1", OPL (4, 64), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered Low" }, + { ps_cmpo1, "ps_cmpo1", OPL (4, 96), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered Low" }, - { ps_merge00, "ps_merge00", OPLC (4, 528, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high"}, - { ps_merge00_dot, "ps_merge00.", OPLC (4, 528, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high"}, - { ps_merge01, "ps_merge01", OPLC (4, 560, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct"}, - { ps_merge01_dot, "ps_merge01.", OPLC (4, 560, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct"}, - { ps_merge10, "ps_merge10", OPLC (4, 592, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped"}, - { ps_merge10_dot, "ps_merge10.", OPLC (4, 592, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped"}, - { ps_merge11, "ps_merge11", OPLC (4, 624, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low"}, - { ps_merge11_dot, "ps_merge11.", OPLC (4, 624, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low"}, + { ps_merge00, "ps_merge00", OPLC (4, 528, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high" }, + { ps_merge00_dot, "ps_merge00.", OPLC (4, 528, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high" }, + { ps_merge01, "ps_merge01", OPLC (4, 560, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct" }, + { ps_merge01_dot, "ps_merge01.", OPLC (4, 560, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct" }, + { ps_merge10, "ps_merge10", OPLC (4, 592, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped" }, + { ps_merge10_dot, "ps_merge10.", OPLC (4, 592, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped" }, + { ps_merge11, "ps_merge11", OPLC (4, 624, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low" }, + { ps_merge11_dot, "ps_merge11.", OPLC (4, 624, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low" }, - { ps_dcbz_l, "dcbz_l", OPL (4, 1014), OPL_MASK, { OP_RA, OP_RB}, "Data Cache Block Set to Zero Locked"}, + { ps_dcbz_l, "dcbz_l", OPL (4, 1014), OPL_MASK, { OP_RA, OP_RB}, "Data Cache Block Set to Zero Locked" }, }; diff --git a/libr/asm/arch/riscv/riscv-opc.c b/libr/asm/arch/riscv/riscv-opc.c index cf750b348c..63a6b18b02 100644 --- a/libr/asm/arch/riscv/riscv-opc.c +++ b/libr/asm/arch/riscv/riscv-opc.c @@ -106,563 +106,563 @@ static int match_c_lui(const struct riscv_opcode *op, insn_t insn) { static const struct riscv_opcode riscv_builtin_opcodes[] = { /* name, isa, operands, match, mask, match_func, pinfo. */ -{"illegal", "C", "", 0, 0xffffU, match_opcode, 0 }, -{"unimp", "I", "", MATCH_CSRRW | (((unsigned)CSR_CYCLE) << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ -{"ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, -{"ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, -{"sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, -{"sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, -{"ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS }, -{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, -{"jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS }, -{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, -{"jr", "I", "o(s)", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, -{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, -{"jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS }, -{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, -{"jalr", "I", "o(s)", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, -{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, -{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS }, -{"jalr", "I", "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, 0 }, -{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 }, -{"j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS }, -{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, -{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 }, -{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, -{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, -{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, -{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, -{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, -{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, -{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, -{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, -{"lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, -{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, -{"li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, -{"li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, -{"li", "C", "d,0", MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, -{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ -{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, -{"mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, -{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, -{"move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, -{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, -{"andi", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, -{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, -{"and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, -{"and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, -{"and", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, -{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, -{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, -{"beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS }, -{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS }, -{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 }, -{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS }, -{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS }, -{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS }, -{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS }, -{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 }, -{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 }, -{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS }, -{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS }, -{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 }, -{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 }, -{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS }, -{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS }, -{"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, -{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, -{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, -{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, -{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, -{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, -{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, -{"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, -{"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, -{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, -{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, -{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, -{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, -{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, -{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, -{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, -{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, -{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ -{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, -{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, -{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, -{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, -{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, -{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, -{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, -{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, -{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, -{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, -{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, -{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, -{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, -{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, -{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, -{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, -{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, -{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 }, -{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, -{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 }, -{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, -{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 }, -{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, -{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 }, -{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, -{"lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS }, -{"lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS }, -{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 }, -{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, -{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS }, -{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, -{"or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, -{"or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, -{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, -{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, -{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, -{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, -{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, -{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, -{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, -{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, -{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, -{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, -{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, -{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, -{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, -{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, -{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, -{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 }, -{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, -{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 }, -{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, -{"sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS }, -{"sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS }, -{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 }, -{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, -{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, -{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, -{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, -{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, -{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, -{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, -{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, -{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, -{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, -{"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, -{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, -{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, -{"xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, -{"xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, -{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, -{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, -{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 }, -{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, -{"ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS }, -{"ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS }, -{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 }, -{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, -{"sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS }, -{"sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS }, -{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 }, -{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, -{"sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, -{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS }, -{"addiw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, -{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, -{"addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, -{"addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, -{"addw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, -{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, -{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, -{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ -{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, -{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, -{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, -{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, -{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, -{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, -{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, -{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, -{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, -{"subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, -{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, +{ "illegal", "C", "", 0, 0xffffU, match_opcode, 0 }, +{ "unimp", "I", "", MATCH_CSRRW | (((unsigned)CSR_CYCLE) << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ +{ "ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{ "ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, +{ "sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{ "sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, +{ "ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS }, +{ "ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS }, +{ "jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "jr", "I", "o(s)", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{ "jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{ "jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS }, +{ "jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "jalr", "I", "o(s)", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{ "jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{ "jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "jalr", "I", "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, 0 }, +{ "jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 }, +{ "j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS }, +{ "j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{ "jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 }, +{ "jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, +{ "jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{ "call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{ "call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, +{ "tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{ "jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, +{ "nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{ "nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{ "lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, +{ "li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{ "li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{ "li", "C", "d,0", MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{ "li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ +{ "li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, +{ "mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{ "mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{ "move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "andi", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{ "andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, +{ "and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{ "and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{ "and", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{ "and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, +{ "and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, +{ "beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS }, +{ "beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS }, +{ "beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 }, +{ "blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS }, +{ "bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS }, +{ "ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS }, +{ "bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS }, +{ "bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 }, +{ "bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 }, +{ "bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{ "bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{ "blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 }, +{ "bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 }, +{ "bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS }, +{ "bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS }, +{ "bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, +{ "bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, +{ "bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, +{ "addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{ "addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{ "addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{ "addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, +{ "add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{ "add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{ "add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{ "add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{ "add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{ "add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{ "add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{ "add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, +{ "la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, +{ "lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, +{ "la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, +{ "la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, +{ "neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{ "slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{ "slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, +{ "sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{ "sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, +{ "sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, +{ "srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{ "srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, +{ "srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{ "srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, +{ "srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, +{ "srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{ "srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, +{ "sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{ "sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, +{ "sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, +{ "sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, +{ "sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, +{ "lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 }, +{ "lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, +{ "lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 }, +{ "lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, +{ "lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 }, +{ "lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, +{ "lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 }, +{ "lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, +{ "lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS }, +{ "lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS }, +{ "lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 }, +{ "lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, +{ "not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, +{ "or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{ "or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{ "or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, +{ "or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, +{ "auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, +{ "seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, +{ "sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{ "sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{ "slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, +{ "slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, +{ "slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, +{ "sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, +{ "sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, +{ "sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, +{ "sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, +{ "sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, +{ "sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 }, +{ "sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, +{ "sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 }, +{ "sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, +{ "sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS }, +{ "sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS }, +{ "sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 }, +{ "sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, +{ "fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, +{ "fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, +{ "rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, +{ "rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, +{ "rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS }, +{ "rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, +{ "rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, +{ "rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, +{ "ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{ "scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{ "xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, +{ "xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{ "xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{ "xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, +{ "xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, +{ "lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 }, +{ "lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, +{ "ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS }, +{ "ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS }, +{ "ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 }, +{ "ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, +{ "sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS }, +{ "sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS }, +{ "sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 }, +{ "sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, +{ "sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{ "sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS }, +{ "addiw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{ "addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, +{ "addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{ "addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{ "addw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{ "addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, +{ "addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, +{ "negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{ "slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, +{ "sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, +{ "sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, +{ "srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, +{ "srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, +{ "srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, +{ "sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, +{ "sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, +{ "sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, +{ "subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, +{ "subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, /* Atomic memory operation instruction subset */ -{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, -{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, -{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, -{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, -{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, -{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, -{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, -{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, -{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, -{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, -{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, -{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, -{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, -{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, -{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, -{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, -{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, -{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, -{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, -{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, -{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, -{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, -{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, -{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, -{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, -{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, -{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, -{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, -{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, -{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, -{"lr.w.aqrl", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, -{"sc.w.aqrl", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, -{"amoadd.w.aqrl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, -{"amoswap.w.aqrl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, -{"amoand.w.aqrl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, -{"amoor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, -{"amoxor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, -{"amomax.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, -{"amomin.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, -{"amominu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, -{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, -{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, -{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, -{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, -{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, -{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, -{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, -{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, -{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, -{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, -{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, -{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, -{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, -{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, -{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, -{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, -{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, -{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, -{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, -{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, -{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, -{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, -{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, -{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, -{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, -{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, -{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, -{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, -{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, -{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, -{"lr.d.aqrl", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, -{"sc.d.aqrl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, -{"amoadd.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, -{"amoswap.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, -{"amoand.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, -{"amoor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, -{"amoxor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, -{"amomax.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, -{"amomaxu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, -{"amomin.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, -{"amominu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{ "lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{ "sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{ "amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{ "amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{ "amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{ "amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{ "lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{ "sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{ "amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{ "amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{ "amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{ "amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{ "lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{ "sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{ "amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{ "amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{ "amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{ "amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{ "lr.w.aqrl", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{ "sc.w.aqrl", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.w.aqrl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.w.aqrl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{ "amoand.w.aqrl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{ "amoor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.w.aqrl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{ "amomax.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{ "amomin.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{ "amominu.w.aqrl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{ "lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{ "sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{ "amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{ "amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{ "amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{ "amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{ "lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{ "sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{ "amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{ "amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{ "amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{ "amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{ "lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{ "sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{ "amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{ "amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{ "amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{ "amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{ "lr.d.aqrl", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{ "sc.d.aqrl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{ "amoadd.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{ "amoswap.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{ "amoand.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{ "amoor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amoxor.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{ "amomax.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{ "amomaxu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{ "amomin.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{ "amominu.d.aqrl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, /* Multiply/Divide instruction subset */ -{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, -{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, -{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, -{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, -{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, -{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, -{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, -{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, -{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, -{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, -{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, -{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, -{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, +{ "mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +{ "mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, +{ "mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, +{ "mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, +{ "div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, +{ "divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, +{ "rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, +{ "remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, +{ "mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, +{ "divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, +{ "divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, +{ "remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, +{ "remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, /* Single-precision floating-point instruction subset */ -{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, -{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, -{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, -{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, -{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, -{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, -{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, -{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, -{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, -{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, -{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, -{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, -{"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, -{"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, -{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, -{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, -{"fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS }, -{"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, -{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, -{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, -{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, -{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, -{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, -{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, -{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 }, -{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, -{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 }, -{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, -{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 }, -{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, -{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 }, -{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, -{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 }, -{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, -{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, -{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, -{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 }, -{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, -{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 }, -{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, -{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 }, -{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, -{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 }, -{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, -{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 }, -{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, -{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 }, -{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, -{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, -{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, -{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, -{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, -{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, -{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, -{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, -{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, -{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, -{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, -{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 }, -{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, -{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 }, -{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, -{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, -{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, -{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, -{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, +{ "frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{ "fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{ "fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{ "frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{ "fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{ "fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{ "frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, +{ "fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, +{ "fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, +{ "frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, +{ "fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, +{ "fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, +{ "flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, +{ "flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, +{ "flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, +{ "flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, +{ "fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS }, +{ "fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, +{ "fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, +{ "fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, +{ "fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, +{ "fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, +{ "fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, +{ "fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, +{ "fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, +{ "fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 }, +{ "fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, +{ "fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 }, +{ "fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, +{ "fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 }, +{ "fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, +{ "fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 }, +{ "fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, +{ "fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 }, +{ "fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, +{ "fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, +{ "fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, +{ "fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 }, +{ "fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, +{ "fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 }, +{ "fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, +{ "fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 }, +{ "fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, +{ "fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 }, +{ "fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, +{ "fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, +{ "fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, +{ "fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, +{ "fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, +{ "fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, +{ "feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, +{ "flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{ "fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{ "fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{ "fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{ "fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, +{ "fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, +{ "fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, +{ "fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, /* Double-precision floating-point instruction subset */ -{"fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS }, -{"fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS }, -{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 }, -{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, -{"fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS }, -{"fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS }, -{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 }, -{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, -{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 }, -{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 }, -{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 }, -{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 }, -{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 }, -{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 }, -{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 }, -{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 }, -{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 }, -{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, -{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{ "fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS }, +{ "fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS }, +{ "fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 }, +{ "fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, +{ "fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS }, +{ "fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS }, +{ "fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 }, +{ "fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, +{ "fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{ "fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{ "fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{ "fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 }, +{ "fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{ "fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 }, +{ "fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{ "fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 }, +{ "fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{ "fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 }, +{ "fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{ "fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 }, +{ "fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{ "fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{ "fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{ "fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 }, +{ "fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{ "fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 }, +{ "fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{ "fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 }, +{ "fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{ "fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 }, +{ "fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{ "fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{ "fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{ "fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 }, +{ "fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 }, +{ "fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{ "fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{ "feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{ "flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{ "fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{ "fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{ "fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{ "fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, +{ "fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, +{ "fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{ "fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{ "fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{ "fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, /* Quad-precision floating-point instruction subset */ -{"flq", "Q", "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, 0 }, -{"flq", "Q", "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, -{"fsq", "Q", "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, 0 }, -{"fsq", "Q", "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, -{"fmv.q", "Q", "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", "Q", "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", "Q", "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", "Q", "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", "Q", "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", "Q", "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", "Q", "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 }, -{"fadd.q", "Q", "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", "Q", "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 }, -{"fsub.q", "Q", "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", "Q", "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 }, -{"fmul.q", "Q", "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 }, -{"fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", "Q", "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 }, -{"fsqrt.q", "Q", "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", "Q", "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", "Q", "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", "Q", "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 }, -{"fmadd.q", "Q", "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", "Q", "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 }, -{"fnmadd.q", "Q", "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", "Q", "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 }, -{"fmsub.q", "Q", "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", "Q", "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 }, -{"fnmsub.q", "Q", "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", "Q", "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", "Q", "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", "Q", "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", "Q", "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", "Q", "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", "Q", "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", "Q", "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", "Q", "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", "Q", "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", "Q", "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", "Q", "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", "Q", "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", "Q", "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", "Q", "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", "Q", "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", "Q", "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", "Q", "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", "Q", "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fmv.x.q", "64Q", "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, -{"fmv.q.x", "64Q", "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, -{"fcvt.l.q", "64Q", "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", "64Q", "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", "64Q", "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", "64Q", "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", "64Q", "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", "64Q", "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", "64Q", "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", "64Q", "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{ "flq", "Q", "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, 0 }, +{ "flq", "Q", "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, +{ "fsq", "Q", "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, 0 }, +{ "fsq", "Q", "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO }, +{ "fmv.q", "Q", "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fneg.q", "Q", "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fabs.q", "Q", "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, +{ "fsgnj.q", "Q", "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, +{ "fsgnjn.q", "Q", "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, +{ "fsgnjx.q", "Q", "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, +{ "fadd.q", "Q", "D,S,T", MATCH_FADD_Q | MASK_RM, MASK_FADD_Q | MASK_RM, match_opcode, 0 }, +{ "fadd.q", "Q", "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{ "fsub.q", "Q", "D,S,T", MATCH_FSUB_Q | MASK_RM, MASK_FSUB_Q | MASK_RM, match_opcode, 0 }, +{ "fsub.q", "Q", "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{ "fmul.q", "Q", "D,S,T", MATCH_FMUL_Q | MASK_RM, MASK_FMUL_Q | MASK_RM, match_opcode, 0 }, +{ "fmul.q", "Q", "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{ "fdiv.q", "Q", "D,S,T", MATCH_FDIV_Q | MASK_RM, MASK_FDIV_Q | MASK_RM, match_opcode, 0 }, +{ "fdiv.q", "Q", "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{ "fsqrt.q", "Q", "D,S", MATCH_FSQRT_Q | MASK_RM, MASK_FSQRT_Q | MASK_RM, match_opcode, 0 }, +{ "fsqrt.q", "Q", "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{ "fmin.q", "Q", "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, +{ "fmax.q", "Q", "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, +{ "fmadd.q", "Q", "D,S,T,R", MATCH_FMADD_Q | MASK_RM, MASK_FMADD_Q | MASK_RM, match_opcode, 0 }, +{ "fmadd.q", "Q", "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{ "fnmadd.q", "Q", "D,S,T,R", MATCH_FNMADD_Q | MASK_RM, MASK_FNMADD_Q | MASK_RM, match_opcode, 0 }, +{ "fnmadd.q", "Q", "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{ "fmsub.q", "Q", "D,S,T,R", MATCH_FMSUB_Q | MASK_RM, MASK_FMSUB_Q | MASK_RM, match_opcode, 0 }, +{ "fmsub.q", "Q", "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{ "fnmsub.q", "Q", "D,S,T,R", MATCH_FNMSUB_Q | MASK_RM, MASK_FNMSUB_Q | MASK_RM, match_opcode, 0 }, +{ "fnmsub.q", "Q", "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{ "fcvt.w.q", "Q", "d,S", MATCH_FCVT_W_Q | MASK_RM, MASK_FCVT_W_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.w.q", "Q", "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{ "fcvt.wu.q", "Q", "d,S", MATCH_FCVT_WU_Q | MASK_RM, MASK_FCVT_WU_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.wu.q", "Q", "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{ "fcvt.q.w", "Q", "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W | MASK_RM, match_opcode, 0 }, +{ "fcvt.q.wu", "Q", "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU | MASK_RM, match_opcode, 0 }, +{ "fcvt.q.s", "Q", "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S | MASK_RM, match_opcode, 0 }, +{ "fcvt.q.d", "Q", "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.q", "Q", "D,S", MATCH_FCVT_S_Q | MASK_RM, MASK_FCVT_S_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.s.q", "Q", "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{ "fcvt.d.q", "Q", "D,S", MATCH_FCVT_D_Q | MASK_RM, MASK_FCVT_D_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.d.q", "Q", "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{ "fclass.q", "Q", "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, +{ "feq.q", "Q", "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, +{ "flt.q", "Q", "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{ "fle.q", "Q", "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{ "fgt.q", "Q", "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, +{ "fge.q", "Q", "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{ "fmv.x.q", "64Q", "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 }, +{ "fmv.q.x", "64Q", "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 }, +{ "fcvt.l.q", "64Q", "d,S", MATCH_FCVT_L_Q | MASK_RM, MASK_FCVT_L_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.l.q", "64Q", "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{ "fcvt.lu.q", "64Q", "d,S", MATCH_FCVT_LU_Q | MASK_RM, MASK_FCVT_LU_Q | MASK_RM, match_opcode, 0 }, +{ "fcvt.lu.q", "64Q", "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{ "fcvt.q.l", "64Q", "D,s", MATCH_FCVT_Q_L | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.q.l", "64Q", "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, +{ "fcvt.q.lu", "64Q", "D,s", MATCH_FCVT_Q_LU | MASK_RM, MASK_FCVT_Q_L | MASK_RM, match_opcode, 0 }, +{ "fcvt.q.lu", "64Q", "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ -{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, -{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 }, -{"c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 }, -{"c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 }, -{"c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 }, -{"c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 }, -{"c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 }, -{"c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, -{"c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 }, -{"c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 }, -{"c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 }, -{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, -{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, -{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, -{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, -{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, -{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, -{"c.addi", "C", "d,Cj,CU", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 }, -{"c.add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, -{"c.sub", "C", "Cs,Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, -{"c.and", "C", "Cs,Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, -{"c.or", "C", "Cs,Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, -{"c.xor", "C", "Cs,Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, -{"c.slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, -{"c.srli", "C", "Cs,Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, -{"c.srai", "C", "Cs,Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, -{"c.andi", "C", "Cs,Cj,Cs", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, -{"c.addiw", "64C", "d,Cj,CU", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, -{"c.addw", "64C", "Cs,Ct,Cs", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, -{"c.subw", "64C", "Cs,Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, -{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, -{"c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 }, -{"c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 }, -{"c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 }, -{"c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 }, -{"c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 }, -{"c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 }, -{"c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 }, -{"c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 }, -{"c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 }, -{"c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 }, -{"c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 }, +{ "c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, +{ "c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 }, +{ "c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 }, +{ "c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 }, +{ "c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 }, +{ "c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 }, +{ "c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 }, +{ "c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, +{ "c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 }, +{ "c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 }, +{ "c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 }, +{ "c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, +{ "c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, +{ "c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, +{ "c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, +{ "c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, +{ "c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +{ "c.addi", "C", "d,Cj,CU", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 }, +{ "c.add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, +{ "c.sub", "C", "Cs,Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, +{ "c.and", "C", "Cs,Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, +{ "c.or", "C", "Cs,Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, +{ "c.xor", "C", "Cs,Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, +{ "c.slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, +{ "c.srli", "C", "Cs,Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, +{ "c.srai", "C", "Cs,Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, +{ "c.andi", "C", "Cs,Cj,Cs", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{ "c.addiw", "64C", "d,Cj,CU", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{ "c.addw", "64C", "Cs,Ct,Cs", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, +{ "c.subw", "64C", "Cs,Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, +{ "c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, +{ "c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 }, +{ "c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 }, +{ "c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 }, +{ "c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 }, +{ "c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 }, +{ "c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 }, +{ "c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 }, +{ "c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 }, +{ "c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 }, +{ "c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 }, +{ "c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 }, /* Supervisor instructions */ -{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS }, -{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, -{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, -{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, -{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, -{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, -{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, -{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, -{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, -{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, -{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, -{"uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 }, -{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, -{"hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, -{"mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, -{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, -{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, -{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, -{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, +{ "csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS }, +{ "csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS }, +{ "csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{ "csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{ "csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{ "csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, +{ "csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, +{ "csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, +{ "csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, +{ "csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, +{ "csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, +{ "uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 }, +{ "sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, +{ "hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, +{ "mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, +{ "dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +{ "sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, +{ "sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{ "wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, }; #define RISCV_NUM_OPCODES ((sizeof riscv_builtin_opcodes) / (sizeof (riscv_builtin_opcodes[0]))) diff --git a/libr/asm/arch/sh/gnu/sh-opc.h b/libr/asm/arch/sh/gnu/sh-opc.h index d0a3d44043..295c8b61ba 100644 --- a/libr/asm/arch/sh/gnu/sh-opc.h +++ b/libr/asm/arch/sh/gnu/sh-opc.h @@ -112,461 +112,461 @@ typedef struct { sh_opcode_info sh_table[] = { -/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, +/* 0111nnnni8*1.... add #, */{ "add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, -/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, +/* 0011nnnnmmmm1100 add , */{ "add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, -/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, +/* 0011nnnnmmmm1110 addc ,*/{ "addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, -/* 0011nnnnmmmm1111 addv ,*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, +/* 0011nnnnmmmm1111 addv ,*/{ "addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, -/* 11001001i8*1.... and #,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, +/* 11001001i8*1.... and #,R0 */{ "and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, -/* 0010nnnnmmmm1001 and , */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, +/* 0010nnnnmmmm1001 and , */{ "and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, -/* 11001101i8*1.... and.b #,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, +/* 11001101i8*1.... and.b #,@(R0,GBR)*/{ "and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, -/* 1010i12......... bra */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}}, +/* 1010i12......... bra */{ "bra",{A_BDISP12},{HEX_A,BRANCH_12}}, -/* 1011i12......... bsr */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, +/* 1011i12......... bsr */{ "bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, -/* 10001001i8p1.... bt */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, +/* 10001001i8p1.... bt */{ "bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, -/* 10001011i8p1.... bf */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, +/* 10001011i8p1.... bf */{ "bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, -/* 10001101i8p1.... bt.s */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, +/* 10001101i8p1.... bt.s */{ "bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, -/* 10001101i8p1.... bt/s */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, +/* 10001101i8p1.... bt/s */{ "bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, -/* 10001111i8p1.... bf.s */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, +/* 10001111i8p1.... bf.s */{ "bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, -/* 10001111i8p1.... bf/s */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, +/* 10001111i8p1.... bf/s */{ "bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, -/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}}, +/* 0000000000101000 clrmac */{ "clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}}, -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}, +/* 0000000001001000 clrs */{ "clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}, -/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}, +/* 0000000000001000 clrt */{ "clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}, -/* 10001000i8*1.... cmp/eq #,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, +/* 10001000i8*1.... cmp/eq #,R0 */{ "cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, -/* 0011nnnnmmmm0000 cmp/eq ,*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, +/* 0011nnnnmmmm0000 cmp/eq ,*/{ "cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, -/* 0011nnnnmmmm0011 cmp/ge ,*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, +/* 0011nnnnmmmm0011 cmp/ge ,*/{ "cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, -/* 0011nnnnmmmm0111 cmp/gt ,*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, +/* 0011nnnnmmmm0111 cmp/gt ,*/{ "cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, -/* 0011nnnnmmmm0110 cmp/hi ,*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, +/* 0011nnnnmmmm0110 cmp/hi ,*/{ "cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, -/* 0011nnnnmmmm0010 cmp/hs ,*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, +/* 0011nnnnmmmm0010 cmp/hs ,*/{ "cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, -/* 0100nnnn00010101 cmp/pl */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, +/* 0100nnnn00010101 cmp/pl */{ "cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, -/* 0100nnnn00010001 cmp/pz */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, +/* 0100nnnn00010001 cmp/pz */{ "cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, -/* 0010nnnnmmmm1100 cmp/str ,*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, +/* 0010nnnnmmmm1100 cmp/str ,*/{ "cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, -/* 0010nnnnmmmm0111 div0s ,*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, +/* 0010nnnnmmmm0111 div0s ,*/{ "div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, -/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}}, +/* 0000000000011001 div0u */{ "div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}}, -/* 0011nnnnmmmm0100 div1 ,*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, +/* 0011nnnnmmmm0100 div1 ,*/{ "div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, -/* 0110nnnnmmmm1110 exts.b ,*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, +/* 0110nnnnmmmm1110 exts.b ,*/{ "exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, -/* 0110nnnnmmmm1111 exts.w ,*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, +/* 0110nnnnmmmm1111 exts.w ,*/{ "exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, -/* 0110nnnnmmmm1100 extu.b ,*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, +/* 0110nnnnmmmm1100 extu.b ,*/{ "extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, -/* 0110nnnnmmmm1101 extu.w ,*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, +/* 0110nnnnmmmm1101 extu.w ,*/{ "extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, -/* 0100nnnn00101011 jmp @ */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, +/* 0100nnnn00101011 jmp @ */{ "jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, -/* 0100nnnn00001011 jsr @ */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, +/* 0100nnnn00001011 jsr @ */{ "jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, -/* 0100nnnn00001110 ldc ,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, +/* 0100nnnn00001110 ldc ,SR */{ "ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, -/* 0100nnnn00011110 ldc ,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, +/* 0100nnnn00011110 ldc ,GBR */{ "ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, -/* 0100nnnn00101110 ldc ,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, +/* 0100nnnn00101110 ldc ,VBR */{ "ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, -/* 0100nnnn00111110 ldc ,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, +/* 0100nnnn00111110 ldc ,SSR */{ "ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, -/* 0100nnnn01001110 ldc ,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, +/* 0100nnnn01001110 ldc ,SPC */{ "ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, -/* 0100nnnn01111110 ldc ,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}}, +/* 0100nnnn01111110 ldc ,DBR */{ "ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}}, -/* 0100nnnn1xxx1110 ldc ,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}}, +/* 0100nnnn1xxx1110 ldc ,Rn_BANK */{ "ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}}, -/* 0100nnnn00000111 ldc.l @+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, +/* 0100nnnn00000111 ldc.l @+,SR */{ "ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, -/* 0100nnnn00010111 ldc.l @+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, +/* 0100nnnn00010111 ldc.l @+,GBR */{ "ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, -/* 0100nnnn00100111 ldc.l @+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, +/* 0100nnnn00100111 ldc.l @+,VBR */{ "ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, -/* 0100nnnn00110111 ldc.l @+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, +/* 0100nnnn00110111 ldc.l @+,SSR */{ "ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, -/* 0100nnnn01000111 ldc.l @+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, +/* 0100nnnn01000111 ldc.l @+,SPC */{ "ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, -/* 0100nnnn01110111 ldc.l @+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}}, +/* 0100nnnn01110111 ldc.l @+,DBR */{ "ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}}, -/* 0100nnnn1xxx0111 ldc.l ,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}}, +/* 0100nnnn1xxx0111 ldc.l ,Rn_BANK */{ "ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}}, -/* 0100nnnn00001010 lds ,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, +/* 0100nnnn00001010 lds ,MACH */{ "lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, -/* 0100nnnn00011010 lds ,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, +/* 0100nnnn00011010 lds ,MACL */{ "lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, -/* 0100nnnn00101010 lds ,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, +/* 0100nnnn00101010 lds ,PR */{ "lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, -/* 0100nnnn01011010 lds ,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, +/* 0100nnnn01011010 lds ,FPUL */{ "lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, -/* 0100nnnn01101010 lds ,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, +/* 0100nnnn01101010 lds ,FPSCR */{ "lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, -/* 0100nnnn00000110 lds.l @+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, +/* 0100nnnn00000110 lds.l @+,MACH*/{ "lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, -/* 0100nnnn00010110 lds.l @+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, +/* 0100nnnn00010110 lds.l @+,MACL*/{ "lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, -/* 0100nnnn00100110 lds.l @+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, +/* 0100nnnn00100110 lds.l @+,PR */{ "lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, -/* 0100nnnn01010110 lds.l @+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, +/* 0100nnnn01010110 lds.l @+,FPUL*/{ "lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, -/* 0100nnnn01100110 lds.l @+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, +/* 0100nnnn01100110 lds.l @+,FPSCR*/{ "lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}}, +/* 0000000000111000 ldtlb */{ "ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}}, -/* 0100nnnnmmmm1111 mac.w @+,@+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, +/* 0100nnnnmmmm1111 mac.w @+,@+*/{ "mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, -/* 1110nnnni8*1.... mov #, */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, +/* 1110nnnni8*1.... mov #, */{ "mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, -/* 0110nnnnmmmm0011 mov , */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, +/* 0110nnnnmmmm0011 mov , */{ "mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, -/* 0000nnnnmmmm0100 mov.b ,@(R0,)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, +/* 0000nnnnmmmm0100 mov.b ,@(R0,)*/{ "mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, -/* 0010nnnnmmmm0100 mov.b ,@-*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, +/* 0010nnnnmmmm0100 mov.b ,@-*/{ "mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, -/* 0010nnnnmmmm0000 mov.b ,@*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, +/* 0010nnnnmmmm0000 mov.b ,@*/{ "mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, -/* 10000100mmmmi4*1 mov.b @(,),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, +/* 10000100mmmmi4*1 mov.b @(,),R0*/{ "mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, -/* 11000100i8*1.... mov.b @(,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, +/* 11000100i8*1.... mov.b @(,GBR),R0*/{ "mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, -/* 0000nnnnmmmm1100 mov.b @(R0,),*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, +/* 0000nnnnmmmm1100 mov.b @(R0,),*/{ "mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, -/* 0110nnnnmmmm0100 mov.b @+,*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, +/* 0110nnnnmmmm0100 mov.b @+,*/{ "mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, -/* 0110nnnnmmmm0000 mov.b @,*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, +/* 0110nnnnmmmm0000 mov.b @,*/{ "mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, -/* 10000000mmmmi4*1 mov.b R0,@(,)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, +/* 10000000mmmmi4*1 mov.b R0,@(,)*/{ "mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, -/* 11000000i8*1.... mov.b R0,@(,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, +/* 11000000i8*1.... mov.b R0,@(,GBR)*/{ "mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, -/* 0001nnnnmmmmi4*4 mov.l ,@(,)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, +/* 0001nnnnmmmmi4*4 mov.l ,@(,)*/{ "mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, -/* 0000nnnnmmmm0110 mov.l ,@(R0,)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, +/* 0000nnnnmmmm0110 mov.l ,@(R0,)*/{ "mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, -/* 0010nnnnmmmm0110 mov.l ,@-*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, +/* 0010nnnnmmmm0110 mov.l ,@-*/{ "mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, -/* 0010nnnnmmmm0010 mov.l ,@*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, +/* 0010nnnnmmmm0010 mov.l ,@*/{ "mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, -/* 0101nnnnmmmmi4*4 mov.l @(,),*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, +/* 0101nnnnmmmmi4*4 mov.l @(,),*/{ "mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, -/* 11000110i8*4.... mov.l @(,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, +/* 11000110i8*4.... mov.l @(,GBR),R0*/{ "mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, -/* 1101nnnni8p4.... mov.l @(,PC),*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, +/* 1101nnnni8p4.... mov.l @(,PC),*/{ "mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, -/* 0000nnnnmmmm1110 mov.l @(R0,),*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, +/* 0000nnnnmmmm1110 mov.l @(R0,),*/{ "mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, -/* 0110nnnnmmmm0110 mov.l @+,*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, +/* 0110nnnnmmmm0110 mov.l @+,*/{ "mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, -/* 0110nnnnmmmm0010 mov.l @,*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, +/* 0110nnnnmmmm0010 mov.l @,*/{ "mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, -/* 11000010i8*4.... mov.l R0,@(,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, +/* 11000010i8*4.... mov.l R0,@(,GBR)*/{ "mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, -/* 0000nnnnmmmm0101 mov.w ,@(R0,)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, +/* 0000nnnnmmmm0101 mov.w ,@(R0,)*/{ "mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, -/* 0010nnnnmmmm0101 mov.w ,@-*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, +/* 0010nnnnmmmm0101 mov.w ,@-*/{ "mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, -/* 0010nnnnmmmm0001 mov.w ,@*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, +/* 0010nnnnmmmm0001 mov.w ,@*/{ "mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, -/* 10000101mmmmi4*2 mov.w @(,),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, +/* 10000101mmmmi4*2 mov.w @(,),R0*/{ "mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, -/* 11000101i8*2.... mov.w @(,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, +/* 11000101i8*2.... mov.w @(,GBR),R0*/{ "mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, -/* 1001nnnni8p2.... mov.w @(,PC),*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, +/* 1001nnnni8p2.... mov.w @(,PC),*/{ "mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, -/* 0000nnnnmmmm1101 mov.w @(R0,),*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, +/* 0000nnnnmmmm1101 mov.w @(R0,),*/{ "mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, -/* 0110nnnnmmmm0101 mov.w @+,*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, +/* 0110nnnnmmmm0101 mov.w @+,*/{ "mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, -/* 0110nnnnmmmm0001 mov.w @,*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, +/* 0110nnnnmmmm0001 mov.w @,*/{ "mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, -/* 10000001mmmmi4*2 mov.w R0,@(,)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, +/* 10000001mmmmi4*2 mov.w R0,@(,)*/{ "mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, -/* 11000001i8*2.... mov.w R0,@(,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, +/* 11000001i8*2.... mov.w R0,@(,GBR)*/{ "mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, -/* 11000111i8p4.... mova @(,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, -/* 0000nnnn11000011 movca.l R0,@ */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}}, +/* 11000111i8p4.... mova @(,PC),R0*/{ "mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, +/* 0000nnnn11000011 movca.l R0,@ */{ "movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}}, -/* 0000nnnn00101001 movt */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, +/* 0000nnnn00101001 movt */{ "movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, -/* 0010nnnnmmmm1111 muls ,*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, +/* 0010nnnnmmmm1111 muls ,*/{ "muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, -/* 0000nnnnmmmm0111 mul.l ,*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, +/* 0000nnnnmmmm0111 mul.l ,*/{ "mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, -/* 0010nnnnmmmm1110 mulu ,*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, +/* 0010nnnnmmmm1110 mulu ,*/{ "mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, -/* 0110nnnnmmmm1011 neg , */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, +/* 0110nnnnmmmm1011 neg , */{ "neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, -/* 0110nnnnmmmm1010 negc ,*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, +/* 0110nnnnmmmm1010 negc ,*/{ "negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, -/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}}, +/* 0000000000001001 nop */{ "nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}}, -/* 0110nnnnmmmm0111 not , */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, -/* 0000nnnn10010011 ocbi @ */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}}, +/* 0110nnnnmmmm0111 not , */{ "not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, +/* 0000nnnn10010011 ocbi @ */{ "ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}}, -/* 0000nnnn10100011 ocbp @ */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}}, +/* 0000nnnn10100011 ocbp @ */{ "ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}}, -/* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}}, +/* 0000nnnn10110011 ocbwb @ */{ "ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}}, -/* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, +/* 11001011i8*1.... or #,R0 */{ "or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, -/* 0010nnnnmmmm1011 or , */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, +/* 0010nnnnmmmm1011 or , */{ "or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, -/* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, +/* 11001111i8*1.... or.b #,@(R0,GBR)*/{ "or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, -/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}}, +/* 0000nnnn10000011 pref @ */{ "pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}}, -/* 0100nnnn00100100 rotcl */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, +/* 0100nnnn00100100 rotcl */{ "rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, -/* 0100nnnn00100101 rotcr */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, +/* 0100nnnn00100101 rotcr */{ "rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, -/* 0100nnnn00000100 rotl */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, +/* 0100nnnn00000100 rotl */{ "rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, -/* 0100nnnn00000101 rotr */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, +/* 0100nnnn00000101 rotr */{ "rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, -/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}}, +/* 0000000000101011 rte */{ "rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}}, -/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}}, +/* 0000000000001011 rts */{ "rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}}, -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}, -/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}, +/* 0000000001011000 sets */{ "sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}, +/* 0000000000011000 sett */{ "sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}, -/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, +/* 0100nnnnmmmm1100 shad ,*/{ "shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, -/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, +/* 0100nnnnmmmm1101 shld ,*/{ "shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, -/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, +/* 0100nnnn00100000 shal */{ "shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, -/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, +/* 0100nnnn00100001 shar */{ "shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, -/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, +/* 0100nnnn00000000 shll */{ "shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, -/* 0100nnnn00101000 shll16 */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, +/* 0100nnnn00101000 shll16 */{ "shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, -/* 0100nnnn00001000 shll2 */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, +/* 0100nnnn00001000 shll2 */{ "shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, -/* 0100nnnn00011000 shll8 */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, +/* 0100nnnn00011000 shll8 */{ "shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, -/* 0100nnnn00000001 shlr */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, +/* 0100nnnn00000001 shlr */{ "shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, -/* 0100nnnn00101001 shlr16 */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, +/* 0100nnnn00101001 shlr16 */{ "shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, -/* 0100nnnn00001001 shlr2 */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, +/* 0100nnnn00001001 shlr2 */{ "shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, -/* 0100nnnn00011001 shlr8 */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, +/* 0100nnnn00011001 shlr8 */{ "shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, -/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}}, +/* 0000000000011011 sleep */{ "sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}}, -/* 0000nnnn00000010 stc SR, */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, +/* 0000nnnn00000010 stc SR, */{ "stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, -/* 0000nnnn00010010 stc GBR, */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, +/* 0000nnnn00010010 stc GBR, */{ "stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, -/* 0000nnnn00100010 stc VBR, */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, +/* 0000nnnn00100010 stc VBR, */{ "stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, -/* 0000nnnn00110010 stc SSR, */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, +/* 0000nnnn00110010 stc SSR, */{ "stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, -/* 0000nnnn01000010 stc SPC, */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, +/* 0000nnnn01000010 stc SPC, */{ "stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, -/* 0000nnnn01100010 stc SGR, */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}}, +/* 0000nnnn01100010 stc SGR, */{ "stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}}, -/* 0000nnnn01110010 stc DBR, */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}}, +/* 0000nnnn01110010 stc DBR, */{ "stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}}, -/* 0000nnnn1xxx0012 stc Rn_BANK, */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}}, +/* 0000nnnn1xxx0012 stc Rn_BANK, */{ "stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}}, -/* 0100nnnn00000011 stc.l SR,@- */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, +/* 0100nnnn00000011 stc.l SR,@- */{ "stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, -/* 0100nnnn00010011 stc.l GBR,@- */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, +/* 0100nnnn00010011 stc.l GBR,@- */{ "stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, -/* 0100nnnn00100011 stc.l VBR,@- */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, +/* 0100nnnn00100011 stc.l VBR,@- */{ "stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, -/* 0100nnnn00110011 stc.l SSR,@- */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, +/* 0100nnnn00110011 stc.l SSR,@- */{ "stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, -/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, +/* 0100nnnn01000011 stc.l SPC,@- */{ "stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, -/* 0100nnnn01100011 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}}, +/* 0100nnnn01100011 stc.l SGR,@- */{ "stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}}, -/* 0100nnnn01110011 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}}, +/* 0100nnnn01110011 stc.l DBR,@- */{ "stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}}, -/* 0100nnnn1xxx0012 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}}, +/* 0100nnnn1xxx0012 stc.l Rn_BANK,@- */{ "stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}}, -/* 0000nnnn00001010 sts MACH, */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, +/* 0000nnnn00001010 sts MACH, */{ "sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, -/* 0000nnnn00011010 sts MACL, */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, +/* 0000nnnn00011010 sts MACL, */{ "sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, -/* 0000nnnn00101010 sts PR, */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, +/* 0000nnnn00101010 sts PR, */{ "sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, -/* 0000nnnn01011010 sts FPUL, */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, +/* 0000nnnn01011010 sts FPUL, */{ "sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, -/* 0000nnnn01101010 sts FPSCR, */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, +/* 0000nnnn01101010 sts FPSCR, */{ "sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, -/* 0100nnnn00000010 sts.l MACH,@-*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, +/* 0100nnnn00000010 sts.l MACH,@-*/{ "sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, -/* 0100nnnn00010010 sts.l MACL,@-*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, +/* 0100nnnn00010010 sts.l MACL,@-*/{ "sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, -/* 0100nnnn00100010 sts.l PR,@- */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, +/* 0100nnnn00100010 sts.l PR,@- */{ "sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, -/* 0100nnnn01010010 sts.l FPUL,@-*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, +/* 0100nnnn01010010 sts.l FPUL,@-*/{ "sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, -/* 0100nnnn01100010 sts.l FPSCR,@-*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, +/* 0100nnnn01100010 sts.l FPSCR,@-*/{ "sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, -/* 0011nnnnmmmm1000 sub , */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, +/* 0011nnnnmmmm1000 sub , */{ "sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, -/* 0011nnnnmmmm1010 subc ,*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, +/* 0011nnnnmmmm1010 subc ,*/{ "subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, -/* 0011nnnnmmmm1011 subv ,*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, +/* 0011nnnnmmmm1011 subv ,*/{ "subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, -/* 0110nnnnmmmm1000 swap.b ,*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, +/* 0110nnnnmmmm1000 swap.b ,*/{ "swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, -/* 0110nnnnmmmm1001 swap.w ,*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, +/* 0110nnnnmmmm1001 swap.w ,*/{ "swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, -/* 0100nnnn00011011 tas.b @ */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, +/* 0100nnnn00011011 tas.b @ */{ "tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, -/* 11000011i8*1.... trapa # */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, +/* 11000011i8*1.... trapa # */{ "trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, -/* 11001000i8*1.... tst #,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, +/* 11001000i8*1.... tst #,R0 */{ "tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, -/* 0010nnnnmmmm1000 tst , */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, +/* 0010nnnnmmmm1000 tst , */{ "tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, -/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, +/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{ "tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, -/* 11001010i8*1.... xor #,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, +/* 11001010i8*1.... xor #,R0 */{ "xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, -/* 0010nnnnmmmm1010 xor , */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, +/* 0010nnnnmmmm1010 xor , */{ "xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, -/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, +/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{ "xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, -/* 0010nnnnmmmm1101 xtrct ,*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, +/* 0010nnnnmmmm1101 xtrct ,*/{ "xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, -/* 0000nnnnmmmm0111 mul.l ,*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, +/* 0000nnnnmmmm0111 mul.l ,*/{ "mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, -/* 0100nnnn00010000 dt */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, +/* 0100nnnn00010000 dt */{ "dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, -/* 0011nnnnmmmm1101 dmuls.l ,*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, +/* 0011nnnnmmmm1101 dmuls.l ,*/{ "dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, -/* 0011nnnnmmmm0101 dmulu.l ,*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, +/* 0011nnnnmmmm0101 dmulu.l ,*/{ "dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, -/* 0000nnnnmmmm1111 mac.l @+,@+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, +/* 0000nnnnmmmm1111 mac.l @+,@+*/{ "mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, -/* 0000nnnn00100011 braf */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, +/* 0000nnnn00100011 braf */{ "braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, -/* 0000nnnn00000011 bsrf */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, +/* 0000nnnn00000011 bsrf */{ "bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, -/* 1111nnnn01011101 fabs */{"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, +/* 1111nnnn01011101 fabs */{ "fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, -/* 1111nnnnmmmm0000 fadd ,*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, -/* 1111nnn0mmm00000 fadd ,*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, +/* 1111nnnnmmmm0000 fadd ,*/{ "fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, +/* 1111nnn0mmm00000 fadd ,*/{ "fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, -/* 1111nnnnmmmm0100 fcmp/eq ,*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, -/* 1111nnn0mmm00100 fcmp/eq ,*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, +/* 1111nnnnmmmm0100 fcmp/eq ,*/{ "fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, +/* 1111nnn0mmm00100 fcmp/eq ,*/{ "fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, -/* 1111nnnnmmmm0101 fcmp/gt ,*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, -/* 1111nnn0mmm00101 fcmp/gt ,*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, +/* 1111nnnnmmmm0101 fcmp/gt ,*/{ "fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, +/* 1111nnn0mmm00101 fcmp/gt ,*/{ "fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, -/* 1111nnn010111101 fcnvds ,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}}, +/* 1111nnn010111101 fcnvds ,FPUL*/{ "fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}}, -/* 1111nnn010101101 fcnvsd FPUL,*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}}, +/* 1111nnn010101101 fcnvsd FPUL,*/{ "fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}}, -/* 1111nnnnmmmm0011 fdiv ,*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, -/* 1111nnn0mmm00011 fdiv ,*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, +/* 1111nnnnmmmm0011 fdiv ,*/{ "fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, +/* 1111nnn0mmm00011 fdiv ,*/{ "fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, -/* 1111nnmm11101101 fipr ,*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}}, +/* 1111nnmm11101101 fipr ,*/{ "fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}}, -/* 1111nnnn10001101 fldi0 */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, +/* 1111nnnn10001101 fldi0 */{ "fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, -/* 1111nnnn10011101 fldi1 */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, +/* 1111nnnn10011101 fldi1 */{ "fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, -/* 1111nnnn00011101 flds ,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, +/* 1111nnnn00011101 flds ,FPUL*/{ "flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, -/* 1111nnnn00101101 float FPUL,*/{"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, +/* 1111nnnn00101101 float FPUL,*/{ "float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, -/* 1111nnnnmmmm1110 fmac FR0,,*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, +/* 1111nnnnmmmm1110 fmac FR0,,*/{ "fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, -/* 1111nnnnmmmm1100 fmov ,*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, -/* 1111nnnnmmmm1100 fmov ,*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, +/* 1111nnnnmmmm1100 fmov ,*/{ "fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, +/* 1111nnnnmmmm1100 fmov ,*/{ "fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, -/* 1111nnnnmmmm1000 fmov @,*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, -/* 1111nnnnmmmm1000 fmov @,*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, +/* 1111nnnnmmmm1000 fmov @,*/{ "fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, +/* 1111nnnnmmmm1000 fmov @,*/{ "fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, -/* 1111nnnnmmmm1010 fmov ,@*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, -/* 1111nnnnmmmm1010 fmov ,@*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, +/* 1111nnnnmmmm1010 fmov ,@*/{ "fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, +/* 1111nnnnmmmm1010 fmov ,@*/{ "fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, -/* 1111nnnnmmmm1001 fmov @+,*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, -/* 1111nnnnmmmm1001 fmov @+,*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, +/* 1111nnnnmmmm1001 fmov @+,*/{ "fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, +/* 1111nnnnmmmm1001 fmov @+,*/{ "fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, -/* 1111nnnnmmmm1011 fmov ,@-*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, -/* 1111nnnnmmmm1011 fmov ,@-*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, +/* 1111nnnnmmmm1011 fmov ,@-*/{ "fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, +/* 1111nnnnmmmm1011 fmov ,@-*/{ "fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, -/* 1111nnnnmmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, -/* 1111nnnnmmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, +/* 1111nnnnmmmm0110 fmov @(R0,),*/{ "fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, +/* 1111nnnnmmmm0110 fmov @(R0,),*/{ "fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, -/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, -/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, +/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{ "fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, +/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{ "fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, -/* 1111nnnnmmmm1000 fmov.d @,*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, +/* 1111nnnnmmmm1000 fmov.d @,*/{ "fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, -/* 1111nnnnmmmm1010 fmov.d ,@*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, +/* 1111nnnnmmmm1010 fmov.d ,@*/{ "fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, -/* 1111nnnnmmmm1001 fmov.d @+,*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, +/* 1111nnnnmmmm1001 fmov.d @+,*/{ "fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, -/* 1111nnnnmmmm1011 fmov.d ,@-*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, +/* 1111nnnnmmmm1011 fmov.d ,@-*/{ "fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, -/* 1111nnnnmmmm0110 fmov.d @(R0,),*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, +/* 1111nnnnmmmm0110 fmov.d @(R0,),*/{ "fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, -/* 1111nnnnmmmm0111 fmov.d ,@(R0,)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, +/* 1111nnnnmmmm0111 fmov.d ,@(R0,)*/{ "fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, -/* 1111nnnnmmmm1000 fmov.s @,*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, +/* 1111nnnnmmmm1000 fmov.s @,*/{ "fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, -/* 1111nnnnmmmm1010 fmov.s ,@*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, +/* 1111nnnnmmmm1010 fmov.s ,@*/{ "fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, -/* 1111nnnnmmmm1001 fmov.s @+,*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, +/* 1111nnnnmmmm1001 fmov.s @+,*/{ "fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, -/* 1111nnnnmmmm1011 fmov.s ,@-*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, +/* 1111nnnnmmmm1011 fmov.s ,@-*/{ "fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, -/* 1111nnnnmmmm0110 fmov.s @(R0,),*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, +/* 1111nnnnmmmm0110 fmov.s @(R0,),*/{ "fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, -/* 1111nnnnmmmm0111 fmov.s ,@(R0,)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, +/* 1111nnnnmmmm0111 fmov.s ,@(R0,)*/{ "fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, -/* 1111nnnnmmmm0010 fmul ,*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, -/* 1111nnn0mmm00010 fmul ,*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, +/* 1111nnnnmmmm0010 fmul ,*/{ "fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, +/* 1111nnn0mmm00010 fmul ,*/{ "fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, -/* 1111nnnn01001101 fneg */{"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, +/* 1111nnnn01001101 fneg */{ "fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, -/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}}, +/* 1111101111111101 frchg */{ "frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}}, -/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}}, +/* 1111001111111101 fschg */{ "fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}}, -/* 1111nnnn01101101 fsqrt */{"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, +/* 1111nnnn01101101 fsqrt */{ "fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, -/* 1111nnnn00001101 fsts FPUL,*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, +/* 1111nnnn00001101 fsts FPUL,*/{ "fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, -/* 1111nnnnmmmm0001 fsub ,*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, -/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, +/* 1111nnnnmmmm0001 fsub ,*/{ "fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, +/* 1111nnn0mmm00001 fsub ,*/{ "fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, -/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, +/* 1111nnnn00111101 ftrc ,FPUL*/{ "ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, -/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}}, +/* 1111nn0111111101 ftrv XMTRX_M4,*/{ "ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}}, { 0 } }; diff --git a/libr/asm/arch/tricore/gnu/tricore-opc.c b/libr/asm/arch/tricore/gnu/tricore-opc.c index 561bcc975d..0eb296e050 100644 --- a/libr/asm/arch/tricore/gnu/tricore-opc.c +++ b/libr/asm/arch/tricore/gnu/tricore-opc.c @@ -28,274 +28,274 @@ Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA const struct tricore_core_register tricore_sfrs[] = { - {"$mmucon", 0x8000, TRICORE_RIDER_D_UP}, - {"$mmu_con", 0x8000, TRICORE_RIDER_D_UP}, - {"$asi", 0x8004, TRICORE_RIDER_D_UP}, - {"$mmu_asi", 0x8004, TRICORE_RIDER_D_UP}, - {"$mmuid", 0x8008, TRICORE_RIDER_D_UP}, - {"$mmu_id", 0x8008, TRICORE_RIDER_D_UP}, - {"$tva", 0x800c, TRICORE_RIDER_D_UP}, - {"$mmu_tva", 0x800c, TRICORE_RIDER_D_UP}, - {"$tpa", 0x8010, TRICORE_RIDER_D_UP}, - {"$mmu_tpa", 0x8010, TRICORE_RIDER_D_UP}, - {"$tpx", 0x8014, TRICORE_RIDER_D_UP}, - {"$mmu_tpx", 0x8014, TRICORE_RIDER_D_UP}, - {"$tfa", 0x8018, TRICORE_RIDER_D_UP}, - {"$mmu_tfa", 0x8018, TRICORE_RIDER_D_UP}, - {"$mmu_lpma", 0x801c, TRICORE_V2_UP}, - {"$mmu_tfas", 0x8020, TRICORE_V2_UP}, + { "$mmucon", 0x8000, TRICORE_RIDER_D_UP}, + { "$mmu_con", 0x8000, TRICORE_RIDER_D_UP}, + { "$asi", 0x8004, TRICORE_RIDER_D_UP}, + { "$mmu_asi", 0x8004, TRICORE_RIDER_D_UP}, + { "$mmuid", 0x8008, TRICORE_RIDER_D_UP}, + { "$mmu_id", 0x8008, TRICORE_RIDER_D_UP}, + { "$tva", 0x800c, TRICORE_RIDER_D_UP}, + { "$mmu_tva", 0x800c, TRICORE_RIDER_D_UP}, + { "$tpa", 0x8010, TRICORE_RIDER_D_UP}, + { "$mmu_tpa", 0x8010, TRICORE_RIDER_D_UP}, + { "$tpx", 0x8014, TRICORE_RIDER_D_UP}, + { "$mmu_tpx", 0x8014, TRICORE_RIDER_D_UP}, + { "$tfa", 0x8018, TRICORE_RIDER_D_UP}, + { "$mmu_tfa", 0x8018, TRICORE_RIDER_D_UP}, + { "$mmu_lpma", 0x801c, TRICORE_V2_UP}, + { "$mmu_tfas", 0x8020, TRICORE_V2_UP}, - {"$dspr", 0x9000, TRICORE_V2_UP}, - {"$dcache", 0x9008, TRICORE_V2_UP}, - {"$memtr", 0x9010, TRICORE_V2_UP}, - {"$datr", 0x9018, TRICORE_V2_UP}, - {"$dttar", 0x901c, TRICORE_V2_UP}, + { "$dspr", 0x9000, TRICORE_V2_UP}, + { "$dcache", 0x9008, TRICORE_V2_UP}, + { "$memtr", 0x9010, TRICORE_V2_UP}, + { "$datr", 0x9018, TRICORE_V2_UP}, + { "$dttar", 0x901c, TRICORE_V2_UP}, - {"$pspr", 0x9200, TRICORE_V2_UP}, - {"$pcache", 0x9208, TRICORE_V2_UP}, - {"$pcon", 0x920c, TRICORE_V2_UP}, - {"$pstr", 0x9214, TRICORE_V2_UP}, + { "$pspr", 0x9200, TRICORE_V2_UP}, + { "$pcache", 0x9208, TRICORE_V2_UP}, + { "$pcon", 0x920c, TRICORE_V2_UP}, + { "$pstr", 0x9214, TRICORE_V2_UP}, - {"$dpr0_0l", 0xc000, TRICORE_GENERIC}, - {"$dpr0_0u", 0xc004, TRICORE_GENERIC}, - {"$dpr0_1l", 0xc008, TRICORE_GENERIC}, - {"$dpr0_1u", 0xc00c, TRICORE_GENERIC}, - {"$dpr0_2l", 0xc010, TRICORE_GENERIC}, - {"$dpr0_2u", 0xc014, TRICORE_GENERIC}, - {"$dpr0_3l", 0xc018, TRICORE_GENERIC}, - {"$dpr0_3u", 0xc01c, TRICORE_GENERIC}, + { "$dpr0_0l", 0xc000, TRICORE_GENERIC}, + { "$dpr0_0u", 0xc004, TRICORE_GENERIC}, + { "$dpr0_1l", 0xc008, TRICORE_GENERIC}, + { "$dpr0_1u", 0xc00c, TRICORE_GENERIC}, + { "$dpr0_2l", 0xc010, TRICORE_GENERIC}, + { "$dpr0_2u", 0xc014, TRICORE_GENERIC}, + { "$dpr0_3l", 0xc018, TRICORE_GENERIC}, + { "$dpr0_3u", 0xc01c, TRICORE_GENERIC}, - {"$dpr1_0l", 0xc400, TRICORE_GENERIC}, - {"$dpr1_0u", 0xc404, TRICORE_GENERIC}, - {"$dpr1_1l", 0xc408, TRICORE_GENERIC}, - {"$dpr1_1u", 0xc40c, TRICORE_GENERIC}, - {"$dpr1_2l", 0xc410, TRICORE_GENERIC}, - {"$dpr1_2u", 0xc414, TRICORE_GENERIC}, - {"$dpr1_3l", 0xc418, TRICORE_GENERIC}, - {"$dpr1_3u", 0xc41c, TRICORE_GENERIC}, + { "$dpr1_0l", 0xc400, TRICORE_GENERIC}, + { "$dpr1_0u", 0xc404, TRICORE_GENERIC}, + { "$dpr1_1l", 0xc408, TRICORE_GENERIC}, + { "$dpr1_1u", 0xc40c, TRICORE_GENERIC}, + { "$dpr1_2l", 0xc410, TRICORE_GENERIC}, + { "$dpr1_2u", 0xc414, TRICORE_GENERIC}, + { "$dpr1_3l", 0xc418, TRICORE_GENERIC}, + { "$dpr1_3u", 0xc41c, TRICORE_GENERIC}, - {"$dpr2_0l", 0xc800, TRICORE_RIDER_B_UP}, - {"$dpr2_0u", 0xc804, TRICORE_RIDER_B_UP}, - {"$dpr2_1l", 0xc808, TRICORE_RIDER_B_UP}, - {"$dpr2_1u", 0xc80c, TRICORE_RIDER_B_UP}, - {"$dpr2_2l", 0xc810, TRICORE_RIDER_B_UP}, - {"$dpr2_2u", 0xc814, TRICORE_RIDER_B_UP}, - {"$dpr2_3l", 0xc818, TRICORE_RIDER_B_UP}, - {"$dpr2_3u", 0xc81c, TRICORE_RIDER_B_UP}, + { "$dpr2_0l", 0xc800, TRICORE_RIDER_B_UP}, + { "$dpr2_0u", 0xc804, TRICORE_RIDER_B_UP}, + { "$dpr2_1l", 0xc808, TRICORE_RIDER_B_UP}, + { "$dpr2_1u", 0xc80c, TRICORE_RIDER_B_UP}, + { "$dpr2_2l", 0xc810, TRICORE_RIDER_B_UP}, + { "$dpr2_2u", 0xc814, TRICORE_RIDER_B_UP}, + { "$dpr2_3l", 0xc818, TRICORE_RIDER_B_UP}, + { "$dpr2_3u", 0xc81c, TRICORE_RIDER_B_UP}, - {"$dpr3_0l", 0xcc00, TRICORE_RIDER_B_UP}, - {"$dpr3_0u", 0xcc04, TRICORE_RIDER_B_UP}, - {"$dpr3_1l", 0xcc08, TRICORE_RIDER_B_UP}, - {"$dpr3_1u", 0xcc0c, TRICORE_RIDER_B_UP}, - {"$dpr3_2l", 0xcc10, TRICORE_RIDER_B_UP}, - {"$dpr3_2u", 0xcc14, TRICORE_RIDER_B_UP}, - {"$dpr3_3l", 0xcc18, TRICORE_RIDER_B_UP}, - {"$dpr3_3u", 0xcc1c, TRICORE_RIDER_B_UP}, + { "$dpr3_0l", 0xcc00, TRICORE_RIDER_B_UP}, + { "$dpr3_0u", 0xcc04, TRICORE_RIDER_B_UP}, + { "$dpr3_1l", 0xcc08, TRICORE_RIDER_B_UP}, + { "$dpr3_1u", 0xcc0c, TRICORE_RIDER_B_UP}, + { "$dpr3_2l", 0xcc10, TRICORE_RIDER_B_UP}, + { "$dpr3_2u", 0xcc14, TRICORE_RIDER_B_UP}, + { "$dpr3_3l", 0xcc18, TRICORE_RIDER_B_UP}, + { "$dpr3_3u", 0xcc1c, TRICORE_RIDER_B_UP}, - {"$cpr0_0l", 0xd000, TRICORE_GENERIC}, - {"$cpr0_0u", 0xd004, TRICORE_GENERIC}, - {"$cpr0_1l", 0xd008, TRICORE_GENERIC}, - {"$cpr0_1u", 0xd00c, TRICORE_GENERIC}, - {"$cpr0_2l", 0xd010, TRICORE_RIDER_B_UP}, - {"$cpr0_2u", 0xd014, TRICORE_RIDER_B_UP}, - {"$cpr0_3l", 0xd018, TRICORE_RIDER_B_UP}, - {"$cpr0_3u", 0xd01c, TRICORE_RIDER_B_UP}, + { "$cpr0_0l", 0xd000, TRICORE_GENERIC}, + { "$cpr0_0u", 0xd004, TRICORE_GENERIC}, + { "$cpr0_1l", 0xd008, TRICORE_GENERIC}, + { "$cpr0_1u", 0xd00c, TRICORE_GENERIC}, + { "$cpr0_2l", 0xd010, TRICORE_RIDER_B_UP}, + { "$cpr0_2u", 0xd014, TRICORE_RIDER_B_UP}, + { "$cpr0_3l", 0xd018, TRICORE_RIDER_B_UP}, + { "$cpr0_3u", 0xd01c, TRICORE_RIDER_B_UP}, - {"$cpr1_0l", 0xd400, TRICORE_GENERIC}, - {"$cpr1_0u", 0xd404, TRICORE_GENERIC}, - {"$cpr1_1l", 0xd408, TRICORE_GENERIC}, - {"$cpr1_1u", 0xd40c, TRICORE_GENERIC}, - {"$cpr1_2l", 0xd410, TRICORE_RIDER_B_UP}, - {"$cpr1_2u", 0xd414, TRICORE_RIDER_B_UP}, - {"$cpr1_3l", 0xd418, TRICORE_RIDER_B_UP}, - {"$cpr1_3u", 0xd41c, TRICORE_RIDER_B_UP}, + { "$cpr1_0l", 0xd400, TRICORE_GENERIC}, + { "$cpr1_0u", 0xd404, TRICORE_GENERIC}, + { "$cpr1_1l", 0xd408, TRICORE_GENERIC}, + { "$cpr1_1u", 0xd40c, TRICORE_GENERIC}, + { "$cpr1_2l", 0xd410, TRICORE_RIDER_B_UP}, + { "$cpr1_2u", 0xd414, TRICORE_RIDER_B_UP}, + { "$cpr1_3l", 0xd418, TRICORE_RIDER_B_UP}, + { "$cpr1_3u", 0xd41c, TRICORE_RIDER_B_UP}, - {"$cpr2_0l", 0xd800, TRICORE_RIDER_B_UP}, - {"$cpr2_0u", 0xd804, TRICORE_RIDER_B_UP}, - {"$cpr2_1l", 0xd808, TRICORE_RIDER_B_UP}, - {"$cpr2_1u", 0xd80c, TRICORE_RIDER_B_UP}, - {"$cpr2_2l", 0xd810, TRICORE_RIDER_B_UP}, - {"$cpr2_2u", 0xd814, TRICORE_RIDER_B_UP}, - {"$cpr2_3l", 0xd818, TRICORE_RIDER_B_UP}, - {"$cpr2_3u", 0xd81c, TRICORE_RIDER_B_UP}, + { "$cpr2_0l", 0xd800, TRICORE_RIDER_B_UP}, + { "$cpr2_0u", 0xd804, TRICORE_RIDER_B_UP}, + { "$cpr2_1l", 0xd808, TRICORE_RIDER_B_UP}, + { "$cpr2_1u", 0xd80c, TRICORE_RIDER_B_UP}, + { "$cpr2_2l", 0xd810, TRICORE_RIDER_B_UP}, + { "$cpr2_2u", 0xd814, TRICORE_RIDER_B_UP}, + { "$cpr2_3l", 0xd818, TRICORE_RIDER_B_UP}, + { "$cpr2_3u", 0xd81c, TRICORE_RIDER_B_UP}, - {"$cpr3_0l", 0xdc00, TRICORE_RIDER_B_UP}, - {"$cpr3_0u", 0xdc04, TRICORE_RIDER_B_UP}, - {"$cpr3_1l", 0xdc08, TRICORE_RIDER_B_UP}, - {"$cpr3_1u", 0xdc0c, TRICORE_RIDER_B_UP}, - {"$cpr3_2l", 0xdc10, TRICORE_RIDER_B_UP}, - {"$cpr3_2u", 0xdc14, TRICORE_RIDER_B_UP}, - {"$cpr3_3l", 0xdc18, TRICORE_RIDER_B_UP}, - {"$cpr3_3u", 0xdc1c, TRICORE_RIDER_B_UP}, + { "$cpr3_0l", 0xdc00, TRICORE_RIDER_B_UP}, + { "$cpr3_0u", 0xdc04, TRICORE_RIDER_B_UP}, + { "$cpr3_1l", 0xdc08, TRICORE_RIDER_B_UP}, + { "$cpr3_1u", 0xdc0c, TRICORE_RIDER_B_UP}, + { "$cpr3_2l", 0xdc10, TRICORE_RIDER_B_UP}, + { "$cpr3_2u", 0xdc14, TRICORE_RIDER_B_UP}, + { "$cpr3_3l", 0xdc18, TRICORE_RIDER_B_UP}, + { "$cpr3_3u", 0xdc1c, TRICORE_RIDER_B_UP}, - {"$dpm0_0", 0xe000, TRICORE_GENERIC}, - {"$dpm0_1", 0xe001, TRICORE_GENERIC}, - {"$dpm0_2", 0xe002, TRICORE_GENERIC}, - {"$dpm0_3", 0xe003, TRICORE_GENERIC}, + { "$dpm0_0", 0xe000, TRICORE_GENERIC}, + { "$dpm0_1", 0xe001, TRICORE_GENERIC}, + { "$dpm0_2", 0xe002, TRICORE_GENERIC}, + { "$dpm0_3", 0xe003, TRICORE_GENERIC}, - {"$dpm1_0", 0xe080, TRICORE_GENERIC}, - {"$dpm1_1", 0xe081, TRICORE_GENERIC}, - {"$dpm1_2", 0xe082, TRICORE_GENERIC}, - {"$dpm1_3", 0xe083, TRICORE_GENERIC}, + { "$dpm1_0", 0xe080, TRICORE_GENERIC}, + { "$dpm1_1", 0xe081, TRICORE_GENERIC}, + { "$dpm1_2", 0xe082, TRICORE_GENERIC}, + { "$dpm1_3", 0xe083, TRICORE_GENERIC}, - {"$cpm0_0", 0xe200, TRICORE_GENERIC}, - {"$cpm0_1", 0xe201, TRICORE_GENERIC}, + { "$cpm0_0", 0xe200, TRICORE_GENERIC}, + { "$cpm0_1", 0xe201, TRICORE_GENERIC}, - {"$cpm1_0", 0xe280, TRICORE_GENERIC}, - {"$cpm1_1", 0xe281, TRICORE_GENERIC}, + { "$cpm1_0", 0xe280, TRICORE_GENERIC}, + { "$cpm1_1", 0xe281, TRICORE_GENERIC}, - {"$dbgsr", 0xfd00, TRICORE_GENERIC}, - {"$gprwb", 0xfd04, TRICORE_GENERIC}, - {"$exevt", 0xfd08, TRICORE_GENERIC}, - {"$crevt", 0xfd0c, TRICORE_GENERIC}, - {"$swevt", 0xfd10, TRICORE_GENERIC}, - {"$tr0evt", 0xfd20, TRICORE_GENERIC}, - {"$tr1evt", 0xfd24, TRICORE_GENERIC}, + { "$dbgsr", 0xfd00, TRICORE_GENERIC}, + { "$gprwb", 0xfd04, TRICORE_GENERIC}, + { "$exevt", 0xfd08, TRICORE_GENERIC}, + { "$crevt", 0xfd0c, TRICORE_GENERIC}, + { "$swevt", 0xfd10, TRICORE_GENERIC}, + { "$tr0evt", 0xfd20, TRICORE_GENERIC}, + { "$tr1evt", 0xfd24, TRICORE_GENERIC}, - {"$pcxi", 0xfe00, TRICORE_GENERIC}, - {"$psw", 0xfe04, TRICORE_GENERIC}, - {"$pc", 0xfe08, TRICORE_GENERIC}, - {"$dbiten", 0xfe0c, TRICORE_RIDER_A}, - {"$syscon", 0xfe14, TRICORE_GENERIC}, - {"$cpuid", 0xfe18, TRICORE_RIDER_B_UP}, - {"$cpu_id", 0xfe18, TRICORE_RIDER_B_UP}, - {"$biv", 0xfe20, TRICORE_GENERIC}, - {"$btv", 0xfe24, TRICORE_GENERIC}, - {"$isp", 0xfe28, TRICORE_GENERIC}, - {"$icr", 0xfe2c, TRICORE_GENERIC}, - {"$fcx", 0xfe38, TRICORE_GENERIC}, - {"$lcx", 0xfe3c, TRICORE_GENERIC}, + { "$pcxi", 0xfe00, TRICORE_GENERIC}, + { "$psw", 0xfe04, TRICORE_GENERIC}, + { "$pc", 0xfe08, TRICORE_GENERIC}, + { "$dbiten", 0xfe0c, TRICORE_RIDER_A}, + { "$syscon", 0xfe14, TRICORE_GENERIC}, + { "$cpuid", 0xfe18, TRICORE_RIDER_B_UP}, + { "$cpu_id", 0xfe18, TRICORE_RIDER_B_UP}, + { "$biv", 0xfe20, TRICORE_GENERIC}, + { "$btv", 0xfe24, TRICORE_GENERIC}, + { "$isp", 0xfe28, TRICORE_GENERIC}, + { "$icr", 0xfe2c, TRICORE_GENERIC}, + { "$fcx", 0xfe38, TRICORE_GENERIC}, + { "$lcx", 0xfe3c, TRICORE_GENERIC}, - {"$d0", 0xff00, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d1", 0xff04, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d2", 0xff08, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d3", 0xff0c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d4", 0xff10, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d5", 0xff14, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d6", 0xff18, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d7", 0xff1c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d8", 0xff20, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d9", 0xff24, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d10", 0xff28, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d11", 0xff2c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d12", 0xff30, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d13", 0xff34, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d14", 0xff38, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$d15", 0xff3c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d0", 0xff00, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d1", 0xff04, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d2", 0xff08, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d3", 0xff0c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d4", 0xff10, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d5", 0xff14, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d6", 0xff18, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d7", 0xff1c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d8", 0xff20, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d9", 0xff24, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d10", 0xff28, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d11", 0xff2c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d12", 0xff30, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d13", 0xff34, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d14", 0xff38, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$d15", 0xff3c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a0", 0xff80, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a1", 0xff84, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a2", 0xff88, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a3", 0xff8c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a4", 0xff90, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a5", 0xff94, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a6", 0xff98, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a7", 0xff9c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a8", 0xffa0, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a9", 0xffa4, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a10", 0xffa8, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a11", 0xffac, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a12", 0xffb0, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a13", 0xffb4, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a14", 0xffb8, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, - {"$a15", 0xffbc, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a0", 0xff80, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a1", 0xff84, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a2", 0xff88, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a3", 0xff8c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a4", 0xff90, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a5", 0xff94, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a6", 0xff98, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a7", 0xff9c, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a8", 0xffa0, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a9", 0xffa4, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a10", 0xffa8, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a11", 0xffac, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a12", 0xffb0, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a13", 0xffb4, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a14", 0xffb8, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, + { "$a15", 0xffbc, TRICORE_RIDER_A | TRICORE_RIDER_D_DN}, /* These are not core SFRs, but they can be accessed using the 18-bit absolute address mode. */ - {"$pwrclc", 0xf0000000, TRICORE_GENERIC}, - {"$pwrid", 0xf0000008, TRICORE_GENERIC}, - {"$rstreq", 0xf0000010, TRICORE_GENERIC}, - {"$rstsr", 0xf0000014, TRICORE_GENERIC}, - {"$wdtcon0", 0xf0000020, TRICORE_GENERIC}, - {"$wdtcon1", 0xf0000024, TRICORE_GENERIC}, - {"$wdtsr", 0xf0000028, TRICORE_GENERIC}, - {"$nmisr", 0xf000002c, TRICORE_GENERIC}, - {"$pmcon", 0xf0000030, TRICORE_GENERIC}, - {"$pmcsr", 0xf0000034, TRICORE_GENERIC}, - {"$pllclc", 0xf0000040, TRICORE_GENERIC}, - {"$eckclc", 0xf0000044, TRICORE_GENERIC}, - {"$icuclc", 0xf0000048, TRICORE_GENERIC}, + { "$pwrclc", 0xf0000000, TRICORE_GENERIC}, + { "$pwrid", 0xf0000008, TRICORE_GENERIC}, + { "$rstreq", 0xf0000010, TRICORE_GENERIC}, + { "$rstsr", 0xf0000014, TRICORE_GENERIC}, + { "$wdtcon0", 0xf0000020, TRICORE_GENERIC}, + { "$wdtcon1", 0xf0000024, TRICORE_GENERIC}, + { "$wdtsr", 0xf0000028, TRICORE_GENERIC}, + { "$nmisr", 0xf000002c, TRICORE_GENERIC}, + { "$pmcon", 0xf0000030, TRICORE_GENERIC}, + { "$pmcsr", 0xf0000034, TRICORE_GENERIC}, + { "$pllclc", 0xf0000040, TRICORE_GENERIC}, + { "$eckclc", 0xf0000044, TRICORE_GENERIC}, + { "$icuclc", 0xf0000048, TRICORE_GENERIC}, - {"$stmclc", 0xf0000300, TRICORE_GENERIC}, - {"$stmid", 0xf0000308, TRICORE_GENERIC}, - {"$systim0", 0xf0000320, TRICORE_GENERIC}, - {"$systim1", 0xf0000324, TRICORE_GENERIC}, - {"$systim2", 0xf0000328, TRICORE_GENERIC}, - {"$systim3", 0xf000032c, TRICORE_GENERIC}, - {"$systim4", 0xf0000330, TRICORE_GENERIC}, - {"$systim5", 0xf0000334, TRICORE_GENERIC}, - {"$systim6", 0xf0000338, TRICORE_GENERIC}, - {"$systim7", 0xf000033c, TRICORE_GENERIC}, + { "$stmclc", 0xf0000300, TRICORE_GENERIC}, + { "$stmid", 0xf0000308, TRICORE_GENERIC}, + { "$systim0", 0xf0000320, TRICORE_GENERIC}, + { "$systim1", 0xf0000324, TRICORE_GENERIC}, + { "$systim2", 0xf0000328, TRICORE_GENERIC}, + { "$systim3", 0xf000032c, TRICORE_GENERIC}, + { "$systim4", 0xf0000330, TRICORE_GENERIC}, + { "$systim5", 0xf0000334, TRICORE_GENERIC}, + { "$systim6", 0xf0000338, TRICORE_GENERIC}, + { "$systim7", 0xf000033c, TRICORE_GENERIC}, - {"$jdpid", 0xf0000408, TRICORE_GENERIC}, - {"$comdata", 0xf0000468, TRICORE_GENERIC}, - {"$iosr", 0xf000046c, TRICORE_GENERIC}, + { "$jdpid", 0xf0000408, TRICORE_GENERIC}, + { "$comdata", 0xf0000468, TRICORE_GENERIC}, + { "$iosr", 0xf000046c, TRICORE_GENERIC}, - {"$ebucon", 0xf0000510, TRICORE_GENERIC}, - {"$drmcon", 0xf0000514, TRICORE_GENERIC}, - {"$drmstat", 0xf0000518, TRICORE_GENERIC}, - {"$addsel0", 0xf0000520, TRICORE_GENERIC}, - {"$addsel1", 0xf0000524, TRICORE_GENERIC}, - {"$addsel2", 0xf0000528, TRICORE_GENERIC}, - {"$addsel3", 0xf000052c, TRICORE_GENERIC}, - {"$addsel4", 0xf0000530, TRICORE_GENERIC}, - {"$addsel5", 0xf0000534, TRICORE_GENERIC}, - {"$addsel6", 0xf0000538, TRICORE_GENERIC}, - {"$addsel7", 0xf000053c, TRICORE_GENERIC}, + { "$ebucon", 0xf0000510, TRICORE_GENERIC}, + { "$drmcon", 0xf0000514, TRICORE_GENERIC}, + { "$drmstat", 0xf0000518, TRICORE_GENERIC}, + { "$addsel0", 0xf0000520, TRICORE_GENERIC}, + { "$addsel1", 0xf0000524, TRICORE_GENERIC}, + { "$addsel2", 0xf0000528, TRICORE_GENERIC}, + { "$addsel3", 0xf000052c, TRICORE_GENERIC}, + { "$addsel4", 0xf0000530, TRICORE_GENERIC}, + { "$addsel5", 0xf0000534, TRICORE_GENERIC}, + { "$addsel6", 0xf0000538, TRICORE_GENERIC}, + { "$addsel7", 0xf000053c, TRICORE_GENERIC}, - {"$buscon0", 0xf0000560, TRICORE_GENERIC}, - {"$buscon1", 0xf0000564, TRICORE_GENERIC}, - {"$buscon2", 0xf0000568, TRICORE_GENERIC}, - {"$buscon3", 0xf000056c, TRICORE_GENERIC}, - {"$buscon4", 0xf0000570, TRICORE_GENERIC}, - {"$buscon5", 0xf0000574, TRICORE_GENERIC}, - {"$buscon6", 0xf0000578, TRICORE_GENERIC}, - {"$buscon7", 0xf000057c, TRICORE_GENERIC}, + { "$buscon0", 0xf0000560, TRICORE_GENERIC}, + { "$buscon1", 0xf0000564, TRICORE_GENERIC}, + { "$buscon2", 0xf0000568, TRICORE_GENERIC}, + { "$buscon3", 0xf000056c, TRICORE_GENERIC}, + { "$buscon4", 0xf0000570, TRICORE_GENERIC}, + { "$buscon5", 0xf0000574, TRICORE_GENERIC}, + { "$buscon6", 0xf0000578, TRICORE_GENERIC}, + { "$buscon7", 0xf000057c, TRICORE_GENERIC}, - {"$gtclc", 0xf0000700, TRICORE_GENERIC}, - {"$gtid", 0xf0000708, TRICORE_GENERIC}, - {"$t01irs", 0xf0000710, TRICORE_GENERIC}, - {"$t01ots", 0xf0000714, TRICORE_GENERIC}, - {"$t2con", 0xf0000718, TRICORE_GENERIC}, - {"$t2rccon", 0xf000071c, TRICORE_GENERIC}, - {"$t2ais", 0xf0000720, TRICORE_GENERIC}, - {"$t2bis", 0xf0000724, TRICORE_GENERIC}, - {"$t2es", 0xf0000728, TRICORE_GENERIC}, - {"$gtosel", 0xf000072c, TRICORE_GENERIC}, - {"$gtout", 0xf0000730, TRICORE_GENERIC}, - {"$t0dcba", 0xf0000734, TRICORE_GENERIC}, - {"$t0cba", 0xf0000738, TRICORE_GENERIC}, - {"$t0rdcba", 0xf000073c, TRICORE_GENERIC}, - {"$t0rcba", 0xf0000740, TRICORE_GENERIC}, - {"$t1dcba", 0xf0000744, TRICORE_GENERIC}, - {"$t1cba", 0xf0000748, TRICORE_GENERIC}, - {"$t1rdcba", 0xf000074c, TRICORE_GENERIC}, - {"$t1rcba", 0xf0000750, TRICORE_GENERIC}, - {"$t2", 0xf0000754, TRICORE_GENERIC}, - {"$t2rc0", 0xf0000758, TRICORE_GENERIC}, - {"$t2rc1", 0xf000075c, TRICORE_GENERIC}, - {"$t012run", 0xf0000760, TRICORE_GENERIC}, + { "$gtclc", 0xf0000700, TRICORE_GENERIC}, + { "$gtid", 0xf0000708, TRICORE_GENERIC}, + { "$t01irs", 0xf0000710, TRICORE_GENERIC}, + { "$t01ots", 0xf0000714, TRICORE_GENERIC}, + { "$t2con", 0xf0000718, TRICORE_GENERIC}, + { "$t2rccon", 0xf000071c, TRICORE_GENERIC}, + { "$t2ais", 0xf0000720, TRICORE_GENERIC}, + { "$t2bis", 0xf0000724, TRICORE_GENERIC}, + { "$t2es", 0xf0000728, TRICORE_GENERIC}, + { "$gtosel", 0xf000072c, TRICORE_GENERIC}, + { "$gtout", 0xf0000730, TRICORE_GENERIC}, + { "$t0dcba", 0xf0000734, TRICORE_GENERIC}, + { "$t0cba", 0xf0000738, TRICORE_GENERIC}, + { "$t0rdcba", 0xf000073c, TRICORE_GENERIC}, + { "$t0rcba", 0xf0000740, TRICORE_GENERIC}, + { "$t1dcba", 0xf0000744, TRICORE_GENERIC}, + { "$t1cba", 0xf0000748, TRICORE_GENERIC}, + { "$t1rdcba", 0xf000074c, TRICORE_GENERIC}, + { "$t1rcba", 0xf0000750, TRICORE_GENERIC}, + { "$t2", 0xf0000754, TRICORE_GENERIC}, + { "$t2rc0", 0xf0000758, TRICORE_GENERIC}, + { "$t2rc1", 0xf000075c, TRICORE_GENERIC}, + { "$t012run", 0xf0000760, TRICORE_GENERIC}, - {"$gtsrsel", 0xf00007dc, TRICORE_GENERIC}, - {"$gtsrc0", 0xf00007e0, TRICORE_GENERIC}, - {"$gtsrc1", 0xf00007e4, TRICORE_GENERIC}, - {"$gtsrc2", 0xf00007e8, TRICORE_GENERIC}, - {"$gtsrc3", 0xf00007ec, TRICORE_GENERIC}, - {"$gtsrc4", 0xf00007f0, TRICORE_GENERIC}, - {"$gtsrc5", 0xf00007f4, TRICORE_GENERIC}, - {"$gtsrc6", 0xf00007f8, TRICORE_GENERIC}, - {"$gtsrc7", 0xf00007fc, TRICORE_GENERIC}, + { "$gtsrsel", 0xf00007dc, TRICORE_GENERIC}, + { "$gtsrc0", 0xf00007e0, TRICORE_GENERIC}, + { "$gtsrc1", 0xf00007e4, TRICORE_GENERIC}, + { "$gtsrc2", 0xf00007e8, TRICORE_GENERIC}, + { "$gtsrc3", 0xf00007ec, TRICORE_GENERIC}, + { "$gtsrc4", 0xf00007f0, TRICORE_GENERIC}, + { "$gtsrc5", 0xf00007f4, TRICORE_GENERIC}, + { "$gtsrc6", 0xf00007f8, TRICORE_GENERIC}, + { "$gtsrc7", 0xf00007fc, TRICORE_GENERIC}, - {"$pcpclc", 0xf0003f00, TRICORE_GENERIC}, - {"$pcpid", 0xf0003f08, TRICORE_GENERIC}, - {"$pcpcs", 0xf0003f10, TRICORE_GENERIC}, - {"$pcpes", 0xf0003f14, TRICORE_GENERIC}, - {"$pcpicr", 0xf0003f20, TRICORE_GENERIC}, - {"$pcpsrc3", 0xf0003ff0, TRICORE_GENERIC}, - {"$pcpsrc2", 0xf0003ff4, TRICORE_GENERIC}, - {"$pcpsrc1", 0xf0003ff8, TRICORE_GENERIC}, - {"$pcpsrc0", 0xf0003ffc, TRICORE_GENERIC} + { "$pcpclc", 0xf0003f00, TRICORE_GENERIC}, + { "$pcpid", 0xf0003f08, TRICORE_GENERIC}, + { "$pcpcs", 0xf0003f10, TRICORE_GENERIC}, + { "$pcpes", 0xf0003f14, TRICORE_GENERIC}, + { "$pcpicr", 0xf0003f20, TRICORE_GENERIC}, + { "$pcpsrc3", 0xf0003ff0, TRICORE_GENERIC}, + { "$pcpsrc2", 0xf0003ff4, TRICORE_GENERIC}, + { "$pcpsrc1", 0xf0003ff8, TRICORE_GENERIC}, + { "$pcpsrc0", 0xf0003ffc, TRICORE_GENERIC} }; const int tricore_numsfrs = sizeof tricore_sfrs / sizeof tricore_sfrs[0]; @@ -308,2069 +308,2069 @@ const int tricore_numsfrs = sizeof tricore_sfrs / sizeof tricore_sfrs[0]; struct tricore_opcode tricore_opcodes[] = { #define INDICES 0, 0 - {"abs", 1, 0x01c0000b, 0x0e3f0ff4, F(RR), 2, "dd", "13", + { "abs", 1, 0x01c0000b, 0x0e3f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"abs.b", 1, 0x05c0000b, 0x0a3f0ff4, F(RR), 2, "dd", "13", + { "abs.b", 1, 0x05c0000b, 0x0a3f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"abs.h", 1, 0x07c0000b, 0x083f0ff4, F(RR), 2, "dd", "13", + { "abs.h", 1, 0x07c0000b, 0x083f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"absdif", 1, 0x00e0000b, 0x0f1f00f4, F(RR), 3, "ddd", "143", + { "absdif", 1, 0x00e0000b, 0x0f1f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"absdif", 1, 0x01c0008b, 0x0e200074, F(RC), 3, "dd9", "132", + { "absdif", 1, 0x01c0008b, 0x0e200074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"absdif.b", 1, 0x04e0000b, 0x0b1f00f4, F(RR), 3, "ddd", "143", + { "absdif.b", 1, 0x04e0000b, 0x0b1f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"absdif.h", 1, 0x06e0000b, 0x091f00f4, F(RR), 3, "ddd", "143", + { "absdif.h", 1, 0x06e0000b, 0x091f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"absdifs", 1, 0x00f0000b, 0x0f0f00f4, F(RR), 3, "ddd", "143", + { "absdifs", 1, 0x00f0000b, 0x0f0f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"absdifs", 1, 0x01e0008b, 0x0e000074, F(RC), 3, "dd9", "132", + { "absdifs", 1, 0x01e0008b, 0x0e000074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"absdifs.b", 1, 0x04f0000b, 0x0b0f00f4, F(RR), 3, "ddd", "143", + { "absdifs.b", 1, 0x04f0000b, 0x0b0f00f4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"absdifs.h", 1, 0x06f0000b, 0x090f00f4, F(RR), 3, "ddd", "143", + { "absdifs.h", 1, 0x06f0000b, 0x090f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"abss", 1, 0x01d0000b, 0x0e2f0ff4, F(RR), 2, "dd", "13", + { "abss", 1, 0x01d0000b, 0x0e2f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"abss.b", 1, 0x05d0000b, 0x0a2f0ff4, F(RR), 2, "dd", "13", + { "abss.b", 1, 0x05d0000b, 0x0a2f0ff4, F(RR), 2, "dd", "13", TRICORE_RIDER_A, INDICES}, - {"abss.h", 1, 0x07d0000b, 0x082f0ff4, F(RR), 2, "dd", "13", + { "abss.h", 1, 0x07d0000b, 0x082f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"add", 0, 0x00000012, 0xffff00ed, F(SRR), 3, "did", "201", + { "add", 0, 0x00000012, 0xffff00ed, F(SRR), 3, "did", "201", TRICORE_RIDER_B_UP, INDICES}, - {"add", 0, 0x00000092, 0xffff006d, F(SRC), 3, "di4", "201", + { "add", 0, 0x00000092, 0xffff006d, F(SRC), 3, "di4", "201", TRICORE_RIDER_B_UP, INDICES}, - {"add", 0, 0x0000001a, 0xffff00e5, F(SRR), 3, "idd", "021", + { "add", 0, 0x0000001a, 0xffff00e5, F(SRR), 3, "idd", "021", TRICORE_GENERIC, INDICES}, - {"add", 0, 0x00000042, 0xffff00bd, F(SRR), 2, "dd", "21", + { "add", 0, 0x00000042, 0xffff00bd, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"add", 0, 0x0000009a, 0xffff0065, F(SRC), 3, "id4", "021", + { "add", 0, 0x0000009a, 0xffff0065, F(SRC), 3, "id4", "021", TRICORE_GENERIC, INDICES}, - {"add", 0, 0x000000c2, 0xffff003d, F(SRC), 2, "d4", "21", + { "add", 0, 0x000000c2, 0xffff003d, F(SRC), 2, "d4", "21", TRICORE_GENERIC, INDICES}, - {"add", 1, 0x0000000b, 0x0fff00f4, F(RR), 3, "ddd", "143", + { "add", 1, 0x0000000b, 0x0fff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"add", 1, 0x0000008b, 0x0fe00074, F(RC), 3, "dd9", "132", + { "add", 1, 0x0000008b, 0x0fe00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"add.a", 0, 0x00000030, 0xffff00cf, F(SRR), 2, "aa", "21", + { "add.a", 0, 0x00000030, 0xffff00cf, F(SRR), 2, "aa", "21", TRICORE_RIDER_B_UP, INDICES}, - {"add.a", 0, 0x000000b0, 0xffff004f, F(SRC), 2, "a4", "21", + { "add.a", 0, 0x000000b0, 0xffff004f, F(SRC), 2, "a4", "21", TRICORE_RIDER_B_UP, INDICES}, - {"add.a", 1, 0x00100001, 0x0fef00fe, F(RR), 3, "aaa", "143", + { "add.a", 1, 0x00100001, 0x0fef00fe, F(RR), 3, "aaa", "143", TRICORE_GENERIC, INDICES}, - {"add.b", 1, 0x0400000b, 0x0bff00f4, F(RR), 3, "ddd", "143", + { "add.b", 1, 0x0400000b, 0x0bff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"add.f", 1, 0x0021006b, 0x00def094, F(RRR), 3, "ddd", "125", + { "add.f", 1, 0x0021006b, 0x00def094, F(RRR), 3, "ddd", "125", TRICORE_RIDER_D_UP, INDICES}, - {"add.h", 1, 0x0600000b, 0x09ff00f4, F(RR), 3, "ddd", "143", + { "add.h", 1, 0x0600000b, 0x09ff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"addc", 1, 0x0050000b, 0x0faf00f4, F(RR), 3, "ddd", "143", + { "addc", 1, 0x0050000b, 0x0faf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"addc", 1, 0x00a0008b, 0x0f400074, F(RC), 3, "dd9", "132", + { "addc", 1, 0x00a0008b, 0x0f400074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"addi", 1, 0x0000001b, 0x000000e4, F(RLC), 3, "ddw", "132", + { "addi", 1, 0x0000001b, 0x000000e4, F(RLC), 3, "ddw", "132", TRICORE_GENERIC, INDICES}, - {"addih", 1, 0x0000009b, 0x00000064, F(RLC), 3, "ddW", "132", + { "addih", 1, 0x0000009b, 0x00000064, F(RLC), 3, "ddW", "132", TRICORE_GENERIC, INDICES}, - {"addih.a", 1, 0x00000011, 0x000000ee, F(RLC), 3, "aaW", "132", + { "addih.a", 1, 0x00000011, 0x000000ee, F(RLC), 3, "aaW", "132", TRICORE_GENERIC, INDICES}, - {"adds", 0, 0x00000022, 0xffff00dd, F(SRR), 2, "dd", "21", + { "adds", 0, 0x00000022, 0xffff00dd, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"adds", 1, 0x0020000b, 0x0fdf00f4, F(RR), 3, "ddd", "143", + { "adds", 1, 0x0020000b, 0x0fdf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"adds", 1, 0x0040008b, 0x0fa00074, F(RC), 3, "dd9", "132", + { "adds", 1, 0x0040008b, 0x0fa00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"adds.b", 1, 0x0420000b, 0x0bdf00f4, F(RR), 3, "ddd", "143", + { "adds.b", 1, 0x0420000b, 0x0bdf00f4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"adds.bu", 1, 0x0430000b, 0x0bcf00f4, F(RR), 3, "ddd", "143", + { "adds.bu", 1, 0x0430000b, 0x0bcf00f4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"adds.h", 1, 0x0620000b, 0x09df00f4, F(RR), 3, "ddd", "143", + { "adds.h", 1, 0x0620000b, 0x09df00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"adds.hu", 1, 0x0630000b, 0x09cf00f4, F(RR), 3, "ddd", "143", + { "adds.hu", 1, 0x0630000b, 0x09cf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"adds.u", 1, 0x0030000b, 0x0fcf00f4, F(RR), 3, "ddd", "143", + { "adds.u", 1, 0x0030000b, 0x0fcf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"adds.u", 1, 0x0060008b, 0x0f800074, F(RC), 3, "dd9", "132", + { "adds.u", 1, 0x0060008b, 0x0f800074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"addsc.a", 0, 0x00000010, 0xffff002f, F(SRRS), 3, "ad2", "213", + { "addsc.a", 0, 0x00000010, 0xffff002f, F(SRRS), 3, "ad2", "213", TRICORE_RIDER_A, INDICES}, - {"addsc.a", 0, 0x00000010, 0xffff002f, F(SRRS), 4, "aai2", "2103", + { "addsc.a", 0, 0x00000010, 0xffff002f, F(SRRS), 4, "aai2", "2103", TRICORE_RIDER_B_UP, INDICES}, - {"addsc.a", 1, 0x06000001, 0x09fc00fe, F(RR), 4, "aad2", "1432", + { "addsc.a", 1, 0x06000001, 0x09fc00fe, F(RR), 4, "aad2", "1432", TRICORE_RIDER_A, INDICES}, - {"addsc.a", 1, 0x06000001, 0x09fc00fe, F(RR), 4, "aad2", "1342", + { "addsc.a", 1, 0x06000001, 0x09fc00fe, F(RR), 4, "aad2", "1342", TRICORE_RIDER_B_UP, INDICES}, - {"addsc.a", 1, 0x06010001, 0x09fc00fe, F(RR), 4, "aad2", "1342", + { "addsc.a", 1, 0x06010001, 0x09fc00fe, F(RR), 4, "aad2", "1342", TRICORE_RIDER_B_UP, INDICES}, - {"addsc.a", 1, 0x06020001, 0x09fc00fe, F(RR), 4, "aad2", "1342", + { "addsc.a", 1, 0x06020001, 0x09fc00fe, F(RR), 4, "aad2", "1342", TRICORE_RIDER_B_UP, INDICES}, - {"addsc.a", 1, 0x06030001, 0x09fc00fe, F(RR), 4, "aad2", "1342", + { "addsc.a", 1, 0x06030001, 0x09fc00fe, F(RR), 4, "aad2", "1342", TRICORE_RIDER_B_UP, INDICES}, - {"addsc.at", 1, 0x06200001, 0x09df00fe, F(RR), 3, "aad", "143", + { "addsc.at", 1, 0x06200001, 0x09df00fe, F(RR), 3, "aad", "143", TRICORE_RIDER_A, INDICES}, - {"addsc.at", 1, 0x06200001, 0x09df00fe, F(RR), 3, "aad", "134", + { "addsc.at", 1, 0x06200001, 0x09df00fe, F(RR), 3, "aad", "134", TRICORE_RIDER_B_UP, INDICES}, - {"addx", 1, 0x0040000b, 0x0fbf00f4, F(RR), 3, "ddd", "143", + { "addx", 1, 0x0040000b, 0x0fbf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"addx", 1, 0x0080008b, 0x0f600074, F(RC), 3, "dd9", "132", + { "addx", 1, 0x0080008b, 0x0f600074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"and", 0, 0x00000016, 0xffff00e9, F(SRR), 2, "dd", "21", + { "and", 0, 0x00000016, 0xffff00e9, F(SRR), 2, "dd", "21", TRICORE_RIDER_A, INDICES}, - {"and", 0, 0x00000026, 0xffff00d9, F(SRR), 2, "dd", "21", + { "and", 0, 0x00000026, 0xffff00d9, F(SRR), 2, "dd", "21", TRICORE_RIDER_B_UP, INDICES}, - {"and", 0, 0x00000096, 0xffff0069, F(SC), 2, "i8", "01", + { "and", 0, 0x00000096, 0xffff0069, F(SC), 2, "i8", "01", TRICORE_RIDER_A, INDICES}, - {"and", 0, 0x00000016, 0xffff00e9, F(SC), 2, "i8", "01", + { "and", 0, 0x00000016, 0xffff00e9, F(SC), 2, "i8", "01", TRICORE_RIDER_B_UP, INDICES}, - {"and", 1, 0x0080000f, 0x0f7f00f0, F(RR), 3, "ddd", "143", + { "and", 1, 0x0080000f, 0x0f7f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and", 1, 0x0100008f, 0x0ee00070, F(RC), 3, "ddn", "132", + { "and", 1, 0x0100008f, 0x0ee00070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"and.and.t", 1, 0x00000047, 0x006000b8, F(BIT), 5, "dd5d5", "15342", + { "and.and.t", 1, 0x00000047, 0x006000b8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"and.andn.t", 1, 0x00600047, 0x000000b8, F(BIT), 5, "dd5d5", "15342", + { "and.andn.t", 1, 0x00600047, 0x000000b8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"and.eq", 1, 0x0200000b, 0x0dff00f4, F(RR), 3, "ddd", "143", + { "and.eq", 1, 0x0200000b, 0x0dff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.eq", 1, 0x0400008b, 0x0be00074, F(RC), 3, "dd9", "132", + { "and.eq", 1, 0x0400008b, 0x0be00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"and.ge", 1, 0x0240000b, 0x0dbf00f4, F(RR), 3, "ddd", "143", + { "and.ge", 1, 0x0240000b, 0x0dbf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.ge", 1, 0x0480008b, 0x0b600074, F(RC), 3, "dd9", "132", + { "and.ge", 1, 0x0480008b, 0x0b600074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"and.ge.u", 1, 0x0250000b, 0x0daf00f4, F(RR), 3, "ddd", "143", + { "and.ge.u", 1, 0x0250000b, 0x0daf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.ge.u", 1, 0x04a0008b, 0x0b400074, F(RC), 3, "ddn", "132", + { "and.ge.u", 1, 0x04a0008b, 0x0b400074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"and.lt", 1, 0x0220000b, 0x0ddf00f4, F(RR), 3, "ddd", "143", + { "and.lt", 1, 0x0220000b, 0x0ddf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.lt", 1, 0x0440008b, 0x0ba00074, F(RC), 3, "dd9", "132", + { "and.lt", 1, 0x0440008b, 0x0ba00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"and.lt.u", 1, 0x0230000b, 0x0dcf00f4, F(RR), 3, "ddd", "143", + { "and.lt.u", 1, 0x0230000b, 0x0dcf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.lt.u", 1, 0x0460008b, 0x0b800074, F(RC), 3, "ddn", "132", + { "and.lt.u", 1, 0x0460008b, 0x0b800074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"and.ne", 1, 0x0210000b, 0x0def00f4, F(RR), 3, "ddd", "143", + { "and.ne", 1, 0x0210000b, 0x0def00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"and.ne", 1, 0x0420008b, 0x0bc00074, F(RC), 3, "dd9", "132", + { "and.ne", 1, 0x0420008b, 0x0bc00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"and.nor.t", 1, 0x00400047, 0x002000b8, F(BIT), 5, "dd5d5", "15342", + { "and.nor.t", 1, 0x00400047, 0x002000b8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"and.or.t", 1, 0x00200047, 0x004000b8, F(BIT), 5, "dd5d5", "15342", + { "and.or.t", 1, 0x00200047, 0x004000b8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"and.t", 1, 0x00000087, 0x00600078, F(BIT), 5, "dd5d5", "15342", + { "and.t", 1, 0x00000087, 0x00600078, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"andn", 1, 0x00e0000f, 0x0f1f00f0, F(RR), 3, "ddd", "143", + { "andn", 1, 0x00e0000f, 0x0f1f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"andn", 1, 0x01c0008f, 0x0e200070, F(RC), 3, "ddn", "132", + { "andn", 1, 0x01c0008f, 0x0e200070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"andn.t", 1, 0x00600087, 0x00000078, F(BIT), 5, "dd5d5", "15342", + { "andn.t", 1, 0x00600087, 0x00000078, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"bisr", 0, 0x000000c0, 0xffff003f, F(SC), 1, "8", "1", + { "bisr", 0, 0x000000c0, 0xffff003f, F(SC), 1, "8", "1", TRICORE_RIDER_A, INDICES}, - {"bisr", 0, 0x000000e0, 0xffff001f, F(SC), 1, "8", "1", + { "bisr", 0, 0x000000e0, 0xffff001f, F(SC), 1, "8", "1", TRICORE_RIDER_B_UP, INDICES}, - {"bisr", 1, 0x000000ad, 0xffe00f52, F(RC), 1, "n", "2", + { "bisr", 1, 0x000000ad, 0xffe00f52, F(RC), 1, "n", "2", TRICORE_GENERIC, INDICES}, - {"bmerge", 1, 0x0000004b, 0x0fff00b4, F(RR), 3, "ddd", "143", + { "bmerge", 1, 0x0000004b, 0x0fff00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"bmerge", 1, 0x0010004b, 0x0fef00b4, F(RR), 3, "ddd", "143", + { "bmerge", 1, 0x0010004b, 0x0fef00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"bsplit", 1, 0x0600004b, 0x09fff0b4, F(RR), 2, "Dd", "14", + { "bsplit", 1, 0x0600004b, 0x09fff0b4, F(RR), 2, "Dd", "14", TRICORE_RIDER_A, INDICES}, - {"bsplit", 1, 0x0090004b, 0x0f6ff0b4, F(RR), 2, "Dd", "14", + { "bsplit", 1, 0x0090004b, 0x0f6ff0b4, F(RR), 2, "Dd", "14", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x03800089, 0x0c400f76, F(BO), 2, ">0", "21", + { "cachea.i", 1, 0x03800089, 0x0c400f76, F(BO), 2, ">0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x038000a9, 0xfc7f0f56, F(BO), 1, "#", "2", + { "cachea.i", 1, 0x038000a9, 0xfc7f0f56, F(BO), 1, "#", "2", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x07800089, 0x08400f76, F(BO), 2, "<0", "21", + { "cachea.i", 1, 0x07800089, 0x08400f76, F(BO), 2, "<0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x078000a9, 0x08400f56, F(BO), 2, "*0", "21", + { "cachea.i", 1, 0x078000a9, 0x08400f56, F(BO), 2, "*0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x0b800089, 0x04400f76, F(BO), 2, "@0", "21", + { "cachea.i", 1, 0x0b800089, 0x04400f76, F(BO), 2, "@0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.i", 1, 0x0b8000a9, 0xf47f0f56, F(BO), 1, "?", "2", + { "cachea.i", 1, 0x0b8000a9, 0xf47f0f56, F(BO), 1, "?", "2", TRICORE_V2_UP, INDICES}, - {"cachea.w", 1, 0x03000089, 0x0cc00f76, F(BO), 2, ">0", "21", + { "cachea.w", 1, 0x03000089, 0x0cc00f76, F(BO), 2, ">0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.w", 1, 0x030000a9, 0xfcff0f56, F(BO), 1, "#", "2", + { "cachea.w", 1, 0x030000a9, 0xfcff0f56, F(BO), 1, "#", "2", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.w", 1, 0x07000089, 0x08c00f76, F(BO), 2, "<0", "21", + { "cachea.w", 1, 0x07000089, 0x08c00f76, F(BO), 2, "<0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.w", 1, 0x070000a9, 0x08c00f56, F(BO), 2, "*0", "21", + { "cachea.w", 1, 0x070000a9, 0x08c00f56, F(BO), 2, "*0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.w", 1, 0x0b000089, 0x04c00f76, F(BO), 2, "@0", "21", + { "cachea.w", 1, 0x0b000089, 0x04c00f76, F(BO), 2, "@0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.w", 1, 0x0b0000a9, 0xf4ff0f56, F(BO), 1, "?", "2", + { "cachea.w", 1, 0x0b0000a9, 0xf4ff0f56, F(BO), 1, "?", "2", TRICORE_V2_UP, INDICES}, - {"cachea.wi", 1, 0x03400089, 0x0c800f76, F(BO), 2, ">0", "21", + { "cachea.wi", 1, 0x03400089, 0x0c800f76, F(BO), 2, ">0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.wi", 1, 0x034000a9, 0xfcbf0f56, F(BO), 1, "#", "2", + { "cachea.wi", 1, 0x034000a9, 0xfcbf0f56, F(BO), 1, "#", "2", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.wi", 1, 0x07400089, 0x08800f76, F(BO), 2, "<0", "21", + { "cachea.wi", 1, 0x07400089, 0x08800f76, F(BO), 2, "<0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.wi", 1, 0x074000a9, 0x08800f56, F(BO), 2, "*0", "21", + { "cachea.wi", 1, 0x074000a9, 0x08800f56, F(BO), 2, "*0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.wi", 1, 0x0b400089, 0x04800f76, F(BO), 2, "@0", "21", + { "cachea.wi", 1, 0x0b400089, 0x04800f76, F(BO), 2, "@0", "21", TRICORE_RIDER_B_UP, INDICES}, - {"cachea.wi", 1, 0x0b4000a9, 0xf4bf0f56, F(BO), 1, "?", "2", + { "cachea.wi", 1, 0x0b4000a9, 0xf4bf0f56, F(BO), 1, "?", "2", TRICORE_V2_UP, INDICES}, - {"cachei.w", 1, 0x02c00089, 0x0d000f76, F(BO), 2, ">0", "21", + { "cachei.w", 1, 0x02c00089, 0x0d000f76, F(BO), 2, ">0", "21", TRICORE_V2_UP, INDICES}, - {"cachei.w", 1, 0x06c00089, 0x09000f76, F(BO), 2, "<0", "21", + { "cachei.w", 1, 0x06c00089, 0x09000f76, F(BO), 2, "<0", "21", TRICORE_V2_UP, INDICES}, - {"cachei.w", 1, 0x0ac00089, 0x05000f76, F(BO), 2, "@0", "21", + { "cachei.w", 1, 0x0ac00089, 0x05000f76, F(BO), 2, "@0", "21", TRICORE_V2_UP, INDICES}, - {"cachei.wi", 1, 0x03c00089, 0x0c000f76, F(BO), 2, ">0", "21", + { "cachei.wi", 1, 0x03c00089, 0x0c000f76, F(BO), 2, ">0", "21", TRICORE_V2_UP, INDICES}, - {"cachei.wi", 1, 0x07c00089, 0x08000f76, F(BO), 2, "<0", "21", + { "cachei.wi", 1, 0x07c00089, 0x08000f76, F(BO), 2, "<0", "21", TRICORE_V2_UP, INDICES}, - {"cachei.wi", 1, 0x0bc00089, 0x04000f76, F(BO), 2, "@0", "21", + { "cachei.wi", 1, 0x0bc00089, 0x04000f76, F(BO), 2, "@0", "21", TRICORE_V2_UP, INDICES}, - {"cadd", 0, 0x0000000a, 0xffff00f5, F(SRR), 3, "did", "201", + { "cadd", 0, 0x0000000a, 0xffff00f5, F(SRR), 3, "did", "201", TRICORE_RIDER_A, INDICES}, - {"cadd", 0, 0x0000008a, 0xffff0075, F(SRC), 3, "di4", "201", + { "cadd", 0, 0x0000008a, 0xffff0075, F(SRC), 3, "di4", "201", TRICORE_GENERIC, INDICES}, - {"cadd", 1, 0x0000002b, 0x00ff00d4, F(RRR), 4, "dddd", "1254", + { "cadd", 1, 0x0000002b, 0x00ff00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"cadd", 1, 0x000000ab, 0x00e00054, F(RCR), 4, "ddd9", "1243", + { "cadd", 1, 0x000000ab, 0x00e00054, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"cadd.a", 1, 0x00000021, 0x00ff00de, F(RRR), 4, "adaa", "1254", + { "cadd.a", 1, 0x00000021, 0x00ff00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"cadd.a", 1, 0x000000a1, 0x00e0005e, F(RCR), 4, "ada9", "1243", + { "cadd.a", 1, 0x000000a1, 0x00e0005e, F(RCR), 4, "ada9", "1243", TRICORE_RIDER_A, INDICES}, - {"caddn", 0, 0x0000004a, 0xffff00b5, F(SRR), 3, "did", "201", + { "caddn", 0, 0x0000004a, 0xffff00b5, F(SRR), 3, "did", "201", TRICORE_RIDER_A, INDICES}, - {"caddn", 0, 0x000000ca, 0xffff0035, F(SRC), 3, "di4", "201", + { "caddn", 0, 0x000000ca, 0xffff0035, F(SRC), 3, "di4", "201", TRICORE_GENERIC, INDICES}, - {"caddn", 1, 0x0010002b, 0x00ef00d4, F(RRR), 4, "dddd", "1254", + { "caddn", 1, 0x0010002b, 0x00ef00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"caddn", 1, 0x002000ab, 0x00c00054, F(RCR), 4, "ddd9", "1243", + { "caddn", 1, 0x002000ab, 0x00c00054, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"caddn.a", 1, 0x00100021, 0x00ef00de, F(RRR), 4, "adaa", "1254", + { "caddn.a", 1, 0x00100021, 0x00ef00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"caddn.a", 1, 0x002000a1, 0x00c0005e, F(RCR), 4, "ada9", "1243", + { "caddn.a", 1, 0x002000a1, 0x00c0005e, F(RCR), 4, "ada9", "1243", TRICORE_RIDER_A, INDICES}, - {"call", 0, 0x0000005c, 0xffff00a3, F(SB), 1, "R", "1", + { "call", 0, 0x0000005c, 0xffff00a3, F(SB), 1, "R", "1", TRICORE_RIDER_B_UP, INDICES}, - {"call", 1, 0x0000006d, 0x00000092, F(B), 1, "O", "1", + { "call", 1, 0x0000006d, 0x00000092, F(B), 1, "O", "1", TRICORE_GENERIC, INDICES}, - {"calla", 1, 0x000000ed, 0x00000012, F(B), 1, "T", "1", + { "calla", 1, 0x000000ed, 0x00000012, F(B), 1, "T", "1", TRICORE_GENERIC, INDICES}, - {"calli", 1, 0x0000002d, 0xffff0fd2, F(RR), 1, "a", "3", + { "calli", 1, 0x0000002d, 0xffff0fd2, F(RR), 1, "a", "3", TRICORE_RIDER_A, INDICES}, - {"calli", 1, 0x0000002d, 0xfffff0d2, F(RR), 1, "a", "4", + { "calli", 1, 0x0000002d, 0xfffff0d2, F(RR), 1, "a", "4", TRICORE_RIDER_B_UP, INDICES}, - {"clo", 1, 0x01c0000f, 0x0e3ff0f0, F(RR), 2, "dd", "14", + { "clo", 1, 0x01c0000f, 0x0e3ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"clo.b", 1, 0x03d0000f, 0x0c2ff0f0, F(RR), 2, "dd", "14", + { "clo.b", 1, 0x03d0000f, 0x0c2ff0f0, F(RR), 2, "dd", "14", TRICORE_RIDER_A, INDICES}, - {"clo.h", 1, 0x07d0000f, 0x082ff0f0, F(RR), 2, "dd", "14", + { "clo.h", 1, 0x07d0000f, 0x082ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"cls", 1, 0x01d0000f, 0x0e2ff0f0, F(RR), 2, "dd", "14", + { "cls", 1, 0x01d0000f, 0x0e2ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"cls.b", 1, 0x03e0000f, 0x0c1ff0f0, F(RR), 2, "dd", "14", + { "cls.b", 1, 0x03e0000f, 0x0c1ff0f0, F(RR), 2, "dd", "14", TRICORE_RIDER_A, INDICES}, - {"cls.h", 1, 0x07e0000f, 0x081ff0f0, F(RR), 2, "dd", "14", + { "cls.h", 1, 0x07e0000f, 0x081ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"clz", 1, 0x01b0000f, 0x0e4ff0f0, F(RR), 2, "dd", "14", + { "clz", 1, 0x01b0000f, 0x0e4ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"clz.b", 1, 0x03c0000f, 0x0c3ff0f0, F(RR), 2, "dd", "14", + { "clz.b", 1, 0x03c0000f, 0x0c3ff0f0, F(RR), 2, "dd", "14", TRICORE_RIDER_A, INDICES}, - {"clz.h", 1, 0x07c0000f, 0x083ff0f0, F(RR), 2, "dd", "14", + { "clz.h", 1, 0x07c0000f, 0x083ff0f0, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"cmov", 0, 0x0000002a, 0xffff00d5, F(SRR), 3, "did", "201", + { "cmov", 0, 0x0000002a, 0xffff00d5, F(SRR), 3, "did", "201", TRICORE_GENERIC, INDICES}, - {"cmov", 0, 0x000000aa, 0xffff0055, F(SRC), 3, "di4", "201", + { "cmov", 0, 0x000000aa, 0xffff0055, F(SRC), 3, "di4", "201", TRICORE_GENERIC, INDICES}, - {"cmovn", 0, 0x0000006a, 0xffff0095, F(SRR), 3, "did", "201", + { "cmovn", 0, 0x0000006a, 0xffff0095, F(SRR), 3, "did", "201", TRICORE_GENERIC, INDICES}, - {"cmovn", 0, 0x000000ea, 0xffff0015, F(SRC), 3, "di4", "201", + { "cmovn", 0, 0x000000ea, 0xffff0015, F(SRC), 3, "di4", "201", TRICORE_GENERIC, INDICES}, - {"cmp.f", 1, 0x0001004b, 0x0ffe00b4, F(RR), 3, "ddd", "143", + { "cmp.f", 1, 0x0001004b, 0x0ffe00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_D_UP, INDICES}, - {"csub", 1, 0x0020002b, 0x00df00d4, F(RRR), 4, "dddd", "1254", + { "csub", 1, 0x0020002b, 0x00df00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"csub.a", 1, 0x00200021, 0x00df00de, F(RRR), 4, "adaa", "1254", + { "csub.a", 1, 0x00200021, 0x00df00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"csubn", 1, 0x0030002b, 0x00cf00d4, F(RRR), 4, "dddd", "1254", + { "csubn", 1, 0x0030002b, 0x00cf00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"csubn.a", 1, 0x00300021, 0x00cf00de, F(RRR), 4, "adaa", "1254", + { "csubn.a", 1, 0x00300021, 0x00cf00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"debug", 0, 0x0000a000, 0xffff5fff, F(SR), 0, "", "", + { "debug", 0, 0x0000a000, 0xffff5fff, F(SR), 0, "", "", TRICORE_GENERIC, INDICES}, - {"debug", 1, 0x0100000d, 0xfefffff2, F(SYS), 0, "", "", + { "debug", 1, 0x0100000d, 0xfefffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"dextr", 1, 0x00000077, 0x007f0088, F(RRPW), 4, "ddd5", "1542", + { "dextr", 1, 0x00000077, 0x007f0088, F(RRPW), 4, "ddd5", "1542", TRICORE_GENERIC, INDICES}, - {"dextr", 1, 0x00800017, 0x007f00e8, F(RRRR), 4, "dddd", "1432", + { "dextr", 1, 0x00800017, 0x007f00e8, F(RRRR), 4, "dddd", "1432", TRICORE_GENERIC, INDICES}, - {"difsc.a", 1, 0x05000001, 0x0afc00fe, F(RR), 4, "daa2", "1432", + { "difsc.a", 1, 0x05000001, 0x0afc00fe, F(RR), 4, "daa2", "1432", TRICORE_RIDER_A, INDICES}, - {"disable", 1, 0x0340000d, 0xfcbffff2, F(SYS), 0, "", "", + { "disable", 1, 0x0340000d, 0xfcbffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"disable", 1, 0x03c0000d, 0xfc3ff0f2, F(SYS), 1, "d", "1", + { "disable", 1, 0x03c0000d, 0xfc3ff0f2, F(SYS), 1, "d", "1", TRICORE_V2_UP, INDICES}, - {"div.f", 1, 0x0051004b, 0x0fae00b4, F(RR), 3, "ddd", "143", + { "div.f", 1, 0x0051004b, 0x0fae00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_D_UP, INDICES}, - {"dsync", 1, 0x0480000d, 0xfb7ffff2, F(SYS), 0, "", "", + { "dsync", 1, 0x0480000d, 0xfb7ffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"dvadj", 0, 0x00000072, 0xffff008d, F(SRR), 2, "Dd", "21", + { "dvadj", 0, 0x00000072, 0xffff008d, F(SRR), 2, "Dd", "21", TRICORE_RIDER_A, INDICES}, - {"dvadj", 1, 0x0080002b, 0x007f0fd4, F(RRR), 3, "DDd", "124", + { "dvadj", 1, 0x0080002b, 0x007f0fd4, F(RRR), 3, "DDd", "124", TRICORE_RIDER_A, INDICES}, - {"dvadj", 1, 0x00d0006b, 0x002f0f94, F(RRR), 3, "DDd", "124", + { "dvadj", 1, 0x00d0006b, 0x002f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit", 1, 0x0000004f, 0x0fff00b0, F(RR), 3, "Ddd", "143", + { "dvinit", 1, 0x0000004f, 0x0fff00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit", 1, 0x01a0004b, 0x0e5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit", 1, 0x01a0004b, 0x0e5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit.b", 1, 0x0040004f, 0x0fbf00b0, F(RR), 3, "Ddd", "143", + { "dvinit.b", 1, 0x0040004f, 0x0fbf00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit.b", 1, 0x05a0004b, 0x0a5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit.b", 1, 0x05a0004b, 0x0a5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit.bu", 1, 0x0050004f, 0x0faf00b0, F(RR), 3, "Ddd", "143", + { "dvinit.bu", 1, 0x0050004f, 0x0faf00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit.bu", 1, 0x04a0004b, 0x0b5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit.bu", 1, 0x04a0004b, 0x0b5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit.h", 1, 0x0020004f, 0x0fdf00b0, F(RR), 3, "Ddd", "143", + { "dvinit.h", 1, 0x0020004f, 0x0fdf00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit.h", 1, 0x03a0004b, 0x0c5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit.h", 1, 0x03a0004b, 0x0c5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit.hu", 1, 0x0030004f, 0x0fcf00b0, F(RR), 3, "Ddd", "143", + { "dvinit.hu", 1, 0x0030004f, 0x0fcf00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit.hu", 1, 0x02a0004b, 0x0d5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit.hu", 1, 0x02a0004b, 0x0d5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvinit.u", 1, 0x0010004f, 0x0fef00b0, F(RR), 3, "Ddd", "143", + { "dvinit.u", 1, 0x0010004f, 0x0fef00b0, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"dvinit.u", 1, 0x00a0004b, 0x0f5f00b4, F(RR), 3, "Ddd", "143", + { "dvinit.u", 1, 0x00a0004b, 0x0f5f00b4, F(RR), 3, "Ddd", "143", TRICORE_RIDER_B_UP, INDICES}, - {"dvstep", 0, 0x00000032, 0xffff00cd, F(SRR), 2, "Dd", "21", + { "dvstep", 0, 0x00000032, 0xffff00cd, F(SRR), 2, "Dd", "21", TRICORE_RIDER_A, INDICES}, - {"dvstep", 1, 0x0090002b, 0x006f0fd4, F(RRR), 3, "DDd", "124", + { "dvstep", 1, 0x0090002b, 0x006f0fd4, F(RRR), 3, "DDd", "124", TRICORE_RIDER_A, INDICES}, - {"dvstep", 1, 0x00f0006b, 0x000f0f94, F(RRR), 3, "DDd", "124", + { "dvstep", 1, 0x00f0006b, 0x000f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_B_UP, INDICES}, - {"dvstep.u", 0, 0x000000b2, 0xffff004d, F(SRR), 2, "Dd", "21", + { "dvstep.u", 0, 0x000000b2, 0xffff004d, F(SRR), 2, "Dd", "21", TRICORE_RIDER_A, INDICES}, - {"dvstep.u", 1, 0x00a0002b, 0x005f0fd4, F(RRR), 3, "DDd", "124", + { "dvstep.u", 1, 0x00a0002b, 0x005f0fd4, F(RRR), 3, "DDd", "124", TRICORE_RIDER_A, INDICES}, - {"dvstep.u", 1, 0x00e0006b, 0x001f0f94, F(RRR), 3, "DDd", "124", + { "dvstep.u", 1, 0x00e0006b, 0x001f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_B_UP, INDICES}, - {"enable", 1, 0x0300000d, 0xfcfffff2, F(SYS), 0, "", "", + { "enable", 1, 0x0300000d, 0xfcfffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"eq", 0, 0x0000003a, 0xffff00c5, F(SRR), 3, "idd", "021", + { "eq", 0, 0x0000003a, 0xffff00c5, F(SRR), 3, "idd", "021", TRICORE_GENERIC, INDICES}, - {"eq", 0, 0x000000ba, 0xffff0045, F(SRC), 3, "id4", "021", + { "eq", 0, 0x000000ba, 0xffff0045, F(SRC), 3, "id4", "021", TRICORE_GENERIC, INDICES}, - {"eq", 1, 0x0100000b, 0x0eff00f4, F(RR), 3, "ddd", "143", + { "eq", 1, 0x0100000b, 0x0eff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eq", 1, 0x0200008b, 0x0de00074, F(RC), 3, "dd9", "132", + { "eq", 1, 0x0200008b, 0x0de00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"eq.a", 1, 0x04000001, 0x0bff00fe, F(RR), 3, "daa", "143", + { "eq.a", 1, 0x04000001, 0x0bff00fe, F(RR), 3, "daa", "143", TRICORE_GENERIC, INDICES}, - {"eq.b", 1, 0x0500000b, 0x0aff00f4, F(RR), 3, "ddd", "143", + { "eq.b", 1, 0x0500000b, 0x0aff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eq.h", 1, 0x0700000b, 0x08ff00f4, F(RR), 3, "ddd", "143", + { "eq.h", 1, 0x0700000b, 0x08ff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eq.w", 1, 0x0900000b, 0x06ff00f4, F(RR), 3, "ddd", "143", + { "eq.w", 1, 0x0900000b, 0x06ff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eqany.b", 1, 0x0560000b, 0x0a9f00f4, F(RR), 3, "ddd", "143", + { "eqany.b", 1, 0x0560000b, 0x0a9f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eqany.b", 1, 0x0ac0008b, 0x05200074, F(RC), 3, "dd9", "132", + { "eqany.b", 1, 0x0ac0008b, 0x05200074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"eqany.h", 1, 0x0760000b, 0x089f00f4, F(RR), 3, "ddd", "143", + { "eqany.h", 1, 0x0760000b, 0x089f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"eqany.h", 1, 0x0ec0008b, 0x01200074, F(RC), 3, "dd9", "132", + { "eqany.h", 1, 0x0ec0008b, 0x01200074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"eqz.a", 1, 0x04800001, 0x0b7ff0fe, F(RR), 2, "da", "14", + { "eqz.a", 1, 0x04800001, 0x0b7ff0fe, F(RR), 2, "da", "14", TRICORE_GENERIC, INDICES}, - {"extr", 1, 0x00400017, 0x00bff0e8, F(RRRR), 3, "ddD", "142", + { "extr", 1, 0x00400017, 0x00bff0e8, F(RRRR), 3, "ddD", "142", TRICORE_GENERIC, INDICES}, - {"extr", 1, 0x00400037, 0x0020f0c8, F(RRPW), 4, "dd55", "1523", + { "extr", 1, 0x00400037, 0x0020f0c8, F(RRPW), 4, "dd55", "1523", TRICORE_GENERIC, INDICES}, - {"extr", 1, 0x00400057, 0x00a0f0a8, F(RRRW), 4, "ddd5", "1523", + { "extr", 1, 0x00400057, 0x00a0f0a8, F(RRRW), 4, "ddd5", "1523", TRICORE_GENERIC, INDICES}, - {"extr.u", 1, 0x00600017, 0x009ff0e8, F(RRRR), 3, "ddD", "142", + { "extr.u", 1, 0x00600017, 0x009ff0e8, F(RRRR), 3, "ddD", "142", TRICORE_GENERIC, INDICES}, - {"extr.u", 1, 0x00600037, 0x0000f0c8, F(RRPW), 4, "dd55", "1523", + { "extr.u", 1, 0x00600037, 0x0000f0c8, F(RRPW), 4, "dd55", "1523", TRICORE_GENERIC, INDICES}, - {"extr.u", 1, 0x00600057, 0x0080f0a8, F(RRRW), 4, "ddd5", "1523", + { "extr.u", 1, 0x00600057, 0x0080f0a8, F(RRRW), 4, "ddd5", "1523", TRICORE_GENERIC, INDICES}, - {"fcall", 1, 0x00000061, 0x0000009e, F(B), 1, "O", "1", + { "fcall", 1, 0x00000061, 0x0000009e, F(B), 1, "O", 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1, 0x0280008b, 0x0d600074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"ge.a", 1, 0x04300001, 0x0bcf00fe, F(RR), 3, "daa", "143", + { "ge.a", 1, 0x04300001, 0x0bcf00fe, F(RR), 3, "daa", "143", TRICORE_GENERIC, INDICES}, - {"ge.u", 1, 0x0150000b, 0x0eaf00f4, F(RR), 3, "ddd", "143", + { "ge.u", 1, 0x0150000b, 0x0eaf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"ge.u", 1, 0x02a0008b, 0x0d400074, F(RC), 3, "ddn", "132", + { "ge.u", 1, 0x02a0008b, 0x0d400074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"imask", 1, 0x00200037, 0x00400fc8, F(RRPW), 4, "Dd55", "1423", + { "imask", 1, 0x00200037, 0x00400fc8, F(RRPW), 4, "Dd55", "1423", TRICORE_GENERIC, INDICES}, - {"imask", 1, 0x00200057, 0x00c00fa8, F(RRRW), 4, "Ddd5", "1423", + { "imask", 1, 0x00200057, 0x00c00fa8, F(RRRW), 4, "Ddd5", "1423", TRICORE_GENERIC, INDICES}, - {"imask", 1, 0x002000b7, 0x00400f48, F(RCPW), 4, "Df55", "1423", + { "imask", 1, 0x002000b7, 0x00400f48, F(RCPW), 4, "Df55", "1423", TRICORE_GENERIC, INDICES}, - {"imask", 1, 0x002000d7, 0x00c00f28, F(RCRW), 4, "Dfd5", "1423", + { "imask", 1, 0x002000d7, 0x00c00f28, F(RCRW), 4, "Dfd5", "1423", TRICORE_GENERIC, INDICES}, - {"ins.t", 1, 0x00000067, 0x00600098, F(BIT), 5, "dd5d5", "15342", + { "ins.t", 1, 0x00000067, 0x00600098, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x00000017, 0x00ff00e8, F(RRRR), 4, "dddD", "1432", + { "insert", 1, 0x00000017, 0x00ff00e8, F(RRRR), 4, "dddD", "1432", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x00000037, 0x006000c8, F(RRPW), 5, "ddd55", "15423", + { "insert", 1, 0x00000037, 0x006000c8, F(RRPW), 5, "ddd55", "15423", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x00000057, 0x00e000a8, F(RRRW), 5, "dddd5", "15423", + { "insert", 1, 0x00000057, 0x00e000a8, F(RRRW), 5, "dddd5", "15423", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x00000097, 0x00ff0068, F(RCRR), 4, "ddfD", "1432", + { "insert", 1, 0x00000097, 0x00ff0068, F(RCRR), 4, "ddfD", "1432", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x000000b7, 0x00600048, F(RCPW), 5, "ddf55", "15423", + { "insert", 1, 0x000000b7, 0x00600048, F(RCPW), 5, "ddf55", "15423", TRICORE_GENERIC, INDICES}, - {"insert", 1, 0x000000d7, 0x00e00028, F(RCRW), 5, "ddfd5", "15423", + { "insert", 1, 0x000000d7, 0x00e00028, F(RCRW), 5, "ddfd5", "15423", TRICORE_GENERIC, INDICES}, - {"insn.t", 1, 0x00200067, 0x00400098, F(BIT), 5, "dd5d5", "15342", + { "insn.t", 1, 0x00200067, 0x00400098, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"isync", 1, 0x04c0000d, 0xfb3ffff2, F(SYS), 0, "", "", + { "isync", 1, 0x04c0000d, 0xfb3ffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"itof", 1, 0x0141004b, 0x0ebef0b4, F(RR), 2, "dd", "14", + { "itof", 1, 0x0141004b, 0x0ebef0b4, F(RR), 2, "dd", "14", TRICORE_RIDER_D_UP, INDICES}, - {"ixmax", 1, 0x00a0006b, 0x005f0f94, F(RRR), 3, "DDd", "124", + { "ixmax", 1, 0x00a0006b, 0x005f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_D_UP, INDICES}, - {"ixmax.u", 1, 0x00b0006b, 0x004f0f94, F(RRR), 3, "DDd", "124", + { "ixmax.u", 1, 0x00b0006b, 0x004f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_D_UP, INDICES}, - {"ixmin", 1, 0x0080006b, 0x007f0f94, F(RRR), 3, "DDd", "124", + { "ixmin", 1, 0x0080006b, 0x007f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_D_UP, INDICES}, - {"ixmin.u", 1, 0x0090006b, 0x006f0f94, F(RRR), 3, "DDd", "124", + { "ixmin.u", 1, 0x0090006b, 0x006f0f94, F(RRR), 3, "DDd", "124", TRICORE_RIDER_D_UP, INDICES}, - {"j", 0, 0x0000005c, 0xffff00a3, F(SB), 1, "R", "1", + { "j", 0, 0x0000005c, 0xffff00a3, F(SB), 1, "R", "1", TRICORE_RIDER_A, INDICES}, - {"j", 0, 0x0000003c, 0xffff00c3, F(SB), 1, "R", "1", + { "j", 0, 0x0000003c, 0xffff00c3, F(SB), 1, "R", "1", TRICORE_RIDER_B_UP, INDICES}, - {"j", 1, 0x0000001d, 0x000000e2, F(B), 1, "O", "1", + { "j", 1, 0x0000001d, 0x000000e2, F(B), 1, "O", "1", TRICORE_GENERIC, INDICES}, - {"ja", 1, 0x0000009d, 0x00000062, F(B), 1, "T", "1", + { "ja", 1, 0x0000009d, 0x00000062, F(B), 1, "T", "1", TRICORE_GENERIC, INDICES}, - {"jeq", 0, 0x0000001e, 0xffff00e1, F(SBR), 3, "idm", "012", + { "jeq", 0, 0x0000001e, 0xffff00e1, F(SBR), 3, "idm", "012", TRICORE_RIDER_A, INDICES}, - {"jeq", 0, 0x0000006e, 0xffff0091, F(SBC), 3, "i4m", "012", + { "jeq", 0, 0x0000006e, 0xffff0091, F(SBC), 3, "i4m", "012", TRICORE_RIDER_A, INDICES}, - {"jeq", 0, 0x000000be, 0xffff0041, F(SBR), 3, "idx", "012", + { "jeq", 0, 0x000000be, 0xffff0041, F(SBR), 3, "idx", "012", TRICORE_V2_UP, INDICES}, - {"jeq", 0, 0x0000009e, 0xffff0061, F(SBC), 3, "i4x", "012", + { "jeq", 0, 0x0000009e, 0xffff0061, F(SBC), 3, "i4x", "012", TRICORE_V2_UP, INDICES}, - {"jeq", 0, 0x0000003e, 0xffff00c1, F(SBR), 3, "idm", "012", + { "jeq", 0, 0x0000003e, 0xffff00c1, F(SBR), 3, "idm", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jeq", 0, 0x0000001e, 0xffff00e1, F(SBC), 3, "i4m", "012", + { "jeq", 0, 0x0000001e, 0xffff00e1, F(SBC), 3, "i4m", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jeq", 1, 0x0000005f, 0x800000a0, F(BRR), 3, "ddo", "321", + { "jeq", 1, 0x0000005f, 0x800000a0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jeq", 1, 0x000000df, 0x80000020, F(BRC), 3, "d4o", "321", + { "jeq", 1, 0x000000df, 0x80000020, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jeq.a", 1, 0x0000007d, 0x80000082, F(BRR), 3, "aao", "321", + { "jeq.a", 1, 0x0000007d, 0x80000082, F(BRR), 3, "aao", "321", TRICORE_GENERIC, INDICES}, - {"jge", 1, 0x0000007f, 0x80000080, F(BRR), 3, "ddo", "321", + { "jge", 1, 0x0000007f, 0x80000080, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jge", 1, 0x000000ff, 0x80000000, F(BRC), 3, "d4o", "321", + { "jge", 1, 0x000000ff, 0x80000000, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jge.u", 1, 0x8000007f, 0x00000080, F(BRR), 3, "ddo", "321", + { "jge.u", 1, 0x8000007f, 0x00000080, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jge.u", 1, 0x800000ff, 0x00000000, F(BRC), 3, "dfo", "321", + { "jge.u", 1, 0x800000ff, 0x00000000, F(BRC), 3, "dfo", "321", TRICORE_GENERIC, INDICES}, - {"jgez", 0, 0x000000fe, 0xffff0001, F(SBR), 2, "dm", "12", + { "jgez", 0, 0x000000fe, 0xffff0001, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jgez", 0, 0x000000ce, 0xffff0031, F(SBR), 2, "dm", "12", + { "jgez", 0, 0x000000ce, 0xffff0031, F(SBR), 2, "dm", "12", TRICORE_RIDER_B_UP, INDICES}, - {"jgtz", 0, 0x0000007e, 0xffff0081, F(SBR), 2, "dm", "12", + { "jgtz", 0, 0x0000007e, 0xffff0081, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jgtz", 0, 0x0000004e, 0xffff00b1, F(SBR), 2, "dm", "12", + { "jgtz", 0, 0x0000004e, 0xffff00b1, F(SBR), 2, "dm", "12", TRICORE_RIDER_D_DN, INDICES}, - {"jgtz", 0, 0x0000004e, 0xffff0031, F(SBR), 2, "dm", "12", + { "jgtz", 0, 0x0000004e, 0xffff0031, F(SBR), 2, "dm", "12", TRICORE_V2_UP, INDICES}, - {"ji", 0, 0x0000003c, 0xffff0fc3, F(SBR), 1, "a", "1", + { "ji", 0, 0x0000003c, 0xffff0fc3, F(SBR), 1, "a", "1", TRICORE_RIDER_A, INDICES}, - {"ji", 0, 0x000000dc, 0xfffff023, F(SR), 1, "a", "1", + { "ji", 0, 0x000000dc, 0xfffff023, F(SR), 1, "a", "1", TRICORE_RIDER_B_UP, INDICES}, - {"ji", 1, 0x0030002d, 0xffcf0fd2, F(RR), 1, "a", "3", + { "ji", 1, 0x0030002d, 0xffcf0fd2, F(RR), 1, "a", "3", TRICORE_RIDER_A, INDICES}, - {"ji", 1, 0x0030002d, 0xffcff0d2, F(RR), 1, "a", "4", + { "ji", 1, 0x0030002d, 0xffcff0d2, F(RR), 1, "a", "4", TRICORE_RIDER_B_UP, INDICES}, - {"jl", 1, 0x0000005d, 0x000000a2, F(B), 1, "O", "1", + { "jl", 1, 0x0000005d, 0x000000a2, F(B), 1, "O", "1", TRICORE_GENERIC, INDICES}, - {"jla", 1, 0x000000dd, 0x00000022, F(B), 1, "T", "1", + { "jla", 1, 0x000000dd, 0x00000022, F(B), 1, "T", "1", TRICORE_GENERIC, INDICES}, - {"jlez", 0, 0x000000be, 0xffff0041, F(SBR), 2, "dm", "12", + { "jlez", 0, 0x000000be, 0xffff0041, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jlez", 0, 0x0000008e, 0xffff0071, F(SBR), 2, "dm", "12", + { "jlez", 0, 0x0000008e, 0xffff0071, F(SBR), 2, "dm", "12", TRICORE_RIDER_B_UP, INDICES}, - {"jli", 1, 0x0020002d, 0xffdf0fd2, F(RR), 1, "a", "3", + { "jli", 1, 0x0020002d, 0xffdf0fd2, F(RR), 1, "a", "3", TRICORE_RIDER_A, INDICES}, - {"jli", 1, 0x0020002d, 0xffdff0d2, F(RR), 1, "a", "4", + { "jli", 1, 0x0020002d, 0xffdff0d2, F(RR), 1, "a", "4", TRICORE_RIDER_B_UP, INDICES}, - {"jlt", 1, 0x0000003f, 0x800000c0, F(BRR), 3, "ddo", "321", + { "jlt", 1, 0x0000003f, 0x800000c0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jlt", 1, 0x000000bf, 0x80000040, F(BRC), 3, "d4o", "321", + { "jlt", 1, 0x000000bf, 0x80000040, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jlt.u", 1, 0x8000003f, 0x000000c0, F(BRR), 3, "ddo", "321", + { "jlt.u", 1, 0x8000003f, 0x000000c0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jlt.u", 1, 0x800000bf, 0x00000040, F(BRC), 3, "dfo", "321", + { "jlt.u", 1, 0x800000bf, 0x00000040, F(BRC), 3, "dfo", "321", TRICORE_GENERIC, INDICES}, - {"jltz", 0, 0x0000003e, 0xffff00c1, F(SBR), 2, "dm", "12", + { "jltz", 0, 0x0000003e, 0xffff00c1, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jltz", 0, 0x0000000e, 0xffff00f1, F(SBR), 2, "dm", "12", + { "jltz", 0, 0x0000000e, 0xffff00f1, F(SBR), 2, "dm", "12", TRICORE_RIDER_D_DN, INDICES}, - {"jltz", 0, 0x0000000e, 0xffff0071, F(SBR), 2, "dm", "12", + { "jltz", 0, 0x0000000e, 0xffff0071, F(SBR), 2, "dm", "12", TRICORE_V2_UP, INDICES}, - {"jne", 0, 0x0000009e, 0xffff0061, F(SBR), 3, "idm", "012", + { "jne", 0, 0x0000009e, 0xffff0061, F(SBR), 3, "idm", "012", TRICORE_RIDER_A, INDICES}, - {"jne", 0, 0x000000ee, 0xffff0011, F(SBC), 3, "i4m", "012", + { "jne", 0, 0x000000ee, 0xffff0011, F(SBC), 3, "i4m", "012", TRICORE_RIDER_A, INDICES}, - {"jne", 0, 0x000000fe, 0xffff0001, F(SBR), 3, "idx", "012", + { "jne", 0, 0x000000fe, 0xffff0001, F(SBR), 3, "idx", "012", TRICORE_V2_UP, INDICES}, - {"jne", 0, 0x000000de, 0xffff0021, F(SBC), 3, "i4x", "012", + { "jne", 0, 0x000000de, 0xffff0021, F(SBC), 3, "i4x", "012", TRICORE_V2_UP, INDICES}, - {"jne", 0, 0x0000007e, 0xffff0081, F(SBR), 3, "idm", "012", + { "jne", 0, 0x0000007e, 0xffff0081, F(SBR), 3, "idm", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jne", 0, 0x0000005e, 0xffff00a1, F(SBC), 3, "i4m", "012", + { "jne", 0, 0x0000005e, 0xffff00a1, F(SBC), 3, "i4m", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jne", 1, 0x8000005f, 0x000000a0, F(BRR), 3, "ddo", "321", + { "jne", 1, 0x8000005f, 0x000000a0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jne", 1, 0x800000df, 0x00000020, F(BRC), 3, "d4o", "321", + { "jne", 1, 0x800000df, 0x00000020, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jne.a", 1, 0x8000007d, 0x00000082, F(BRR), 3, "aao", "321", + { "jne.a", 1, 0x8000007d, 0x00000082, F(BRR), 3, "aao", "321", TRICORE_GENERIC, INDICES}, - {"jned", 1, 0x8000001f, 0x000000e0, F(BRR), 3, "ddo", "321", + { "jned", 1, 0x8000001f, 0x000000e0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jned", 1, 0x8000009f, 0x00000060, F(BRC), 3, "d4o", "321", + { "jned", 1, 0x8000009f, 0x00000060, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jnei", 1, 0x0000001f, 0x800000e0, F(BRR), 3, "ddo", "321", + { "jnei", 1, 0x0000001f, 0x800000e0, F(BRR), 3, "ddo", "321", TRICORE_GENERIC, INDICES}, - {"jnei", 1, 0x0000009f, 0x80000060, F(BRC), 3, "d4o", "321", + { "jnei", 1, 0x0000009f, 0x80000060, F(BRC), 3, "d4o", "321", TRICORE_GENERIC, INDICES}, - {"jnz", 0, 0x000000ae, 0xffff0051, F(SB), 2, "iR", "01", + { "jnz", 0, 0x000000ae, 0xffff0051, F(SB), 2, "iR", "01", TRICORE_RIDER_A, INDICES}, - {"jnz", 0, 0x000000ee, 0xffff0011, F(SB), 2, "iR", "01", + { "jnz", 0, 0x000000ee, 0xffff0011, F(SB), 2, "iR", "01", TRICORE_RIDER_B_UP, INDICES}, - {"jnz", 0, 0x000000de, 0xffff0021, F(SBR), 2, "dm", "12", + { "jnz", 0, 0x000000de, 0xffff0021, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jnz", 0, 0x000000f6, 0xffff0009, F(SBR), 2, "dm", "12", + { "jnz", 0, 0x000000f6, 0xffff0009, F(SBR), 2, "dm", "12", TRICORE_RIDER_B_UP, INDICES}, - {"jnz.a", 0, 0x0000007c, 0xffff0083, F(SBR), 2, "am", "12", + { "jnz.a", 0, 0x0000007c, 0xffff0083, F(SBR), 2, "am", "12", TRICORE_RIDER_A | TRICORE_RIDER_D_DN, INDICES}, - {"jnz.a", 0, 0x0000007c, 0xffff0003, F(SBR), 2, "am", "12", + { "jnz.a", 0, 0x0000007c, 0xffff0003, F(SBR), 2, "am", "12", TRICORE_V2_UP, INDICES}, - {"jnz.a", 1, 0x800000bd, 0x0000f042, F(BRR), 2, "ao", "31", + { "jnz.a", 1, 0x800000bd, 0x0000f042, F(BRR), 2, "ao", "31", TRICORE_GENERIC, INDICES}, - {"jnz.t", 0, 0x0000004e, 0xffff0031, F(SBRN), 3, "i5m", "012", + { "jnz.t", 0, 0x0000004e, 0xffff0031, F(SBRN), 3, "i5m", "012", TRICORE_RIDER_A, INDICES}, - {"jnz.t", 0, 0x000000ae, 0xffff0051, F(SBRN), 3, "ifm", "012", + { "jnz.t", 0, 0x000000ae, 0xffff0051, F(SBRN), 3, "ifm", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jnz.t", 1, 0x8000006f, 0x00000010, F(BRN), 3, "d5o", "321", + { "jnz.t", 1, 0x8000006f, 0x00000010, F(BRN), 3, "d5o", "321", TRICORE_GENERIC, INDICES}, - {"jz", 0, 0x0000002e, 0xffff00d1, F(SB), 2, "iR", "01", + { "jz", 0, 0x0000002e, 0xffff00d1, F(SB), 2, "iR", "01", TRICORE_RIDER_A, INDICES}, - {"jz", 0, 0x0000006e, 0xffff0091, F(SB), 2, "iR", "01", + { "jz", 0, 0x0000006e, 0xffff0091, F(SB), 2, "iR", "01", TRICORE_RIDER_B_UP, INDICES}, - {"jz", 0, 0x0000005e, 0xffff00a1, F(SBR), 2, "dm", "12", + { "jz", 0, 0x0000005e, 0xffff00a1, F(SBR), 2, "dm", "12", TRICORE_RIDER_A, INDICES}, - {"jz", 0, 0x00000076, 0xffff0089, F(SBR), 2, "dm", "12", + { "jz", 0, 0x00000076, 0xffff0089, F(SBR), 2, "dm", "12", TRICORE_RIDER_D_DN, INDICES}, - {"jz", 0, 0x00000076, 0xffff0009, F(SBR), 2, "dm", "12", + { "jz", 0, 0x00000076, 0xffff0009, F(SBR), 2, "dm", "12", TRICORE_V2_UP, INDICES}, - {"jz.a", 0, 0x000000bc, 0xffff0043, F(SBR), 2, "am", "12", + { "jz.a", 0, 0x000000bc, 0xffff0043, F(SBR), 2, "am", "12", TRICORE_GENERIC, INDICES}, - {"jz.a", 1, 0x000000bd, 0x8000f042, F(BRR), 2, "ao", "31", + { "jz.a", 1, 0x000000bd, 0x8000f042, F(BRR), 2, "ao", "31", TRICORE_GENERIC, INDICES}, - {"jz.t", 0, 0x0000000e, 0xffff0071, F(SBRN), 3, "i5m", "012", + { "jz.t", 0, 0x0000000e, 0xffff0071, F(SBRN), 3, "i5m", "012", TRICORE_RIDER_A, INDICES}, - {"jz.t", 0, 0x0000002e, 0xffff00d1, F(SBRN), 3, "ifm", "012", + { "jz.t", 0, 0x0000002e, 0xffff00d1, F(SBRN), 3, "ifm", "012", TRICORE_RIDER_B_UP, INDICES}, - {"jz.t", 1, 0x0000006f, 0x80000010, F(BRN), 3, "d5o", "321", + { "jz.t", 1, 0x0000006f, 0x80000010, F(BRN), 3, "d5o", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 0, 0x000000d8, 0xffff0027, F(SC), 3, "I&k", "001", + { "ld.a", 0, 0x000000d8, 0xffff0027, F(SC), 3, "I&k", "001", TRICORE_RIDER_B_UP, INDICES}, - {"ld.a", 0, 0x0000000c, 0xffff00f3, F(SLRO), 3, "aS6", "201", + { "ld.a", 0, 0x0000000c, 0xffff00f3, F(SLRO), 3, "aS6", "201", TRICORE_RIDER_A, INDICES}, - {"ld.a", 0, 0x000000c8, 0xffff0037, F(SLRO), 3, "aS6", "201", + { "ld.a", 0, 0x000000c8, 0xffff0037, F(SLRO), 3, "aS6", "201", TRICORE_RIDER_B_UP, INDICES}, - {"ld.a", 0, 0x00000028, 0xffff00d7, F(SRO), 3, "I@6", "012", + { "ld.a", 0, 0x00000028, 0xffff00d7, F(SRO), 3, "I@6", "012", TRICORE_RIDER_A, INDICES}, - {"ld.a", 0, 0x000000cc, 0xffff0033, F(SRO), 3, "I@6", "012", + { "ld.a", 0, 0x000000cc, 0xffff0033, F(SRO), 3, "I@6", "012", TRICORE_RIDER_B_UP, INDICES}, - {"ld.a", 0, 0x00000064, 0xffff009b, F(SLR), 2, "a>", "21", + { "ld.a", 0, 0x00000064, 0xffff009b, F(SLR), 2, "a>", "21", TRICORE_RIDER_A, INDICES}, - {"ld.a", 0, 0x000000c4, 0xffff003b, F(SLR), 2, "a>", "21", + { "ld.a", 0, 0x000000c4, 0xffff003b, F(SLR), 2, "a>", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.a", 0, 0x000000b8, 0xffff0047, F(SLR), 2, "a@", "21", + { "ld.a", 0, 0x000000b8, 0xffff0047, F(SLR), 2, "a@", "21", TRICORE_RIDER_A, INDICES}, - {"ld.a", 0, 0x000000d4, 0xffff002b, F(SLR), 2, "a@", "21", + { "ld.a", 0, 0x000000d4, 0xffff002b, F(SLR), 2, "a@", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.a", 1, 0x00000099, 0x00000066, F(BOL), 3, "a@w", "321", + { "ld.a", 1, 0x00000099, 0x00000066, F(BOL), 3, "a@w", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x01800009, 0x0e4000f6, F(BO), 3, "a>0", "321", + { "ld.a", 1, 0x01800009, 0x0e4000f6, F(BO), 3, "a>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x01800029, 0xfe7f00d6, F(BO), 2, "a#", "32", + { "ld.a", 1, 0x01800029, 0xfe7f00d6, F(BO), 2, "a#", "32", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x05800009, 0x0a4000f6, F(BO), 3, "a<0", "321", + { "ld.a", 1, 0x05800009, 0x0a4000f6, F(BO), 3, "a<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x05800029, 0x0a4000d6, F(BO), 3, "a*0", "321", + { "ld.a", 1, 0x05800029, 0x0a4000d6, F(BO), 3, "a*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x08000085, 0x0400007a, F(ABS), 2, "at", "21", + { "ld.a", 1, 0x08000085, 0x0400007a, F(ABS), 2, "at", "21", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x09800009, 0x064000f6, F(BO), 3, "a@0", "321", + { "ld.a", 1, 0x09800009, 0x064000f6, F(BO), 3, "a@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.a", 1, 0x09800029, 0xf67f00d6, F(BO), 2, "a?", "32", + { "ld.a", 1, 0x09800029, 0xf67f00d6, F(BO), 2, "a?", "32", TRICORE_V2_UP, INDICES}, - {"ld.b", 0, 0x00000008, 0xffff00f7, F(SRO), 3, "i@f", "012", + { "ld.b", 0, 0x00000008, 0xffff00f7, F(SRO), 3, "i@f", "012", TRICORE_RIDER_A, INDICES}, - {"ld.b", 0, 0x00000034, 0xffff00cb, F(SLRO), 3, "dSf", "201", + { "ld.b", 0, 0x00000034, 0xffff00cb, F(SLRO), 3, "dSf", "201", TRICORE_RIDER_A, INDICES}, - {"ld.b", 0, 0x00000044, 0xffff00bb, F(SLR), 2, "d>", "21", + { "ld.b", 0, 0x00000044, 0xffff00bb, F(SLR), 2, "d>", "21", TRICORE_RIDER_A, INDICES}, - {"ld.b", 0, 0x00000098, 0xffff0067, F(SLR), 2, "d@", "21", + { "ld.b", 0, 0x00000098, 0xffff0067, F(SLR), 2, "d@", "21", TRICORE_RIDER_A, INDICES}, - {"ld.b", 1, 0x00000005, 0x0c0000fa, F(ABS), 2, "dt", "21", + { "ld.b", 1, 0x00000005, 0x0c0000fa, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x00000009, 0x0fc000f6, F(BO), 3, "d>0", "321", + { "ld.b", 1, 0x00000009, 0x0fc000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x00000029, 0xffff00d6, F(BO), 2, "d#", "32", + { "ld.b", 1, 0x00000029, 0xffff00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x04000009, 0x0bc000f6, F(BO), 3, "d<0", "321", + { "ld.b", 1, 0x04000009, 0x0bc000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x04000029, 0x0bc000d6, F(BO), 3, "d*0", "321", + { "ld.b", 1, 0x04000029, 0x0bc000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x08000009, 0x07c000f6, F(BO), 3, "d@0", "321", + { "ld.b", 1, 0x08000009, 0x07c000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.b", 1, 0x08000029, 0xf7ff00d6, F(BO), 2, "d?", "32", + { "ld.b", 1, 0x08000029, 0xf7ff00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ld.bu", 0, 0x00000058, 0xffff00a7, F(SLR), 2, "d@", "21", + { "ld.bu", 0, 0x00000058, 0xffff00a7, F(SLR), 2, "d@", "21", TRICORE_RIDER_A, INDICES}, - {"ld.bu", 0, 0x00000014, 0xffff00eb, F(SLR), 2, "d@", "21", + { "ld.bu", 0, 0x00000014, 0xffff00eb, F(SLR), 2, "d@", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.bu", 0, 0x00000088, 0xffff0077, F(SRO), 3, "i@f", "012", + { "ld.bu", 0, 0x00000088, 0xffff0077, F(SRO), 3, "i@f", "012", TRICORE_RIDER_A, INDICES}, - {"ld.bu", 0, 0x0000000c, 0xffff00f3, F(SRO), 3, "i@f", "012", + { "ld.bu", 0, 0x0000000c, 0xffff00f3, F(SRO), 3, "i@f", "012", TRICORE_RIDER_B_UP, INDICES}, - {"ld.bu", 0, 0x000000b4, 0xffff004b, F(SLRO), 3, "dSf", "201", + { "ld.bu", 0, 0x000000b4, 0xffff004b, F(SLRO), 3, "dSf", "201", TRICORE_RIDER_A, INDICES}, - {"ld.bu", 0, 0x00000008, 0xffff00f7, F(SLRO), 3, "dSf", "201", + { "ld.bu", 0, 0x00000008, 0xffff00f7, F(SLRO), 3, "dSf", "201", TRICORE_RIDER_B_UP, INDICES}, - {"ld.bu", 0, 0x000000c4, 0xffff003b, F(SLR), 2, "d>", "21", + { "ld.bu", 0, 0x000000c4, 0xffff003b, F(SLR), 2, "d>", "21", TRICORE_RIDER_A, INDICES}, - {"ld.bu", 0, 0x00000004, 0xffff00fb, F(SLR), 2, "d>", "21", + { "ld.bu", 0, 0x00000004, 0xffff00fb, F(SLR), 2, "d>", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.bu", 1, 0x00400009, 0x0f8000f6, F(BO), 3, "d>0", "321", + { "ld.bu", 1, 0x00400009, 0x0f8000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x00400029, 0xffbf00d6, F(BO), 2, "d#", "32", + { "ld.bu", 1, 0x00400029, 0xffbf00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x04000005, 0x080000fa, F(ABS), 2, "dt", "21", + { "ld.bu", 1, 0x04000005, 0x080000fa, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x04400009, 0x0b8000f6, F(BO), 3, "d<0", "321", + { "ld.bu", 1, 0x04400009, 0x0b8000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x04400029, 0x0b8000d6, F(BO), 3, "d*0", "321", + { "ld.bu", 1, 0x04400029, 0x0b8000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x08400009, 0x078000f6, F(BO), 3, "d@0", "321", + { "ld.bu", 1, 0x08400009, 0x078000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.bu", 1, 0x08400029, 0xf7bf00d6, F(BO), 2, "d?", "32", + { "ld.bu", 1, 0x08400029, 0xf7bf00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ld.d", 1, 0x01400009, 0x0e8000f6, F(BO), 3, "D>0", "321", + { "ld.d", 1, 0x01400009, 0x0e8000f6, F(BO), 3, "D>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x01400029, 0xfebf00d6, F(BO), 2, "D#", "32", + { "ld.d", 1, 0x01400029, 0xfebf00d6, F(BO), 2, "D#", "32", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x04000085, 0x0800007a, F(ABS), 2, "Dt", "21", + { "ld.d", 1, 0x04000085, 0x0800007a, F(ABS), 2, "Dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x05400009, 0x0a8000f6, F(BO), 3, "D<0", "321", + { "ld.d", 1, 0x05400009, 0x0a8000f6, F(BO), 3, "D<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x05400029, 0x0a8000d6, F(BO), 3, "D*0", "321", + { "ld.d", 1, 0x05400029, 0x0a8000d6, F(BO), 3, "D*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x09400009, 0x068000f6, F(BO), 3, "D@0", "321", + { "ld.d", 1, 0x09400009, 0x068000f6, F(BO), 3, "D@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.d", 1, 0x09400029, 0xf6bf00d6, F(BO), 2, "D?", "32", + { "ld.d", 1, 0x09400029, 0xf6bf00d6, F(BO), 2, "D?", "32", TRICORE_V2_UP, INDICES}, - {"ld.da", 1, 0x01c00009, 0x0e0000f6, F(BO), 3, "A>0", "321", + { "ld.da", 1, 0x01c00009, 0x0e0000f6, F(BO), 3, "A>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x01c00029, 0xfe3f00d6, F(BO), 2, "A#", "32", + { "ld.da", 1, 0x01c00029, 0xfe3f00d6, F(BO), 2, "A#", "32", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x05c00009, 0x0a0000f6, F(BO), 3, "A<0", "321", + { "ld.da", 1, 0x05c00009, 0x0a0000f6, F(BO), 3, "A<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x05c00029, 0x0a0000d6, F(BO), 3, "A*0", "321", + { "ld.da", 1, 0x05c00029, 0x0a0000d6, F(BO), 3, "A*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x09c00009, 0x060000f6, F(BO), 3, "A@0", "321", + { "ld.da", 1, 0x09c00009, 0x060000f6, F(BO), 3, "A@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x0c000085, 0x0000007a, F(ABS), 2, "At", "21", + { "ld.da", 1, 0x0c000085, 0x0000007a, F(ABS), 2, "At", "21", TRICORE_GENERIC, INDICES}, - {"ld.da", 1, 0x09c00029, 0xf63f00d6, F(BO), 2, "A?", "32", + { "ld.da", 1, 0x09c00029, 0xf63f00d6, F(BO), 2, "A?", "32", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x02400009, 0x0d8000f6, F(BO), 3, "D>0", "321", + { "ld.dd", 1, 0x02400009, 0x0d8000f6, F(BO), 3, "D>0", "321", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x02400029, 0xfdbf00d6, F(BO), 2, "D#", "32", + { "ld.dd", 1, 0x02400029, 0xfdbf00d6, F(BO), 2, "D#", "32", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x06400009, 0x098000f6, F(BO), 3, "D<0", "321", + { "ld.dd", 1, 0x06400009, 0x098000f6, F(BO), 3, "D<0", "321", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x06400029, 0x098000d6, F(BO), 3, "D*0", "321", + { "ld.dd", 1, 0x06400029, 0x098000d6, F(BO), 3, "D*0", "321", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x0a400009, 0x058000f6, F(BO), 3, "D@0", "321", + { "ld.dd", 1, 0x0a400009, 0x058000f6, F(BO), 3, "D@0", "321", TRICORE_V2_UP, INDICES}, - {"ld.dd", 1, 0x0a400029, 0xf5bf00d6, F(BO), 2, "D?", "32", + { "ld.dd", 1, 0x0a400029, 0xf5bf00d6, F(BO), 2, "D?", "32", TRICORE_V2_UP, INDICES}, - {"ld.h", 0, 0x00000024, 0xffff00db, F(SLR), 2, "d>", "21", + { "ld.h", 0, 0x00000024, 0xffff00db, F(SLR), 2, "d>", "21", TRICORE_RIDER_A, INDICES}, - {"ld.h", 0, 0x00000084, 0xffff007b, F(SLR), 2, "d>", "21", + { "ld.h", 0, 0x00000084, 0xffff007b, F(SLR), 2, "d>", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.h", 0, 0x00000048, 0xffff00b7, F(SRO), 3, "i@v", "012", + { "ld.h", 0, 0x00000048, 0xffff00b7, F(SRO), 3, "i@v", "012", TRICORE_RIDER_A, INDICES}, - {"ld.h", 0, 0x0000008c, 0xffff0073, F(SRO), 3, "i@v", "012", + { "ld.h", 0, 0x0000008c, 0xffff0073, F(SRO), 3, "i@v", "012", TRICORE_RIDER_B_UP, INDICES}, - {"ld.h", 0, 0x00000074, 0xffff008b, F(SLRO), 3, "dSv", "201", + { "ld.h", 0, 0x00000074, 0xffff008b, F(SLRO), 3, "dSv", "201", TRICORE_RIDER_A, INDICES}, - {"ld.h", 0, 0x00000088, 0xffff0077, F(SLRO), 3, "dSv", "201", + { "ld.h", 0, 0x00000088, 0xffff0077, F(SLRO), 3, "dSv", "201", TRICORE_RIDER_B_UP, INDICES}, - {"ld.h", 0, 0x000000d8, 0xffff0027, F(SLR), 2, "d@", "21", + { "ld.h", 0, 0x000000d8, 0xffff0027, F(SLR), 2, "d@", "21", TRICORE_RIDER_A, INDICES}, - {"ld.h", 0, 0x00000094, 0xffff006b, F(SLR), 2, "d@", "21", + { "ld.h", 0, 0x00000094, 0xffff006b, F(SLR), 2, "d@", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.h", 1, 0x00800009, 0x0f4000f6, F(BO), 3, "d>0", "321", + { "ld.h", 1, 0x00800009, 0x0f4000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x00800029, 0xff7f00d6, F(BO), 2, "d#", "32", + { "ld.h", 1, 0x00800029, 0xff7f00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x04800009, 0x0b4000f6, F(BO), 3, "d<0", "321", + { "ld.h", 1, 0x04800009, 0x0b4000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x04800029, 0x0b4000d6, F(BO), 3, "d*0", "321", + { "ld.h", 1, 0x04800029, 0x0b4000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x08000005, 0x040000fa, F(ABS), 2, "dt", "21", + { "ld.h", 1, 0x08000005, 0x040000fa, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x08800009, 0x074000f6, F(BO), 3, "d@0", "321", + { "ld.h", 1, 0x08800009, 0x074000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.h", 1, 0x08800029, 0xf77f00d6, F(BO), 2, "d?", "32", + { "ld.h", 1, 0x08800029, 0xf77f00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ld.hu", 1, 0x00c00009, 0x0f0000f6, F(BO), 3, "d>0", "321", + { "ld.hu", 1, 0x00c00009, 0x0f0000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x00c00029, 0xff3f00d6, F(BO), 2, "d#", "32", + { "ld.hu", 1, 0x00c00029, 0xff3f00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x04c00009, 0x0b0000f6, F(BO), 3, "d<0", "321", + { "ld.hu", 1, 0x04c00009, 0x0b0000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x04c00029, 0x0b0000d6, F(BO), 3, "d*0", "321", + { "ld.hu", 1, 0x04c00029, 0x0b0000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x08c00009, 0x070000f6, F(BO), 3, "d@0", "321", + { "ld.hu", 1, 0x08c00009, 0x070000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x0c000005, 0x000000fa, F(ABS), 2, "dt", "21", + { "ld.hu", 1, 0x0c000005, 0x000000fa, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.hu", 1, 0x08c00029, 0xf73f00d6, F(BO), 2, "d?", "32", + { "ld.hu", 1, 0x08c00029, 0xf73f00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ld.q", 1, 0x00000045, 0x0c0000ba, F(ABS), 2, "dt", "21", + { "ld.q", 1, 0x00000045, 0x0c0000ba, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x02000009, 0x0dc000f6, F(BO), 3, "d>0", "321", + { "ld.q", 1, 0x02000009, 0x0dc000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x02000029, 0xfdff00d6, F(BO), 2, "d#", "32", + { "ld.q", 1, 0x02000029, 0xfdff00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x06000009, 0x09c000f6, F(BO), 3, "d<0", "321", + { "ld.q", 1, 0x06000009, 0x09c000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x06000029, 0x09c000d6, F(BO), 3, "d*0", "321", + { "ld.q", 1, 0x06000029, 0x09c000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x0a000009, 0x05c000f6, F(BO), 3, "d@0", "321", + { "ld.q", 1, 0x0a000009, 0x05c000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.q", 1, 0x0a000029, 0xf5ff00d6, F(BO), 2, "d?", "32", + { "ld.q", 1, 0x0a000029, 0xf5ff00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ld.w", 0, 0x00000058, 0xffff00a7, F(SC), 3, "i&k", "001", + { "ld.w", 0, 0x00000058, 0xffff00a7, F(SC), 3, "i&k", "001", TRICORE_RIDER_B_UP, INDICES}, - {"ld.w", 0, 0x00000038, 0xffff00c7, F(SLR), 2, "d@", "21", + { "ld.w", 0, 0x00000038, 0xffff00c7, F(SLR), 2, "d@", "21", TRICORE_RIDER_A, INDICES}, - {"ld.w", 0, 0x00000054, 0xffff00ab, F(SLR), 2, "d@", "21", + { "ld.w", 0, 0x00000054, 0xffff00ab, F(SLR), 2, "d@", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.w", 0, 0x000000a4, 0xffff005b, F(SLR), 2, "d>", "21", + { "ld.w", 0, 0x000000a4, 0xffff005b, F(SLR), 2, "d>", "21", TRICORE_RIDER_A, INDICES}, - {"ld.w", 0, 0x00000044, 0xffff00bb, F(SLR), 2, "d>", "21", + { "ld.w", 0, 0x00000044, 0xffff00bb, F(SLR), 2, "d>", "21", TRICORE_RIDER_B_UP, INDICES}, - {"ld.w", 0, 0x000000c8, 0xffff0037, F(SRO), 3, "i@6", "012", + { "ld.w", 0, 0x000000c8, 0xffff0037, F(SRO), 3, "i@6", "012", TRICORE_RIDER_A, INDICES}, - {"ld.w", 0, 0x0000004c, 0xffff00b3, F(SRO), 3, "i@6", "012", + { "ld.w", 0, 0x0000004c, 0xffff00b3, F(SRO), 3, "i@6", "012", TRICORE_RIDER_B_UP, INDICES}, - {"ld.w", 0, 0x000000f4, 0xffff000b, F(SLRO), 3, "dS6", "201", + { "ld.w", 0, 0x000000f4, 0xffff000b, F(SLRO), 3, "dS6", "201", TRICORE_RIDER_A, INDICES}, - {"ld.w", 0, 0x00000048, 0xffff00b7, F(SLRO), 3, "dS6", "201", + { "ld.w", 0, 0x00000048, 0xffff00b7, F(SLRO), 3, "dS6", "201", TRICORE_RIDER_B_UP, INDICES}, - {"ld.w", 1, 0x00000019, 0x000000e6, F(BOL), 3, "d@w", "321", + { "ld.w", 1, 0x00000019, 0x000000e6, F(BOL), 3, "d@w", "321", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x00000085, 0x0c00007a, F(ABS), 2, "dt", "21", + { "ld.w", 1, 0x00000085, 0x0c00007a, F(ABS), 2, "dt", "21", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x01000009, 0x0ec000f6, F(BO), 3, "d>0", "321", + { "ld.w", 1, 0x01000009, 0x0ec000f6, F(BO), 3, "d>0", "321", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x01000029, 0xfeff00d6, F(BO), 2, "d#", "32", + { "ld.w", 1, 0x01000029, 0xfeff00d6, F(BO), 2, "d#", "32", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x05000009, 0x0ac000f6, F(BO), 3, "d<0", "321", + { "ld.w", 1, 0x05000009, 0x0ac000f6, F(BO), 3, "d<0", "321", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x05000029, 0x0ac000d6, F(BO), 3, "d*0", "321", + { "ld.w", 1, 0x05000029, 0x0ac000d6, F(BO), 3, "d*0", "321", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x09000009, 0x06c000f6, F(BO), 3, "d@0", "321", + { "ld.w", 1, 0x09000009, 0x06c000f6, F(BO), 3, "d@0", "321", TRICORE_GENERIC, INDICES}, - {"ld.w", 1, 0x09000029, 0xf6ff00d6, F(BO), 2, "d?", "32", + { "ld.w", 1, 0x09000029, 0xf6ff00d6, F(BO), 2, "d?", "32", TRICORE_V2_UP, INDICES}, - {"ldlcx", 1, 0x08000015, 0x04000fea, F(ABS), 1, "t", "1", + { "ldlcx", 1, 0x08000015, 0x04000fea, F(ABS), 1, "t", "1", TRICORE_GENERIC, INDICES}, - {"ldlcx", 1, 0x09000049, 0x06c00fb6, F(BO), 2, "@0", "21", + { "ldlcx", 1, 0x09000049, 0x06c00fb6, F(BO), 2, "@0", "21", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x00400049, 0x0f8000b6, F(BO), 3, ">0D", "213", + { "ldmst", 1, 0x00400049, 0x0f8000b6, F(BO), 3, ">0D", "213", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x00400069, 0xffbf0096, F(BO), 2, "#D", "23", + { "ldmst", 1, 0x00400069, 0xffbf0096, F(BO), 2, "#D", "23", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x040000e5, 0x0800001a, F(ABS), 2, "tD", "12", + { "ldmst", 1, 0x040000e5, 0x0800001a, F(ABS), 2, "tD", "12", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x04400049, 0x0b8000b6, F(BO), 3, "<0D", "213", + { "ldmst", 1, 0x04400049, 0x0b8000b6, F(BO), 3, "<0D", "213", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x04400069, 0x0b800096, F(BO), 3, "*0D", "213", + { "ldmst", 1, 0x04400069, 0x0b800096, F(BO), 3, "*0D", "213", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x08400049, 0x078000b6, F(BO), 3, "@0D", "213", + { "ldmst", 1, 0x08400049, 0x078000b6, F(BO), 3, "@0D", "213", TRICORE_GENERIC, INDICES}, - {"ldmst", 1, 0x08400069, 0xf7bf0096, F(BO), 2, "?D", "23", + { "ldmst", 1, 0x08400069, 0xf7bf0096, F(BO), 2, "?D", "23", TRICORE_V2_UP, INDICES}, - {"lducx", 1, 0x09400049, 0x06800fb6, F(BO), 2, "@0", "21", + { "lducx", 1, 0x09400049, 0x06800fb6, F(BO), 2, "@0", "21", TRICORE_GENERIC, INDICES}, - {"lducx", 1, 0x0c000015, 0x00000fea, F(ABS), 1, "t", "1", + { "lducx", 1, 0x0c000015, 0x00000fea, F(ABS), 1, "t", "1", TRICORE_GENERIC, INDICES}, - {"lea", 1, 0x000000c5, 0x0c00003a, F(ABS), 2, "at", "21", + { "lea", 1, 0x000000c5, 0x0c00003a, F(ABS), 2, "at", "21", TRICORE_GENERIC, INDICES}, - {"lea", 1, 0x000000d9, 0x00000026, F(BOL), 3, "a@w", "321", + { "lea", 1, 0x000000d9, 0x00000026, F(BOL), 3, "a@w", "321", TRICORE_GENERIC, INDICES}, - {"lea", 1, 0x0a000049, 0x05c000b6, F(BO), 3, "a@0", "321", + { "lea", 1, 0x0a000049, 0x05c000b6, F(BO), 3, "a@0", "321", TRICORE_GENERIC, INDICES}, - {"loop", 0, 0x000000fc, 0xffff0003, F(SBR), 2, "ar", "12", + { "loop", 0, 0x000000fc, 0xffff0003, F(SBR), 2, "ar", "12", TRICORE_GENERIC, INDICES}, - {"loop", 1, 0x000000fd, 0x80000f02, F(BRR), 2, "ao", "21", + { "loop", 1, 0x000000fd, 0x80000f02, F(BRR), 2, "ao", "21", TRICORE_GENERIC, INDICES}, - {"loopu", 1, 0x800000fd, 0x0000ff02, F(BRR), 1, "o", "1", + { "loopu", 1, 0x800000fd, 0x0000ff02, F(BRR), 1, "o", "1", TRICORE_RIDER_B_UP, INDICES}, - {"lt", 0, 0x0000007a, 0xffff0085, F(SRR), 3, "idd", "021", + { "lt", 0, 0x0000007a, 0xffff0085, F(SRR), 3, "idd", "021", TRICORE_GENERIC, INDICES}, - {"lt", 0, 0x000000fa, 0xffff0005, F(SRC), 3, "id4", "021", + { "lt", 0, 0x000000fa, 0xffff0005, F(SRC), 3, "id4", "021", TRICORE_GENERIC, INDICES}, - {"lt", 1, 0x0120000b, 0x0edf00f4, F(RR), 3, "ddd", "143", + { "lt", 1, 0x0120000b, 0x0edf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt", 1, 0x0240008b, 0x0da00074, F(RC), 3, "dd9", "132", + { "lt", 1, 0x0240008b, 0x0da00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"lt.a", 1, 0x04200001, 0x0bdf00fe, F(RR), 3, "daa", "143", + { "lt.a", 1, 0x04200001, 0x0bdf00fe, F(RR), 3, "daa", "143", TRICORE_GENERIC, INDICES}, - {"lt.b", 1, 0x0520000b, 0x0adf00f4, F(RR), 3, "ddd", "143", + { "lt.b", 1, 0x0520000b, 0x0adf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.bu", 1, 0x0530000b, 0x0acf00f4, F(RR), 3, "ddd", "143", + { "lt.bu", 1, 0x0530000b, 0x0acf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.h", 1, 0x0720000b, 0x08df00f4, F(RR), 3, "ddd", "143", + { "lt.h", 1, 0x0720000b, 0x08df00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.hu", 1, 0x0730000b, 0x08cf00f4, F(RR), 3, "ddd", "143", + { "lt.hu", 1, 0x0730000b, 0x08cf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.u", 0, 0x00000006, 0xffff00f9, F(SRR), 3, "idd", "021", + { "lt.u", 0, 0x00000006, 0xffff00f9, F(SRR), 3, "idd", "021", TRICORE_RIDER_A, INDICES}, - {"lt.u", 0, 0x00000086, 0xffff0079, F(SRC), 3, "idf", "021", + { "lt.u", 0, 0x00000086, 0xffff0079, F(SRC), 3, "idf", "021", TRICORE_RIDER_A, INDICES}, - {"lt.u", 1, 0x0130000b, 0x0ecf00f4, F(RR), 3, "ddd", "143", + { "lt.u", 1, 0x0130000b, 0x0ecf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.u", 1, 0x0260008b, 0x0d800074, F(RC), 3, "ddn", "132", + { "lt.u", 1, 0x0260008b, 0x0d800074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"lt.w", 1, 0x0920000b, 0x06df00f4, F(RR), 3, "ddd", "143", + { "lt.w", 1, 0x0920000b, 0x06df00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"lt.wu", 1, 0x0930000b, 0x06cf00f4, F(RR), 3, "ddd", "143", + { "lt.wu", 1, 0x0930000b, 0x06cf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"madd", 1, 0x000a0003, 0x00f500fc, F(RRR2), 4, "dddd", "1243", + { "madd", 1, 0x000a0003, 0x00f500fc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"madd", 1, 0x00200013, 0x00c000ec, F(RCR), 4, "ddd9", "1243", + { "madd", 1, 0x00200013, 0x00c000ec, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"madd", 1, 0x00600013, 0x008000ec, F(RCR), 4, "DDd9", "1243", + { "madd", 1, 0x00600013, 0x008000ec, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madd", 1, 0x006a0003, 0x009500fc, F(RRR2), 4, "DDdd", "1243", + { "madd", 1, 0x006a0003, 0x009500fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madd.f", 1, 0x0061006b, 0x009e0094, F(RRR), 4, "dddd", "1254", + { "madd.f", 1, 0x0061006b, 0x009e0094, F(RRR), 4, "dddd", "1254", TRICORE_RIDER_D_UP, INDICES}, - {"madd.h", 1, 0x00600083, 0x009c007c, F(RRR1), 5, "DDdd1", "12543", + { "madd.h", 1, 0x00600083, 0x009c007c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"madd.h", 1, 0x00600083, 0x009c007c, F(RRR1), 5, "DDdL1", "12543", + { "madd.h", 1, 0x00600083, 0x009c007c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.h", 1, 0x00640083, 0x0098007c, F(RRR1), 5, "DDdl1", "12543", + { "madd.h", 1, 0x00640083, 0x0098007c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.h", 1, 0x00680083, 0x0094007c, F(RRR1), 5, "DDd-1", "12543", + { "madd.h", 1, 0x00680083, 0x0094007c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.h", 1, 0x006c0083, 0x0090007c, F(RRR1), 5, "DDd+1", "12543", + { "madd.h", 1, 0x006c0083, 0x0090007c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00100043, 0x00ec00bc, F(RRR1), 5, "dddd1", "12543", + { "madd.q", 1, 0x00100043, 0x00ec00bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"madd.q", 1, 0x00100043, 0x00ec00bc, F(RRR1), 5, "ddGG1", "12543", + { "madd.q", 1, 0x00100043, 0x00ec00bc, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00000043, 0x00fc00bc, F(RRR1), 5, "dddG1", "12543", + { "madd.q", 1, 0x00000043, 0x00fc00bc, F(RRR1), 5, "dddG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00040043, 0x00f800bc, F(RRR1), 5, "dddg1", "12543", + { "madd.q", 1, 0x00040043, 0x00f800bc, F(RRR1), 5, "dddg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00080043, 0x00f400bc, F(RRR1), 5, "dddd1", "12543", + { "madd.q", 1, 0x00080043, 0x00f400bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00140043, 0x00e800bc, F(RRR1), 5, "ddgg1", "12543", + { "madd.q", 1, 0x00140043, 0x00e800bc, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00600043, 0x009c00bc, F(RRR1), 5, "DDdG1", "12543", + { "madd.q", 1, 0x00600043, 0x009c00bc, F(RRR1), 5, "DDdG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00640043, 0x009800bc, F(RRR1), 5, "DDdg1", "12543", + { "madd.q", 1, 0x00640043, 0x009800bc, F(RRR1), 5, "DDdg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x006c0043, 0x009000bc, F(RRR1), 5, "DDdd1", "12543", + { "madd.q", 1, 0x006c0043, 0x009000bc, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00700043, 0x008c00bc, F(RRR1), 5, "DDGG1", "12543", + { "madd.q", 1, 0x00700043, 0x008c00bc, F(RRR1), 5, "DDGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.q", 1, 0x00740043, 0x008800bc, F(RRR1), 5, "DDgg1", "12543", + { "madd.q", 1, 0x00740043, 0x008800bc, F(RRR1), 5, "DDgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madd.u", 1, 0x00400013, 0x00a000ec, F(RCR), 4, "DDdn", "1243", + { "madd.u", 1, 0x00400013, 0x00a000ec, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madd.u", 1, 0x00680003, 0x009700fc, F(RRR2), 4, "DDdd", "1243", + { "madd.u", 1, 0x00680003, 0x009700fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"maddm", 1, 0x00600013, 0x008000ec, F(RCR), 4, "DDd9", "1243", + { "maddm", 1, 0x00600013, 0x008000ec, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_A, INDICES}, - {"maddm", 1, 0x006a0003, 0x009500fc, F(RRR2), 4, "DDdd", "1243", + { "maddm", 1, 0x006a0003, 0x009500fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"maddm.h", 1, 0x00700083, 0x008f007c, F(RRR1), 4, "DDdd", "1254", + { "maddm.h", 1, 0x00700083, 0x008f007c, F(RRR1), 4, "DDdd", "1254", TRICORE_RIDER_A, INDICES}, - {"maddm.h", 1, 0x00700083, 0x008c007c, F(RRR1), 5, "DDdL1", "12543", + { "maddm.h", 1, 0x00700083, 0x008c007c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddm.h", 1, 0x00740083, 0x0088007c, F(RRR1), 5, "DDdl1", "12543", + { "maddm.h", 1, 0x00740083, 0x0088007c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddm.h", 1, 0x00780083, 0x0084007c, F(RRR1), 5, "DDd-1", "12543", + { "maddm.h", 1, 0x00780083, 0x0084007c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddm.h", 1, 0x007c0083, 0x0080007c, F(RRR1), 5, "DDd+1", "12543", + { "maddm.h", 1, 0x007c0083, 0x0080007c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddm.q", 1, 0x00700043, 0x008f00bc, F(RRR1), 4, "DDdd", "1254", + { "maddm.q", 1, 0x00700043, 0x008f00bc, F(RRR1), 4, "DDdd", "1254", TRICORE_RIDER_A, INDICES}, - {"maddm.u", 1, 0x00400013, 0x00a000ec, F(RCR), 4, "DDdn", "1243", + { "maddm.u", 1, 0x00400013, 0x00a000ec, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_A, INDICES}, - {"maddm.u", 1, 0x00680003, 0x009700fc, F(RRR2), 4, "DDdd", "1243", + { "maddm.u", 1, 0x00680003, 0x009700fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"maddms", 1, 0x00e00013, 0x000000ec, F(RCR), 4, "DDd9", "1243", + { "maddms", 1, 0x00e00013, 0x000000ec, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_A, INDICES}, - {"maddms", 1, 0x00ea0003, 0x001500fc, F(RRR2), 4, "DDdd", "1243", + { "maddms", 1, 0x00ea0003, 0x001500fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"maddms.h", 1, 0x00f00083, 0x000c007c, F(RRR1), 5, "DDdL1", "12543", + { "maddms.h", 1, 0x00f00083, 0x000c007c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddms.h", 1, 0x00f40083, 0x0008007c, F(RRR1), 5, "DDdl1", "12543", + { "maddms.h", 1, 0x00f40083, 0x0008007c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddms.h", 1, 0x00f80083, 0x0004007c, F(RRR1), 5, "DDd-1", "12543", + { "maddms.h", 1, 0x00f80083, 0x0004007c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddms.h", 1, 0x00fc0083, 0x0000007c, F(RRR1), 5, "DDd+1", "12543", + { "maddms.h", 1, 0x00fc0083, 0x0000007c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddms.u", 1, 0x00c00013, 0x002000ec, F(RCR), 4, "DDdn", "1243", + { "maddms.u", 1, 0x00c00013, 0x002000ec, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_A, INDICES}, - {"maddms.u", 1, 0x00e80003, 0x001700fc, F(RRR2), 4, "DDdd", "1243", + { "maddms.u", 1, 0x00e80003, 0x001700fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"maddr.h", 1, 0x00780043, 0x008400bc, F(RRR1), 5, "dDdd1", "12543", + { "maddr.h", 1, 0x00780043, 0x008400bc, F(RRR1), 5, "dDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"maddr.h", 1, 0x00780043, 0x008400bc, F(RRR1), 5, "dDdL1", "12543", + { "maddr.h", 1, 0x00780043, 0x008400bc, F(RRR1), 5, "dDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.h", 1, 0x00300083, 0x00cc007c, F(RRR1), 5, "dddL1", "12543", + { "maddr.h", 1, 0x00300083, 0x00cc007c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.h", 1, 0x00340083, 0x00c8007c, F(RRR1), 5, "dddl1", "12543", + { "maddr.h", 1, 0x00340083, 0x00c8007c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.h", 1, 0x00380083, 0x00c4007c, F(RRR1), 5, "ddd-1", "12543", + { "maddr.h", 1, 0x00380083, 0x00c4007c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.h", 1, 0x003c0083, 0x00c0007c, F(RRR1), 5, "ddd+1", "12543", + { "maddr.h", 1, 0x003c0083, 0x00c0007c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.q", 1, 0x00180043, 0x00e400bc, F(RRR1), 5, "dddd1", "12543", + { "maddr.q", 1, 0x00180043, 0x00e400bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"maddr.q", 1, 0x00180043, 0x00e400bc, F(RRR1), 5, "ddGG1", "12543", + { "maddr.q", 1, 0x00180043, 0x00e400bc, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddr.q", 1, 0x001c0043, 0x00e000bc, F(RRR1), 5, "ddgg1", "12543", + { "maddr.q", 1, 0x001c0043, 0x00e000bc, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.h", 1, 0x00f80043, 0x000400bc, F(RRR1), 5, "dDdd1", "12543", + { "maddrs.h", 1, 0x00f80043, 0x000400bc, F(RRR1), 5, "dDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"maddrs.h", 1, 0x00f80043, 0x000400bc, F(RRR1), 5, "dDdL1", "12543", + { "maddrs.h", 1, 0x00f80043, 0x000400bc, F(RRR1), 5, "dDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.h", 1, 0x00b00083, 0x004c007c, F(RRR1), 5, "dddL1", "12543", + { "maddrs.h", 1, 0x00b00083, 0x004c007c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.h", 1, 0x00b40083, 0x0048007c, F(RRR1), 5, "dddl1", "12543", + { "maddrs.h", 1, 0x00b40083, 0x0048007c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.h", 1, 0x00b80083, 0x0044007c, F(RRR1), 5, "ddd-1", "12543", + { "maddrs.h", 1, 0x00b80083, 0x0044007c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.h", 1, 0x00bc0083, 0x0040007c, F(RRR1), 5, "ddd+1", "12543", + { "maddrs.h", 1, 0x00bc0083, 0x0040007c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.q", 1, 0x00980043, 0x006400bc, F(RRR1), 5, "dddd1", "12543", + { "maddrs.q", 1, 0x00980043, 0x006400bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"maddrs.q", 1, 0x00980043, 0x006400bc, F(RRR1), 5, "ddGG1", "12543", + { "maddrs.q", 1, 0x00980043, 0x006400bc, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddrs.q", 1, 0x009c0043, 0x006000bc, F(RRR1), 5, "ddgg1", "12543", + { "maddrs.q", 1, 0x009c0043, 0x006000bc, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds", 1, 0x008a0003, 0x007500fc, F(RRR2), 4, "dddd", "1243", + { "madds", 1, 0x008a0003, 0x007500fc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"madds", 1, 0x00a00013, 0x004000ec, F(RCR), 4, "ddd9", "1243", + { "madds", 1, 0x00a00013, 0x004000ec, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"madds", 1, 0x00e00013, 0x000000ec, F(RCR), 4, "DDd9", "1243", + { "madds", 1, 0x00e00013, 0x000000ec, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madds", 1, 0x00ea0003, 0x001500fc, F(RRR2), 4, "DDdd", "1243", + { "madds", 1, 0x00ea0003, 0x001500fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madds.h", 1, 0x00e00083, 0x001c007c, F(RRR1), 5, "DDdd1", "12543", + { "madds.h", 1, 0x00e00083, 0x001c007c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"madds.h", 1, 0x00e00083, 0x001c007c, F(RRR1), 5, "DDdL1", "12543", + { "madds.h", 1, 0x00e00083, 0x001c007c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.h", 1, 0x00e40083, 0x0018007c, F(RRR1), 5, "DDdl1", "12543", + { "madds.h", 1, 0x00e40083, 0x0018007c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.h", 1, 0x00e80083, 0x0014007c, F(RRR1), 5, "DDd-1", "12543", + { "madds.h", 1, 0x00e80083, 0x0014007c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.h", 1, 0x00ec0083, 0x0010007c, F(RRR1), 5, "DDd+1", "12543", + { "madds.h", 1, 0x00ec0083, 0x0010007c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00900043, 0x006c00bc, F(RRR1), 5, "dddd1", "12543", + { "madds.q", 1, 0x00900043, 0x006c00bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"madds.q", 1, 0x00900043, 0x006c00bc, F(RRR1), 5, "ddGG1", "12543", + { "madds.q", 1, 0x00900043, 0x006c00bc, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00800043, 0x007c00bc, F(RRR1), 5, "dddG1", "12543", + { "madds.q", 1, 0x00800043, 0x007c00bc, F(RRR1), 5, "dddG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00840043, 0x007800bc, F(RRR1), 5, "dddg1", "12543", + { "madds.q", 1, 0x00840043, 0x007800bc, F(RRR1), 5, "dddg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00880043, 0x007400bc, F(RRR1), 5, "dddd1", "12543", + { "madds.q", 1, 0x00880043, 0x007400bc, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00940043, 0x006800bc, F(RRR1), 5, "ddgg1", "12543", + { "madds.q", 1, 0x00940043, 0x006800bc, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00e00043, 0x001c00bc, F(RRR1), 5, "DDdG1", "12543", + { "madds.q", 1, 0x00e00043, 0x001c00bc, F(RRR1), 5, "DDdG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00e40043, 0x001800bc, F(RRR1), 5, "DDdg1", "12543", + { "madds.q", 1, 0x00e40043, 0x001800bc, F(RRR1), 5, "DDdg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00ec0043, 0x001000bc, F(RRR1), 5, "DDdd1", "12543", + { "madds.q", 1, 0x00ec0043, 0x001000bc, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00f00043, 0x000c00bc, F(RRR1), 5, "DDGG1", "12543", + { "madds.q", 1, 0x00f00043, 0x000c00bc, F(RRR1), 5, "DDGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.q", 1, 0x00f40043, 0x000800bc, F(RRR1), 5, "DDgg1", "12543", + { "madds.q", 1, 0x00f40043, 0x000800bc, F(RRR1), 5, "DDgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"madds.u", 1, 0x00800013, 0x006000ec, F(RCR), 4, "dddn", "1243", + { "madds.u", 1, 0x00800013, 0x006000ec, F(RCR), 4, "dddn", "1243", TRICORE_GENERIC, INDICES}, - {"madds.u", 1, 0x00880003, 0x007700fc, F(RRR2), 4, "dddd", "1243", + { "madds.u", 1, 0x00880003, 0x007700fc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"madds.u", 1, 0x00c00013, 0x002000ec, F(RCR), 4, "DDdn", "1243", + { "madds.u", 1, 0x00c00013, 0x002000ec, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"madds.u", 1, 0x00e80003, 0x001700fc, F(RRR2), 4, "DDdd", "1243", + { "madds.u", 1, 0x00e80003, 0x001700fc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"maddsu.h", 1, 0x006000c3, 0x009c003c, F(RRR1), 5, "DDdL1", "12543", + { "maddsu.h", 1, 0x006000c3, 0x009c003c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsu.h", 1, 0x006400c3, 0x0098003c, F(RRR1), 5, "DDdl1", "12543", + { "maddsu.h", 1, 0x006400c3, 0x0098003c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsu.h", 1, 0x006800c3, 0x0094003c, F(RRR1), 5, "DDd-1", "12543", + { "maddsu.h", 1, 0x006800c3, 0x0094003c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsu.h", 1, 0x006c00c3, 0x0090003c, F(RRR1), 5, "DDd+1", "12543", + { "maddsu.h", 1, 0x006c00c3, 0x0090003c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsum.h", 1, 0x007000c3, 0x008c003c, F(RRR1), 5, "DDdL1", "12543", + { "maddsum.h", 1, 0x007000c3, 0x008c003c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsum.h", 1, 0x007400c3, 0x0088003c, F(RRR1), 5, "DDdl1", "12543", + { "maddsum.h", 1, 0x007400c3, 0x0088003c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsum.h", 1, 0x007800c3, 0x0084003c, F(RRR1), 5, "DDd-1", "12543", + { "maddsum.h", 1, 0x007800c3, 0x0084003c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsum.h", 1, 0x007c00c3, 0x0080003c, F(RRR1), 5, "DDd+1", "12543", + { "maddsum.h", 1, 0x007c00c3, 0x0080003c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsums.h", 1, 0x00f000c3, 0x000c003c, F(RRR1), 5, "DDdL1", "12543", + { "maddsums.h", 1, 0x00f000c3, 0x000c003c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsums.h", 1, 0x00f400c3, 0x0008003c, F(RRR1), 5, "DDdl1", "12543", + { "maddsums.h", 1, 0x00f400c3, 0x0008003c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsums.h", 1, 0x00f800c3, 0x0004003c, F(RRR1), 5, "DDd-1", "12543", + { "maddsums.h", 1, 0x00f800c3, 0x0004003c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsums.h", 1, 0x00fc00c3, 0x0000003c, F(RRR1), 5, "DDd+1", "12543", + { "maddsums.h", 1, 0x00fc00c3, 0x0000003c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsur.h", 1, 0x003000c3, 0x00cc003c, F(RRR1), 5, "dddL1", "12543", + { "maddsur.h", 1, 0x003000c3, 0x00cc003c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsur.h", 1, 0x003400c3, 0x00c8003c, F(RRR1), 5, "dddl1", "12543", + { "maddsur.h", 1, 0x003400c3, 0x00c8003c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsur.h", 1, 0x003800c3, 0x00c4003c, F(RRR1), 5, "ddd-1", "12543", + { "maddsur.h", 1, 0x003800c3, 0x00c4003c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsur.h", 1, 0x003c00c3, 0x00c0003c, F(RRR1), 5, "ddd+1", "12543", + { "maddsur.h", 1, 0x003c00c3, 0x00c0003c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsurs.h", 1, 0x00b000c3, 0x004c003c, F(RRR1), 5, "dddL1", "12543", + { "maddsurs.h", 1, 0x00b000c3, 0x004c003c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsurs.h", 1, 0x00b400c3, 0x0048003c, F(RRR1), 5, "dddl1", "12543", + { "maddsurs.h", 1, 0x00b400c3, 0x0048003c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsurs.h", 1, 0x00b800c3, 0x0044003c, F(RRR1), 5, "ddd-1", "12543", + { "maddsurs.h", 1, 0x00b800c3, 0x0044003c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsurs.h", 1, 0x00bc00c3, 0x0040003c, F(RRR1), 5, "ddd+1", "12543", + { "maddsurs.h", 1, 0x00bc00c3, 0x0040003c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsus.h", 1, 0x00e000c3, 0x001c003c, F(RRR1), 5, "DDdL1", "12543", + { "maddsus.h", 1, 0x00e000c3, 0x001c003c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsus.h", 1, 0x00e400c3, 0x0018003c, F(RRR1), 5, "DDdl1", "12543", + { "maddsus.h", 1, 0x00e400c3, 0x0018003c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsus.h", 1, 0x00e800c3, 0x0014003c, F(RRR1), 5, "DDd-1", "12543", + { "maddsus.h", 1, 0x00e800c3, 0x0014003c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"maddsus.h", 1, 0x00ec00c3, 0x0010003c, F(RRR1), 5, "DDd+1", "12543", + { "maddsus.h", 1, 0x00ec00c3, 0x0010003c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"max", 1, 0x01a0000b, 0x0e5f00f4, F(RR), 3, "ddd", "143", + { "max", 1, 0x01a0000b, 0x0e5f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max", 1, 0x0340008b, 0x0ca00074, F(RC), 3, "dd9", "132", + { "max", 1, 0x0340008b, 0x0ca00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"max.b", 1, 0x05a0000b, 0x0a5f00f4, F(RR), 3, "ddd", "143", + { "max.b", 1, 0x05a0000b, 0x0a5f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max.bu", 1, 0x05b0000b, 0x0a4f00f4, F(RR), 3, "ddd", "143", + { "max.bu", 1, 0x05b0000b, 0x0a4f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max.h", 1, 0x07a0000b, 0x085f00f4, F(RR), 3, "ddd", "143", + { "max.h", 1, 0x07a0000b, 0x085f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max.hu", 1, 0x07b0000b, 0x084f00f4, F(RR), 3, "ddd", "143", + { "max.hu", 1, 0x07b0000b, 0x084f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max.u", 1, 0x01b0000b, 0x0e4f00f4, F(RR), 3, "ddd", "143", + { "max.u", 1, 0x01b0000b, 0x0e4f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"max.u", 1, 0x0360008b, 0x0c800074, F(RC), 3, "ddn", "132", + { "max.u", 1, 0x0360008b, 0x0c800074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"mfcr", 1, 0x0000004d, 0x00000fb2, F(RLC), 2, "dW", "12", + { "mfcr", 1, 0x0000004d, 0x00000fb2, F(RLC), 2, "dW", "12", TRICORE_GENERIC, INDICES}, - {"mffr", 1, 0x01d1004b, 0x0e2ef0b4, F(RR), 2, "dd", "14", + { "mffr", 1, 0x01d1004b, 0x0e2ef0b4, F(RR), 2, "dd", "14", TRICORE_V2_UP, INDICES}, - {"min", 1, 0x0180000b, 0x0e7f00f4, F(RR), 3, "ddd", "143", + { "min", 1, 0x0180000b, 0x0e7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min", 1, 0x0300008b, 0x0ce00074, F(RC), 3, "dd9", "132", + { "min", 1, 0x0300008b, 0x0ce00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"min.b", 1, 0x0580000b, 0x0a7f00f4, F(RR), 3, "ddd", "143", + { "min.b", 1, 0x0580000b, 0x0a7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min.bu", 1, 0x0590000b, 0x0a6f00f4, F(RR), 3, "ddd", "143", + { "min.bu", 1, 0x0590000b, 0x0a6f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min.h", 1, 0x0780000b, 0x087f00f4, F(RR), 3, "ddd", "143", + { "min.h", 1, 0x0780000b, 0x087f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min.hu", 1, 0x0790000b, 0x086f00f4, F(RR), 3, "ddd", "143", + { "min.hu", 1, 0x0790000b, 0x086f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min.u", 1, 0x0190000b, 0x0e6f00f4, F(RR), 3, "ddd", "143", + { "min.u", 1, 0x0190000b, 0x0e6f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"min.u", 1, 0x0320008b, 0x0cc00074, F(RC), 3, "ddn", "132", + { "min.u", 1, 0x0320008b, 0x0cc00074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"mov", 0, 0x00000002, 0xffff00fd, F(SRR), 2, "dd", "21", + { "mov", 0, 0x00000002, 0xffff00fd, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"mov", 0, 0x00000082, 0xffff007d, F(SRC), 2, "d4", "21", + { "mov", 0, 0x00000082, 0xffff007d, F(SRC), 2, "d4", "21", TRICORE_GENERIC, INDICES}, - {"mov", 0, 0x000000d2, 0xffff002d, F(SRC), 2, "D4", "21", + { "mov", 0, 0x000000d2, 0xffff002d, F(SRC), 2, "D4", "21", TRICORE_V2_UP, INDICES}, - {"mov", 0, 0x000000c6, 0xffff0039, F(SC), 2, "i8", "01", + { "mov", 0, 0x000000c6, 0xffff0039, F(SC), 2, "i8", "01", TRICORE_RIDER_A, INDICES}, - {"mov", 0, 0x000000da, 0xffff0025, F(SC), 2, "i8", "01", + { "mov", 0, 0x000000da, 0xffff0025, F(SC), 2, "i8", "01", TRICORE_RIDER_B_UP, INDICES}, - {"mov", 1, 0x0000003b, 0x00000fc4, F(RLC), 2, "dw", "12", + { "mov", 1, 0x0000003b, 0x00000fc4, F(RLC), 2, "dw", "12", TRICORE_GENERIC, INDICES}, - {"mov", 1, 0x01f0000b, 0x0e0f0ff4, F(RR), 2, "dd", "13", + { "mov", 1, 0x01f0000b, 0x0e0f0ff4, F(RR), 2, "dd", "13", TRICORE_GENERIC, INDICES}, - {"mov", 1, 0x000000fb, 0x00000f04, F(RLC), 2, "Dw", "12", + { "mov", 1, 0x000000fb, 0x00000f04, F(RLC), 2, "Dw", "12", TRICORE_V2_UP, INDICES}, - {"mov", 1, 0x0800000b, 0x07ff0ff4, F(RR), 2, "Dd", "13", + { "mov", 1, 0x0800000b, 0x07ff0ff4, F(RR), 2, "Dd", "13", TRICORE_V2_UP, INDICES}, - {"mov", 1, 0x0810000b, 0x07ef00f4, F(RR), 3, "Ddd", "143", + { "mov", 1, 0x0810000b, 0x07ef00f4, F(RR), 3, "Ddd", "143", TRICORE_V2_UP, INDICES}, - {"mov.a", 0, 0x000000a0, 0xffff005f, F(SRC), 2, "af", "21", + { "mov.a", 0, 0x000000a0, 0xffff005f, F(SRC), 2, "af", "21", TRICORE_RIDER_B_UP, INDICES}, - {"mov.a", 0, 0x00000030, 0xffff00cf, F(SRR), 2, "ad", "21", + { "mov.a", 0, 0x00000030, 0xffff00cf, F(SRR), 2, "ad", "21", TRICORE_RIDER_A, INDICES}, - {"mov.a", 0, 0x00000060, 0xffff009f, F(SRR), 2, "ad", "21", + { "mov.a", 0, 0x00000060, 0xffff009f, F(SRR), 2, "ad", "21", TRICORE_RIDER_B_UP, INDICES}, - {"mov.a", 1, 0x06300001, 0x09cf0ffe, F(RR), 2, "ad", "13", + { "mov.a", 1, 0x06300001, 0x09cf0ffe, F(RR), 2, "ad", "13", TRICORE_GENERIC, INDICES}, - {"mov.aa", 0, 0x00000080, 0xffff007f, F(SRR), 2, "aa", "21", + { "mov.aa", 0, 0x00000080, 0xffff007f, F(SRR), 2, "aa", "21", TRICORE_RIDER_A, INDICES}, - {"mov.aa", 0, 0x00000040, 0xffff00bf, F(SRR), 2, "aa", "21", + { "mov.aa", 0, 0x00000040, 0xffff00bf, F(SRR), 2, "aa", "21", TRICORE_RIDER_B_UP, INDICES}, - {"mov.aa", 1, 0x00000001, 0x0fff0ffe, F(RR), 2, "aa", "13", + { "mov.aa", 1, 0x00000001, 0x0fff0ffe, F(RR), 2, "aa", "13", TRICORE_GENERIC, INDICES}, - {"mov.d", 0, 0x00000020, 0xffff00df, F(SRR), 2, "da", "21", + { "mov.d", 0, 0x00000020, 0xffff00df, F(SRR), 2, "da", "21", TRICORE_RIDER_A, INDICES}, - {"mov.d", 0, 0x00000080, 0xffff007f, F(SRR), 2, "da", "21", + { "mov.d", 0, 0x00000080, 0xffff007f, F(SRR), 2, "da", "21", TRICORE_RIDER_B_UP, INDICES}, - {"mov.d", 1, 0x04c00001, 0x0b3f0ffe, F(RR), 2, "da", "13", + { "mov.d", 1, 0x04c00001, 0x0b3f0ffe, F(RR), 2, "da", "13", TRICORE_GENERIC, INDICES}, - {"mov.u", 1, 0x000000bb, 0x00000f44, F(RLC), 2, "dW", "12", + { "mov.u", 1, 0x000000bb, 0x00000f44, F(RLC), 2, "dW", "12", TRICORE_GENERIC, INDICES}, - {"movh", 1, 0x0000007b, 0x00000f84, F(RLC), 2, "dW", "12", + { "movh", 1, 0x0000007b, 0x00000f84, F(RLC), 2, "dW", "12", TRICORE_GENERIC, INDICES}, - {"movh.a", 1, 0x00000091, 0x00000f6e, F(RLC), 2, "aW", "12", + { "movh.a", 1, 0x00000091, 0x00000f6e, F(RLC), 2, "aW", "12", TRICORE_GENERIC, INDICES}, - {"movz.a", 0, 0x00001000, 0xffffe0ff, F(SR), 1, "a", "1", + { "movz.a", 0, 0x00001000, 0xffffe0ff, F(SR), 1, "a", "1", TRICORE_RIDER_A, INDICES}, - {"msub", 1, 0x000a0023, 0x00f500dc, F(RRR2), 4, "dddd", "1243", + { "msub", 1, 0x000a0023, 0x00f500dc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"msub", 1, 0x00200033, 0x00c000cc, F(RCR), 4, "ddd9", "1243", + { "msub", 1, 0x00200033, 0x00c000cc, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"msub", 1, 0x00600033, 0x008000cc, F(RCR), 4, "DDd9", "1243", + { "msub", 1, 0x00600033, 0x008000cc, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msub", 1, 0x006a0023, 0x009500dc, F(RRR2), 4, "DDdd", "1243", + { "msub", 1, 0x006a0023, 0x009500dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msub.f", 1, 0x0071006b, 0x008e0094, F(RRR), 4, "dddd", "1254", + { "msub.f", 1, 0x0071006b, 0x008e0094, F(RRR), 4, "dddd", "1254", TRICORE_RIDER_D_UP, INDICES}, - {"msub.h", 1, 0x006000a3, 0x009c005c, F(RRR1), 5, "DDdd1", "12543", + { "msub.h", 1, 0x006000a3, 0x009c005c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msub.h", 1, 0x006000a3, 0x009c005c, F(RRR1), 5, "DDdL1", "12543", + { "msub.h", 1, 0x006000a3, 0x009c005c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.h", 1, 0x006400a3, 0x0098005c, F(RRR1), 5, "DDdl1", "12543", + { "msub.h", 1, 0x006400a3, 0x0098005c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.h", 1, 0x006800a3, 0x0094005c, F(RRR1), 5, "DDd-1", "12543", + { "msub.h", 1, 0x006800a3, 0x0094005c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.h", 1, 0x006c00a3, 0x0090005c, F(RRR1), 5, "DDd+1", "12543", + { "msub.h", 1, 0x006c00a3, 0x0090005c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00100063, 0x00ec009c, F(RRR1), 5, "dddd1", "12543", + { "msub.q", 1, 0x00100063, 0x00ec009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msub.q", 1, 0x00100063, 0x00ec009c, F(RRR1), 5, "ddGG1", "12543", + { "msub.q", 1, 0x00100063, 0x00ec009c, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00000063, 0x00fc009c, F(RRR1), 5, "dddG1", "12543", + { "msub.q", 1, 0x00000063, 0x00fc009c, F(RRR1), 5, "dddG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00040063, 0x00f8009c, F(RRR1), 5, "dddg1", "12543", + { "msub.q", 1, 0x00040063, 0x00f8009c, F(RRR1), 5, "dddg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00080063, 0x00f4009c, F(RRR1), 5, "dddd1", "12543", + { "msub.q", 1, 0x00080063, 0x00f4009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00140063, 0x00e8009c, F(RRR1), 5, "ddgg1", "12543", + { "msub.q", 1, 0x00140063, 0x00e8009c, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00600063, 0x009c009c, F(RRR1), 5, "DDdG1", "12543", + { "msub.q", 1, 0x00600063, 0x009c009c, F(RRR1), 5, "DDdG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00640063, 0x0098009c, F(RRR1), 5, "DDdg1", "12543", + { "msub.q", 1, 0x00640063, 0x0098009c, F(RRR1), 5, "DDdg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x006c0063, 0x0090009c, F(RRR1), 5, "DDdd1", "12543", + { "msub.q", 1, 0x006c0063, 0x0090009c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00700063, 0x008c009c, F(RRR1), 5, "DDGG1", "12543", + { "msub.q", 1, 0x00700063, 0x008c009c, F(RRR1), 5, "DDGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.q", 1, 0x00740063, 0x0088009c, F(RRR1), 5, "DDgg1", "12543", + { "msub.q", 1, 0x00740063, 0x0088009c, F(RRR1), 5, "DDgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msub.u", 1, 0x00400033, 0x00a000cc, F(RCR), 4, "DDdn", "1243", + { "msub.u", 1, 0x00400033, 0x00a000cc, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msub.u", 1, 0x00680023, 0x009700dc, F(RRR2), 4, "DDdd", "1243", + { "msub.u", 1, 0x00680023, 0x009700dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msubad.h", 1, 0x006000e3, 0x009c001c, F(RRR1), 5, "DDdL1", "12543", + { "msubad.h", 1, 0x006000e3, 0x009c001c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubad.h", 1, 0x006400e3, 0x0098001c, F(RRR1), 5, "DDdl1", "12543", + { "msubad.h", 1, 0x006400e3, 0x0098001c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubad.h", 1, 0x006800e3, 0x0094001c, F(RRR1), 5, "DDd-1", "12543", + { "msubad.h", 1, 0x006800e3, 0x0094001c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubad.h", 1, 0x006c00e3, 0x0090001c, F(RRR1), 5, "DDd+1", "12543", + { "msubad.h", 1, 0x006c00e3, 0x0090001c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadm.h", 1, 0x007000e3, 0x008c001c, F(RRR1), 5, "DDdL1", "12543", + { "msubadm.h", 1, 0x007000e3, 0x008c001c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadm.h", 1, 0x007400e3, 0x0088001c, F(RRR1), 5, "DDdl1", "12543", + { "msubadm.h", 1, 0x007400e3, 0x0088001c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadm.h", 1, 0x007800e3, 0x0084001c, F(RRR1), 5, "DDd-1", "12543", + { "msubadm.h", 1, 0x007800e3, 0x0084001c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadm.h", 1, 0x007c00e3, 0x0080001c, F(RRR1), 5, "DDd+1", "12543", + { "msubadm.h", 1, 0x007c00e3, 0x0080001c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadms.h", 1, 0x00f000e3, 0x000c001c, F(RRR1), 5, "DDdL1", "12543", + { "msubadms.h", 1, 0x00f000e3, 0x000c001c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadms.h", 1, 0x00f400e3, 0x0008001c, F(RRR1), 5, "DDdl1", "12543", + { "msubadms.h", 1, 0x00f400e3, 0x0008001c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadms.h", 1, 0x00f800e3, 0x0004001c, F(RRR1), 5, "DDd-1", "12543", + { "msubadms.h", 1, 0x00f800e3, 0x0004001c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadms.h", 1, 0x00fc00e3, 0x0000001c, F(RRR1), 5, "DDd+1", "12543", + { "msubadms.h", 1, 0x00fc00e3, 0x0000001c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadr.h", 1, 0x003000e3, 0x00cc001c, F(RRR1), 5, "dddL1", "12543", + { "msubadr.h", 1, 0x003000e3, 0x00cc001c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadr.h", 1, 0x003400e3, 0x00c8001c, F(RRR1), 5, "dddl1", "12543", + { "msubadr.h", 1, 0x003400e3, 0x00c8001c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadr.h", 1, 0x003800e3, 0x00c4001c, F(RRR1), 5, "ddd-1", "12543", + { "msubadr.h", 1, 0x003800e3, 0x00c4001c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadr.h", 1, 0x003c00e3, 0x00c0001c, F(RRR1), 5, "ddd+1", "12543", + { "msubadr.h", 1, 0x003c00e3, 0x00c0001c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadrs.h", 1, 0x00b000e3, 0x004c001c, F(RRR1), 5, "dddL1", "12543", + { "msubadrs.h", 1, 0x00b000e3, 0x004c001c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadrs.h", 1, 0x00b400e3, 0x0048001c, F(RRR1), 5, "dddl1", "12543", + { "msubadrs.h", 1, 0x00b400e3, 0x0048001c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadrs.h", 1, 0x00b800e3, 0x0044001c, F(RRR1), 5, "ddd-1", "12543", + { "msubadrs.h", 1, 0x00b800e3, 0x0044001c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubadrs.h", 1, 0x00bc00e3, 0x0040001c, F(RRR1), 5, "ddd+1", "12543", + { "msubadrs.h", 1, 0x00bc00e3, 0x0040001c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubads.h", 1, 0x00e000e3, 0x001c001c, F(RRR1), 5, "DDdL1", "12543", + { "msubads.h", 1, 0x00e000e3, 0x001c001c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubads.h", 1, 0x00e400e3, 0x0018001c, F(RRR1), 5, "DDdl1", "12543", + { "msubads.h", 1, 0x00e400e3, 0x0018001c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubads.h", 1, 0x00e800e3, 0x0014001c, F(RRR1), 5, "DDd-1", "12543", + { "msubads.h", 1, 0x00e800e3, 0x0014001c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubads.h", 1, 0x00ec00e3, 0x0010001c, F(RRR1), 5, "DDd+1", "12543", + { "msubads.h", 1, 0x00ec00e3, 0x0010001c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubm", 1, 0x00600033, 0x008000cc, F(RCR), 4, "DDd9", "1243", + { "msubm", 1, 0x00600033, 0x008000cc, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_A, INDICES}, - {"msubm", 1, 0x006a0023, 0x009500dc, F(RRR2), 4, "DDdd", "1243", + { "msubm", 1, 0x006a0023, 0x009500dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"msubm.h", 1, 0x007000a3, 0x008f005c, F(RRR1), 4, "DDdd", "1254", + { "msubm.h", 1, 0x007000a3, 0x008f005c, F(RRR1), 4, "DDdd", "1254", TRICORE_RIDER_A, INDICES}, - {"msubm.h", 1, 0x007000a3, 0x008c005c, F(RRR1), 5, "DDdL1", "12543", + { "msubm.h", 1, 0x007000a3, 0x008c005c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubm.h", 1, 0x007400a3, 0x0088005c, F(RRR1), 5, "DDdl1", "12543", + { "msubm.h", 1, 0x007400a3, 0x0088005c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubm.h", 1, 0x007800a3, 0x0084005c, F(RRR1), 5, "DDd-1", "12543", + { "msubm.h", 1, 0x007800a3, 0x0084005c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubm.h", 1, 0x007c00a3, 0x0080005c, F(RRR1), 5, "DDd+1", "12543", + { "msubm.h", 1, 0x007c00a3, 0x0080005c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubm.q", 1, 0x00700063, 0x008f009c, F(RRR1), 4, "DDdd", "1254", + { "msubm.q", 1, 0x00700063, 0x008f009c, F(RRR1), 4, "DDdd", "1254", TRICORE_RIDER_A, INDICES}, - {"msubm.u", 1, 0x00400033, 0x00a000cc, F(RCR), 4, "DDdn", "1243", + { "msubm.u", 1, 0x00400033, 0x00a000cc, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_A, INDICES}, - {"msubm.u", 1, 0x00680023, 0x009700dc, F(RRR2), 4, "DDdd", "1243", + { "msubm.u", 1, 0x00680023, 0x009700dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"msubms", 1, 0x00e00033, 0x000000cc, F(RCR), 4, "DDd9", "1243", + { "msubms", 1, 0x00e00033, 0x000000cc, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_A, INDICES}, - {"msubms", 1, 0x00ea0023, 0x001500dc, F(RRR2), 4, "DDdd", "1243", + { "msubms", 1, 0x00ea0023, 0x001500dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"msubms.h", 1, 0x00f000a3, 0x000c005c, F(RRR1), 5, "DDdL1", "12543", + { "msubms.h", 1, 0x00f000a3, 0x000c005c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubms.h", 1, 0x00f400a3, 0x0008005c, F(RRR1), 5, "DDdl1", "12543", + { "msubms.h", 1, 0x00f400a3, 0x0008005c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubms.h", 1, 0x00f800a3, 0x0004005c, F(RRR1), 5, "DDd-1", "12543", + { "msubms.h", 1, 0x00f800a3, 0x0004005c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubms.h", 1, 0x00fc00a3, 0x0000005c, F(RRR1), 5, "DDd+1", "12543", + { "msubms.h", 1, 0x00fc00a3, 0x0000005c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubms.u", 1, 0x00c00033, 0x002000cc, F(RCR), 4, "DDdn", "1243", + { "msubms.u", 1, 0x00c00033, 0x002000cc, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_A, INDICES}, - {"msubms.u", 1, 0x00e80023, 0x001700dc, F(RRR2), 4, "DDdd", "1243", + { "msubms.u", 1, 0x00e80023, 0x001700dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_A, INDICES}, - {"msubr.h", 1, 0x00780063, 0x0084009c, F(RRR1), 5, "dDdd1", "12543", + { "msubr.h", 1, 0x00780063, 0x0084009c, F(RRR1), 5, "dDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubr.h", 1, 0x00780063, 0x0084009c, F(RRR1), 5, "dDdL1", "12543", + { "msubr.h", 1, 0x00780063, 0x0084009c, F(RRR1), 5, "dDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.h", 1, 0x003000a3, 0x00cc005c, F(RRR1), 5, "dddL1", "12543", + { "msubr.h", 1, 0x003000a3, 0x00cc005c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.h", 1, 0x003400a3, 0x00c8005c, F(RRR1), 5, "dddl1", "12543", + { "msubr.h", 1, 0x003400a3, 0x00c8005c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.h", 1, 0x003800a3, 0x00c4005c, F(RRR1), 5, "ddd-1", "12543", + { "msubr.h", 1, 0x003800a3, 0x00c4005c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.h", 1, 0x003c00a3, 0x00c0005c, F(RRR1), 5, "ddd+1", "12543", + { "msubr.h", 1, 0x003c00a3, 0x00c0005c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.q", 1, 0x00180063, 0x00e4009c, F(RRR1), 5, "dddd1", "12543", + { "msubr.q", 1, 0x00180063, 0x00e4009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubr.q", 1, 0x00180063, 0x00e4009c, F(RRR1), 5, "ddGG1", "12543", + { "msubr.q", 1, 0x00180063, 0x00e4009c, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubr.q", 1, 0x001c0063, 0x00e0009c, F(RRR1), 5, "ddgg1", "12543", + { "msubr.q", 1, 0x001c0063, 0x00e0009c, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.h", 1, 0x00f80063, 0x0004009c, F(RRR1), 5, "dDdd1", "12543", + { "msubrs.h", 1, 0x00f80063, 0x0004009c, F(RRR1), 5, "dDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubrs.h", 1, 0x00f80063, 0x0004009c, F(RRR1), 5, "dDdL1", "12543", + { "msubrs.h", 1, 0x00f80063, 0x0004009c, F(RRR1), 5, "dDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.h", 1, 0x00b000a3, 0x004c005c, F(RRR1), 5, "dddL1", "12543", + { "msubrs.h", 1, 0x00b000a3, 0x004c005c, F(RRR1), 5, "dddL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.h", 1, 0x00b400a3, 0x0048005c, F(RRR1), 5, "dddl1", "12543", + { "msubrs.h", 1, 0x00b400a3, 0x0048005c, F(RRR1), 5, "dddl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.h", 1, 0x00b800a3, 0x0044005c, F(RRR1), 5, "ddd-1", "12543", + { "msubrs.h", 1, 0x00b800a3, 0x0044005c, F(RRR1), 5, "ddd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.h", 1, 0x00bc00a3, 0x0040005c, F(RRR1), 5, "ddd+1", "12543", + { "msubrs.h", 1, 0x00bc00a3, 0x0040005c, F(RRR1), 5, "ddd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.q", 1, 0x00980063, 0x0064009c, F(RRR1), 5, "dddd1", "12543", + { "msubrs.q", 1, 0x00980063, 0x0064009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubrs.q", 1, 0x00980063, 0x0064009c, F(RRR1), 5, "ddGG1", "12543", + { "msubrs.q", 1, 0x00980063, 0x0064009c, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubrs.q", 1, 0x009c0063, 0x0060009c, F(RRR1), 5, "ddgg1", "12543", + { "msubrs.q", 1, 0x009c0063, 0x0060009c, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs", 1, 0x008a0023, 0x007500dc, F(RRR2), 4, "dddd", "1243", + { "msubs", 1, 0x008a0023, 0x007500dc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"msubs", 1, 0x00a00033, 0x004000cc, F(RCR), 4, "ddd9", "1243", + { "msubs", 1, 0x00a00033, 0x004000cc, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"msubs", 1, 0x00e00033, 0x000000cc, F(RCR), 4, "DDd9", "1243", + { "msubs", 1, 0x00e00033, 0x000000cc, F(RCR), 4, "DDd9", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msubs", 1, 0x00ea0023, 0x001500dc, F(RRR2), 4, "DDdd", "1243", + { "msubs", 1, 0x00ea0023, 0x001500dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.h", 1, 0x00e000a3, 0x001c005c, F(RRR1), 5, "DDdd1", "12543", + { "msubs.h", 1, 0x00e000a3, 0x001c005c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubs.h", 1, 0x00e000a3, 0x001c005c, F(RRR1), 5, "DDdL1", "12543", + { "msubs.h", 1, 0x00e000a3, 0x001c005c, F(RRR1), 5, "DDdL1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.h", 1, 0x00e400a3, 0x0018005c, F(RRR1), 5, "DDdl1", "12543", + { "msubs.h", 1, 0x00e400a3, 0x0018005c, F(RRR1), 5, "DDdl1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.h", 1, 0x00e800a3, 0x0014005c, F(RRR1), 5, "DDd-1", "12543", + { "msubs.h", 1, 0x00e800a3, 0x0014005c, F(RRR1), 5, "DDd-1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.h", 1, 0x00ec00a3, 0x0010005c, F(RRR1), 5, "DDd+1", "12543", + { "msubs.h", 1, 0x00ec00a3, 0x0010005c, F(RRR1), 5, "DDd+1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00900063, 0x006c009c, F(RRR1), 5, "dddd1", "12543", + { "msubs.q", 1, 0x00900063, 0x006c009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_A, INDICES}, - {"msubs.q", 1, 0x00900063, 0x006c009c, F(RRR1), 5, "ddGG1", "12543", + { "msubs.q", 1, 0x00900063, 0x006c009c, F(RRR1), 5, "ddGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00800063, 0x007c009c, F(RRR1), 5, "dddG1", "12543", + { "msubs.q", 1, 0x00800063, 0x007c009c, F(RRR1), 5, "dddG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00840063, 0x0078009c, F(RRR1), 5, "dddg1", "12543", + { "msubs.q", 1, 0x00840063, 0x0078009c, F(RRR1), 5, "dddg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00880063, 0x0074009c, F(RRR1), 5, "dddd1", "12543", + { "msubs.q", 1, 0x00880063, 0x0074009c, F(RRR1), 5, "dddd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00940063, 0x0068009c, F(RRR1), 5, "ddgg1", "12543", + { "msubs.q", 1, 0x00940063, 0x0068009c, F(RRR1), 5, "ddgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00e00063, 0x001c009c, F(RRR1), 5, "DDdG1", "12543", + { "msubs.q", 1, 0x00e00063, 0x001c009c, F(RRR1), 5, "DDdG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00e40063, 0x0018009c, F(RRR1), 5, "DDdg1", "12543", + { "msubs.q", 1, 0x00e40063, 0x0018009c, F(RRR1), 5, "DDdg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00ec0063, 0x0010009c, F(RRR1), 5, "DDdd1", "12543", + { "msubs.q", 1, 0x00ec0063, 0x0010009c, F(RRR1), 5, "DDdd1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00f00063, 0x000c009c, F(RRR1), 5, "DDGG1", "12543", + { "msubs.q", 1, 0x00f00063, 0x000c009c, F(RRR1), 5, "DDGG1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.q", 1, 0x00f40063, 0x0008009c, F(RRR1), 5, "DDgg1", "12543", + { "msubs.q", 1, 0x00f40063, 0x0008009c, F(RRR1), 5, "DDgg1", "12543", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.u", 1, 0x00800033, 0x006000cc, F(RCR), 4, "dddn", "1243", + { "msubs.u", 1, 0x00800033, 0x006000cc, F(RCR), 4, "dddn", "1243", TRICORE_GENERIC, INDICES}, - {"msubs.u", 1, 0x00880023, 0x007700dc, F(RRR2), 4, "dddd", "1243", + { "msubs.u", 1, 0x00880023, 0x007700dc, F(RRR2), 4, "dddd", "1243", TRICORE_GENERIC, INDICES}, - {"msubs.u", 1, 0x00c00033, 0x002000cc, F(RCR), 4, "DDdn", "1243", + { "msubs.u", 1, 0x00c00033, 0x002000cc, F(RCR), 4, "DDdn", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"msubs.u", 1, 0x00e80023, 0x001700dc, F(RRR2), 4, "DDdd", "1243", + { "msubs.u", 1, 0x00e80023, 0x001700dc, F(RRR2), 4, "DDdd", "1243", TRICORE_RIDER_B_UP, INDICES}, - {"mtcr", 1, 0x000000cd, 0xf0000032, F(RLC), 2, "Wd", "23", + { "mtcr", 1, 0x000000cd, 0xf0000032, F(RLC), 2, "Wd", "23", TRICORE_GENERIC, INDICES}, - {"mtfr", 1, 0x01c1004b, 0xfe3e00b4, F(RR), 2, "dd", "43", + { "mtfr", 1, 0x01c1004b, 0xfe3e00b4, F(RR), 2, "dd", "43", TRICORE_V2_UP, INDICES}, - {"mul", 0, 0x000000e2, 0xffff001d, F(SRR), 2, "dd", "21", + { "mul", 0, 0x000000e2, 0xffff001d, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"mul", 1, 0x00200053, 0x0fc000ac, F(RC), 3, "dd9", "132", + { "mul", 1, 0x00200053, 0x0fc000ac, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"mul", 1, 0x00a00073, 0x0f5f008c, F(RR), 3, "ddd", "143", + { "mul", 1, 0x00a00073, 0x0f5f008c, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"mul", 1, 0x000a0073, 0x0ff5008c, F(RR2), 3, "ddd", "132", + { "mul", 1, 0x000a0073, 0x0ff5008c, F(RR2), 3, "ddd", "132", TRICORE_RIDER_B_UP, INDICES}, - {"mul", 1, 0x00600053, 0x0f8000ac, F(RC), 3, "Dd9", "132", + { "mul", 1, 0x00600053, 0x0f8000ac, F(RC), 3, "Dd9", "132", TRICORE_RIDER_B_UP, INDICES}, - {"mul", 1, 0x006a0073, 0x0f95008c, F(RR2), 3, "Ddd", "132", + { "mul", 1, 0x006a0073, 0x0f95008c, F(RR2), 3, "Ddd", "132", TRICORE_RIDER_B_UP, INDICES}, - {"mul.f", 1, 0x0041004b, 0x0fbe00b4, F(RR), 3, "ddd", "143", + { "mul.f", 1, 0x0041004b, 0x0fbe00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_D_UP, INDICES}, - {"mul.h", 1, 0x018000b3, 0x0e7c004c, F(RR), 4, "Ddd1", "1432", + { "mul.h", 1, 0x018000b3, 0x0e7c004c, F(RR), 4, "Ddd1", "1432", TRICORE_RIDER_A, INDICES}, - {"mul.h", 1, 0x006000b3, 0x0f9c004c, F(RR1), 4, "DdL1", "1432", + { "mul.h", 1, 0x006000b3, 0x0f9c004c, F(RR1), 4, "DdL1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.h", 1, 0x006400b3, 0x0f98004c, F(RR1), 4, "Ddl1", "1432", + { "mul.h", 1, 0x006400b3, 0x0f98004c, F(RR1), 4, "Ddl1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.h", 1, 0x006800b3, 0x0f94004c, F(RR1), 4, "Dd-1", "1432", + { "mul.h", 1, 0x006800b3, 0x0f94004c, F(RR1), 4, "Dd-1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.h", 1, 0x006c00b3, 0x0f90004c, F(RR1), 4, "Dd+1", "1432", + { "mul.h", 1, 0x006c00b3, 0x0f90004c, F(RR1), 4, "Dd+1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00400093, 0x0fbc006c, F(RR), 4, "ddd1", "1432", + { "mul.q", 1, 0x00400093, 0x0fbc006c, F(RR), 4, "ddd1", "1432", TRICORE_RIDER_A, INDICES}, - {"mul.q", 1, 0x00000093, 0x0ffc006c, F(RR1), 4, "ddG1", "1432", + { "mul.q", 1, 0x00000093, 0x0ffc006c, F(RR1), 4, "ddG1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00040093, 0x0ff8006c, F(RR1), 4, "ddg1", "1432", + { "mul.q", 1, 0x00040093, 0x0ff8006c, F(RR1), 4, "ddg1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00080093, 0x0ff4006c, F(RR1), 4, "ddd1", "1432", + { "mul.q", 1, 0x00080093, 0x0ff4006c, F(RR1), 4, "ddd1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00100093, 0x0fec006c, F(RR1), 4, "dGG1", "1432", + { "mul.q", 1, 0x00100093, 0x0fec006c, F(RR1), 4, "dGG1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00140093, 0x0fe8006c, F(RR1), 4, "dgg1", "1432", + { "mul.q", 1, 0x00140093, 0x0fe8006c, F(RR1), 4, "dgg1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00600093, 0x0f9c006c, F(RR1), 4, "DdG1", "1432", + { "mul.q", 1, 0x00600093, 0x0f9c006c, F(RR1), 4, "DdG1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x00640093, 0x0f98006c, F(RR1), 4, "Ddg1", "1432", + { "mul.q", 1, 0x00640093, 0x0f98006c, F(RR1), 4, "Ddg1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.q", 1, 0x006c0093, 0x0f90006c, F(RR1), 4, "Ddd1", "1432", + { "mul.q", 1, 0x006c0093, 0x0f90006c, F(RR1), 4, "Ddd1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mul.u", 1, 0x00400053, 0x0fa000ac, F(RC), 3, "Ddn", "132", + { "mul.u", 1, 0x00400053, 0x0fa000ac, F(RC), 3, "Ddn", "132", TRICORE_RIDER_B_UP, INDICES}, - {"mul.u", 1, 0x00680073, 0x0f97008c, F(RR2), 3, "Ddd", "132", + { "mul.u", 1, 0x00680073, 0x0f97008c, F(RR2), 3, "Ddd", "132", TRICORE_RIDER_B_UP, INDICES}, - {"mulm", 1, 0x00600053, 0x0f8000ac, F(RC), 3, "Dd9", "132", + { "mulm", 1, 0x00600053, 0x0f8000ac, F(RC), 3, "Dd9", "132", TRICORE_RIDER_A, INDICES}, - {"mulm", 1, 0x06a00073, 0x095f008c, F(RR), 3, "Ddd", "143", + { "mulm", 1, 0x06a00073, 0x095f008c, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"mulm.h", 1, 0x007000b3, 0x0f8c004c, F(RR1), 4, "DdL1", "1432", + { "mulm.h", 1, 0x007000b3, 0x0f8c004c, F(RR1), 4, "DdL1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulm.h", 1, 0x007400b3, 0x0f88004c, F(RR1), 4, "Ddl1", "1432", + { "mulm.h", 1, 0x007400b3, 0x0f88004c, F(RR1), 4, "Ddl1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulm.h", 1, 0x007800b3, 0x0f84004c, F(RR1), 4, "Dd-1", "1432", + { "mulm.h", 1, 0x007800b3, 0x0f84004c, F(RR1), 4, "Dd-1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulm.h", 1, 0x007c00b3, 0x0f80004c, F(RR1), 4, "Dd+1", "1432", + { "mulm.h", 1, 0x007c00b3, 0x0f80004c, F(RR1), 4, "Dd+1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulm.u", 1, 0x00400053, 0x0fa000ac, F(RC), 3, "Ddn", "132", + { "mulm.u", 1, 0x00400053, 0x0fa000ac, F(RC), 3, "Ddn", "132", TRICORE_RIDER_A, INDICES}, - {"mulm.u", 1, 0x06800073, 0x097f008c, F(RR), 3, "Ddd", "143", + { "mulm.u", 1, 0x06800073, 0x097f008c, F(RR), 3, "Ddd", "143", TRICORE_RIDER_A, INDICES}, - {"mulms.h", 1, 0x00f000b3, 0x0f0c004c, F(RR1), 4, "DdL1", "1432", + { "mulms.h", 1, 0x00f000b3, 0x0f0c004c, F(RR1), 4, "DdL1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulms.h", 1, 0x00f400b3, 0x0f08004c, F(RR1), 4, "Ddl1", "1432", + { "mulms.h", 1, 0x00f400b3, 0x0f08004c, F(RR1), 4, "Ddl1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulms.h", 1, 0x00f800b3, 0x0f04004c, F(RR1), 4, "Dd-1", "1432", + { "mulms.h", 1, 0x00f800b3, 0x0f04004c, F(RR1), 4, "Dd-1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulms.h", 1, 0x00fc00b3, 0x0f00004c, F(RR1), 4, "Dd+1", "1432", + { "mulms.h", 1, 0x00fc00b3, 0x0f00004c, F(RR1), 4, "Dd+1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.h", 1, 0x00c000b3, 0x0f3c004c, F(RR), 4, "ddd1", "1432", + { "mulr.h", 1, 0x00c000b3, 0x0f3c004c, F(RR), 4, "ddd1", "1432", TRICORE_RIDER_A, INDICES}, - {"mulr.h", 1, 0x003000b3, 0x0fcc004c, F(RR1), 4, "ddL1", "1432", + { "mulr.h", 1, 0x003000b3, 0x0fcc004c, F(RR1), 4, "ddL1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.h", 1, 0x003400b3, 0x0fc8004c, F(RR1), 4, "ddl1", "1432", + { "mulr.h", 1, 0x003400b3, 0x0fc8004c, F(RR1), 4, "ddl1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.h", 1, 0x003800b3, 0x0fc4004c, F(RR1), 4, "dd-1", "1432", + { "mulr.h", 1, 0x003800b3, 0x0fc4004c, F(RR1), 4, "dd-1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.h", 1, 0x003c00b3, 0x0fc0004c, F(RR1), 4, "dd+1", "1432", + { "mulr.h", 1, 0x003c00b3, 0x0fc0004c, F(RR1), 4, "dd+1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.q", 1, 0x00600093, 0x0f9c006c, F(RR), 4, "ddd1", "1432", + { "mulr.q", 1, 0x00600093, 0x0f9c006c, F(RR), 4, "ddd1", "1432", TRICORE_RIDER_A, INDICES}, - {"mulr.q", 1, 0x00180093, 0x0fe4006c, F(RR1), 4, "dGG1", "1432", + { "mulr.q", 1, 0x00180093, 0x0fe4006c, F(RR1), 4, "dGG1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"mulr.q", 1, 0x001c0093, 0x0fe0006c, F(RR1), 4, "dgg1", "1432", + { "mulr.q", 1, 0x001c0093, 0x0fe0006c, F(RR1), 4, "dgg1", "1432", TRICORE_RIDER_B_UP, INDICES}, - {"muls", 1, 0x00a00053, 0x0f4000ac, F(RC), 3, "dd9", "132", + { "muls", 1, 0x00a00053, 0x0f4000ac, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"muls", 1, 0x08a00073, 0x075f008c, F(RR), 3, "ddd", "143", + { "muls", 1, 0x08a00073, 0x075f008c, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"muls", 1, 0x008a0073, 0x0f75008c, F(RR2), 3, "ddd", "132", + { "muls", 1, 0x008a0073, 0x0f75008c, F(RR2), 3, "ddd", "132", TRICORE_RIDER_B_UP, INDICES}, - {"muls.u", 1, 0x00800053, 0x0f6000ac, F(RC), 3, "ddn", "132", + { "muls.u", 1, 0x00800053, 0x0f6000ac, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"muls.u", 1, 0x08800073, 0x077f008c, F(RR), 3, "ddd", "143", + { "muls.u", 1, 0x08800073, 0x077f008c, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"muls.u", 1, 0x00880073, 0x0f77008c, F(RR2), 3, "ddd", "132", + { "muls.u", 1, 0x00880073, 0x0f77008c, F(RR2), 3, "ddd", "132", TRICORE_RIDER_B_UP, INDICES}, - {"nand", 1, 0x0090000f, 0x0f6f00f0, F(RR), 3, "ddd", "143", + { "nand", 1, 0x0090000f, 0x0f6f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"nand", 1, 0x0120008f, 0x0ec00070, F(RC), 3, "ddn", "132", + { "nand", 1, 0x0120008f, 0x0ec00070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"nand.t", 1, 0x00000007, 0x006000f8, F(BIT), 5, "dd5d5", "15342", + { "nand.t", 1, 0x00000007, 0x006000f8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"ne", 1, 0x0110000b, 0x0eef00f4, F(RR), 3, "ddd", "143", + { "ne", 1, 0x0110000b, 0x0eef00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"ne", 1, 0x0220008b, 0x0dc00074, F(RC), 3, "dd9", "132", + { "ne", 1, 0x0220008b, 0x0dc00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"ne.a", 1, 0x04100001, 0x0bef00fe, F(RR), 3, "daa", "143", + { "ne.a", 1, 0x04100001, 0x0bef00fe, F(RR), 3, "daa", "143", TRICORE_GENERIC, INDICES}, - {"nez.a", 1, 0x04900001, 0x0b6ff0fe, F(RR), 2, "da", "14", + { "nez.a", 1, 0x04900001, 0x0b6ff0fe, F(RR), 2, "da", "14", TRICORE_GENERIC, INDICES}, - {"nop", 0, 0x00000000, 0xffffffff, F(SR), 0, "", "", + { "nop", 0, 0x00000000, 0xffffffff, F(SR), 0, "", "", TRICORE_GENERIC, INDICES}, - {"nop", 1, 0x0000000d, 0xfffffff2, F(SYS), 0, "", "", + { "nop", 1, 0x0000000d, 0xfffffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"nor", 0, 0x00000036, 0xfffff0c9, F(SR), 1, "d", "1", + { "nor", 0, 0x00000036, 0xfffff0c9, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"nor", 0, 0x00000046, 0xfffff0b9, F(SR), 1, "d", "1", + { "nor", 0, 0x00000046, 0xfffff0b9, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"nor", 1, 0x00b0000f, 0x0f4f00f0, F(RR), 3, "ddd", "143", + { "nor", 1, 0x00b0000f, 0x0f4f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"nor", 1, 0x0160008f, 0x0e800070, F(RC), 3, "ddn", "132", + { "nor", 1, 0x0160008f, 0x0e800070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"nor.t", 1, 0x00400087, 0x00200078, F(BIT), 5, "dd5d5", "15342", + { "nor.t", 1, 0x00400087, 0x00200078, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"or", 0, 0x00000056, 0xffff00a9, F(SRR), 2, "dd", "21", + { "or", 0, 0x00000056, 0xffff00a9, F(SRR), 2, "dd", "21", TRICORE_RIDER_A, INDICES}, - {"or", 0, 0x000000a6, 0xffff0059, F(SRR), 2, "dd", "21", + { "or", 0, 0x000000a6, 0xffff0059, F(SRR), 2, "dd", "21", TRICORE_RIDER_B_UP, INDICES}, - {"or", 0, 0x000000d6, 0xffff0029, F(SC), 2, "i8", "01", + { "or", 0, 0x000000d6, 0xffff0029, F(SC), 2, "i8", "01", TRICORE_RIDER_A, INDICES}, - {"or", 0, 0x00000096, 0xffff0069, F(SC), 2, "i8", "01", + { "or", 0, 0x00000096, 0xffff0069, F(SC), 2, "i8", "01", TRICORE_RIDER_B_UP, INDICES}, - {"or", 1, 0x00a0000f, 0x0f5f00f0, F(RR), 3, "ddd", "143", + { "or", 1, 0x00a0000f, 0x0f5f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or", 1, 0x0140008f, 0x0ea00070, F(RC), 3, "ddn", "132", + { "or", 1, 0x0140008f, 0x0ea00070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"or.and.t", 1, 0x000000c7, 0x00600038, F(BIT), 5, "dd5d5", "15342", + { "or.and.t", 1, 0x000000c7, 0x00600038, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"or.andn.t", 1, 0x006000c7, 0x00000038, F(BIT), 5, "dd5d5", "15342", + { "or.andn.t", 1, 0x006000c7, 0x00000038, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"or.eq", 1, 0x0270000b, 0x0d8f00f4, F(RR), 3, "ddd", "143", + { "or.eq", 1, 0x0270000b, 0x0d8f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.eq", 1, 0x04e0008b, 0x0b000074, F(RC), 3, "dd9", "132", + { "or.eq", 1, 0x04e0008b, 0x0b000074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"or.ge", 1, 0x02b0000b, 0x0d4f00f4, F(RR), 3, "ddd", "143", + { "or.ge", 1, 0x02b0000b, 0x0d4f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.ge", 1, 0x0560008b, 0x0a800074, F(RC), 3, "dd9", "132", + { "or.ge", 1, 0x0560008b, 0x0a800074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"or.ge.u", 1, 0x02c0000b, 0x0d3f00f4, F(RR), 3, "ddd", "143", + { "or.ge.u", 1, 0x02c0000b, 0x0d3f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.ge.u", 1, 0x0580008b, 0x0a600074, F(RC), 3, "ddn", "132", + { "or.ge.u", 1, 0x0580008b, 0x0a600074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"or.lt", 1, 0x0290000b, 0x0d6f00f4, F(RR), 3, "ddd", "143", + { "or.lt", 1, 0x0290000b, 0x0d6f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.lt", 1, 0x0520008b, 0x0ac00074, F(RC), 3, "dd9", "132", + { "or.lt", 1, 0x0520008b, 0x0ac00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"or.lt.u", 1, 0x02a0000b, 0x0d5f00f4, F(RR), 3, "ddd", "143", + { "or.lt.u", 1, 0x02a0000b, 0x0d5f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.lt.u", 1, 0x0540008b, 0x0aa00074, F(RC), 3, "ddn", "132", + { "or.lt.u", 1, 0x0540008b, 0x0aa00074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"or.ne", 1, 0x0280000b, 0x0d7f00f4, F(RR), 3, "ddd", "143", + { "or.ne", 1, 0x0280000b, 0x0d7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"or.ne", 1, 0x0500008b, 0x0ae00074, F(RC), 3, "dd9", "132", + { "or.ne", 1, 0x0500008b, 0x0ae00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"or.nor.t", 1, 0x004000c7, 0x00200038, F(BIT), 5, "dd5d5", "15342", + { "or.nor.t", 1, 0x004000c7, 0x00200038, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"or.or.t", 1, 0x002000c7, 0x00400038, F(BIT), 5, "dd5d5", "15342", + { "or.or.t", 1, 0x002000c7, 0x00400038, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"or.t", 1, 0x00200087, 0x00400078, F(BIT), 5, "dd5d5", "15342", + { "or.t", 1, 0x00200087, 0x00400078, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"orn", 1, 0x00f0000f, 0x0f0f00f0, F(RR), 3, "ddd", "143", + { "orn", 1, 0x00f0000f, 0x0f0f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"orn", 1, 0x01e0008f, 0x0e000070, F(RC), 3, "ddn", "132", + { "orn", 1, 0x01e0008f, 0x0e000070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"orn.t", 1, 0x00200007, 0x004000f8, F(BIT), 5, "dd5d5", "15342", + { "orn.t", 1, 0x00200007, 0x004000f8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"pack", 1, 0x0000006b, 0x00fff094, F(RRR), 3, "dDd", "125", + { "pack", 1, 0x0000006b, 0x00fff094, F(RRR), 3, "dDd", "125", TRICORE_GENERIC, INDICES}, - {"parity", 1, 0x0080004b, 0x0f7ff0b4, F(RR), 2, "dd", "14", + { "parity", 1, 0x0080004b, 0x0f7ff0b4, F(RR), 2, "dd", "14", TRICORE_RIDER_A, INDICES}, - {"parity", 1, 0x0020004b, 0x0fdff0b4, F(RR), 2, "dd", "14", + { "parity", 1, 0x0020004b, 0x0fdff0b4, F(RR), 2, "dd", "14", TRICORE_RIDER_B_UP, INDICES}, - {"q31tof", 1, 0x0151004b, 0x0eae00b4, F(RR), 3, "ddd", "143", + { "q31tof", 1, 0x0151004b, 0x0eae00b4, F(RR), 3, "ddd", "143", TRICORE_RIDER_D_UP, INDICES}, - {"qseed.f", 1, 0x0191004b, 0x0e6ef0b4, F(RR), 2, "dd", "14", + { "qseed.f", 1, 0x0191004b, 0x0e6ef0b4, F(RR), 2, "dd", "14", TRICORE_RIDER_D_UP, INDICES}, - {"restore", 1, 0x0380000d, 0xfc7ff0f2, F(SYS), 1, "d", "1", + { "restore", 1, 0x0380000d, 0xfc7ff0f2, F(SYS), 1, "d", "1", TRICORE_V2_UP, INDICES}, - {"ret", 0, 0x00009000, 0xffff6fff, F(SR), 0, "", "", + { "ret", 0, 0x00009000, 0xffff6fff, F(SR), 0, "", "", TRICORE_GENERIC, INDICES}, - {"ret", 1, 0x0140000d, 0xfebffff2, F(SYS), 0, "", "", + { "ret", 1, 0x0140000d, 0xfebffff2, F(SYS), 0, "", "", TRICORE_RIDER_A, INDICES}, - {"ret", 1, 0x0180000d, 0xfe7ffff2, F(SYS), 0, "", "", + { "ret", 1, 0x0180000d, 0xfe7ffff2, F(SYS), 0, "", "", TRICORE_RIDER_B_UP, INDICES}, - {"rfe", 0, 0x00008000, 0xffff7fff, F(SR), 0, "", "", + { "rfe", 0, 0x00008000, 0xffff7fff, F(SR), 0, "", "", TRICORE_GENERIC, INDICES}, - {"rfe", 1, 0x0180000d, 0xfe7ffff2, F(SYS), 0, "", "", + { "rfe", 1, 0x0180000d, 0xfe7ffff2, F(SYS), 0, "", "", TRICORE_RIDER_A, INDICES}, - {"rfe", 1, 0x01c0000d, 0xfe3ffff2, F(SYS), 0, "", "", + { "rfe", 1, 0x01c0000d, 0xfe3ffff2, F(SYS), 0, "", "", TRICORE_RIDER_B_UP, INDICES}, - {"rfm", 1, 0x0140000d, 0xfebffff2, F(SYS), 0, "", "", + { "rfm", 1, 0x0140000d, 0xfebffff2, F(SYS), 0, "", "", TRICORE_RIDER_B_UP, INDICES}, - {"rslcx", 1, 0x0240000d, 0xfdbffff2, F(SYS), 0, "", "", + { "rslcx", 1, 0x0240000d, 0xfdbffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"rstv", 1, 0x0000002f, 0xffffffd0, F(SYS), 0, "", "", + { "rstv", 1, 0x0000002f, 0xffffffd0, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"rsub", 0, 0x000050d2, 0xffffa02d, F(SR), 1, "d", "1", + { "rsub", 0, 0x000050d2, 0xffffa02d, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"rsub", 0, 0x00005032, 0xffffa0cd, F(SR), 1, "d", "1", + { "rsub", 0, 0x00005032, 0xffffa0cd, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"rsub", 1, 0x0100008b, 0x0ee00074, F(RC), 3, "dd9", "132", + { "rsub", 1, 0x0100008b, 0x0ee00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"rsubs", 1, 0x0140008b, 0x0ea00074, F(RC), 3, "dd9", "132", + { "rsubs", 1, 0x0140008b, 0x0ea00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"rsubs.u", 1, 0x0160008b, 0x0e800074, F(RC), 3, "dd9", "132", + { "rsubs.u", 1, 0x0160008b, 0x0e800074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sat.b", 0, 0x000000d2, 0xfffff02d, F(SR), 1, "d", "1", + { "sat.b", 0, 0x000000d2, 0xfffff02d, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"sat.b", 0, 0x00000032, 0xfffff0cd, F(SR), 1, "d", "1", + { "sat.b", 0, 0x00000032, 0xfffff0cd, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"sat.b", 1, 0x05e0000b, 0x0a1ff0f4, F(RR), 2, "dd", "14", + { "sat.b", 1, 0x05e0000b, 0x0a1ff0f4, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"sat.bu", 0, 0x000010d2, 0xffffe02d, F(SR), 1, "d", "1", + { "sat.bu", 0, 0x000010d2, 0xffffe02d, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"sat.bu", 0, 0x00001032, 0xffffe0cd, F(SR), 1, "d", "1", + { "sat.bu", 0, 0x00001032, 0xffffe0cd, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"sat.bu", 1, 0x05f0000b, 0x0a0ff0f4, F(RR), 2, "dd", "14", + { "sat.bu", 1, 0x05f0000b, 0x0a0ff0f4, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"sat.h", 0, 0x000020d2, 0xffffd02d, F(SR), 1, "d", "1", + { "sat.h", 0, 0x000020d2, 0xffffd02d, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"sat.h", 0, 0x00002032, 0xffffd0cd, F(SR), 1, "d", "1", + { "sat.h", 0, 0x00002032, 0xffffd0cd, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"sat.h", 1, 0x07e0000b, 0x081ff0f4, F(RR), 2, "dd", "14", + { "sat.h", 1, 0x07e0000b, 0x081ff0f4, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"sat.hu", 0, 0x000030d2, 0xffffc02d, F(SR), 1, "d", "1", + { "sat.hu", 0, 0x000030d2, 0xffffc02d, F(SR), 1, "d", "1", TRICORE_RIDER_A, INDICES}, - {"sat.hu", 0, 0x00003032, 0xffffc0cd, F(SR), 1, "d", "1", + { "sat.hu", 0, 0x00003032, 0xffffc0cd, F(SR), 1, "d", "1", TRICORE_RIDER_B_UP, INDICES}, - {"sat.hu", 1, 0x07f0000b, 0x080ff0f4, F(RR), 2, "dd", "14", + { "sat.hu", 1, 0x07f0000b, 0x080ff0f4, F(RR), 2, "dd", "14", TRICORE_GENERIC, INDICES}, - {"sel", 1, 0x0040002b, 0x00bf00d4, F(RRR), 4, "dddd", "1254", + { "sel", 1, 0x0040002b, 0x00bf00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"sel", 1, 0x008000ab, 0x00600054, F(RCR), 4, "ddd9", "1243", + { "sel", 1, 0x008000ab, 0x00600054, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"sel.a", 1, 0x00400021, 0x00bf00de, F(RRR), 4, "adaa", "1254", + { "sel.a", 1, 0x00400021, 0x00bf00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"sel.a", 1, 0x008000a1, 0x0060005e, F(RCR), 4, "ada9", "1243", + { "sel.a", 1, 0x008000a1, 0x0060005e, F(RCR), 4, "ada9", "1243", TRICORE_RIDER_A, INDICES}, - {"seln", 1, 0x0050002b, 0x00af00d4, F(RRR), 4, "dddd", "1254", + { "seln", 1, 0x0050002b, 0x00af00d4, F(RRR), 4, "dddd", "1254", TRICORE_GENERIC, INDICES}, - {"seln", 1, 0x00a000ab, 0x00400054, F(RCR), 4, "ddd9", "1243", + { "seln", 1, 0x00a000ab, 0x00400054, F(RCR), 4, "ddd9", "1243", TRICORE_GENERIC, INDICES}, - {"seln.a", 1, 0x00500021, 0x00af00de, F(RRR), 4, "adaa", "1254", + { "seln.a", 1, 0x00500021, 0x00af00de, F(RRR), 4, "adaa", "1254", TRICORE_RIDER_A, INDICES}, - {"seln.a", 1, 0x00a000a1, 0x0040005e, F(RCR), 4, "ada9", "1243", + { "seln.a", 1, 0x00a000a1, 0x0040005e, F(RCR), 4, "ada9", "1243", TRICORE_RIDER_A, INDICES}, - {"sh", 0, 0x00000026, 0xffff00d9, F(SRC), 2, "d4", "21", + { "sh", 0, 0x00000026, 0xffff00d9, F(SRC), 2, "d4", "21", TRICORE_RIDER_A, INDICES}, - {"sh", 0, 0x00000006, 0xffff00f9, F(SRC), 2, "d4", "21", + { "sh", 0, 0x00000006, 0xffff00f9, F(SRC), 2, "d4", "21", TRICORE_RIDER_B_UP, INDICES}, - {"sh", 1, 0x0000000f, 0x0fff00f0, F(RR), 3, "ddd", "143", + { "sh", 1, 0x0000000f, 0x0fff00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh", 1, 0x0000008f, 0x0fe00070, F(RC), 3, "dd9", "132", + { "sh", 1, 0x0000008f, 0x0fe00070, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.and.t", 1, 0x00000027, 0x006000d8, F(BIT), 5, "dd5d5", "15342", + { "sh.and.t", 1, 0x00000027, 0x006000d8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.andn.t", 1, 0x00600027, 0x000000d8, F(BIT), 5, "dd5d5", "15342", + { "sh.andn.t", 1, 0x00600027, 0x000000d8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.b", 1, 0x0200000f, 0x0dff00f0, F(RR), 3, "ddd", "143", + { "sh.b", 1, 0x0200000f, 0x0dff00f0, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"sh.b", 1, 0x0400008f, 0x0be00070, F(RC), 3, "dd9", "132", + { "sh.b", 1, 0x0400008f, 0x0be00070, F(RC), 3, "dd9", "132", TRICORE_RIDER_A, INDICES}, - {"sh.eq", 1, 0x0370000b, 0x0c8f00f4, F(RR), 3, "ddd", "143", + { "sh.eq", 1, 0x0370000b, 0x0c8f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.eq", 1, 0x06e0008b, 0x09000074, F(RC), 3, "dd9", "132", + { "sh.eq", 1, 0x06e0008b, 0x09000074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.ge", 1, 0x03b0000b, 0x0c4f00f4, F(RR), 3, "ddd", "143", + { "sh.ge", 1, 0x03b0000b, 0x0c4f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.ge", 1, 0x0760008b, 0x08800074, F(RC), 3, "dd9", "132", + { "sh.ge", 1, 0x0760008b, 0x08800074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.ge.u", 1, 0x03c0000b, 0x0c3f00f4, F(RR), 3, "ddd", "143", + { "sh.ge.u", 1, 0x03c0000b, 0x0c3f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.ge.u", 1, 0x0780008b, 0x08600074, F(RC), 3, "ddn", "132", + { "sh.ge.u", 1, 0x0780008b, 0x08600074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"sh.h", 1, 0x0400000f, 0x0bff00f0, F(RR), 3, "ddd", "143", + { "sh.h", 1, 0x0400000f, 0x0bff00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.h", 1, 0x0800008f, 0x07e00070, F(RC), 3, "dd9", "132", + { "sh.h", 1, 0x0800008f, 0x07e00070, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.lt", 1, 0x0390000b, 0x0c6f00f4, F(RR), 3, "ddd", "143", + { "sh.lt", 1, 0x0390000b, 0x0c6f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.lt", 1, 0x0720008b, 0x08c00074, F(RC), 3, "dd9", "132", + { "sh.lt", 1, 0x0720008b, 0x08c00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.lt.u", 1, 0x03a0000b, 0x0c5f00f4, F(RR), 3, "ddd", "143", + { "sh.lt.u", 1, 0x03a0000b, 0x0c5f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.lt.u", 1, 0x0740008b, 0x08a00074, F(RC), 3, "ddn", "132", + { "sh.lt.u", 1, 0x0740008b, 0x08a00074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"sh.nand.t", 1, 0x000000a7, 0x00600058, F(BIT), 5, "dd5d5", "15342", + { "sh.nand.t", 1, 0x000000a7, 0x00600058, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.ne", 1, 0x0380000b, 0x0c7f00f4, F(RR), 3, "ddd", "143", + { "sh.ne", 1, 0x0380000b, 0x0c7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sh.ne", 1, 0x0700008b, 0x08e00074, F(RC), 3, "dd9", "132", + { "sh.ne", 1, 0x0700008b, 0x08e00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sh.nor.t", 1, 0x00400027, 0x002000d8, F(BIT), 5, "dd5d5", "15342", + { "sh.nor.t", 1, 0x00400027, 0x002000d8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.or.t", 1, 0x00200027, 0x004000d8, F(BIT), 5, "dd5d5", "15342", + { "sh.or.t", 1, 0x00200027, 0x004000d8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.orn.t", 1, 0x002000a7, 0x00400058, F(BIT), 5, "dd5d5", "15342", + { "sh.orn.t", 1, 0x002000a7, 0x00400058, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.xnor.t", 1, 0x004000a7, 0x00200058, F(BIT), 5, "dd5d5", "15342", + { "sh.xnor.t", 1, 0x004000a7, 0x00200058, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sh.xor.t", 1, 0x006000a7, 0x00000058, F(BIT), 5, "dd5d5", "15342", + { "sh.xor.t", 1, 0x006000a7, 0x00000058, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"sha", 0, 0x000000a6, 0xffff0059, F(SRC), 2, "d4", "21", + { "sha", 0, 0x000000a6, 0xffff0059, F(SRC), 2, "d4", "21", TRICORE_RIDER_A, INDICES}, - {"sha", 0, 0x00000086, 0xffff0079, F(SRC), 2, "d4", "21", + { "sha", 0, 0x00000086, 0xffff0079, F(SRC), 2, "d4", "21", TRICORE_RIDER_B_UP, INDICES}, - {"sha", 1, 0x0010000f, 0x0fef00f0, F(RR), 3, "ddd", "143", + { "sha", 1, 0x0010000f, 0x0fef00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sha", 1, 0x0020008f, 0x0fc00070, F(RC), 3, "dd9", "132", + { "sha", 1, 0x0020008f, 0x0fc00070, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"sha.b", 1, 0x0210000f, 0x0def00f0, F(RR), 3, "ddd", "143", + { "sha.b", 1, 0x0210000f, 0x0def00f0, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"sha.b", 1, 0x0420008f, 0x0bc00070, F(RC), 3, "dd9", "132", + { "sha.b", 1, 0x0420008f, 0x0bc00070, F(RC), 3, "dd9", "132", TRICORE_RIDER_A, INDICES}, - {"sha.h", 1, 0x0410000f, 0x0bef00f0, F(RR), 3, "ddd", "143", + { "sha.h", 1, 0x0410000f, 0x0bef00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sha.h", 1, 0x0820008f, 0x07c00070, F(RC), 3, "dd9", "132", + { "sha.h", 1, 0x0820008f, 0x07c00070, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"shas", 1, 0x0020000f, 0x0fdf00f0, F(RR), 3, "ddd", "143", + { "shas", 1, 0x0020000f, 0x0fdf00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"shas", 1, 0x0040008f, 0x0fa00070, F(RC), 3, "dd9", "132", + { "shas", 1, 0x0040008f, 0x0fa00070, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"st.a", 0, 0x000000f8, 0xffff0007, F(SC), 3, "&kI", "010", + { "st.a", 0, 0x000000f8, 0xffff0007, F(SC), 3, "&kI", "010", TRICORE_RIDER_B_UP, INDICES}, - {"st.a", 0, 0x00000018, 0xffff00e7, F(SRO), 3, "@6I", "120", + { "st.a", 0, 0x00000018, 0xffff00e7, F(SRO), 3, "@6I", "120", TRICORE_RIDER_A, INDICES}, - {"st.a", 0, 0x000000ec, 0xffff0013, F(SRO), 3, "@6I", "120", + { "st.a", 0, 0x000000ec, 0xffff0013, F(SRO), 3, "@6I", "120", TRICORE_RIDER_B_UP, INDICES}, - {"st.a", 0, 0x0000002c, 0xffff00d3, F(SSRO), 3, "S6a", "012", + { "st.a", 0, 0x0000002c, 0xffff00d3, F(SSRO), 3, "S6a", "012", TRICORE_RIDER_A, INDICES}, - {"st.a", 0, 0x000000e8, 0xffff0017, F(SSRO), 3, "S6a", "012", + { "st.a", 0, 0x000000e8, 0xffff0017, F(SSRO), 3, "S6a", "012", TRICORE_RIDER_B_UP, INDICES}, - {"st.a", 0, 0x00000054, 0xffff00ab, F(SSR), 2, ">a", "12", + { "st.a", 0, 0x00000054, 0xffff00ab, F(SSR), 2, ">a", "12", TRICORE_RIDER_A, INDICES}, - {"st.a", 0, 0x000000e4, 0xffff001b, F(SSR), 2, ">a", "12", + { "st.a", 0, 0x000000e4, 0xffff001b, F(SSR), 2, ">a", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.a", 0, 0x00000084, 0xffff007b, F(SSR), 2, "@a", "12", + { "st.a", 0, 0x00000084, 0xffff007b, F(SSR), 2, "@a", "12", TRICORE_RIDER_A, INDICES}, - {"st.a", 0, 0x000000f4, 0xffff000b, F(SSR), 2, "@a", "12", + { "st.a", 0, 0x000000f4, 0xffff000b, F(SSR), 2, "@a", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.a", 1, 0x01800089, 0x0e400076, F(BO), 3, ">0a", "213", + { "st.a", 1, 0x01800089, 0x0e400076, F(BO), 3, ">0a", "213", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x018000a9, 0xfe7f0056, F(BO), 2, "#a", "23", + { "st.a", 1, 0x018000a9, 0xfe7f0056, F(BO), 2, "#a", "23", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x05800089, 0x0a400076, F(BO), 3, "<0a", "213", + { "st.a", 1, 0x05800089, 0x0a400076, F(BO), 3, "<0a", "213", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x058000a9, 0x0a400056, F(BO), 3, "*0a", "213", + { "st.a", 1, 0x058000a9, 0x0a400056, F(BO), 3, "*0a", "213", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x080000a5, 0x0400005a, F(ABS), 2, "ta", "12", + { "st.a", 1, 0x080000a5, 0x0400005a, F(ABS), 2, "ta", "12", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x09800089, 0x06400076, F(BO), 3, "@0a", "213", + { "st.a", 1, 0x09800089, 0x06400076, F(BO), 3, "@0a", "213", TRICORE_GENERIC, INDICES}, - {"st.a", 1, 0x098000a9, 0xf67f0056, F(BO), 2, "?a", "23", + { "st.a", 1, 0x098000a9, 0xf67f0056, F(BO), 2, "?a", "23", TRICORE_V2_UP, INDICES}, - {"st.b", 0, 0x00000078, 0xffff0087, F(SSR), 2, "@d", "12", + { "st.b", 0, 0x00000078, 0xffff0087, F(SSR), 2, "@d", "12", TRICORE_RIDER_A, INDICES}, - {"st.b", 0, 0x00000034, 0xffff00cb, F(SSR), 2, "@d", "12", + { "st.b", 0, 0x00000034, 0xffff00cb, F(SSR), 2, "@d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.b", 0, 0x0000008c, 0xffff0073, F(SSRO), 3, "Sfd", "012", + { "st.b", 0, 0x0000008c, 0xffff0073, F(SSRO), 3, "Sfd", "012", TRICORE_RIDER_A, INDICES}, - {"st.b", 0, 0x00000028, 0xffff00d7, F(SSRO), 3, "Sfd", "012", + { "st.b", 0, 0x00000028, 0xffff00d7, F(SSRO), 3, "Sfd", "012", TRICORE_RIDER_B_UP, INDICES}, - {"st.b", 0, 0x000000a8, 0xffff0057, F(SRO), 3, "@fi", "120", + { "st.b", 0, 0x000000a8, 0xffff0057, F(SRO), 3, "@fi", "120", TRICORE_RIDER_A, INDICES}, - {"st.b", 0, 0x0000002c, 0xffff00d3, F(SRO), 3, "@fi", "120", + { "st.b", 0, 0x0000002c, 0xffff00d3, F(SRO), 3, "@fi", "120", TRICORE_RIDER_B_UP, INDICES}, - {"st.b", 0, 0x000000e4, 0xffff001b, F(SSR), 2, ">d", "12", + { "st.b", 0, 0x000000e4, 0xffff001b, F(SSR), 2, ">d", "12", TRICORE_RIDER_A, INDICES}, - {"st.b", 0, 0x00000024, 0xffff00db, F(SSR), 2, ">d", "12", + { "st.b", 0, 0x00000024, 0xffff00db, F(SSR), 2, ">d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.b", 1, 0x00000025, 0x0c0000da, F(ABS), 2, "td", "12", + { "st.b", 1, 0x00000025, 0x0c0000da, F(ABS), 2, "td", "12", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x000000e9, 0x00000016, F(BOL), 3, "@wd", "213", + { "st.b", 1, 0x000000e9, 0x00000016, F(BOL), 3, "@wd", "213", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x00000089, 0x0fc00076, F(BO), 3, ">0d", "213", + { "st.b", 1, 0x00000089, 0x0fc00076, F(BO), 3, ">0d", "213", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x000000a9, 0xffff0056, F(BO), 2, "#d", "23", + { "st.b", 1, 0x000000a9, 0xffff0056, F(BO), 2, "#d", "23", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x04000089, 0x0bc00076, F(BO), 3, "<0d", "213", + { "st.b", 1, 0x04000089, 0x0bc00076, F(BO), 3, "<0d", "213", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x040000a9, 0x0bc00056, F(BO), 3, "*0d", "213", + { "st.b", 1, 0x040000a9, 0x0bc00056, F(BO), 3, "*0d", "213", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x08000089, 0x07c00076, F(BO), 3, "@0d", "213", + { "st.b", 1, 0x08000089, 0x07c00076, F(BO), 3, "@0d", "213", TRICORE_GENERIC, INDICES}, - {"st.b", 1, 0x080000a9, 0xf7ff0056, F(BO), 2, "?d", "23", + { "st.b", 1, 0x080000a9, 0xf7ff0056, F(BO), 2, "?d", "23", TRICORE_V2_UP, INDICES}, - {"st.d", 1, 0x01400089, 0x0e800076, F(BO), 3, ">0D", "213", + { "st.d", 1, 0x01400089, 0x0e800076, F(BO), 3, ">0D", "213", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x014000a9, 0xfebf0056, F(BO), 2, "#D", "23", + { "st.d", 1, 0x014000a9, 0xfebf0056, F(BO), 2, "#D", "23", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x040000a5, 0x0800005a, F(ABS), 2, "tD", "12", + { "st.d", 1, 0x040000a5, 0x0800005a, F(ABS), 2, "tD", "12", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x05400089, 0x0a800076, F(BO), 3, "<0D", "213", + { "st.d", 1, 0x05400089, 0x0a800076, F(BO), 3, "<0D", "213", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x054000a9, 0x0a800056, F(BO), 3, "*0D", "213", + { "st.d", 1, 0x054000a9, 0x0a800056, F(BO), 3, "*0D", "213", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x09400089, 0x06800076, F(BO), 3, "@0D", "213", + { "st.d", 1, 0x09400089, 0x06800076, F(BO), 3, "@0D", "213", TRICORE_GENERIC, INDICES}, - {"st.d", 1, 0x094000a9, 0xf6bf0056, F(BO), 2, "?D", "23", + { "st.d", 1, 0x094000a9, 0xf6bf0056, F(BO), 2, "?D", "23", TRICORE_V2_UP, INDICES}, - {"st.da", 1, 0x01c00089, 0x0e000076, F(BO), 3, ">0A", "213", + { "st.da", 1, 0x01c00089, 0x0e000076, F(BO), 3, ">0A", "213", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x01c000a9, 0xfe3f0056, F(BO), 2, "#A", "23", + { "st.da", 1, 0x01c000a9, 0xfe3f0056, F(BO), 2, "#A", "23", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x05c00089, 0x0a000076, F(BO), 3, "<0A", "213", + { "st.da", 1, 0x05c00089, 0x0a000076, F(BO), 3, "<0A", "213", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x05c000a9, 0x0a000056, F(BO), 3, "*0A", "213", + { "st.da", 1, 0x05c000a9, 0x0a000056, F(BO), 3, "*0A", "213", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x09c00089, 0x06000076, F(BO), 3, "@0A", "213", + { "st.da", 1, 0x09c00089, 0x06000076, F(BO), 3, "@0A", "213", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x0c0000a5, 0x0000005a, F(ABS), 2, "tA", "12", + { "st.da", 1, 0x0c0000a5, 0x0000005a, F(ABS), 2, "tA", "12", TRICORE_GENERIC, INDICES}, - {"st.da", 1, 0x09c000a9, 0xf63f0056, F(BO), 2, "?A", "23", + { "st.da", 1, 0x09c000a9, 0xf63f0056, F(BO), 2, "?A", "23", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x02400089, 0x0d800076, F(BO), 3, ">0D", "213", + { "st.dd", 1, 0x02400089, 0x0d800076, F(BO), 3, ">0D", "213", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x024000a9, 0xfdbf0056, F(BO), 2, "#D", "23", + { "st.dd", 1, 0x024000a9, 0xfdbf0056, F(BO), 2, "#D", "23", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x06400089, 0x09800076, F(BO), 3, "<0D", "213", + { "st.dd", 1, 0x06400089, 0x09800076, F(BO), 3, "<0D", "213", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x064000a9, 0x09800056, F(BO), 3, "*0D", "213", + { "st.dd", 1, 0x064000a9, 0x09800056, F(BO), 3, "*0D", "213", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x0a400089, 0x05800076, F(BO), 3, "@0D", "213", + { "st.dd", 1, 0x0a400089, 0x05800076, F(BO), 3, "@0D", "213", TRICORE_V2_UP, INDICES}, - {"st.dd", 1, 0x0a4000a9, 0xf5bf0056, F(BO), 2, "?D", "23", + { "st.dd", 1, 0x0a4000a9, 0xf5bf0056, F(BO), 2, "?D", "23", TRICORE_V2_UP, INDICES}, - {"st.h", 0, 0x00000014, 0xffff00eb, F(SSR), 2, ">d", "12", + { "st.h", 0, 0x00000014, 0xffff00eb, F(SSR), 2, ">d", "12", TRICORE_RIDER_A, INDICES}, - {"st.h", 0, 0x000000a4, 0xffff005b, F(SSR), 2, ">d", "12", + { "st.h", 0, 0x000000a4, 0xffff005b, F(SSR), 2, ">d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.h", 0, 0x0000004c, 0xffff00b3, F(SSRO), 3, "Svd", "012", + { "st.h", 0, 0x0000004c, 0xffff00b3, F(SSRO), 3, "Svd", "012", TRICORE_RIDER_A, INDICES}, - {"st.h", 0, 0x000000a8, 0xffff0057, F(SSRO), 3, "Svd", "012", + { "st.h", 0, 0x000000a8, 0xffff0057, F(SSRO), 3, "Svd", "012", TRICORE_RIDER_B_UP, INDICES}, - {"st.h", 0, 0x00000068, 0xffff0097, F(SRO), 3, "@vi", "120", + { "st.h", 0, 0x00000068, 0xffff0097, F(SRO), 3, "@vi", "120", TRICORE_RIDER_A, INDICES}, - {"st.h", 0, 0x000000ac, 0xffff0053, F(SRO), 3, "@vi", "120", + { "st.h", 0, 0x000000ac, 0xffff0053, F(SRO), 3, "@vi", "120", TRICORE_RIDER_B_UP, INDICES}, - {"st.h", 0, 0x000000f8, 0xffff0007, F(SSR), 2, "@d", "12", + { "st.h", 0, 0x000000f8, 0xffff0007, F(SSR), 2, "@d", "12", TRICORE_RIDER_A, INDICES}, - {"st.h", 0, 0x000000b4, 0xffff004b, F(SSR), 2, "@d", "12", + { "st.h", 0, 0x000000b4, 0xffff004b, F(SSR), 2, "@d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.h", 1, 0x00800089, 0x0f400076, F(BO), 3, ">0d", "213", + { "st.h", 1, 0x00800089, 0x0f400076, F(BO), 3, ">0d", "213", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x008000a9, 0xff7f0056, F(BO), 2, "#d", "23", + { "st.h", 1, 0x008000a9, 0xff7f0056, F(BO), 2, "#d", "23", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x04800089, 0x0b400076, F(BO), 3, "<0d", "213", + { "st.h", 1, 0x04800089, 0x0b400076, F(BO), 3, "<0d", "213", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x048000a9, 0x0b400056, F(BO), 3, "*0d", "213", + { "st.h", 1, 0x048000a9, 0x0b400056, F(BO), 3, "*0d", "213", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x08000025, 0x040000da, F(ABS), 2, "td", "12", + { "st.h", 1, 0x08000025, 0x040000da, F(ABS), 2, "td", "12", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x08800089, 0x07400076, F(BO), 3, "@0d", "213", + { "st.h", 1, 0x08800089, 0x07400076, F(BO), 3, "@0d", "213", TRICORE_GENERIC, INDICES}, - {"st.h", 1, 0x088000a9, 0xf77f0056, F(BO), 2, "?d", "23", + { "st.h", 1, 0x088000a9, 0xf77f0056, F(BO), 2, "?d", "23", TRICORE_V2_UP, INDICES}, - {"st.q", 1, 0x00000065, 0x0c00009a, F(ABS), 2, "td", "12", + { "st.q", 1, 0x00000065, 0x0c00009a, F(ABS), 2, "td", "12", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x02000089, 0x0dc00076, F(BO), 3, ">0d", "213", + { "st.q", 1, 0x02000089, 0x0dc00076, F(BO), 3, ">0d", "213", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x020000a9, 0xfdff0056, F(BO), 2, "#d", "23", + { "st.q", 1, 0x020000a9, 0xfdff0056, F(BO), 2, "#d", "23", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x06000089, 0x09c00076, F(BO), 3, "<0d", "213", + { "st.q", 1, 0x06000089, 0x09c00076, F(BO), 3, "<0d", "213", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x060000a9, 0x09c00056, F(BO), 3, "*0d", "213", + { "st.q", 1, 0x060000a9, 0x09c00056, F(BO), 3, "*0d", "213", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x0a000089, 0x05c00076, F(BO), 3, "@0d", "213", + { "st.q", 1, 0x0a000089, 0x05c00076, F(BO), 3, "@0d", "213", TRICORE_GENERIC, INDICES}, - {"st.q", 1, 0x0a0000a9, 0xf5ff0056, F(BO), 2, "?d", "23", + { "st.q", 1, 0x0a0000a9, 0xf5ff0056, F(BO), 2, "?d", "23", TRICORE_V2_UP, INDICES}, - {"st.t", 1, 0x000000d5, 0x0c00002a, F(ABSB), 3, "t31", "132", + { "st.t", 1, 0x000000d5, 0x0c00002a, F(ABSB), 3, "t31", "132", TRICORE_GENERIC, INDICES}, - {"st.w", 0, 0x00000078, 0xffff0087, F(SC), 3, "&ki", "010", + { "st.w", 0, 0x00000078, 0xffff0087, F(SC), 3, "&ki", "010", TRICORE_RIDER_B_UP, INDICES}, - {"st.w", 0, 0x00000004, 0xffff00fb, F(SSR), 2, "@d", "12", + { "st.w", 0, 0x00000004, 0xffff00fb, F(SSR), 2, "@d", "12", TRICORE_RIDER_A, INDICES}, - {"st.w", 0, 0x00000074, 0xffff008b, F(SSR), 2, "@d", "12", + { "st.w", 0, 0x00000074, 0xffff008b, F(SSR), 2, "@d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.w", 0, 0x00000094, 0xffff006b, F(SSR), 2, ">d", "12", + { "st.w", 0, 0x00000094, 0xffff006b, F(SSR), 2, ">d", "12", TRICORE_RIDER_A, INDICES}, - {"st.w", 0, 0x00000064, 0xffff009b, F(SSR), 2, ">d", "12", + { "st.w", 0, 0x00000064, 0xffff009b, F(SSR), 2, ">d", "12", TRICORE_RIDER_B_UP, INDICES}, - {"st.w", 0, 0x000000cc, 0xffff0033, F(SSRO), 3, "S6d", "012", + { "st.w", 0, 0x000000cc, 0xffff0033, F(SSRO), 3, "S6d", "012", TRICORE_RIDER_A, INDICES}, - {"st.w", 0, 0x00000068, 0xffff0097, F(SSRO), 3, "S6d", "012", + { "st.w", 0, 0x00000068, 0xffff0097, F(SSRO), 3, "S6d", "012", TRICORE_RIDER_B_UP, INDICES}, - {"st.w", 0, 0x000000e8, 0xffff0017, F(SRO), 3, "@6i", "120", + { "st.w", 0, 0x000000e8, 0xffff0017, F(SRO), 3, "@6i", "120", TRICORE_RIDER_A, INDICES}, - {"st.w", 0, 0x0000006c, 0xffff0093, F(SRO), 3, "@6i", "120", + { "st.w", 0, 0x0000006c, 0xffff0093, F(SRO), 3, "@6i", "120", TRICORE_RIDER_B_UP, INDICES}, - {"st.w", 1, 0x00000059, 0x000000a6, F(BOL), 3, "@wd", "213", + { "st.w", 1, 0x00000059, 0x000000a6, F(BOL), 3, "@wd", "213", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x000000a5, 0x0c00005a, F(ABS), 2, "td", "12", + { "st.w", 1, 0x000000a5, 0x0c00005a, F(ABS), 2, "td", "12", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x01000089, 0x0ec00076, F(BO), 3, ">0d", "213", + { "st.w", 1, 0x01000089, 0x0ec00076, F(BO), 3, ">0d", "213", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x010000a9, 0xfeff0056, F(BO), 2, "#d", "23", + { "st.w", 1, 0x010000a9, 0xfeff0056, F(BO), 2, "#d", "23", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x05000089, 0x0ac00076, F(BO), 3, "<0d", "213", + { "st.w", 1, 0x05000089, 0x0ac00076, F(BO), 3, "<0d", "213", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x050000a9, 0x0ac00056, F(BO), 3, "*0d", "213", + { "st.w", 1, 0x050000a9, 0x0ac00056, F(BO), 3, "*0d", "213", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x09000089, 0x06c00076, F(BO), 3, "@0d", "213", + { "st.w", 1, 0x09000089, 0x06c00076, F(BO), 3, "@0d", "213", TRICORE_GENERIC, INDICES}, - {"st.w", 1, 0x090000a9, 0xf6ff0056, F(BO), 2, "?d", "23", + { "st.w", 1, 0x090000a9, 0xf6ff0056, F(BO), 2, "?d", "23", TRICORE_V2_UP, INDICES}, - {"stlcx", 1, 0x00000015, 0x0c000fea, F(ABS), 1, "t", "1", + { "stlcx", 1, 0x00000015, 0x0c000fea, F(ABS), 1, "t", "1", TRICORE_GENERIC, INDICES}, - {"stlcx", 1, 0x09800049, 0x06400fb6, F(BO), 2, "@0", "21", + { "stlcx", 1, 0x09800049, 0x06400fb6, F(BO), 2, "@0", "21", TRICORE_GENERIC, INDICES}, - {"stucx", 1, 0x04000015, 0x08000fea, F(ABS), 1, "t", "1", + { "stucx", 1, 0x04000015, 0x08000fea, F(ABS), 1, "t", "1", TRICORE_GENERIC, INDICES}, - {"stucx", 1, 0x09c00049, 0x06000fb6, F(BO), 2, "@0", "21", + { "stucx", 1, 0x09c00049, 0x06000fb6, F(BO), 2, "@0", "21", TRICORE_GENERIC, INDICES}, - {"sub", 0, 0x00000052, 0xffff00ad, F(SRR), 3, "did", "201", + { "sub", 0, 0x00000052, 0xffff00ad, F(SRR), 3, "did", "201", TRICORE_RIDER_B_UP, INDICES}, - {"sub", 0, 0x0000005a, 0xffff00a5, F(SRR), 3, "idd", "021", + { "sub", 0, 0x0000005a, 0xffff00a5, F(SRR), 3, "idd", "021", TRICORE_GENERIC, INDICES}, - {"sub", 0, 0x000000a2, 0xffff005d, F(SRR), 2, "dd", "21", + { "sub", 0, 0x000000a2, 0xffff005d, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"sub", 1, 0x0080000b, 0x0f7f00f4, F(RR), 3, "ddd", "143", + { "sub", 1, 0x0080000b, 0x0f7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sub.a", 0, 0x00000040, 0xffff00bf, F(SC), 2, "P8", "01", + { "sub.a", 0, 0x00000040, 0xffff00bf, F(SC), 2, "P8", "01", TRICORE_RIDER_A, INDICES}, - {"sub.a", 0, 0x00000020, 0xffff00df, F(SC), 2, "P8", "01", + { "sub.a", 0, 0x00000020, 0xffff00df, F(SC), 2, "P8", "01", TRICORE_RIDER_B_UP, INDICES}, - {"sub.a", 1, 0x00200001, 0x0fdf00fe, F(RR), 3, "aaa", "143", + { "sub.a", 1, 0x00200001, 0x0fdf00fe, F(RR), 3, "aaa", "143", TRICORE_GENERIC, INDICES}, - {"sub.b", 1, 0x0480000b, 0x0b7f00f4, F(RR), 3, "ddd", "143", + { "sub.b", 1, 0x0480000b, 0x0b7f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"sub.f", 1, 0x0031006b, 0x00cef094, F(RRR), 3, "ddd", "125", + { "sub.f", 1, 0x0031006b, 0x00cef094, F(RRR), 3, "ddd", "125", TRICORE_RIDER_D_UP, INDICES}, - {"sub.h", 1, 0x0680000b, 0x097f00f4, F(RR), 3, "ddd", "143", + { "sub.h", 1, 0x0680000b, 0x097f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subc", 1, 0x00d0000b, 0x0f2f00f4, F(RR), 3, "ddd", "143", + { "subc", 1, 0x00d0000b, 0x0f2f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subs", 0, 0x00000062, 0xffff009d, F(SRR), 2, "dd", "21", + { "subs", 0, 0x00000062, 0xffff009d, F(SRR), 2, "dd", "21", TRICORE_GENERIC, INDICES}, - {"subs", 1, 0x00a0000b, 0x0f5f00f4, F(RR), 3, "ddd", "143", + { "subs", 1, 0x00a0000b, 0x0f5f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subs.b", 1, 0x04a0000b, 0x0b5f00f4, F(RR), 3, "ddd", "143", + { "subs.b", 1, 0x04a0000b, 0x0b5f00f4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"subs.bu", 1, 0x04b0000b, 0x0b4f00f4, F(RR), 3, "ddd", "143", + { "subs.bu", 1, 0x04b0000b, 0x0b4f00f4, F(RR), 3, "ddd", "143", TRICORE_RIDER_A, INDICES}, - {"subs.h", 1, 0x06a0000b, 0x095f00f4, F(RR), 3, "ddd", "143", + { "subs.h", 1, 0x06a0000b, 0x095f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subs.hu", 1, 0x06b0000b, 0x094f00f4, F(RR), 3, "ddd", "143", + { "subs.hu", 1, 0x06b0000b, 0x094f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subs.u", 1, 0x00b0000b, 0x0f4f00f4, F(RR), 3, "ddd", "143", + { "subs.u", 1, 0x00b0000b, 0x0f4f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"subsc.a", 1, 0x06100001, 0x09ec00fe, F(RR), 4, "aad2", "1432", + { "subsc.a", 1, 0x06100001, 0x09ec00fe, F(RR), 4, "aad2", "1432", TRICORE_RIDER_A, INDICES}, - {"subx", 1, 0x00c0000b, 0x0f3f00f4, F(RR), 3, "ddd", "143", + { "subx", 1, 0x00c0000b, 0x0f3f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"svlcx", 1, 0x0200000d, 0xfdfffff2, F(SYS), 0, "", "", + { "svlcx", 1, 0x0200000d, 0xfdfffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"swap.a", 1, 0x00800049, 0x0f4000b6, F(BO), 3, ">0a", "213", + { "swap.a", 1, 0x00800049, 0x0f4000b6, F(BO), 3, ">0a", "213", TRICORE_RIDER_A, INDICES}, - {"swap.a", 1, 0x00800069, 0xff7f0096, F(BO), 2, "#a", "23", + { "swap.a", 1, 0x00800069, 0xff7f0096, F(BO), 2, "#a", "23", TRICORE_RIDER_A, INDICES}, - {"swap.a", 1, 0x04800049, 0x0b4000b6, F(BO), 3, "<0a", "213", + { "swap.a", 1, 0x04800049, 0x0b4000b6, F(BO), 3, "<0a", "213", TRICORE_RIDER_A, INDICES}, - {"swap.a", 1, 0x04800069, 0x0b400096, F(BO), 3, "*0a", "213", + { "swap.a", 1, 0x04800069, 0x0b400096, F(BO), 3, "*0a", "213", TRICORE_RIDER_A, INDICES}, - {"swap.a", 1, 0x080000e5, 0x0400001a, F(ABS), 2, "ta", "12", + { "swap.a", 1, 0x080000e5, 0x0400001a, F(ABS), 2, "ta", "12", TRICORE_RIDER_A, INDICES}, - {"swap.a", 1, 0x08800049, 0x074000b6, F(BO), 3, "@0a", "213", + { "swap.a", 1, 0x08800049, 0x074000b6, F(BO), 3, "@0a", "213", TRICORE_RIDER_A, INDICES}, - {"swap.w", 1, 0x00000049, 0x0fc000b6, F(BO), 3, ">0d", "213", + { "swap.w", 1, 0x00000049, 0x0fc000b6, F(BO), 3, ">0d", "213", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x00000069, 0xffff0096, F(BO), 2, "#d", "23", + { "swap.w", 1, 0x00000069, 0xffff0096, F(BO), 2, "#d", "23", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x000000e5, 0x0c00001a, F(ABS), 2, "td", "12", + { "swap.w", 1, 0x000000e5, 0x0c00001a, F(ABS), 2, "td", "12", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x04000049, 0x0bc000b6, F(BO), 3, "<0d", "213", + { "swap.w", 1, 0x04000049, 0x0bc000b6, F(BO), 3, "<0d", "213", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x04000069, 0x0bc00096, F(BO), 3, "*0d", "213", + { "swap.w", 1, 0x04000069, 0x0bc00096, F(BO), 3, "*0d", "213", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x08000049, 0x07c000b6, F(BO), 3, "@0d", "213", + { "swap.w", 1, 0x08000049, 0x07c000b6, F(BO), 3, "@0d", "213", TRICORE_GENERIC, INDICES}, - {"swap.w", 1, 0x08000069, 0xf7ff0096, F(BO), 2, "?d", "23", + { "swap.w", 1, 0x08000069, 0xf7ff0096, F(BO), 2, "?d", "23", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x00800049, 0x0f4000b6, F(BO), 3, ">0D", "213", + { "swapmsk", 1, 0x00800049, 0x0f4000b6, F(BO), 3, ">0D", "213", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x00800069, 0xff7f0096, F(BO), 2, "#D", "23", + { "swapmsk", 1, 0x00800069, 0xff7f0096, F(BO), 2, "#D", "23", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x04800049, 0x0b4000b6, F(BO), 3, "<0D", "213", + { "swapmsk", 1, 0x04800049, 0x0b4000b6, F(BO), 3, "<0D", "213", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x04800069, 0x0b400096, F(BO), 3, "*0D", "213", + { "swapmsk", 1, 0x04800069, 0x0b400096, F(BO), 3, "*0D", "213", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x08800049, 0x074000b6, F(BO), 3, "@0D", "213", + { "swapmsk", 1, 0x08800049, 0x074000b6, F(BO), 3, "@0D", "213", TRICORE_V2_UP, INDICES}, - {"swapmsk", 1, 0x08800069, 0xf77f0096, F(BO), 2, "?D", "23", + { "swapmsk", 1, 0x08800069, 0xf77f0096, F(BO), 2, "?D", "23", TRICORE_V2_UP, INDICES}, - {"syscall", 1, 0x008000ad, 0xff600f52, F(RC), 1, "n", "2", + { "syscall", 1, 0x008000ad, 0xff600f52, F(RC), 1, "n", "2", TRICORE_GENERIC, INDICES}, - {"tlbdemap", 1, 0x00000075, 0xfffff08a, F(RR), 1, "d", "4", + { "tlbdemap", 1, 0x00000075, 0xfffff08a, F(RR), 1, "d", "4", TRICORE_RIDER_D_UP, INDICES}, - {"tlbflush.a", 1, 0x00400075, 0xffbfff8a, F(RR), 0, "", "", + { "tlbflush.a", 1, 0x00400075, 0xffbfff8a, F(RR), 0, "", "", TRICORE_RIDER_D_UP, INDICES}, - {"tlbflush.b", 1, 0x00500075, 0xffafff8a, F(RR), 0, "", "", + { "tlbflush.b", 1, 0x00500075, 0xffafff8a, F(RR), 0, "", "", TRICORE_RIDER_D_UP, INDICES}, - {"tlbmap", 1, 0x04000075, 0xfbfff08a, F(RR), 1, "D", "4", + { "tlbmap", 1, 0x04000075, 0xfbfff08a, F(RR), 1, "D", "4", TRICORE_RIDER_D_UP, INDICES}, - {"tlbprobe.a", 1, 0x00800075, 0xff7ff08a, F(RR), 1, "d", "4", + { "tlbprobe.a", 1, 0x00800075, 0xff7ff08a, F(RR), 1, "d", "4", TRICORE_RIDER_D_UP, INDICES}, - {"tlbprobe.i", 1, 0x00900075, 0xff6ff08a, F(RR), 1, "d", "4", + { "tlbprobe.i", 1, 0x00900075, 0xff6ff08a, F(RR), 1, "d", "4", TRICORE_RIDER_D_UP, INDICES}, - {"trapsv", 1, 0x0540000d, 0xfabffff2, F(SYS), 0, "", "", + { "trapsv", 1, 0x0540000d, 0xfabffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"trapv", 1, 0x0500000d, 0xfafffff2, F(SYS), 0, "", "", + { "trapv", 1, 0x0500000d, 0xfafffff2, F(SYS), 0, "", "", TRICORE_GENERIC, INDICES}, - {"unpack", 1, 0x0500004b, 0x0afff0b4, F(RR), 2, "Dd", "14", + { "unpack", 1, 0x0500004b, 0x0afff0b4, F(RR), 2, "Dd", "14", TRICORE_RIDER_A, INDICES}, - {"unpack", 1, 0x0080004b, 0x0f7ff0b4, F(RR), 2, "Dd", "14", + { "unpack", 1, 0x0080004b, 0x0f7ff0b4, F(RR), 2, "Dd", "14", TRICORE_RIDER_B_UP, INDICES}, - {"updfl", 1, 0x00c1004b, 0xff3ef0b4, F(RR), 1, "d", "4", + { "updfl", 1, 0x00c1004b, 0xff3ef0b4, F(RR), 1, "d", "4", TRICORE_RIDER_D_UP, INDICES}, - {"utof", 1, 0x0161004b, 0x0e9ef0b4, F(RR), 2, "dd", "14", + { "utof", 1, 0x0161004b, 0x0e9ef0b4, F(RR), 2, "dd", "14", TRICORE_RIDER_D_UP, INDICES}, - {"xnor", 1, 0x00d0000f, 0x0f2f00f0, F(RR), 3, "ddd", "143", + { "xnor", 1, 0x00d0000f, 0x0f2f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xnor", 1, 0x01a0008f, 0x0e400070, F(RC), 3, "ddn", "132", + { "xnor", 1, 0x01a0008f, 0x0e400070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"xnor.t", 1, 0x00400007, 0x002000f8, F(BIT), 5, "dd5d5", "15342", + { "xnor.t", 1, 0x00400007, 0x002000f8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"xor", 0, 0x000000c6, 0xffff0039, F(SRR), 2, "dd", "21", + { "xor", 0, 0x000000c6, 0xffff0039, F(SRR), 2, "dd", "21", TRICORE_RIDER_B_UP, INDICES}, - {"xor", 1, 0x00c0000f, 0x0f3f00f0, F(RR), 3, "ddd", "143", + { "xor", 1, 0x00c0000f, 0x0f3f00f0, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor", 1, 0x0180008f, 0x0e600070, F(RC), 3, "ddn", "132", + { "xor", 1, 0x0180008f, 0x0e600070, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"xor.eq", 1, 0x02f0000b, 0x0d0f00f4, F(RR), 3, "ddd", "143", + { "xor.eq", 1, 0x02f0000b, 0x0d0f00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.eq", 1, 0x05e0008b, 0x0a000074, F(RC), 3, "dd9", "132", + { "xor.eq", 1, 0x05e0008b, 0x0a000074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"xor.ge", 1, 0x0330000b, 0x0ccf00f4, F(RR), 3, "ddd", "143", + { "xor.ge", 1, 0x0330000b, 0x0ccf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.ge", 1, 0x0660008b, 0x09800074, F(RC), 3, "dd9", "132", + { "xor.ge", 1, 0x0660008b, 0x09800074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"xor.ge.u", 1, 0x0340000b, 0x0cbf00f4, F(RR), 3, "ddd", "143", + { "xor.ge.u", 1, 0x0340000b, 0x0cbf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.ge.u", 1, 0x0680008b, 0x09600074, F(RC), 3, "ddn", "132", + { "xor.ge.u", 1, 0x0680008b, 0x09600074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"xor.lt", 1, 0x0310000b, 0x0cef00f4, F(RR), 3, "ddd", "143", + { "xor.lt", 1, 0x0310000b, 0x0cef00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.lt", 1, 0x0620008b, 0x09c00074, F(RC), 3, "dd9", "132", + { "xor.lt", 1, 0x0620008b, 0x09c00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"xor.lt.u", 1, 0x0320000b, 0x0cdf00f4, F(RR), 3, "ddd", "143", + { "xor.lt.u", 1, 0x0320000b, 0x0cdf00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.lt.u", 1, 0x0640008b, 0x09a00074, F(RC), 3, "ddn", "132", + { "xor.lt.u", 1, 0x0640008b, 0x09a00074, F(RC), 3, "ddn", "132", TRICORE_GENERIC, INDICES}, - {"xor.ne", 1, 0x0300000b, 0x0cff00f4, F(RR), 3, "ddd", "143", + { "xor.ne", 1, 0x0300000b, 0x0cff00f4, F(RR), 3, "ddd", "143", TRICORE_GENERIC, INDICES}, - {"xor.ne", 1, 0x0600008b, 0x09e00074, F(RC), 3, "dd9", "132", + { "xor.ne", 1, 0x0600008b, 0x09e00074, F(RC), 3, "dd9", "132", TRICORE_GENERIC, INDICES}, - {"xor.t", 1, 0x00600007, 0x000000f8, F(BIT), 5, "dd5d5", "15342", + { "xor.t", 1, 0x00600007, 0x000000f8, F(BIT), 5, "dd5d5", "15342", TRICORE_GENERIC, INDICES}, - {"xpose.b", 1, 0x0830000b, 0x07cf00f4, F(RR), 3, "Ddd", "143", + { "xpose.b", 1, 0x0830000b, 0x07cf00f4, F(RR), 3, "Ddd", "143", TRICORE_V2_UP, INDICES}, - {"xpose.h", 1, 0x0820000b, 0x07df00f4, F(RR), 3, "Ddd", "143", + { "xpose.h", 1, 0x0820000b, 0x07df00f4, F(RR), 3, "Ddd", "143", TRICORE_V2_UP, INDICES} #undef INDICES }; @@ -2386,128 +2386,128 @@ const int tricore_numopcodes = struct pcp_opcode pcp_opcodes[] = { #define INDICES TRICORE_PCP, 0, 0 - {"add", 0, 0x6000, 0x9e00, 3, 0, 3, "arr", INDICES}, - {"add", 0, 0x6000, 0x9e00, 3, 0, 3, "rra", INDICES}, - {"add.f", 0, 0x2000, 0xde04, 1, 0, 3, "rRf", INDICES}, - {"add.f", 0, 0x2000, 0xde04, 1, 0, 3, "rrf", INDICES}, - {"add.i", 0, 0x8000, 0x7e00, 4, 0, 2, "re", INDICES}, - {"add.pi", 0, 0x4000, 0xbe00, 2, 0, 2, "rE", INDICES}, - {"add.pi", 0, 0x4000, 0xbe00, 2, 0, 2, "re", INDICES}, - {"and", 0, 0x6a00, 0x9400, 3, 0, 3, "arr", INDICES}, - {"and", 0, 0x6a00, 0x9400, 3, 0, 3, "rra", INDICES}, - {"and.f", 0, 0x2a00, 0xd404, 1, 0, 3, "rRf", INDICES}, - {"and.f", 0, 0x2a00, 0xd404, 1, 0, 3, "rrf", INDICES}, - {"and.pi", 0, 0x4a00, 0xb400, 2, 0, 2, "rE", INDICES}, - {"and.pi", 0, 0x4a00, 0xb400, 2, 0, 2, "re", INDICES}, - {"bcopy", 0, 0x1800, 0xe013, 0, 1, 4, "dscn", INDICES}, - {"chkb", 0, 0x9c00, 0x6200, 4, 0, 3, "rel", INDICES}, - {"chkb", 0, 0x9c20, 0x6220, 4, 0, 3, "rek", INDICES}, - {"clr", 0, 0x9600, 0x6820, 4, 0, 2, "re", INDICES}, - {"clr.f", 0, 0xb000, 0x4c00, 5, 0, 3, "Ref", INDICES}, - {"clr.f", 0, 0xb000, 0x4c00, 5, 0, 3, "ref", INDICES}, - {"comp", 0, 0x6400, 0x9a00, 3, 0, 3, "arr", INDICES}, - {"comp", 0, 0x6400, 0x9a00, 3, 0, 3, "rra", INDICES}, - {"comp.f", 0, 0x2400, 0xda04, 1, 0, 3, "rRf", INDICES}, - {"comp.f", 0, 0x2400, 0xda04, 1, 0, 3, "rrf", INDICES}, - {"comp.i", 0, 0x8400, 0x7a00, 4, 0, 2, "re", INDICES}, - {"comp.pi", 0, 0x4400, 0xba00, 2, 0, 2, "rE", INDICES}, - {"comp.pi", 0, 0x4400, 0xba00, 2, 0, 2, "re", INDICES}, - {"copy", 0, 0x0800, 0xf000, 0, 1, 5, "dscnf", INDICES}, - {"debug", 0, 0xfc00, 0x0030, 7, 1, 5, "bmopq", INDICES}, - {"debug", 0, 0xfc00, 0x0030, 7, 1, 5, "amopq", INDICES}, - {"dinit", 0, 0xc000, 0x3e07, 6, 0, 2, "rr", INDICES}, - {"dstep", 0, 0xc200, 0x3c07, 6, 0, 2, "rr", INDICES}, - {"exb", 0, 0x9c20, 0x6200, 4, 0, 2, "re", INDICES}, - {"exib", 0, 0x9c00, 0x6220, 4, 0, 2, "re", INDICES}, - {"exit", 0, 0x1000, 0xe870, 0, 1, 5, "ghijb", INDICES}, - {"exit", 0, 0x1000, 0xe870, 0, 1, 5, "ghija", INDICES}, - {"inb", 0, 0x7a00, 0x8400, 3, 0, 3, "arr", INDICES}, - {"inb", 0, 0x7a00, 0x8400, 3, 0, 3, "rra", INDICES}, - {"inb.i", 0, 0x9a00, 0x6420, 4, 0, 2, "re", INDICES}, - {"jc", 0, 0xe400, 0x1800, 7, 1, 2, "be", INDICES}, - {"jc", 0, 0xe400, 0x1800, 7, 1, 2, "ae", INDICES}, - {"jc.a", 1, 0xe800, 0x143f, 7, 1, 2, "be", INDICES}, - {"jc.a", 1, 0xe800, 0x143f, 7, 1, 2, "ae", INDICES}, - {"jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "bR", INDICES}, - {"jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "br", INDICES}, - {"jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "aR", INDICES}, - {"jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "ar", INDICES}, - {"jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "bR", INDICES}, - {"jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "br", INDICES}, - {"jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "aR", INDICES}, - {"jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "ar", INDICES}, - {"jl", 0, 0xe000, 0x1c00, 7, 0, 1, "e", INDICES}, - {"ld.f", 0, 0x3200, 0xcc04, 1, 0, 3, "rRf", INDICES}, - {"ld.f", 0, 0x3200, 0xcc04, 1, 0, 3, "rrf", INDICES}, - {"ld.i", 0, 0x9800, 0x6600, 4, 0, 2, "re", INDICES}, - {"ld.if", 0, 0xb400, 0x4800, 5, 0, 3, "Ref", INDICES}, - {"ld.if", 0, 0xb400, 0x4800, 5, 0, 3, "ref", INDICES}, - {"ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "arR", INDICES}, - {"ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "arr", INDICES}, - {"ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "rRa", INDICES}, - {"ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "rra", INDICES}, - {"ld.pi", 0, 0x5200, 0xac00, 2, 0, 2, "rE", INDICES}, - {"ld.pi", 0, 0x5200, 0xac00, 2, 0, 2, "re", INDICES}, - {"ldl.il", 1, 0x9200, 0x6c3f, 4, 0, 2, "re", INDICES}, - {"ldl.iu", 1, 0x9000, 0x6e3f, 4, 0, 2, "re", INDICES}, - {"mclr.pi", 0, 0x4800, 0xb600, 2, 0, 2, "rE", INDICES}, - {"mclr.pi", 0, 0x4800, 0xb600, 2, 0, 2, "re", INDICES}, - {"minit", 0, 0xc400, 0x3a07, 6, 0, 2, "rr", INDICES}, - {"mov", 0, 0x7800, 0x8600, 3, 0, 3, "arr", INDICES}, - {"mov", 0, 0x7800, 0x8600, 3, 0, 3, "rra", INDICES}, - {"mset.pi", 0, 0x4c00, 0xb200, 2, 0, 2, "rE", INDICES}, - {"mset.pi", 0, 0x4c00, 0xb200, 2, 0, 2, "re", INDICES}, - {"mstep.l", 0, 0xc600, 0x3807, 6, 0, 2, "rr", INDICES}, - {"mstep.u", 0, 0xc800, 0x3607, 6, 0, 2, "rr", INDICES}, - {"mstep32", 0, 0xc600, 0x3807, 6, 0, 2, "rr", INDICES}, - {"mstep64", 0, 0xc800, 0x3607, 6, 0, 2, "rr", INDICES}, - {"neg", 0, 0x6600, 0x9800, 3, 0, 3, "arr", INDICES}, - {"neg", 0, 0x6600, 0x9800, 3, 0, 3, "rra", INDICES}, - {"nop", 0, 0x0000, 0xffff, 0, 0, 0, "", INDICES}, - {"not", 0, 0x6800, 0x9600, 3, 0, 3, "arr", INDICES}, - {"not", 0, 0x6800, 0x9600, 3, 0, 3, "rra", INDICES}, - {"or", 0, 0x6e00, 0x9000, 3, 0, 3, "arr", INDICES}, - {"or", 0, 0x6e00, 0x9000, 3, 0, 3, "rra", INDICES}, - {"or.f", 0, 0x2e00, 0xd004, 1, 0, 3, "rRf", INDICES}, - {"or.f", 0, 0x2e00, 0xd004, 1, 0, 3, "rrf", INDICES}, - {"or.pi", 0, 0x4e00, 0xb000, 2, 0, 2, "rE", INDICES}, - {"or.pi", 0, 0x4e00, 0xb000, 2, 0, 2, "re", INDICES}, - {"pri", 0, 0x7c00, 0x8200, 3, 0, 3, "arr", INDICES}, - {"pri", 0, 0x7c00, 0x8200, 3, 0, 3, "rra", INDICES}, - {"rl", 0, 0x8e00, 0x7020, 4, 0, 2, "re", INDICES}, - {"rr", 0, 0x8c00, 0x7220, 4, 0, 2, "re", INDICES}, - {"set", 0, 0x9400, 0x6a20, 4, 0, 2, "re", INDICES}, - {"set.f", 0, 0xac00, 0x5000, 5, 0, 3, "Ref", INDICES}, - {"set.f", 0, 0xac00, 0x5000, 5, 0, 3, "ref", INDICES}, - {"shl", 0, 0x8a00, 0x7420, 4, 0, 2, "re", INDICES}, - {"shr", 0, 0x8800, 0x7620, 4, 0, 2, "re", INDICES}, - {"st.f", 0, 0x3400, 0xca04, 1, 0, 3, "rRf", INDICES}, - {"st.f", 0, 0x3400, 0xca04, 1, 0, 3, "rrf", INDICES}, - {"st.if", 0, 0xb800, 0x4400, 5, 0, 3, "Ref", INDICES}, - {"st.if", 0, 0xb800, 0x4400, 5, 0, 3, "ref", INDICES}, - {"st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "arR", INDICES}, - {"st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "arr", INDICES}, - {"st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "rRa", INDICES}, - {"st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "rra", INDICES}, - {"st.pi", 0, 0x5400, 0xaa00, 2, 0, 2, "rE", INDICES}, - {"st.pi", 0, 0x5400, 0xaa00, 2, 0, 2, "re", INDICES}, - {"sub", 0, 0x6200, 0x9c00, 3, 0, 3, "arr", INDICES}, - {"sub", 0, 0x6200, 0x9c00, 3, 0, 3, "rra", INDICES}, - {"sub.f", 0, 0x2200, 0xdc04, 1, 0, 3, "rRf", INDICES}, - {"sub.f", 0, 0x2200, 0xdc04, 1, 0, 3, "rrf", INDICES}, - {"sub.i", 0, 0x8200, 0x7c00, 4, 0, 2, "re", INDICES}, - {"sub.pi", 0, 0x4200, 0xbc00, 2, 0, 2, "rE", INDICES}, - {"sub.pi", 0, 0x4200, 0xbc00, 2, 0, 2, "re", INDICES}, - {"xch.f", 0, 0x3600, 0xc804, 1, 0, 3, "rRf", INDICES}, - {"xch.f", 0, 0x3600, 0xc804, 1, 0, 3, "rrf", INDICES}, - {"xch.pi", 0, 0x5600, 0xa800, 2, 0, 2, "rE", INDICES}, - {"xch.pi", 0, 0x5600, 0xa800, 2, 0, 2, "re", INDICES}, - {"xor", 0, 0x7000, 0x8e00, 3, 0, 3, "arr", INDICES}, - {"xor", 0, 0x7000, 0x8e00, 3, 0, 3, "rra", INDICES}, - {"xor.f", 0, 0x3000, 0xce04, 1, 0, 3, "rRf", INDICES}, - {"xor.f", 0, 0x3000, 0xce04, 1, 0, 3, "rrf", INDICES}, - {"xor.pi", 0, 0x5000, 0xae00, 2, 0, 2, "rE", INDICES}, - {"xor.pi", 0, 0x5000, 0xae00, 2, 0, 2, "re", INDICES} + { "add", 0, 0x6000, 0x9e00, 3, 0, 3, "arr", INDICES}, + { "add", 0, 0x6000, 0x9e00, 3, 0, 3, "rra", INDICES}, + { "add.f", 0, 0x2000, 0xde04, 1, 0, 3, "rRf", INDICES}, + { "add.f", 0, 0x2000, 0xde04, 1, 0, 3, "rrf", INDICES}, + { "add.i", 0, 0x8000, 0x7e00, 4, 0, 2, "re", INDICES}, + { "add.pi", 0, 0x4000, 0xbe00, 2, 0, 2, "rE", INDICES}, + { "add.pi", 0, 0x4000, 0xbe00, 2, 0, 2, "re", INDICES}, + { "and", 0, 0x6a00, 0x9400, 3, 0, 3, "arr", INDICES}, + { "and", 0, 0x6a00, 0x9400, 3, 0, 3, "rra", INDICES}, + { "and.f", 0, 0x2a00, 0xd404, 1, 0, 3, "rRf", INDICES}, + { "and.f", 0, 0x2a00, 0xd404, 1, 0, 3, "rrf", INDICES}, + { "and.pi", 0, 0x4a00, 0xb400, 2, 0, 2, "rE", INDICES}, + { "and.pi", 0, 0x4a00, 0xb400, 2, 0, 2, "re", INDICES}, + { "bcopy", 0, 0x1800, 0xe013, 0, 1, 4, "dscn", INDICES}, + { "chkb", 0, 0x9c00, 0x6200, 4, 0, 3, "rel", INDICES}, + { "chkb", 0, 0x9c20, 0x6220, 4, 0, 3, "rek", INDICES}, + { "clr", 0, 0x9600, 0x6820, 4, 0, 2, "re", INDICES}, + { "clr.f", 0, 0xb000, 0x4c00, 5, 0, 3, "Ref", INDICES}, + { "clr.f", 0, 0xb000, 0x4c00, 5, 0, 3, "ref", INDICES}, + { "comp", 0, 0x6400, 0x9a00, 3, 0, 3, "arr", INDICES}, + { "comp", 0, 0x6400, 0x9a00, 3, 0, 3, "rra", INDICES}, + { "comp.f", 0, 0x2400, 0xda04, 1, 0, 3, "rRf", INDICES}, + { "comp.f", 0, 0x2400, 0xda04, 1, 0, 3, "rrf", INDICES}, + { "comp.i", 0, 0x8400, 0x7a00, 4, 0, 2, "re", INDICES}, + { "comp.pi", 0, 0x4400, 0xba00, 2, 0, 2, "rE", INDICES}, + { "comp.pi", 0, 0x4400, 0xba00, 2, 0, 2, "re", INDICES}, + { "copy", 0, 0x0800, 0xf000, 0, 1, 5, "dscnf", INDICES}, + { "debug", 0, 0xfc00, 0x0030, 7, 1, 5, "bmopq", INDICES}, + { "debug", 0, 0xfc00, 0x0030, 7, 1, 5, "amopq", INDICES}, + { "dinit", 0, 0xc000, 0x3e07, 6, 0, 2, "rr", INDICES}, + { "dstep", 0, 0xc200, 0x3c07, 6, 0, 2, "rr", INDICES}, + { "exb", 0, 0x9c20, 0x6200, 4, 0, 2, "re", INDICES}, + { "exib", 0, 0x9c00, 0x6220, 4, 0, 2, "re", INDICES}, + { "exit", 0, 0x1000, 0xe870, 0, 1, 5, "ghijb", INDICES}, + { "exit", 0, 0x1000, 0xe870, 0, 1, 5, "ghija", INDICES}, + { "inb", 0, 0x7a00, 0x8400, 3, 0, 3, "arr", INDICES}, + { "inb", 0, 0x7a00, 0x8400, 3, 0, 3, "rra", INDICES}, + { "inb.i", 0, 0x9a00, 0x6420, 4, 0, 2, "re", INDICES}, + { "jc", 0, 0xe400, 0x1800, 7, 1, 2, "be", INDICES}, + { "jc", 0, 0xe400, 0x1800, 7, 1, 2, "ae", INDICES}, + { "jc.a", 1, 0xe800, 0x143f, 7, 1, 2, "be", INDICES}, + { "jc.a", 1, 0xe800, 0x143f, 7, 1, 2, "ae", INDICES}, + { "jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "bR", INDICES}, + { "jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "br", INDICES}, + { "jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "aR", INDICES}, + { "jc.i", 0, 0xf000, 0x0c07, 7, 1, 2, "ar", INDICES}, + { "jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "bR", INDICES}, + { "jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "br", INDICES}, + { "jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "aR", INDICES}, + { "jc.ia", 0, 0xf400, 0x0807, 7, 1, 2, "ar", INDICES}, + { "jl", 0, 0xe000, 0x1c00, 7, 0, 1, "e", INDICES}, + { "ld.f", 0, 0x3200, 0xcc04, 1, 0, 3, "rRf", INDICES}, + { "ld.f", 0, 0x3200, 0xcc04, 1, 0, 3, "rrf", INDICES}, + { "ld.i", 0, 0x9800, 0x6600, 4, 0, 2, "re", INDICES}, + { "ld.if", 0, 0xb400, 0x4800, 5, 0, 3, "Ref", INDICES}, + { "ld.if", 0, 0xb400, 0x4800, 5, 0, 3, "ref", INDICES}, + { "ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "arR", INDICES}, + { "ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "arr", INDICES}, + { "ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "rRa", INDICES}, + { "ld.p", 0, 0x7200, 0x8c00, 3, 0, 3, "rra", INDICES}, + { "ld.pi", 0, 0x5200, 0xac00, 2, 0, 2, "rE", INDICES}, + { "ld.pi", 0, 0x5200, 0xac00, 2, 0, 2, "re", INDICES}, + { "ldl.il", 1, 0x9200, 0x6c3f, 4, 0, 2, "re", INDICES}, + { "ldl.iu", 1, 0x9000, 0x6e3f, 4, 0, 2, "re", INDICES}, + { "mclr.pi", 0, 0x4800, 0xb600, 2, 0, 2, "rE", INDICES}, + { "mclr.pi", 0, 0x4800, 0xb600, 2, 0, 2, "re", INDICES}, + { "minit", 0, 0xc400, 0x3a07, 6, 0, 2, "rr", INDICES}, + { "mov", 0, 0x7800, 0x8600, 3, 0, 3, "arr", INDICES}, + { "mov", 0, 0x7800, 0x8600, 3, 0, 3, "rra", INDICES}, + { "mset.pi", 0, 0x4c00, 0xb200, 2, 0, 2, "rE", INDICES}, + { "mset.pi", 0, 0x4c00, 0xb200, 2, 0, 2, "re", INDICES}, + { "mstep.l", 0, 0xc600, 0x3807, 6, 0, 2, "rr", INDICES}, + { "mstep.u", 0, 0xc800, 0x3607, 6, 0, 2, "rr", INDICES}, + { "mstep32", 0, 0xc600, 0x3807, 6, 0, 2, "rr", INDICES}, + { "mstep64", 0, 0xc800, 0x3607, 6, 0, 2, "rr", INDICES}, + { "neg", 0, 0x6600, 0x9800, 3, 0, 3, "arr", INDICES}, + { "neg", 0, 0x6600, 0x9800, 3, 0, 3, "rra", INDICES}, + { "nop", 0, 0x0000, 0xffff, 0, 0, 0, "", INDICES}, + { "not", 0, 0x6800, 0x9600, 3, 0, 3, "arr", INDICES}, + { "not", 0, 0x6800, 0x9600, 3, 0, 3, "rra", INDICES}, + { "or", 0, 0x6e00, 0x9000, 3, 0, 3, "arr", INDICES}, + { "or", 0, 0x6e00, 0x9000, 3, 0, 3, "rra", INDICES}, + { "or.f", 0, 0x2e00, 0xd004, 1, 0, 3, "rRf", INDICES}, + { "or.f", 0, 0x2e00, 0xd004, 1, 0, 3, "rrf", INDICES}, + { "or.pi", 0, 0x4e00, 0xb000, 2, 0, 2, "rE", INDICES}, + { "or.pi", 0, 0x4e00, 0xb000, 2, 0, 2, "re", INDICES}, + { "pri", 0, 0x7c00, 0x8200, 3, 0, 3, "arr", INDICES}, + { "pri", 0, 0x7c00, 0x8200, 3, 0, 3, "rra", INDICES}, + { "rl", 0, 0x8e00, 0x7020, 4, 0, 2, "re", INDICES}, + { "rr", 0, 0x8c00, 0x7220, 4, 0, 2, "re", INDICES}, + { "set", 0, 0x9400, 0x6a20, 4, 0, 2, "re", INDICES}, + { "set.f", 0, 0xac00, 0x5000, 5, 0, 3, "Ref", INDICES}, + { "set.f", 0, 0xac00, 0x5000, 5, 0, 3, "ref", INDICES}, + { "shl", 0, 0x8a00, 0x7420, 4, 0, 2, "re", INDICES}, + { "shr", 0, 0x8800, 0x7620, 4, 0, 2, "re", INDICES}, + { "st.f", 0, 0x3400, 0xca04, 1, 0, 3, "rRf", INDICES}, + { "st.f", 0, 0x3400, 0xca04, 1, 0, 3, "rrf", INDICES}, + { "st.if", 0, 0xb800, 0x4400, 5, 0, 3, "Ref", INDICES}, + { "st.if", 0, 0xb800, 0x4400, 5, 0, 3, "ref", INDICES}, + { "st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "arR", INDICES}, + { "st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "arr", INDICES}, + { "st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "rRa", INDICES}, + { "st.p", 0, 0x7400, 0x8a00, 3, 0, 3, "rra", INDICES}, + { "st.pi", 0, 0x5400, 0xaa00, 2, 0, 2, "rE", INDICES}, + { "st.pi", 0, 0x5400, 0xaa00, 2, 0, 2, "re", INDICES}, + { "sub", 0, 0x6200, 0x9c00, 3, 0, 3, "arr", INDICES}, + { "sub", 0, 0x6200, 0x9c00, 3, 0, 3, "rra", INDICES}, + { "sub.f", 0, 0x2200, 0xdc04, 1, 0, 3, "rRf", INDICES}, + { "sub.f", 0, 0x2200, 0xdc04, 1, 0, 3, "rrf", INDICES}, + { "sub.i", 0, 0x8200, 0x7c00, 4, 0, 2, "re", INDICES}, + { "sub.pi", 0, 0x4200, 0xbc00, 2, 0, 2, "rE", INDICES}, + { "sub.pi", 0, 0x4200, 0xbc00, 2, 0, 2, "re", INDICES}, + { "xch.f", 0, 0x3600, 0xc804, 1, 0, 3, "rRf", INDICES}, + { "xch.f", 0, 0x3600, 0xc804, 1, 0, 3, "rrf", INDICES}, + { "xch.pi", 0, 0x5600, 0xa800, 2, 0, 2, "rE", INDICES}, + { "xch.pi", 0, 0x5600, 0xa800, 2, 0, 2, "re", INDICES}, + { "xor", 0, 0x7000, 0x8e00, 3, 0, 3, "arr", INDICES}, + { "xor", 0, 0x7000, 0x8e00, 3, 0, 3, "rra", INDICES}, + { "xor.f", 0, 0x3000, 0xce04, 1, 0, 3, "rRf", INDICES}, + { "xor.f", 0, 0x3000, 0xce04, 1, 0, 3, "rrf", INDICES}, + { "xor.pi", 0, 0x5000, 0xae00, 2, 0, 2, "rE", INDICES}, + { "xor.pi", 0, 0x5000, 0xae00, 2, 0, 2, "re", INDICES} #undef INDICES }; diff --git a/libr/asm/p/asm_x86_nz.c b/libr/asm/p/asm_x86_nz.c index fa0ba9354c..66947d2c79 100644 --- a/libr/asm/p/asm_x86_nz.c +++ b/libr/asm/p/asm_x86_nz.c @@ -4225,365 +4225,365 @@ typedef struct lookup_t { } LookupTable; LookupTable oplookup[] = { - {"aaa", 0, NULL, 0x37, 1}, - {"aad", 0, NULL, 0xd50a, 2}, - {"aam", 0, opaam, 0}, - {"aas", 0, NULL, 0x3f, 1}, - {"adc", 0, &opadc, 0}, - {"add", 0, &opadd, 0}, - {"adx", 0, NULL, 0xd4, 1}, - {"amx", 0, NULL, 0xd5, 1}, - {"and", 0, &opand, 0}, - {"bsf", 0, &opbs, 0}, - {"bsr", 0, &opbs, 0}, - {"bswap", 0, &opbswap, 0}, - {"call", 0, &opcall, 0}, - {"cbw", 0, NULL, 0x6698, 2}, - {"cdq", 0, NULL, 0x99, 1}, - {"cdqe", 0, &opcdqe, 0}, - {"cwde", 0, &opcdqe, 0}, - {"clc", 0, NULL, 0xf8, 1}, - {"cld", 0, NULL, 0xfc, 1}, - {"clflush", 0, &opclflush, 0}, - {"clgi", 0, NULL, 0x0f01dd, 3}, - {"cli", 0, NULL, 0xfa, 1}, - {"clts", 0, NULL, 0x0f06, 2}, - {"cmc", 0, NULL, 0xf5, 1}, - {"cmovo", 0, &opcmov, 0}, - {"cmovno", 0, &opcmov, 0}, - {"cmovb", 0, &opcmov, 0}, - {"cmovc", 0, &opcmov, 0}, - {"cmovnae", 0, &opcmov, 0}, - {"cmovae", 0, &opcmov, 0}, - {"cmovnb", 0, &opcmov, 0}, - {"cmovnc", 0, &opcmov, 0}, - {"cmove", 0, &opcmov, 0}, - {"cmovz", 0, &opcmov, 0}, - {"cmovne", 0, &opcmov, 0}, - {"cmovnz", 0, &opcmov, 0}, - {"cmovbe", 0, &opcmov, 0}, - {"cmovna", 0, &opcmov, 0}, - {"cmova", 0, &opcmov, 0}, - {"cmovnbe", 0, &opcmov, 0}, - {"cmovne", 0, &opcmov, 0}, - {"cmovnz", 0, &opcmov, 0}, - {"cmovs", 0, &opcmov, 0}, - {"cmovns", 0, &opcmov, 0}, - {"cmovp", 0, &opcmov, 0}, - {"cmovpe", 0, &opcmov, 0}, - {"cmovnp", 0, &opcmov, 0}, - {"cmovpo", 0, &opcmov, 0}, - {"cmovl", 0, &opcmov, 0}, - {"cmovnge", 0, &opcmov, 0}, - {"cmovge", 0, &opcmov, 0}, - {"cmovnl", 0, &opcmov, 0}, - {"cmovle", 0, &opcmov, 0}, - {"cmovng", 0, &opcmov, 0}, - {"cmovg", 0, &opcmov, 0}, - {"cmovnle", 0, &opcmov, 0}, - {"cmp", 0, &opcmp, 0}, - {"cmpsb", 0, NULL, 0xa6, 1}, - {"cmpsd", 0, NULL, 0xa7, 1}, - {"cmpsw", 0, NULL, 0x66a7, 2}, - {"cpuid", 0, NULL, 0x0fa2, 2}, - {"cwd", 0, NULL, 0x6699, 2}, - {"cwde", 0, NULL, 0x98, 1}, - {"daa", 0, NULL, 0x27, 1}, - {"das", 0, NULL, 0x2f, 1}, - {"dec", 0, &opdec, 0}, - {"div", 0, &opdiv, 0}, - {"emms", 0, NULL, 0x0f77, 2}, - {"endbr32", 0, endbr32, 0}, - {"endbr64", 0, endbr64, 0}, - {"f2xm1", 0, NULL, 0xd9f0, 2}, - {"fabs", 0, NULL, 0xd9e1, 2}, - {"fadd", 0, &opfadd, 0}, - {"faddp", 0, &opfaddp, 0}, - {"fbld", 0, &opfbld, 0}, - {"fbstp", 0, &opfbstp, 0}, - {"fchs", 0, NULL, 0xd9e0, 2}, - {"fclex", 0, NULL, 0x9bdbe2, 3}, - {"fcmovb", 0, &opfcmov, 0}, - {"fcmove", 0, &opfcmov, 0}, - {"fcmovbe", 0, &opfcmov, 0}, - {"fcmovu", 0, &opfcmov, 0}, - {"fcmovnb", 0, &opfcmov, 0}, - {"fcmovne", 0, &opfcmov, 0}, - {"fcmovnbe", 0, &opfcmov, 0}, - {"fcmovnu", 0, &opfcmov, 0}, - {"fcos", 0, NULL, 0xd9ff, 2}, - {"fdecstp", 0, NULL, 0xd9f6, 2}, - {"fdiv", 0, &opfdiv, 0}, - {"fdivp", 0, &opfdivp, 0}, - {"fdivr", 0, &opfdivr, 0}, - {"fdivrp", 0, &opfdivrp, 0}, - {"femms", 0, NULL, 0x0f0e, 2}, - {"ffree", 0, &opffree, 0}, - {"fiadd", 0, &opfiadd, 0}, - {"ficom", 0, &opficom, 0}, - {"ficomp", 0, &opficomp, 0}, - {"fidiv", 0, &opfidiv, 0}, - {"fidivr", 0, &opfidivr, 0}, - {"fild", 0, &opfild, 0}, - {"fimul", 0, &opfimul, 0}, - {"fincstp", 0, NULL, 0xd9f7, 2}, - {"finit", 0, NULL, 0x9bdbe3, 3}, - {"fist", 0, &opfist, 0}, - {"fistp", 0, &opfistp, 0}, - {"fisttp", 0, &opfisttp, 0}, - {"fisub", 0, &opfisub, 0}, - {"fisubr", 0, &opfisubr, 0}, - {"fld1", 0, NULL, 0xd9e8, 2}, - {"fldcw", 0, &opfldcw, 0}, - {"fldenv", 0, &opfldenv, 0}, - {"fldl2t", 0, NULL, 0xd9e9, 2}, - {"fldl2e", 0, NULL, 0xd9ea, 2}, - {"fldlg2", 0, NULL, 0xd9ec, 2}, - {"fldln2", 0, NULL, 0xd9ed, 2}, - {"fldpi", 0, NULL, 0xd9eb, 2}, - {"fldz", 0, NULL, 0xd9ee, 2}, - {"fmul", 0, &opfmul, 0}, - {"fmulp", 0, &opfmulp, 0}, - {"fnclex", 0, NULL, 0xdbe2, 2}, - {"fninit", 0, NULL, 0xdbe3, 2}, - {"fnop", 0, NULL, 0xd9d0, 2}, - {"fnsave", 0, &opfnsave, 0}, - {"fnstcw", 0, &opfnstcw, 0}, - {"fnstenv", 0, &opfnstenv, 0}, - {"fnstsw", 0, &opfnstsw, 0}, - {"fpatan", 0, NULL, 0xd9f3, 2}, - {"fprem", 0, NULL, 0xd9f8, 2}, - {"fprem1", 0, NULL, 0xd9f5, 2}, - {"fptan", 0, NULL, 0xd9f2, 2}, - {"frndint", 0, NULL, 0xd9fc, 2}, - {"frstor", 0, &opfrstor, 0}, - {"fsave", 0, &opfsave, 0}, - {"fscale", 0, NULL, 0xd9fd, 2}, - {"fsin", 0, NULL, 0xd9fe, 2}, - {"fsincos", 0, NULL, 0xd9fb, 2}, - {"fsqrt", 0, NULL, 0xd9fa, 2}, - {"fstcw", 0, &opfstcw, 0}, - {"fstenv", 0, &opfstenv, 0}, - {"fstsw", 0, &opfstsw, 0}, - {"fsub", 0, &opfsub, 0}, - {"fsubp", 0, &opfsubp, 0}, - {"fsubr", 0, &opfsubr, 0}, - {"fsubrp", 0, &opfsubrp, 0}, - {"ftst", 0, NULL, 0xd9e4, 2}, - {"fucom", 0, &opfucom, 0}, - {"fucomp", 0, &opfucomp, 0}, - {"fucompp", 0, NULL, 0xdae9, 2}, - {"fwait", 0, NULL, 0x9b, 1}, - {"fxam", 0, NULL, 0xd9e5, 2}, - {"fxch", 0, &opfxch, 0}, - {"fxrstor", 0, &opfxrstor, 0}, - {"fxsave", 0, &opfxsave, 0}, - {"fxtract", 0, NULL, 0xd9f4, 2}, - {"fyl2x", 0, NULL, 0xd9f1, 2}, - {"fyl2xp1", 0, NULL, 0xd9f9, 2}, - {"getsec", 0, NULL, 0x0f37, 2}, - {"hlt", 0, NULL, 0xf4, 1}, - {"idiv", 0, &opidiv, 0}, - {"imul", 0, &opimul, 0}, - {"in", 0, &opin, 0}, - {"inc", 0, &opinc, 0}, - {"ins", 0, NULL, 0x6d, 1}, - {"insb", 0, NULL, 0x6c, 1}, - {"insd", 0, NULL, 0x6d, 1}, - {"insw", 0, NULL, 0x666d, 2}, - {"int", 0, &opint, 0}, - {"int1", 0, NULL, 0xf1, 1}, - {"int3", 0, NULL, 0xcc, 1}, - {"into", 0, NULL, 0xce, 1}, - {"invd", 0, NULL, 0x0f08, 2}, - {"iret", 0, NULL, 0x66cf, 2}, - {"iretd", 0, NULL, 0xcf, 1}, - {"ja", 0, &opjc, 0}, - {"jae", 0, &opjc, 0}, - {"jb", 0, &opjc, 0}, - {"jbe", 0, &opjc, 0}, - {"jc", 0, &opjc, 0}, - {"je", 0, &opjc, 0}, - {"jg", 0, &opjc, 0}, - {"jge", 0, &opjc, 0}, - {"jl", 0, &opjc, 0}, - {"jle", 0, &opjc, 0}, - {"jmp", 0, &opjc, 0}, - {"jna", 0, &opjc, 0}, - {"jnae", 0, &opjc, 0}, - {"jnb", 0, &opjc, 0}, - {"jnbe", 0, &opjc, 0}, - {"jnc", 0, &opjc, 0}, - {"jne", 0, &opjc, 0}, - {"jng", 0, &opjc, 0}, - {"jnge", 0, &opjc, 0}, - {"jnl", 0, &opjc, 0}, - {"jnle", 0, &opjc, 0}, - {"jno", 0, &opjc, 0}, - {"jnp", 0, &opjc, 0}, - {"jns", 0, &opjc, 0}, - {"jnz", 0, &opjc, 0}, - {"jo", 0, &opjc, 0}, - {"jp", 0, &opjc, 0}, - {"jpe", 0, &opjc, 0}, - {"jpo", 0, &opjc, 0}, - {"js", 0, &opjc, 0}, - {"jz", 0, &opjc, 0}, - {"jcxz", 0, &opjc, 0}, - {"jecxz", 0, &opjc, 0}, - {"jrcxz", 0, &opjc, 0}, - {"lahf", 0, NULL, 0x9f, 1}, - {"lea", 0, &oplea, 0}, - {"leave", 0, NULL, 0xc9, 1}, - {"les", 0, &oples, 0}, - {"lfence", 0, NULL, 0x0faee8, 3}, - {"lgdt", 0, &oplgdt, 0}, - {"lidt", 0, &oplidt, 0}, - {"lldt", 0, &oplldt, 0}, - {"lmsw", 0, &oplmsw, 0}, - {"lodsb", 0, NULL, 0xac, 1}, - {"lodsd", 0, NULL, 0xad, 1}, - {"lodsw", 0, NULL, 0x66ad, 2}, - {"loop", 0, &oploop, 0}, - {"mfence", 0, NULL, 0x0faef0, 3}, - {"monitor", 0, NULL, 0x0f01c8, 3}, - {"mov", 0, &opmov, 0}, - {"movsb", 0, NULL, 0xa4, 1}, - {"movsd", 0, NULL, 0xa5, 1}, - {"movsw", 0, NULL, 0x66a5, 2}, - {"movzx", 0, &opmovx, 0}, - {"movsx", 0, &opmovx, 0}, - {"movabs", 0, &opmovabs, 0}, - {"mul", 0, &opmul, 0}, - {"mwait", 0, NULL, 0x0f01c9, 3}, - {"neg", 0, &opneg, 0}, - {"nop", 0, NULL, 0x90, 1}, - {"not", 0, &opnot, 0}, - {"or", 0, &opor, 0}, - {"out", 0, &opout, 0}, - {"outsb", 0, NULL, 0x6e, 1}, - {"outs", 0, NULL, 0x6f, 1}, - {"outsd", 0, NULL, 0x6f, 1}, - {"outsw", 0, NULL, 0x666f, 2}, - {"pop", 0, &oppop, 0}, - {"popa", 1, NULL, 0x61, 1}, - {"popad", 1, NULL, 0x61, 1}, - {"popal", 1, NULL, 0x61, 1}, - {"popaw", 1, NULL, 0x6661, 2}, - {"popfd", 1, NULL, 0x9d, 1}, - {"prefetch", 0, NULL, 0x0f0d, 2}, - {"push", 0, &oppush, 0}, - {"pusha", 1, NULL, 0x60, 1}, - {"pushad", 1, NULL, 0x60, 1}, - {"pushal", 1, NULL, 0x60, 1}, - {"pushf", 0, NULL, 0x669c, 2}, - {"popf", 0, NULL, 0x669d, 2}, - {"pushfd", 0, NULL, 0x9c, 1}, - {"rcl", 0, &process_group_2, 0}, - {"rcr", 0, &process_group_2, 0}, - {"rep", 0, &oprep, 0}, - {"repe", 0, &oprep, 0}, - {"repne", 0, &oprep, 0}, - {"repz", 0, &oprep, 0}, - {"repnz", 0, &oprep, 0}, - {"rdmsr", 0, NULL, 0x0f32, 2}, - {"rdpmc", 0, NULL, 0x0f33, 2}, - {"rdtsc", 0, NULL, 0x0f31, 2}, - {"rdtscp", 0, NULL, 0x0f01f9, 3}, - {"ret", 0, &opret, 0}, - {"retf", 0, &opretf, 0}, - {"retw", 0, NULL, 0x66c3, 2}, - {"rol", 0, &process_group_2, 0}, - {"ror", 0, &process_group_2, 0}, - {"rsm", 0, NULL, 0x0faa, 2}, - {"sahf", 0, NULL, 0x9e, 1}, - {"sal", 0, &process_group_2, 0}, - {"salc", 0, NULL, 0xd6, 1}, - {"sar", 0, &process_group_2, 0}, - {"sbb", 0, &opsbb, 0}, - {"scasb", 0, NULL, 0xae, 1}, - {"scasd", 0, NULL, 0xaf, 1}, - {"scasw", 0, NULL, 0x66af, 2}, - {"seto", 0, &opset, 0}, - {"setno", 0, &opset, 0}, - {"setb", 0, &opset, 0}, - {"setnae", 0, &opset, 0}, - {"setc", 0, &opset, 0}, - {"setnb", 0, &opset, 0}, - {"setae", 0, &opset, 0}, - {"setnc", 0, &opset, 0}, - {"setz", 0, &opset, 0}, - {"sete", 0, &opset, 0}, - {"setnz", 0, &opset, 0}, - {"setne", 0, &opset, 0}, - {"setbe", 0, &opset, 0}, - {"setna", 0, &opset, 0}, - {"setnbe", 0, &opset, 0}, - {"seta", 0, &opset, 0}, - {"sets", 0, &opset, 0}, - {"setns", 0, &opset, 0}, - {"setp", 0, &opset, 0}, - {"setpe", 0, &opset, 0}, - {"setnp", 0, &opset, 0}, - {"setpo", 0, &opset, 0}, - {"setl", 0, &opset, 0}, - {"setnge", 0, &opset, 0}, - {"setnl", 0, &opset, 0}, - {"setge", 0, &opset, 0}, - {"setle", 0, &opset, 0}, - {"setng", 0, &opset, 0}, - {"setnle", 0, &opset, 0}, - {"setg", 0, &opset, 0}, - {"sfence", 0, NULL, 0x0faef8, 3}, - {"sgdt", 0, &opsgdt, 0}, - {"shl", 0, &process_group_2, 0}, - {"shr", 0, &process_group_2, 0}, - {"sidt", 0, &opsidt, 0}, - {"sldt", 0, &opsldt, 0}, - {"smsw", 0, &opsmsw, 0}, - {"stc", 0, NULL, 0xf9, 1}, - {"std", 0, NULL, 0xfd, 1}, - {"stgi", 0, NULL, 0x0f01dc, 3}, - {"sti", 0, NULL, 0xfb, 1}, - {"stmxcsr", 0, &opstmxcsr, 0}, - {"stosb", 0, &opstos, 0}, - {"stosd", 0, &opstos, 0}, - {"stosw", 0, &opstos, 0}, - {"str", 0, &opstr, 0}, - {"sub", 0, &opsub, 0}, - {"swapgs", 0, NULL, 0x0f1ff8, 3}, - {"syscall", 0, NULL, 0x0f05, 2}, - {"sysenter", 0, NULL, 0x0f34, 2}, - {"sysexit", 0, NULL, 0x0f35, 2}, - {"sysret", 0, NULL, 0x0f07, 2}, - {"ud2", 0, NULL, 0x0f0b, 2}, - {"verr", 0, &opverr, 0}, - {"verw", 0, &opverw, 0}, - {"vmcall", 0, NULL, 0x0f01c1, 3}, - {"vmclear", 0, &opvmclear, 0}, - {"vmlaunch", 0, NULL, 0x0f01c2, 3}, - {"vmload", 0, NULL, 0x0f01da, 3}, - {"vmmcall", 0, NULL, 0x0f01d9, 3}, - {"vmptrld", 0, &opvmptrld, 0}, - {"vmptrst", 0, &opvmptrst, 0}, - {"vmresume", 0, NULL, 0x0f01c3, 3}, - {"vmrun", 0, NULL, 0x0f01d8, 3}, - {"vmsave", 0, NULL, 0x0f01db, 3}, - {"vmxoff", 0, NULL, 0x0f01c4, 3}, - {"vmxon", 0, &opvmon, 0}, - {"vzeroall", 0, NULL, 0xc5fc77, 3}, - {"vzeroupper", 0, NULL, 0xc5f877, 3}, - {"wait", 0, NULL, 0x9b, 1}, - {"wbinvd", 0, NULL, 0x0f09, 2}, - {"wrmsr", 0, NULL, 0x0f30, 2}, - {"xadd", 0, &opxadd, 0}, - {"xchg", 0, &opxchg, 0}, - {"xgetbv", 0, NULL, 0x0f01d0, 3}, - {"xlatb", 0, NULL, 0xd7, 1}, - {"xor", 0, &opxor, 0}, - {"xsetbv", 0, NULL, 0x0f01d1, 3}, - {"test", 0, &optest, 0}, - {"null", 0, NULL, 0, 0} + { "aaa", 0, NULL, 0x37, 1}, + { "aad", 0, NULL, 0xd50a, 2}, + { "aam", 0, opaam, 0}, + { "aas", 0, NULL, 0x3f, 1}, + { "adc", 0, &opadc, 0}, + { "add", 0, &opadd, 0}, + { "adx", 0, NULL, 0xd4, 1}, + { "amx", 0, NULL, 0xd5, 1}, + { "and", 0, &opand, 0}, + { "bsf", 0, &opbs, 0}, + { "bsr", 0, &opbs, 0}, + { "bswap", 0, &opbswap, 0}, + { "call", 0, &opcall, 0}, + { "cbw", 0, NULL, 0x6698, 2}, + { "cdq", 0, NULL, 0x99, 1}, + { "cdqe", 0, &opcdqe, 0}, + { "cwde", 0, &opcdqe, 0}, + { "clc", 0, NULL, 0xf8, 1}, + { "cld", 0, NULL, 0xfc, 1}, + { "clflush", 0, &opclflush, 0}, + { "clgi", 0, NULL, 0x0f01dd, 3}, + { "cli", 0, NULL, 0xfa, 1}, + { "clts", 0, NULL, 0x0f06, 2}, + { "cmc", 0, NULL, 0xf5, 1}, + { "cmovo", 0, &opcmov, 0}, + { "cmovno", 0, &opcmov, 0}, + { "cmovb", 0, &opcmov, 0}, + { "cmovc", 0, &opcmov, 0}, + { "cmovnae", 0, &opcmov, 0}, + { "cmovae", 0, &opcmov, 0}, + { "cmovnb", 0, &opcmov, 0}, + { "cmovnc", 0, &opcmov, 0}, + { "cmove", 0, &opcmov, 0}, + { "cmovz", 0, &opcmov, 0}, + { "cmovne", 0, &opcmov, 0}, + { "cmovnz", 0, &opcmov, 0}, + { "cmovbe", 0, &opcmov, 0}, + { "cmovna", 0, &opcmov, 0}, + { "cmova", 0, &opcmov, 0}, + { "cmovnbe", 0, &opcmov, 0}, + { "cmovne", 0, &opcmov, 0}, + { "cmovnz", 0, &opcmov, 0}, + { "cmovs", 0, &opcmov, 0}, + { "cmovns", 0, &opcmov, 0}, + { "cmovp", 0, &opcmov, 0}, + { "cmovpe", 0, &opcmov, 0}, + { "cmovnp", 0, &opcmov, 0}, + { "cmovpo", 0, &opcmov, 0}, + { "cmovl", 0, &opcmov, 0}, + { "cmovnge", 0, &opcmov, 0}, + { "cmovge", 0, &opcmov, 0}, + { "cmovnl", 0, &opcmov, 0}, + { "cmovle", 0, &opcmov, 0}, + { "cmovng", 0, &opcmov, 0}, + { "cmovg", 0, &opcmov, 0}, + { "cmovnle", 0, &opcmov, 0}, + { "cmp", 0, &opcmp, 0}, + { "cmpsb", 0, NULL, 0xa6, 1}, + { "cmpsd", 0, NULL, 0xa7, 1}, + { "cmpsw", 0, NULL, 0x66a7, 2}, + { "cpuid", 0, NULL, 0x0fa2, 2}, + { "cwd", 0, NULL, 0x6699, 2}, + { "cwde", 0, NULL, 0x98, 1}, + { "daa", 0, NULL, 0x27, 1}, + { "das", 0, NULL, 0x2f, 1}, + { "dec", 0, &opdec, 0}, + { "div", 0, &opdiv, 0}, + { "emms", 0, NULL, 0x0f77, 2}, + { "endbr32", 0, endbr32, 0}, + { "endbr64", 0, endbr64, 0}, + { "f2xm1", 0, NULL, 0xd9f0, 2}, + { "fabs", 0, NULL, 0xd9e1, 2}, + { "fadd", 0, &opfadd, 0}, + { "faddp", 0, &opfaddp, 0}, + { "fbld", 0, &opfbld, 0}, + { "fbstp", 0, &opfbstp, 0}, + { "fchs", 0, NULL, 0xd9e0, 2}, + { "fclex", 0, NULL, 0x9bdbe2, 3}, + { "fcmovb", 0, &opfcmov, 0}, + { "fcmove", 0, &opfcmov, 0}, + { "fcmovbe", 0, &opfcmov, 0}, + { "fcmovu", 0, &opfcmov, 0}, + { "fcmovnb", 0, &opfcmov, 0}, + { "fcmovne", 0, &opfcmov, 0}, + { "fcmovnbe", 0, &opfcmov, 0}, + { "fcmovnu", 0, &opfcmov, 0}, + { "fcos", 0, NULL, 0xd9ff, 2}, + { "fdecstp", 0, NULL, 0xd9f6, 2}, + { "fdiv", 0, &opfdiv, 0}, + { "fdivp", 0, &opfdivp, 0}, + { "fdivr", 0, &opfdivr, 0}, + { "fdivrp", 0, &opfdivrp, 0}, + { "femms", 0, NULL, 0x0f0e, 2}, + { "ffree", 0, &opffree, 0}, + { "fiadd", 0, &opfiadd, 0}, + { "ficom", 0, &opficom, 0}, + { "ficomp", 0, &opficomp, 0}, + { "fidiv", 0, &opfidiv, 0}, + { "fidivr", 0, &opfidivr, 0}, + { "fild", 0, &opfild, 0}, + { "fimul", 0, &opfimul, 0}, + { "fincstp", 0, NULL, 0xd9f7, 2}, + { "finit", 0, NULL, 0x9bdbe3, 3}, + { "fist", 0, &opfist, 0}, + { "fistp", 0, &opfistp, 0}, + { "fisttp", 0, &opfisttp, 0}, + { "fisub", 0, &opfisub, 0}, + { "fisubr", 0, &opfisubr, 0}, + { "fld1", 0, NULL, 0xd9e8, 2}, + { "fldcw", 0, &opfldcw, 0}, + { "fldenv", 0, &opfldenv, 0}, + { "fldl2t", 0, NULL, 0xd9e9, 2}, + { "fldl2e", 0, NULL, 0xd9ea, 2}, + { "fldlg2", 0, NULL, 0xd9ec, 2}, + { "fldln2", 0, NULL, 0xd9ed, 2}, + { "fldpi", 0, NULL, 0xd9eb, 2}, + { "fldz", 0, NULL, 0xd9ee, 2}, + { "fmul", 0, &opfmul, 0}, + { "fmulp", 0, &opfmulp, 0}, + { "fnclex", 0, NULL, 0xdbe2, 2}, + { "fninit", 0, NULL, 0xdbe3, 2}, + { "fnop", 0, NULL, 0xd9d0, 2}, + { "fnsave", 0, &opfnsave, 0}, + { "fnstcw", 0, &opfnstcw, 0}, + { "fnstenv", 0, &opfnstenv, 0}, + { "fnstsw", 0, &opfnstsw, 0}, + { "fpatan", 0, NULL, 0xd9f3, 2}, + { "fprem", 0, NULL, 0xd9f8, 2}, + { "fprem1", 0, NULL, 0xd9f5, 2}, + { "fptan", 0, NULL, 0xd9f2, 2}, + { "frndint", 0, NULL, 0xd9fc, 2}, + { "frstor", 0, &opfrstor, 0}, + { "fsave", 0, &opfsave, 0}, + { "fscale", 0, NULL, 0xd9fd, 2}, + { "fsin", 0, NULL, 0xd9fe, 2}, + { "fsincos", 0, NULL, 0xd9fb, 2}, + { "fsqrt", 0, NULL, 0xd9fa, 2}, + { "fstcw", 0, &opfstcw, 0}, + { "fstenv", 0, &opfstenv, 0}, + { "fstsw", 0, &opfstsw, 0}, + { "fsub", 0, &opfsub, 0}, + { "fsubp", 0, &opfsubp, 0}, + { "fsubr", 0, &opfsubr, 0}, + { "fsubrp", 0, &opfsubrp, 0}, + { "ftst", 0, NULL, 0xd9e4, 2}, + { "fucom", 0, &opfucom, 0}, + { "fucomp", 0, &opfucomp, 0}, + { "fucompp", 0, NULL, 0xdae9, 2}, + { "fwait", 0, NULL, 0x9b, 1}, + { "fxam", 0, NULL, 0xd9e5, 2}, + { "fxch", 0, &opfxch, 0}, + { "fxrstor", 0, &opfxrstor, 0}, + { "fxsave", 0, &opfxsave, 0}, + { "fxtract", 0, NULL, 0xd9f4, 2}, + { "fyl2x", 0, NULL, 0xd9f1, 2}, + { "fyl2xp1", 0, NULL, 0xd9f9, 2}, + { "getsec", 0, NULL, 0x0f37, 2}, + { "hlt", 0, NULL, 0xf4, 1}, + { "idiv", 0, &opidiv, 0}, + { "imul", 0, &opimul, 0}, + { "in", 0, &opin, 0}, + { "inc", 0, &opinc, 0}, + { "ins", 0, NULL, 0x6d, 1}, + { "insb", 0, NULL, 0x6c, 1}, + { "insd", 0, NULL, 0x6d, 1}, + { "insw", 0, NULL, 0x666d, 2}, + { "int", 0, &opint, 0}, + { "int1", 0, NULL, 0xf1, 1}, + { "int3", 0, NULL, 0xcc, 1}, + { "into", 0, NULL, 0xce, 1}, + { "invd", 0, NULL, 0x0f08, 2}, + { "iret", 0, NULL, 0x66cf, 2}, + { "iretd", 0, NULL, 0xcf, 1}, + { "ja", 0, &opjc, 0}, + { "jae", 0, &opjc, 0}, + { "jb", 0, &opjc, 0}, + { "jbe", 0, &opjc, 0}, + { "jc", 0, &opjc, 0}, + { "je", 0, &opjc, 0}, + { "jg", 0, &opjc, 0}, + { "jge", 0, &opjc, 0}, + { "jl", 0, &opjc, 0}, + { "jle", 0, &opjc, 0}, + { "jmp", 0, &opjc, 0}, + { "jna", 0, &opjc, 0}, + { "jnae", 0, &opjc, 0}, + { "jnb", 0, &opjc, 0}, + { "jnbe", 0, &opjc, 0}, + { "jnc", 0, &opjc, 0}, + { "jne", 0, &opjc, 0}, + { "jng", 0, &opjc, 0}, + { "jnge", 0, &opjc, 0}, + { "jnl", 0, &opjc, 0}, + { "jnle", 0, &opjc, 0}, + { "jno", 0, &opjc, 0}, + { "jnp", 0, &opjc, 0}, + { "jns", 0, &opjc, 0}, + { "jnz", 0, &opjc, 0}, + { "jo", 0, &opjc, 0}, + { "jp", 0, &opjc, 0}, + { "jpe", 0, &opjc, 0}, + { "jpo", 0, &opjc, 0}, + { "js", 0, &opjc, 0}, + { "jz", 0, &opjc, 0}, + { "jcxz", 0, &opjc, 0}, + { "jecxz", 0, &opjc, 0}, + { "jrcxz", 0, &opjc, 0}, + { "lahf", 0, NULL, 0x9f, 1}, + { "lea", 0, &oplea, 0}, + { "leave", 0, NULL, 0xc9, 1}, + { "les", 0, &oples, 0}, + { "lfence", 0, NULL, 0x0faee8, 3}, + { "lgdt", 0, &oplgdt, 0}, + { "lidt", 0, &oplidt, 0}, + { "lldt", 0, &oplldt, 0}, + { "lmsw", 0, &oplmsw, 0}, + { "lodsb", 0, NULL, 0xac, 1}, + { "lodsd", 0, NULL, 0xad, 1}, + { "lodsw", 0, NULL, 0x66ad, 2}, + { "loop", 0, &oploop, 0}, + { "mfence", 0, NULL, 0x0faef0, 3}, + { "monitor", 0, NULL, 0x0f01c8, 3}, + { "mov", 0, &opmov, 0}, + { "movsb", 0, NULL, 0xa4, 1}, + { "movsd", 0, NULL, 0xa5, 1}, + { "movsw", 0, NULL, 0x66a5, 2}, + { "movzx", 0, &opmovx, 0}, + { "movsx", 0, &opmovx, 0}, + { "movabs", 0, &opmovabs, 0}, + { "mul", 0, &opmul, 0}, + { "mwait", 0, NULL, 0x0f01c9, 3}, + { "neg", 0, &opneg, 0}, + { "nop", 0, NULL, 0x90, 1}, + { "not", 0, &opnot, 0}, + { "or", 0, &opor, 0}, + { "out", 0, &opout, 0}, + { "outsb", 0, NULL, 0x6e, 1}, + { "outs", 0, NULL, 0x6f, 1}, + { "outsd", 0, NULL, 0x6f, 1}, + { "outsw", 0, NULL, 0x666f, 2}, + { "pop", 0, &oppop, 0}, + { "popa", 1, NULL, 0x61, 1}, + { "popad", 1, NULL, 0x61, 1}, + { "popal", 1, NULL, 0x61, 1}, + { "popaw", 1, NULL, 0x6661, 2}, + { "popfd", 1, NULL, 0x9d, 1}, + { "prefetch", 0, NULL, 0x0f0d, 2}, + { "push", 0, &oppush, 0}, + { "pusha", 1, NULL, 0x60, 1}, + { "pushad", 1, NULL, 0x60, 1}, + { "pushal", 1, NULL, 0x60, 1}, + { "pushf", 0, NULL, 0x669c, 2}, + { "popf", 0, NULL, 0x669d, 2}, + { "pushfd", 0, NULL, 0x9c, 1}, + { "rcl", 0, &process_group_2, 0}, + { "rcr", 0, &process_group_2, 0}, + { "rep", 0, &oprep, 0}, + { "repe", 0, &oprep, 0}, + { "repne", 0, &oprep, 0}, + { "repz", 0, &oprep, 0}, + { "repnz", 0, &oprep, 0}, + { "rdmsr", 0, NULL, 0x0f32, 2}, + { "rdpmc", 0, NULL, 0x0f33, 2}, + { "rdtsc", 0, NULL, 0x0f31, 2}, + { "rdtscp", 0, NULL, 0x0f01f9, 3}, + { "ret", 0, &opret, 0}, + { "retf", 0, &opretf, 0}, + { "retw", 0, NULL, 0x66c3, 2}, + { "rol", 0, &process_group_2, 0}, + { "ror", 0, &process_group_2, 0}, + { "rsm", 0, NULL, 0x0faa, 2}, + { "sahf", 0, NULL, 0x9e, 1}, + { "sal", 0, &process_group_2, 0}, + { "salc", 0, NULL, 0xd6, 1}, + { "sar", 0, &process_group_2, 0}, + { "sbb", 0, &opsbb, 0}, + { "scasb", 0, NULL, 0xae, 1}, + { "scasd", 0, NULL, 0xaf, 1}, + { "scasw", 0, NULL, 0x66af, 2}, + { "seto", 0, &opset, 0}, + { "setno", 0, &opset, 0}, + { "setb", 0, &opset, 0}, + { "setnae", 0, &opset, 0}, + { "setc", 0, &opset, 0}, + { "setnb", 0, &opset, 0}, + { "setae", 0, &opset, 0}, + { "setnc", 0, &opset, 0}, + { "setz", 0, &opset, 0}, + { "sete", 0, &opset, 0}, + { "setnz", 0, &opset, 0}, + { "setne", 0, &opset, 0}, + { "setbe", 0, &opset, 0}, + { "setna", 0, &opset, 0}, + { "setnbe", 0, &opset, 0}, + { "seta", 0, &opset, 0}, + { "sets", 0, &opset, 0}, + { "setns", 0, &opset, 0}, + { "setp", 0, &opset, 0}, + { "setpe", 0, &opset, 0}, + { "setnp", 0, &opset, 0}, + { "setpo", 0, &opset, 0}, + { "setl", 0, &opset, 0}, + { "setnge", 0, &opset, 0}, + { "setnl", 0, &opset, 0}, + { "setge", 0, &opset, 0}, + { "setle", 0, &opset, 0}, + { "setng", 0, &opset, 0}, + { "setnle", 0, &opset, 0}, + { "setg", 0, &opset, 0}, + { "sfence", 0, NULL, 0x0faef8, 3}, + { "sgdt", 0, &opsgdt, 0}, + { "shl", 0, &process_group_2, 0}, + { "shr", 0, &process_group_2, 0}, + { "sidt", 0, &opsidt, 0}, + { "sldt", 0, &opsldt, 0}, + { "smsw", 0, &opsmsw, 0}, + { "stc", 0, NULL, 0xf9, 1}, + { "std", 0, NULL, 0xfd, 1}, + { "stgi", 0, NULL, 0x0f01dc, 3}, + { "sti", 0, NULL, 0xfb, 1}, + { "stmxcsr", 0, &opstmxcsr, 0}, + { "stosb", 0, &opstos, 0}, + { "stosd", 0, &opstos, 0}, + { "stosw", 0, &opstos, 0}, + { "str", 0, &opstr, 0}, + { "sub", 0, &opsub, 0}, + { "swapgs", 0, NULL, 0x0f1ff8, 3}, + { "syscall", 0, NULL, 0x0f05, 2}, + { "sysenter", 0, NULL, 0x0f34, 2}, + { "sysexit", 0, NULL, 0x0f35, 2}, + { "sysret", 0, NULL, 0x0f07, 2}, + { "ud2", 0, NULL, 0x0f0b, 2}, + { "verr", 0, &opverr, 0}, + { "verw", 0, &opverw, 0}, + { "vmcall", 0, NULL, 0x0f01c1, 3}, + { "vmclear", 0, &opvmclear, 0}, + { "vmlaunch", 0, NULL, 0x0f01c2, 3}, + { "vmload", 0, NULL, 0x0f01da, 3}, + { "vmmcall", 0, NULL, 0x0f01d9, 3}, + { "vmptrld", 0, &opvmptrld, 0}, + { "vmptrst", 0, &opvmptrst, 0}, + { "vmresume", 0, NULL, 0x0f01c3, 3}, + { "vmrun", 0, NULL, 0x0f01d8, 3}, + { "vmsave", 0, NULL, 0x0f01db, 3}, + { "vmxoff", 0, NULL, 0x0f01c4, 3}, + { "vmxon", 0, &opvmon, 0}, + { "vzeroall", 0, NULL, 0xc5fc77, 3}, + { "vzeroupper", 0, NULL, 0xc5f877, 3}, + { "wait", 0, NULL, 0x9b, 1}, + { "wbinvd", 0, NULL, 0x0f09, 2}, + { "wrmsr", 0, NULL, 0x0f30, 2}, + { "xadd", 0, &opxadd, 0}, + { "xchg", 0, &opxchg, 0}, + { "xgetbv", 0, NULL, 0x0f01d0, 3}, + { "xlatb", 0, NULL, 0xd7, 1}, + { "xor", 0, &opxor, 0}, + { "xsetbv", 0, NULL, 0x0f01d1, 3}, + { "test", 0, &optest, 0}, + { "null", 0, NULL, 0, 0} }; static x86newTokenType getToken(const char *str, size_t *begin, size_t *end) { diff --git a/libr/bin/format/pdb/main.c b/libr/bin/format/pdb/main.c index f4c9bcb96e..7b1ca76ab6 100644 --- a/libr/bin/format/pdb/main.c +++ b/libr/bin/format/pdb/main.c @@ -12,10 +12,10 @@ static void print_usage(void) { /////////////////////////////////////////////////////////////////////////////// static const struct option long_options[] = { - {"pdb_file", required_argument, 0, 'f'}, - {"print_types", no_argument, 0, 't'}, - {"print_globals", required_argument, 0, 'g'}, - {"help", no_argument, 0, 'h'}, + { "pdb_file", required_argument, 0, 'f'}, + { "print_types", no_argument, 0, 't'}, + { "print_globals", required_argument, 0, 'g'}, + { "help", no_argument, 0, 'h'}, {NULL, 0, 0, 0} }; diff --git a/libr/bin/format/xnu/r_cf_dict.c b/libr/bin/format/xnu/r_cf_dict.c index a65eaaa197..01328f939d 100644 --- a/libr/bin/format/xnu/r_cf_dict.c +++ b/libr/bin/format/xnu/r_cf_dict.c @@ -1,5 +1,5 @@ -#include -#include +/* radare - LGPL - Copyright 2019-2022 - mrmacete, pancake */ + #include #include #include @@ -346,7 +346,6 @@ static void r_cf_value_dict_add(RCFValueDict *dict, RCFKeyValue *key_value) { if (!dict || !dict->pairs) { return; } - r_list_push (dict->pairs, key_value); } @@ -368,28 +367,21 @@ static void r_cf_value_dict_print(RCFValueDict *dict) { static RCFValueArray *r_cf_value_array_new(void) { RCFValueArray *array = R_NEW0 (RCFValueArray); - if (!array) { - return NULL; + if (array) { + array->type = R_CF_ARRAY; + array->values = r_list_newf ((RListFree)&r_cf_value_free); } - - array->type = R_CF_ARRAY; - array->values = r_list_newf ((RListFree)&r_cf_value_free); - return array; } static void r_cf_value_array_free(RCFValueArray *array) { - if (!array) { - return; + if (array) { + if (array->values) { + r_list_free (array->values); + array->values = NULL; + } + free (array); } - - if (array->values) { - r_list_free (array->values); - array->values = NULL; - } - - array->type = R_CF_INVALID; - R_FREE (array); } static void r_cf_value_array_add(RCFValueArray *array, RCFValue *value) { diff --git a/libr/bin/p/bin_vsf.c b/libr/bin/p/bin_vsf.c index 8209608158..031992779e 100644 --- a/libr/bin/p/bin_vsf.c +++ b/libr/bin/p/bin_vsf.c @@ -19,8 +19,8 @@ static const struct { const int offset_mem; const int ram_size; } _machines[] = { - {"C64", "Commodore 64", r_offsetof(struct vsf_c64mem, ram), 64 * 1024}, - {"C128", "Commodore 128", r_offsetof(struct vsf_c128mem, ram), 128 * 1024}, + { "C64", "Commodore 64", r_offsetof(struct vsf_c64mem, ram), 64 * 1024}, + { "C128", "Commodore 128", r_offsetof(struct vsf_c128mem, ram), 128 * 1024}, }; static const int MACHINES_MAX = sizeof (_machines) / sizeof (_machines[0]); @@ -343,133 +343,133 @@ static RList* symbols(RBinFile *bf) { const ut16 address; const char* symbol_name; } _symbols[] = { -// {0xfffa, "NMI_VECTOR_LSB"}, -// {0xfffb, "NMI_VECTOR_MSB"}, -// {0xfffe, "IRQ_VECTOR_LSB"}, -// {0xffff, "IRQ_VECTOR_MSB"}, +// {0xfffa, "NMI_VECTOR_LSB" }, +// {0xfffb, "NMI_VECTOR_MSB" }, +// {0xfffe, "IRQ_VECTOR_LSB" }, +// {0xffff, "IRQ_VECTOR_MSB" }, // Defines taken from c64.inc from cc65 // I/O: VIC - {0xd000, "VIC_SPR0_X"}, - {0xd001, "VIC_SPR0_Y"}, - {0xd002, "VIC_SPR1_X"}, - {0xd003, "VIC_SPR1_Y"}, - {0xd004, "VIC_SPR2_X"}, - {0xd005, "VIC_SPR2_Y"}, - {0xd006, "VIC_SPR3_X"}, - {0xd007, "VIC_SPR3_Y"}, - {0xd008, "VIC_SPR4_X"}, - {0xd009, "VIC_SPR4_Y"}, - {0xd00a, "VIC_SPR5_X"}, - {0xd00b, "VIC_SPR5_Y"}, - {0xd00c, "VIC_SPR6_X"}, - {0xd00d, "VIC_SPR6_Y"}, - {0xd00e, "VIC_SPR7_X"}, - {0xd00f, "VIC_SPR7_Y"}, - {0xd010, "VIC_SPR_HI_X"}, - {0xd015, "VIC_SPR_ENA"}, - {0xd017, "VIC_SPR_EXP_Y"}, - {0xd01d, "VIC_SPR_EXP_X"}, - {0xd01c, "VIC_SPR_MCOLOR"}, - {0xd01b, "VIC_SPR_BG_PRIO"}, + {0xd000, "VIC_SPR0_X" }, + {0xd001, "VIC_SPR0_Y" }, + {0xd002, "VIC_SPR1_X" }, + {0xd003, "VIC_SPR1_Y" }, + {0xd004, "VIC_SPR2_X" }, + {0xd005, "VIC_SPR2_Y" }, + {0xd006, "VIC_SPR3_X" }, + {0xd007, "VIC_SPR3_Y" }, + {0xd008, "VIC_SPR4_X" }, + {0xd009, "VIC_SPR4_Y" }, + {0xd00a, "VIC_SPR5_X" }, + {0xd00b, "VIC_SPR5_Y" }, + {0xd00c, "VIC_SPR6_X" }, + {0xd00d, "VIC_SPR6_Y" }, + {0xd00e, "VIC_SPR7_X" }, + {0xd00f, "VIC_SPR7_Y" }, + {0xd010, "VIC_SPR_HI_X" }, + {0xd015, "VIC_SPR_ENA" }, + {0xd017, "VIC_SPR_EXP_Y" }, + {0xd01d, "VIC_SPR_EXP_X" }, + {0xd01c, "VIC_SPR_MCOLOR" }, + {0xd01b, "VIC_SPR_BG_PRIO" }, - {0xd025, "VIC_SPR_MCOLOR0"}, - {0xd026, "VIC_SPR_MCOLOR1"}, + {0xd025, "VIC_SPR_MCOLOR0" }, + {0xd026, "VIC_SPR_MCOLOR1" }, - {0xd027, "VIC_SPR0_COLOR"}, - {0xd028, "VIC_SPR1_COLOR"}, - {0xd029, "VIC_SPR2_COLOR"}, - {0xd02A, "VIC_SPR3_COLOR"}, - {0xd02B, "VIC_SPR4_COLOR"}, - {0xd02C, "VIC_SPR5_COLOR"}, - {0xd02D, "VIC_SPR6_COLOR"}, - {0xd02E, "VIC_SPR7_COLOR"}, + {0xd027, "VIC_SPR0_COLOR" }, + {0xd028, "VIC_SPR1_COLOR" }, + {0xd029, "VIC_SPR2_COLOR" }, + {0xd02A, "VIC_SPR3_COLOR" }, + {0xd02B, "VIC_SPR4_COLOR" }, + {0xd02C, "VIC_SPR5_COLOR" }, + {0xd02D, "VIC_SPR6_COLOR" }, + {0xd02E, "VIC_SPR7_COLOR" }, - {0xd011, "VIC_CTRL1"}, - {0xd016, "VIC_CTRL2"}, + {0xd011, "VIC_CTRL1" }, + {0xd016, "VIC_CTRL2" }, - {0xd012, "VIC_HLINE"}, + {0xd012, "VIC_HLINE" }, - {0xd013, "VIC_LPEN_X"}, - {0xd014, "VIC_LPEN_Y"}, + {0xd013, "VIC_LPEN_X" }, + {0xd014, "VIC_LPEN_Y" }, - {0xd018, "VIC_VIDEO_ADR"}, + {0xd018, "VIC_VIDEO_ADR" }, - {0xd019, "VIC_IRR"}, - {0xd01a, "VIC_IMR"}, + {0xd019, "VIC_IRR" }, + {0xd01a, "VIC_IMR" }, - {0xd020, "VIC_BORDERCOLOR"}, - {0xd021, "VIC_BG_COLOR0"}, - {0xd022, "VIC_BG_COLOR1"}, - {0xd023, "VIC_BG_COLOR2"}, - {0xd024, "VIC_BG_COLOR3"}, + {0xd020, "VIC_BORDERCOLOR" }, + {0xd021, "VIC_BG_COLOR0" }, + {0xd022, "VIC_BG_COLOR1" }, + {0xd023, "VIC_BG_COLOR2" }, + {0xd024, "VIC_BG_COLOR3" }, // 128 stuff - {0xd02F, "VIC_KBD_128"}, - {0xd030, "VIC_CLK_128"}, + {0xd02F, "VIC_KBD_128" }, + {0xd030, "VIC_CLK_128" }, // I/O: SID - {0xD400, "SID_S1Lo"}, - {0xD401, "SID_S1Hi"}, - {0xD402, "SID_PB1Lo"}, - {0xD403, "SID_PB1Hi"}, - {0xD404, "SID_Ctl1"}, - {0xD405, "SID_AD1"}, - {0xD406, "SID_SUR1"}, + {0xD400, "SID_S1Lo" }, + {0xD401, "SID_S1Hi" }, + {0xD402, "SID_PB1Lo" }, + {0xD403, "SID_PB1Hi" }, + {0xD404, "SID_Ctl1" }, + {0xD405, "SID_AD1" }, + {0xD406, "SID_SUR1" }, - {0xD407, "SID_S2Lo"}, - {0xD408, "SID_S2Hi"}, - {0xD409, "SID_PB2Lo"}, - {0xD40A, "SID_PB2Hi"}, - {0xD40B, "SID_Ctl2"}, - {0xD40C, "SID_AD2"}, - {0xD40D, "SID_SUR2"}, + {0xD407, "SID_S2Lo" }, + {0xD408, "SID_S2Hi" }, + {0xD409, "SID_PB2Lo" }, + {0xD40A, "SID_PB2Hi" }, + {0xD40B, "SID_Ctl2" }, + {0xD40C, "SID_AD2" }, + {0xD40D, "SID_SUR2" }, - {0xD40E, "SID_S3Lo"}, - {0xD40F, "SID_S3Hi"}, - {0xD410, "SID_PB3Lo"}, - {0xD411, "SID_PB3Hi"}, - {0xD412, "SID_Ctl3"}, - {0xD413, "SID_AD3"}, - {0xD414, "SID_SUR3"}, + {0xD40E, "SID_S3Lo" }, + {0xD40F, "SID_S3Hi" }, + {0xD410, "SID_PB3Lo" }, + {0xD411, "SID_PB3Hi" }, + {0xD412, "SID_Ctl3" }, + {0xD413, "SID_AD3" }, + {0xD414, "SID_SUR3" }, - {0xD415, "SID_FltLo"}, - {0xD416, "SID_FltHi"}, - {0xD417, "SID_FltCtl"}, - {0xD418, "SID_Amp"}, - {0xD419, "SID_ADConv1"}, - {0xD41A, "SID_ADConv2"}, - {0xD41B, "SID_Noise"}, - {0xD41C, "SID_Read3"}, + {0xD415, "SID_FltLo" }, + {0xD416, "SID_FltHi" }, + {0xD417, "SID_FltCtl" }, + {0xD418, "SID_Amp" }, + {0xD419, "SID_ADConv1" }, + {0xD41A, "SID_ADConv2" }, + {0xD41B, "SID_Noise" }, + {0xD41C, "SID_Read3" }, // I/O: VDC (128 only) - {0xd600, "VDC_INDEX"}, - {0xd601, "VDC_DATA"}, + {0xd600, "VDC_INDEX" }, + {0xd601, "VDC_DATA" }, // I/O: CIAs - {0xDC00, "CIA1_PRA"}, - {0xDC01, "CIA1_PRB"}, - {0xDC02, "CIA1_DDRA"}, - {0xDC03, "CIA1_DDRB"}, - {0xDC08, "CIA1_TOD10"}, - {0xDC09, "CIA1_TODSEC"}, - {0xDC0A, "CIA1_TODMIN"}, - {0xDC0B, "CIA1_TODHR"}, - {0xDC0D, "CIA1_ICR"}, - {0xDC0E, "CIA1_CRA"}, - {0xDC0F, "CIA1_CRB"}, + {0xDC00, "CIA1_PRA" }, + {0xDC01, "CIA1_PRB" }, + {0xDC02, "CIA1_DDRA" }, + {0xDC03, "CIA1_DDRB" }, + {0xDC08, "CIA1_TOD10" }, + {0xDC09, "CIA1_TODSEC" }, + {0xDC0A, "CIA1_TODMIN" }, + {0xDC0B, "CIA1_TODHR" }, + {0xDC0D, "CIA1_ICR" }, + {0xDC0E, "CIA1_CRA" }, + {0xDC0F, "CIA1_CRB" }, - {0xDD00, "CIA2_PRA"}, - {0xDD01, "CIA2_PRB"}, - {0xDD02, "CIA2_DDRA"}, - {0xDD03, "CIA2_DDRB"}, - {0xDD08, "CIA2_TOD10"}, - {0xDD09, "CIA2_TODSEC"}, - {0xDD0A, "CIA2_TODMIN"}, - {0xDD0B, "CIA2_TODHR"}, - {0xDD0D, "CIA2_ICR"}, - {0xDD0E, "CIA2_CRA"}, - {0xDD0F, "CIA2_CRB"}, + {0xDD00, "CIA2_PRA" }, + {0xDD01, "CIA2_PRB" }, + {0xDD02, "CIA2_DDRA" }, + {0xDD03, "CIA2_DDRB" }, + {0xDD08, "CIA2_TOD10" }, + {0xDD09, "CIA2_TODSEC" }, + {0xDD0A, "CIA2_TODMIN" }, + {0xDD0B, "CIA2_TODHR" }, + {0xDD0D, "CIA2_ICR" }, + {0xDD0E, "CIA2_CRA" }, + {0xDD0F, "CIA2_CRB" }, }; static const int SYMBOLS_MAX = sizeof (_symbols) / sizeof (_symbols[0]); struct r_bin_vsf_obj* vsf_obj = (struct r_bin_vsf_obj*) bf->o->bin_obj; diff --git a/libr/core/canal.c b/libr/core/canal.c index 1e22646e2a..afb3115674 100644 --- a/libr/core/canal.c +++ b/libr/core/canal.c @@ -543,8 +543,10 @@ R_API void r_core_anal_autoname_all_golang_fcns(RCore *core) { r_name_filter ((char *)func_name, 0); //r_cons_printf ("[x] Found symbol %s at 0x%x\n", func_name, func_addr); char *flagname = r_str_newf ("sym.go.%s", func_name); - r_flag_set (core->flags, flagname, func_addr, 1); - free (flagname); + if (flagname) { + r_flag_set (core->flags, flagname, func_addr, 1); + free (flagname); + } offset += 2 * ptr_size; num_syms++; } @@ -599,12 +601,13 @@ static bool r_anal_try_get_fcn(RCore *core, RAnalRef *ref, int fcndepth, int ref if (map->perm & R_PERM_X) { ut8 buf[64]; r_io_read_at (core->io, ref->addr, buf, sizeof (buf)); - bool looksLikeAFunction = r_anal_check_fcn (core->anal, buf, sizeof (buf), ref->addr, r_io_map_begin (map), - r_io_map_end (map)); + bool looksLikeAFunction = r_anal_check_fcn (core->anal, buf, sizeof (buf), ref->addr, r_io_map_begin (map), r_io_map_end (map)); if (looksLikeAFunction) { if (core->anal->limit) { - if (ref->addr < core->anal->limit->from || - ref->addr > core->anal->limit->to) { + if (ref->addr < core->anal->limit->from) { + return 1; + } + if (ref->addr > core->anal->limit->to) { return 1; } } diff --git a/libr/core/cmd.c b/libr/core/cmd.c index 2b91622e92..7e020120ca 100644 --- a/libr/core/cmd.c +++ b/libr/core/cmd.c @@ -5912,55 +5912,55 @@ R_API void r_core_cmd_init(RCore *core) { const char *description; RCmdCb cb; } cmds[] = { - {"!", "run system command", cmd_system }, - {"_", "print last output", cmd_last }, - {"#", "calculate hash", cmd_hash }, - {"$", "alias", cmd_alias }, - {"%", "short version of 'env' command", cmd_env }, - {"&", "tasks", cmd_tasks }, - {"(", "macro", cmd_macro }, - {"*", "pointer read/write", cmd_pointer }, - {"+", "relative seek forward", cmd_plus }, - {"-", "open cfg.editor and run script", cmd_stdin }, - {".", "interpret", cmd_interpret }, - {",", "create and manipulate tables", cmd_table }, - {"/", "search kw, pattern aes", cmd_search }, - {"=", "io pipe", cmd_rap }, - {"?", "help message", cmd_help }, - {":", "alias for =!", cmd_rap_run }, - {"0", "alias for s 0x", cmd_ox }, - {"a", "analysis", cmd_anal }, - {"b", "change block size", cmd_bsize }, - {"c", "compare memory", cmd_cmp }, - {"C", "code metadata", cmd_meta }, - {"d", "debugger operations", cmd_debug }, - {"e", "evaluate configuration variable", cmd_eval }, - {"f", "get/set flags", cmd_flag }, - {"g", "egg manipulation", cmd_egg }, - {"i", "get file info", cmd_info }, - {"k", "perform sdb query", cmd_kuery }, - {"l", "list files and directories", cmd_l }, - {"j", "join the contents of the two files", cmd_join }, - {"h", "show the top n number of line in file", cmd_head }, - {"L", "manage dynamically loaded plugins", cmd_plugins }, - {"m", "mount filesystem", cmd_mount }, - {"o", "open or map file", cmd_open }, - {"p", "print current block", cmd_print }, - {"P", "project", cmd_project }, - {"q", "exit program session", cmd_quit }, - {"Q", "alias for q!", cmd_Quit }, - {"r", "change file size", cmd_resize }, - {"s", "seek to an offset", cmd_seek }, - {"t", "type information (cparse)", cmd_type }, - {"T", "Text log utility", cmd_log }, - {"u", "uname/undo", cmd_undo }, - {"<", "pipe into RCons.readChar", cmd_pipein }, - {"V", "enter visual mode", cmd_visual }, - {"v", "enter visual panels", cmd_panels }, - {"w", "write bytes", cmd_write }, - {"x", "alias for px", cmd_hexdump }, - {"y", "yank bytes", cmd_yank }, - {"z", "zignatures", cmd_zign }, + { "!", "run system command", cmd_system }, + { "_", "print last output", cmd_last }, + { "#", "calculate hash", cmd_hash }, + { "$", "alias", cmd_alias }, + { "%", "short version of 'env' command", cmd_env }, + { "&", "tasks", cmd_tasks }, + { "(", "macro", cmd_macro }, + { "*", "pointer read/write", cmd_pointer }, + { "+", "relative seek forward", cmd_plus }, + { "-", "open cfg.editor and run script", cmd_stdin }, + { ".", "interpret", cmd_interpret }, + { ",", "create and manipulate tables", cmd_table }, + { "/", "search kw, pattern aes", cmd_search }, + { "=", "io pipe", cmd_rap }, + { "?", "help message", cmd_help }, + { ":", "alias for =!", cmd_rap_run }, + { "0", "alias for s 0x", cmd_ox }, + { "a", "analysis", cmd_anal }, + { "b", "change block size", cmd_bsize }, + { "c", "compare memory", cmd_cmp }, + { "C", "code metadata", cmd_meta }, + { "d", "debugger operations", cmd_debug }, + { "e", "evaluate configuration variable", cmd_eval }, + { "f", "get/set flags", cmd_flag }, + { "g", "egg manipulation", cmd_egg }, + { "i", "get file info", cmd_info }, + { "k", "perform sdb query", cmd_kuery }, + { "l", "list files and directories", cmd_l }, + { "j", "join the contents of the two files", cmd_join }, + { "h", "show the top n number of line in file", cmd_head }, + { "L", "manage dynamically loaded plugins", cmd_plugins }, + { "m", "mount filesystem", cmd_mount }, + { "o", "open or map file", cmd_open }, + { "p", "print current block", cmd_print }, + { "P", "project", cmd_project }, + { "q", "exit program session", cmd_quit }, + { "Q", "alias for q!", cmd_Quit }, + { "r", "change file size", cmd_resize }, + { "s", "seek to an offset", cmd_seek }, + { "t", "type information (cparse)", cmd_type }, + { "T", "Text log utility", cmd_log }, + { "u", "uname/undo", cmd_undo }, + { "<", "pipe into RCons.readChar", cmd_pipein }, + { "V", "enter visual mode", cmd_visual }, + { "v", "enter visual panels", cmd_panels }, + { "w", "write bytes", cmd_write }, + { "x", "alias for px", cmd_hexdump }, + { "y", "yank bytes", cmd_yank }, + { "z", "zignatures", cmd_zign }, }; core->rcmd = r_cmd_new (); diff --git a/libr/core/cmd_debug.c b/libr/core/cmd_debug.c index a9299217e3..8a8fc5d97e 100644 --- a/libr/core/cmd_debug.c +++ b/libr/core/cmd_debug.c @@ -4850,7 +4850,7 @@ static int cmd_debug_desc(RCore *core, const char *input) { } /* Wait to move the first arg forward past the first 'd' until after argv creation. - * "dd filename" results in {"", "filename"} instead of {"filename"}. + * "dd filename" results in { "", "filename" } instead of { "filename" }. * * This mimics passing input+1 but allows a possible empty argv[0] * to preserve argument positions. diff --git a/libr/core/cmd_hash.c b/libr/core/cmd_hash.c index abee24c73b..552d6381c9 100644 --- a/libr/core/cmd_hash.c +++ b/libr/core/cmd_hash.c @@ -433,24 +433,24 @@ static int cmd_hash(void *data, const char *input) { } static RHashHashHandlers hash_handlers[] = { - {"md4", handle_md4}, - {"md5", handle_md5}, - {"sha1", handle_sha1}, - {"sha256", handle_sha256}, - {"sha512", handle_sha512}, - {"adler32", handle_adler32}, - {"xor", handle_xor}, - {"xorpair", handle_xorpair}, - {"entropy", handle_entropy}, - {"parity", handle_parity}, - {"hamdist", handle_hamdist}, - {"pcprint", handle_pcprint}, - {"mod255", handle_mod255}, - {"xxhash", handle_xxhash}, - {"luhn", handle_luhn}, - {"ssdeep", handle_ssdeep}, + { "md4", handle_md4}, + { "md5", handle_md5}, + { "sha1", handle_sha1}, + { "sha256", handle_sha256}, + { "sha512", handle_sha512}, + { "adler32", handle_adler32}, + { "xor", handle_xor}, + { "xorpair", handle_xorpair}, + { "entropy", handle_entropy}, + { "parity", handle_parity}, + { "hamdist", handle_hamdist}, + { "pcprint", handle_pcprint}, + { "mod255", handle_mod255}, + { "xxhash", handle_xxhash}, + { "luhn", handle_luhn}, + { "ssdeep", handle_ssdeep}, - {"crc8smbus", handle_crc8_smbus}, + { "crc8smbus", handle_crc8_smbus}, #if R_HAVE_CRC8_EXTRA { /* CRC-8/CDMA2000 */ "crc8cdma2000", handle_crc8_cdma2000}, { /* CRC-8/DARC */ "crc8darc", handle_crc8_darc}, @@ -464,11 +464,11 @@ static RHashHashHandlers hash_handlers[] = { #endif /* #if R_HAVE_CRC8_EXTRA */ #if R_HAVE_CRC15_EXTRA - {"crc15can", handle_crc15_can}, + { "crc15can", handle_crc15_can}, #endif /* #if R_HAVE_CRC15_EXTRA */ - {"crc16", handle_crc16}, - {"crc16hdlc", handle_crc16_hdlc}, + { "crc16", handle_crc16}, + { "crc16hdlc", handle_crc16_hdlc}, { /* CRC-16/USB */ "crc16usb", handle_crc16_usb}, { /* CRC-16/CCITT-FALSE */ "crc16citt", handle_crc16_citt}, #if R_HAVE_CRC16_EXTRA @@ -495,12 +495,12 @@ static RHashHashHandlers hash_handlers[] = { #endif /* #if R_HAVE_CRC16_EXTRA */ #if R_HAVE_CRC24 - {"crc24", handle_crc24}, + { "crc24", handle_crc24}, #endif /* #if R_HAVE_CRC24 */ - {"crc32", handle_crc32}, - {"crc32c", handle_crc32c}, - {"crc32ecma267", handle_crc32_ecma_267}, + { "crc32", handle_crc32}, + { "crc32c", handle_crc32c}, + { "crc32ecma267", handle_crc32_ecma_267}, #if R_HAVE_CRC32_EXTRA { /* CRC-32/BZIP2 */ "crc32bzip2", handle_crc32_bzip2 }, { /* CRC-32D */ "crc32d", handle_crc32d }, @@ -521,9 +521,9 @@ static RHashHashHandlers hash_handlers[] = { { /* CRC-64/XZ */ "crc64xz", handle_crc64_xz }, { /* CRC-64/ISO */ "crc64iso", handle_crc64_iso }, #endif /* #if R_HAVE_CRC64_EXTRA */ - {"fletcher8", handle_fletcher8}, - {"fletcher16", handle_fletcher16}, - {"fletcher32", handle_fletcher32}, - {"fletcher64", handle_fletcher64}, + { "fletcher8", handle_fletcher8}, + { "fletcher16", handle_fletcher16}, + { "fletcher32", handle_fletcher32}, + { "fletcher64", handle_fletcher64}, {NULL, NULL}, }; diff --git a/libr/core/cmd_help.c b/libr/core/cmd_help.c index 9fee65994c..0e16a2c23a 100644 --- a/libr/core/cmd_help.c +++ b/libr/core/cmd_help.c @@ -2,7 +2,7 @@ #include -static const char *help_msg_at[] = { +static RCoreHelpMessage help_msg_at = { "Usage: [.][#][*] [`cmd`] [@ addr] [~grep] [|syscmd] [>[>]file]", "", "", "0", "", "alias for 's 0'", "0x", "addr", "alias for 's 0x..'", @@ -58,7 +58,7 @@ static const char *help_msg_at[] = { NULL }; -static const char *help_msg_at_at[] = { +static RCoreHelpMessage help_msg_at_at = { "@@", "", " # foreach iterator command:", "x", " @@ sym.*", "run 'x' over all flags matching 'sym.' in current flagspace", "x", " @@.file", "run 'x' over the offsets specified in the file (one offset per line)", @@ -79,7 +79,7 @@ static const char *help_msg_at_at[] = { NULL }; -static const char *help_msg_at_at_at[] = { +static RCoreHelpMessage help_msg_at_at_at = { "@@@", "", " # foreach offset+size iterator command:", "x", " @@@=", "[addr] [size] ([addr] [size] ...)", "x", " @@@C:cmd", "comments matching", @@ -217,7 +217,7 @@ static const char *help_msg_root[] = { NULL }; -static const char *help_msg_question_i[] = { +static RCoreHelpMessage help_msg_question_i = { "Usage: ?e[=bdgnpst] arg", "print/echo things", "", "?i", " ([prompt])", "inquery the user and save that text into the yank clipboard (y)", "?ie", " [msg]", "same as ?i, but prints the output, useful for oneliners", @@ -229,7 +229,7 @@ static const char *help_msg_question_i[] = { "?ip", " ([path])", "interactive hud mode to find files in given path", NULL }; -static const char *help_msg_question_e[] = { +static RCoreHelpMessage help_msg_question_e = { "Usage: ?e[=bdgnpst] arg", "print/echo things", "", "?e", "", "echo message with newline", "?e=", " 32", "progress bar at 32 percentage", @@ -245,7 +245,7 @@ static const char *help_msg_question_e[] = { NULL }; -static const char *help_msg_question[] = { +static RCoreHelpMessage help_msg_question = { "Usage: ?[?[?]] expression", "", "", "?!", " [cmd]", "run cmd if $? == 0", "?", " eip-0x804800", "show all representation result for this math expr", diff --git a/libr/core/disasm.c b/libr/core/disasm.c index 84a27eae4b..ae9970a05e 100644 --- a/libr/core/disasm.c +++ b/libr/core/disasm.c @@ -1747,7 +1747,7 @@ static void ds_show_functions_argvar(RDisasmState *ds, RAnalFunction *fcn, RAnal var->name, COLOR_ARG (ds, color_func_var_addr), constr? " { ":"", r_str_get (constr), - constr? "} ":"", + constr? " } ":"", base, sign, delta); if (ds->show_varsum == -1) { char *val = r_core_cmd_strf (ds->core, ".afvd %s", var->name); @@ -3523,15 +3523,15 @@ static void ds_print_vliw(RDisasmState *ds, bool after) { if (c > 0) { ds->vliw_count--; if (c == 1) { - r_cons_printf (" }"); + r_cons_printf ("}"); } } } else { if (v > 0) { if (c > 0) { - r_cons_printf ("}{ "); + r_cons_printf ("}{"); } else { - r_cons_printf ("{ "); + r_cons_printf ("{"); } ds->vliw_count = v; } diff --git a/libr/core/linux_heap_glibc.c b/libr/core/linux_heap_glibc.c index 6f0eedbf73..b0907770e1 100644 --- a/libr/core/linux_heap_glibc.c +++ b/libr/core/linux_heap_glibc.c @@ -370,8 +370,8 @@ static void GH(print_arena_stats)(RCore *core, GHT m_arena, MallocState *main_ar r_cons_newline (); } - PRINT_GA (" }\n"); - PRINT_GA (" binmap = {"); + PRINT_GA ("}\n"); + PRINT_GA (" binmap = { "); for (i = 0; i < BINMAPSIZE; i++) { if (i) { diff --git a/libr/core/linux_heap_jemalloc.c b/libr/core/linux_heap_jemalloc.c index 81d70acd78..b2fbacc481 100644 --- a/libr/core/linux_heap_jemalloc.c +++ b/libr/core/linux_heap_jemalloc.c @@ -237,7 +237,7 @@ static void GH(jemalloc_get_chunks)(RCore *core, const char *input) { r_io_read_at (core->io, (GHT)(size_t)node->ql_link.qre_next, (ut8 *)node, sizeof (extent_node_t)); } } - PRINT_GA ("}\n"); + PRINT_GA (" }\n"); } } free (ar); @@ -298,7 +298,7 @@ static void GH(jemalloc_print_narenas)(RCore *core, const char *input) { PRINTF_BA ("@ 0x%"PFMT64x"\n", at); } } - PRINT_GA ("}\n"); + PRINT_GA (" }\n"); break; case ' ': arena = r_num_math (core->num, input + 1); @@ -339,7 +339,7 @@ static void GH(jemalloc_print_narenas)(RCore *core, const char *input) { PRINTF_BA (" chunks_hooks = 0x%"PFMT64x"\n", OO(chunk_hooks)); PRINTF_BA (" bins = %d 0x%"PFMT64x"\n", JM_NBINS, OO(bins)); PRINTF_BA (" runs_avail = %d 0x%"PFMT64x"\n", NPSIZES, OO(runs_avail)); - PRINT_GA ("}\n"); + PRINT_GA (" }\n"); break; } free (ar); @@ -419,7 +419,7 @@ static void GH(jemalloc_get_bins)(RCore *core, const char *input) { PRINT_YA (" }\n"); } } - PRINT_GA ("}\n"); + PRINT_GA (" }\n"); break; } free (ar); diff --git a/libr/core/p/core_java.c b/libr/core/p/core_java.c index 94e7ec106e..ae0e6edb07 100644 --- a/libr/core/p/core_java.c +++ b/libr/core/p/core_java.c @@ -1,11 +1,10 @@ -/* radare - Apache - Copyright 2014-2020 - dso, pancake */ +/* radare - Apache - Copyright 2014-2022 - dso, pancake */ #include #include #include #include #include -#include #include #include "../../../shlr/java/ops.h" @@ -16,7 +15,6 @@ #undef IFDBG #define IFDBG if (DO_THE_DBG) - typedef struct found_idx_t { ut16 idx; ut64 addr; diff --git a/libr/core/rtr.c b/libr/core/rtr.c index d9fa059e48..f4b24bb6e3 100644 --- a/libr/core/rtr.c +++ b/libr/core/rtr.c @@ -731,12 +731,12 @@ R_API void r_core_rtr_add(RCore *core, const char *_input) { const char *name; int protocol; } uris[7] = { - {"tcp", RTR_PROTOCOL_TCP}, - {"udp", RTR_PROTOCOL_UDP}, - {"rap", RTR_PROTOCOL_RAP}, - {"r2p", RTR_PROTOCOL_RAP}, - {"http", RTR_PROTOCOL_HTTP}, - {"unix", RTR_PROTOCOL_UNIX}, + { "tcp", RTR_PROTOCOL_TCP}, + { "udp", RTR_PROTOCOL_UDP}, + { "rap", RTR_PROTOCOL_RAP}, + { "r2p", RTR_PROTOCOL_RAP}, + { "http", RTR_PROTOCOL_HTTP}, + { "unix", RTR_PROTOCOL_UNIX}, {NULL, 0} }; char *s = r_str_ndup (input, pikaboo - input); @@ -1326,7 +1326,7 @@ beach: #else R_API int r_core_rtr_cmds(RCore *core, const char *port) { - unsigned char buf[4097]; + ut8 buf[4097]; RSocket *ch = NULL; int i, ret; char *str; diff --git a/libr/core/vmenus.c b/libr/core/vmenus.c index 2e3d61e869..75dea4de71 100644 --- a/libr/core/vmenus.c +++ b/libr/core/vmenus.c @@ -3853,7 +3853,7 @@ static void handleHints(RCore *core) { //TODO extend for more anal hints int i = 0; char ch[64] = {0}; - const char *lines[] = {"[dh]- Define anal hint:" + const char *lines[] = { "[dh]- Define anal hint:" ," b [16,32,64] set bits hint" , NULL}; for (i = 0; lines[i]; i++) { diff --git a/libr/crypto/hash/hash.c b/libr/crypto/hash/hash.c index 5e859ff1e1..c90dbdcec8 100644 --- a/libr/crypto/hash/hash.c +++ b/libr/crypto/hash/hash.c @@ -30,9 +30,9 @@ static const struct { { "hamdist", R_HASH_HAMDIST }, { "pcprint", R_HASH_PCPRINT }, { "mod255", R_HASH_MOD255 }, - // {"base64", R_HASH_BASE64}, - // {"base91", R_HASH_BASE91}, - // {"punycode", R_HASH_PUNYCODE}, + // { "base64", R_HASH_BASE64}, + // { "base91", R_HASH_BASE91}, + // { "punycode", R_HASH_PUNYCODE}, { "luhn", R_HASH_LUHN }, { "ssdeep", R_HASH_SSDEEP }, diff --git a/libr/debug/dsession.c b/libr/debug/dsession.c index 3d1512dd9b..311527ed81 100644 --- a/libr/debug/dsession.c +++ b/libr/debug/dsession.c @@ -275,7 +275,7 @@ static void serialize_registers(Sdb *db, HtUP *registers) { ht_up_foreach (registers, serialize_register_cb, db); } -// 0x={"size":, "a":[]}}, +// 0x={ "size":, "a":[]}}, static bool serialize_memory_cb(void *db, const ut64 k, const void *v) { RDebugChangeMem *mem; RVector *vmem = (RVector *)v; @@ -311,8 +311,8 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) { r_vector_foreach (checkpoints, chkpt) { // 0x={ - // registers:{"":, ...}, - // snaps:{"size":, "a":[]} + // registers:{ "":, ...}, + // snaps:{ "size":, "a":[]} // } PJ *j = pj_new (); if (!j) { @@ -321,7 +321,7 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) { pj_o (j); // Serialize RRegArena to "registers" - // {"size":, "bytes":""} + // { "size":, "bytes":"" } pj_ka (j, "registers"); for (i = 0; i < R_REG_TYPE_LAST; i++) { RRegArena *arena = chkpt->arena[i]; @@ -338,7 +338,7 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) { pj_end (j); // Serialize RDebugSnap to "snaps" - // {"name":, "addr":, "addr_end":, "size":, + // { "name":, "addr":, "addr_end":, "size":, // "data":"", "perm":, "user":, "shared":} pj_ka (j, "snaps"); r_list_foreach (chkpt->snaps, iter, snap) { @@ -375,28 +375,28 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) { * maxcnum= * * /registers - * 0x={"size":, "a":[]} + * 0x={ "size":, "a":[]} * * /memory - * 0x={"size":, "a":[]} + * 0x={ "size":, "a":[]} * * /checkpoints * 0x={ - * registers:{"":, ...}, - * snaps:{"size":, "a":[]} + * registers:{ "":, ...}, + * snaps:{ "size":, "a":[]} * } * * RDebugChangeReg JSON: - * {"cnum":, "data":} + * { "cnum":, "data":} * * RDebugChangeMem JSON: - * {"cnum":, "data":} + * { "cnum":, "data":} * * RRegArena JSON: - * {"size":, "bytes":""} + * { "size":, "bytes":"" } * * RDebugSnap JSON: - * {"name":, "addr":, "addr_end":, "size":, + * { "name":, "addr":, "addr_end":, "size":, * "data":"", "perm":, "user":, "shared":} * * Notes: diff --git a/libr/egg/egg_cfile.c b/libr/egg/egg_cfile.c index 296a5cf69f..417640085f 100644 --- a/libr/egg/egg_cfile.c +++ b/libr/egg/egg_cfile.c @@ -18,7 +18,7 @@ struct cEnv_t { static char* r_egg_cfile_getCompiler(void) { size_t i; - const char *compilers[] = {"llvm-gcc", "clang", "gcc"}; + const char *compilers[] = { "llvm-gcc", "clang", "gcc" }; char *output = r_sys_getenv ("CC"); if (output) { @@ -223,7 +223,7 @@ static bool r_egg_cfile_parseCompiled(const char *file) { buffer = r_str_replace (buffer, "rodata", "text", false); buffer = r_str_replace (buffer, "get_pc_thunk.bx", "__getesp__", true); - const char *words[] = {".cstring", "size", "___main", "section", "__alloca", "zero", "cfi"}; + const char *words[] = { ".cstring", "size", "___main", "section", "__alloca", "zero", "cfi" }; size_t i; for (i = 0; i < 7; i++) { r_str_stripLine (buffer, words[i]); @@ -325,7 +325,7 @@ R_API char* r_egg_cfile_parser(const char *file, const char *arch, const char *o } size_t i; - const char *extArray[] = {"bin", "tmp", "s", "o"}; + const char *extArray[] = { "bin", "tmp", "s", "o" }; for (i = 0; i < 4; i++) { free (fileExt); if (!(fileExt = r_str_newf ("%s.%s", file, extArray[i]))) { diff --git a/libr/egg/emit_arm.c b/libr/egg/emit_arm.c index 722ce73026..fb75b2fc63 100644 --- a/libr/egg/emit_arm.c +++ b/libr/egg/emit_arm.c @@ -160,7 +160,7 @@ static void emit_arg(REgg *egg, int xs, int num, const char *str) { if (d) { r_egg_printf (egg, " add "R_BP ", %d\n", d); } - r_egg_printf (egg, " push {"R_BP "}\n"); + r_egg_printf (egg, " push { "R_BP " }\n"); if (d) { r_egg_printf (egg, " sub "R_BP ", %d\n", d); } diff --git a/libr/egg/emit_esil.c b/libr/egg/emit_esil.c index d23a4d85df..9bf6ed6957 100644 --- a/libr/egg/emit_esil.c +++ b/libr/egg/emit_esil.c @@ -125,7 +125,7 @@ static void emit_arg(REgg *egg, int xs, int num, const char *str) { if (d) { r_egg_printf (egg, " add "R_BP ", %d\n", d); } - r_egg_printf (egg, " push {"R_BP "}\n"); + r_egg_printf (egg, " push { "R_BP " }\n"); if (d) { r_egg_printf (egg, " sub "R_BP ", %d\n", d); } diff --git a/libr/fs/fs.c b/libr/fs/fs.c index 832d9b67c3..d44b976705 100644 --- a/libr/fs/fs.c +++ b/libr/fs/fs.c @@ -530,19 +530,19 @@ static int fs_parhook(void* disk, void* ptr, void* closure) { static RFSPartitionType partitions[] = { /* LGPL code */ - {"dos", &fs_part_dos, fs_parhook}, + { "dos", &fs_part_dos, fs_parhook}, #if USE_GRUB /* WARNING GPL code */ #if !__EMSCRIPTEN__ // wtf for some reason is not available on emscripten - {"msdos", &grub_msdos_partition_map, grub_parhook}, + { "msdos", &grub_msdos_partition_map, grub_parhook}, #endif - {"apple", &grub_apple_partition_map, grub_parhook}, - {"sun", &grub_sun_partition_map, grub_parhook}, - {"sunpc", &grub_sun_pc_partition_map, grub_parhook}, - {"amiga", &grub_amiga_partition_map, grub_parhook}, - {"bsdlabel", &grub_bsdlabel_partition_map, grub_parhook}, - {"gpt", &grub_gpt_partition_map, grub_parhook}, + { "apple", &grub_apple_partition_map, grub_parhook}, + { "sun", &grub_sun_partition_map, grub_parhook}, + { "sunpc", &grub_sun_pc_partition_map, grub_parhook}, + { "amiga", &grub_amiga_partition_map, grub_parhook}, + { "bsdlabel", &grub_bsdlabel_partition_map, grub_parhook}, + { "gpt", &grub_gpt_partition_map, grub_parhook}, #endif // XXX: In BURG all bsd partition map are in bsdlabel //{ "openbsdlabel", &grub_openbsd_partition_map }, diff --git a/libr/fs/p/fs_r2.c b/libr/fs/p/fs_r2.c index ce11135784..965e97d64f 100644 --- a/libr/fs/p/fs_r2.c +++ b/libr/fs/p/fs_r2.c @@ -29,12 +29,12 @@ static RList *__cfg(RFSRoot *root, const char *path); static RList *__flags(RFSRoot *root, const char *path); static Routes routes[] = { - {"/cfg", &__cfg, &__cfg_cat, &__cfg_write }, - {"/flags", &__flags, &__flags_cat, NULL}, - {"/version", NULL, &__version, NULL}, - {"/seek", NULL, &__seek_cat, &__seek_write }, - {"/bsize", NULL, &__bsize_cat, &__bsize_write }, - {"/", &__root}, + { "/cfg", &__cfg, &__cfg_cat, &__cfg_write }, + { "/flags", &__flags, &__flags_cat, NULL}, + { "/version", NULL, &__version, NULL}, + { "/seek", NULL, &__seek_cat, &__seek_write }, + { "/bsize", NULL, &__bsize_cat, &__bsize_write }, + { "/", &__root}, {NULL, NULL} }; diff --git a/libr/include/heap/r_jemalloc/internal/witness.h b/libr/include/heap/r_jemalloc/internal/witness.h index 30d8c7e902..77e15ea6f7 100644 --- a/libr/include/heap/r_jemalloc/internal/witness.h +++ b/libr/include/heap/r_jemalloc/internal/witness.h @@ -49,7 +49,7 @@ typedef int witness_comp_t (const witness_t *, const witness_t *); #define WITNESS_RANK_PROF_NEXT_THR_UID WITNESS_RANK_LEAF #define WITNESS_RANK_PROF_THREAD_ACTIVE_INIT WITNESS_RANK_LEAF -#define WITNESS_INITIALIZER(rank) {"initializer", rank, NULL, {NULL, NULL}} +#define WITNESS_INITIALIZER(rank) { "initializer", rank, NULL, {NULL, NULL}} #endif /* JEMALLOC_H_TYPES */ /******************************************************************************/ diff --git a/libr/io/p/io_zip.c b/libr/io/p/io_zip.c index b6814d43e1..6f958cb552 100644 --- a/libr/io/p/io_zip.c +++ b/libr/io/p/io_zip.c @@ -23,18 +23,18 @@ typedef struct r_io_zip_uri_const_t { } RIOZipConstURI; static RIOZipConstURI ZIP_URIS[] = { - {"zip://", 6}, - {"ipa://", 6}, - {"jar://", 6}, + { "zip://", 6}, + { "ipa://", 6}, + { "jar://", 6}, {NULL, 0} }; static RIOZipConstURI ZIP_ALL_URIS[] = { - {"apk://", 6}, - {"zipall://", 9}, - {"apkall://", 9}, - {"ipaall://", 9}, - {"jarall://", 9}, + { "apk://", 6}, + { "zipall://", 9}, + { "apkall://", 9}, + { "ipaall://", 9}, + { "jarall://", 9}, {NULL, 0} }; diff --git a/libr/magic/names.h b/libr/magic/names.h index afa8b744c5..44931a0c52 100644 --- a/libr/magic/names.h +++ b/libr/magic/names.h @@ -120,55 +120,55 @@ static const struct names { } names[] = { /* These must be sorted by eye for optimal hit rate */ /* Add to this list only after substantial meditation */ - {"msgid", L_PO}, - {"dnl", L_M4}, - {"import", L_JAVA}, - {"\"libhdr\"", L_BCPL}, - {"\"LIBHDR\"", L_BCPL}, - {"//", L_CC}, - {"template", L_CC}, - {"virtual", L_CC}, - {"class", L_CC}, - {"public:", L_CC}, - {"private:", L_CC}, - {"/*", L_C}, /* must precede "The", "the", etc. */ - {"#include", L_C}, - {"char", L_C}, - {"The", L_ENG}, - {"the", L_ENG}, - {"double", L_C}, - {"extern", L_C}, - {"float", L_C}, - {"struct", L_C}, - {"union", L_C}, - {"CFLAGS", L_MAKE}, - {"LDFLAGS", L_MAKE}, - {"all:", L_MAKE}, - {".PRECIOUS", L_MAKE}, - {".ascii", L_MACH}, - {".asciiz", L_MACH}, - {".byte", L_MACH}, - {".even", L_MACH}, - {".globl", L_MACH}, - {".text", L_MACH}, - {"clr", L_MACH}, - {"(input,", L_PAS}, - {"program", L_PAS}, - {"record", L_PAS}, - {"dcl", L_PLI}, - {"Received:", L_MAIL}, - {">From", L_MAIL}, - {"Return-Path:",L_MAIL}, - {"Cc:", L_MAIL}, - {"Newsgroups:", L_NEWS}, - {"Path:", L_NEWS}, - {"Organization:",L_NEWS}, - {"href=", L_HTML}, - {"HREF=", L_HTML}, - {"From", L_MAIL}, + { "Return-Path:",L_MAIL}, + { "Cc:", L_MAIL}, + { "Newsgroups:", L_NEWS}, + { "Path:", L_NEWS}, + { "Organization:",L_NEWS}, + { "href=", L_HTML}, + { "HREF=", L_HTML}, + { "= 0) goto A"}, - { "brlo", "if (var < 0) goto A"}, - { "brmi", "if (var < 0) goto A"}, - { "brpl", "if (var > 0) goto A"}, - { "brge", "if (var >= 0) goto A"}, - { "brlt", "if (var < 0) goto A"}, - { "mov", "A = B"}, - { "movw", "A+1:A = B+1:B"}, - { "ldi", "A = B"}, - { "lds", "A = *(B)"}, - { "ld", "A = *(B)"}, - { "ldd", "A = *(B)"}, - { "lpm", "r0 = z"}, - { "in", "A = B"}, - { "out", "A = B"}, - { "push", "push(A)"}, - { "pop", "A = pop()"}, - { "lsl", "A <<= 1"}, - { "lsr", "A >>= 1"}, - { "rol", "A = (A << 1) | (A >> 7)"}, - { "ror", "A = (A << 7) | (A >> 1)"}, - { "asr", "A >>= 1"}, - { "swap", "A = ((A & 0xf0) >> 4) | ((A & 0x0f) << 4)"}, - { "sec", "c = 1"}, - { "clc", "c = 0"}, - { "sen", "n = 1"}, - { "cln", "n = 0"}, - { "sez", "z = 1"}, - { "clz", "z = 0"}, - { "sei", "i = 1"}, - { "cli", "i = 0"}, - { "ses", "s = 1"}, - { "cls", "s = 0"}, - { "sev", "v = 1"}, - { "clv", "v = 0"}, - { "set", "t = 1"}, - { "clt", "t = 0"}, - { "seh", "h = 1"}, - { "clh", "h = 0"}, - { "nop", ""}, - { "halt", "_halt()"}, - { "wdr", "_watchdog_reset()"}, - { "std", "*(A) = B"}, - { "st", "*(A) = B"}, - { "sts", "*(A) = B"}, + { "add", "A += B" }, + { "adc", "A += B + carry" }, + { "adiw", "A+1:A += B" }, + { "sub", "A -= B" }, + { "subi", "A -= B" }, + { "sbc", "A -= (B + carry)" }, + { "sbci", "A -= (B + carry)" }, + { "sbiw", "A+1:A -= B" }, + { "and", "A &= B" }, + { "andi", "A &= B" }, + { "or", "A |= B" }, + { "ori", "A |= B" }, + { "eor", "A ^= B" }, + { "com", "A = 0xff - A" }, + { "neg", "A = -A" }, + { "sbr", "A |= B" }, + { "cbr", "A &= (0xff - B)" }, + { "inc", "A++" }, + { "dec", "A--" }, + { "tst", "A &= A" }, + { "clr", "A ^= A" }, + { "ser", "A = 0xff" }, + { "mul", "r1:r0 = A * B" }, + { "rjmp", "goto A" }, + { "ijmp", "goto z" }, + { "jmp", "goto A" }, + { "rcall", "goto A" }, + { "icall", "goto z" }, + { "call", "goto A" }, + { "ret", "return" }, + { "iret", "return_interrupt()" }, + { "cp", "var = A - B" }, + { "cpc", "var = A - B - carry" }, + { "cpi", "var = A - B" }, + { "breq", "if (!var) goto A" }, + { "brne", "if (var) goto A" }, + { "brsh", "if (var >= 0) goto A" }, + { "brlo", "if (var < 0) goto A" }, + { "brmi", "if (var < 0) goto A" }, + { "brpl", "if (var > 0) goto A" }, + { "brge", "if (var >= 0) goto A" }, + { "brlt", "if (var < 0) goto A" }, + { "mov", "A = B" }, + { "movw", "A+1:A = B+1:B" }, + { "ldi", "A = B" }, + { "lds", "A = *(B)" }, + { "ld", "A = *(B)" }, + { "ldd", "A = *(B)" }, + { "lpm", "r0 = z" }, + { "in", "A = B" }, + { "out", "A = B" }, + { "push", "push(A)" }, + { "pop", "A = pop()" }, + { "lsl", "A <<= 1" }, + { "lsr", "A >>= 1" }, + { "rol", "A = (A << 1) | (A >> 7)" }, + { "ror", "A = (A << 7) | (A >> 1)" }, + { "asr", "A >>= 1" }, + { "swap", "A = ((A & 0xf0) >> 4) | ((A & 0x0f) << 4)" }, + { "sec", "c = 1" }, + { "clc", "c = 0" }, + { "sen", "n = 1" }, + { "cln", "n = 0" }, + { "sez", "z = 1" }, + { "clz", "z = 0" }, + { "sei", "i = 1" }, + { "cli", "i = 0" }, + { "ses", "s = 1" }, + { "cls", "s = 0" }, + { "sev", "v = 1" }, + { "clv", "v = 0" }, + { "set", "t = 1" }, + { "clt", "t = 0" }, + { "seh", "h = 1" }, + { "clh", "h = 0" }, + { "nop", "" }, + { "halt", "_halt()" }, + { "wdr", "_watchdog_reset()" }, + { "std", "*(A) = B" }, + { "st", "*(A) = B" }, + { "sts", "*(A) = B" }, { NULL } }; diff --git a/libr/parse/p/parse_dalvik_pseudo.c b/libr/parse/p/parse_dalvik_pseudo.c index 3201f22c75..50c8af4472 100644 --- a/libr/parse/p/parse_dalvik_pseudo.c +++ b/libr/parse/p/parse_dalvik_pseudo.c @@ -15,181 +15,181 @@ static int replace(int argc, const char *argv[], char *newstr) { const char *op; const char *str; } ops[] = { - { "rsub-int", "1 = 2 - 3"}, - { "float-to-double", "1 = (double)(float) 2"}, - { "float-to-long", "1 = (long)(float) 2"}, - { "float-to-int", "1 = (int)(float) 2"}, - { "long-to-float", "1 = (float)(long) 2"}, - { "long-to-int", "1 = (int)(long) 2"}, - { "long-to-double", "1 = (double) 2"}, - { "double-to-long", "1 = (long) 2"}, - { "double-to-int", "1 = (int) 2"}, - { "int-to-double", "1 = (double) 2"}, - { "int-to-long", "1 = (long) 2"}, - { "int-to-byte", "1 = (byte) 2"}, - { "aget-byte", "1 = (byte) 2[3]"}, - { "aget-short", "1 = (short) 2[3]"}, - { "aget-object", "1 = (object) 2[3]"}, - { "sput-wide", "1 = 2"}, - { "sput-object", "1 = 2"}, - { "add-long", "1 = 2 + 3"}, - { "add-double", "1 = 2 + 3"}, - { "mul-long", "1 = 2 * 3"}, - { "const-string/jumbo", "1 = (jumbo-string) 2"}, - { "const-string", "1 = (string) 2"}, - { "const-wide", "1 = (wide) 2"}, - { "const/4", "1 = (wide) 2"}, - { "cmp-int", "1 = (2 == 3)"}, - { "cmp-long", "1 = (2 == 3)"}, - { "cmpl-double", "1 = (double)(2 == 3)"}, - { "cmpl-float", "1 = (float)(2 == 3)"}, - { "cmpl-int", "1 = (int)(2 == 3)"}, - { "cmpg-double", "1 = (2 == 3)"}, - { "cmpg-float", "1 = (2 == 3)"}, - { "or-int/2addr", "1 |= 2"}, - { "or-long", "1 |= 2"}, - { "and-long/2addr", "1 &= (long) 2"}, - { "and-int", "1 &= (int) 2"}, - { "and-byte", "1 &= (byte) 2"}, - { "sub-float/2addr", "1 -= 2"}, - { "sub-float", "1 = 2 - 3"}, - { "sub-int", "1 = (int) 2 - 3"}, - { "sub-long", "1 = (long) 2 - 3"}, - { "sub-long/2addr", "1 -= (long) 2"}, - { "sub-int/2addr", "1 -= 2"}, - { "move", "1 = 2"}, - { "move/16", "1 = 2"}, - { "move-object", "1 = (object) 2"}, - { "move-object/16", "1 = (object) 2"}, - { "move-object/from16", "1 = (object) 2"}, - { "move-wide/from16", "1 = (wide) 2"}, - { "array-length", "1 = Array.length (2)"}, - { "new-array", "1 = new array (2, 3)"}, - { "new-instance", "1 = new 2"}, - { "shr-long/2addr", "1 >>= 2"}, - { "shr-long", "1 = (long) 2 >> 3"}, - { "shr-int", "1 = (int) 2 >> 3"}, - { "ushr-int", "1 = (int) 2 >>> 3"}, - { "ushr-int/2addr", "1 >>>= 2"}, - { "ushr-long", "1 = (long) 2 >>> 3"}, - { "ushl-int/2addr", "1 <<<= 2"}, - { "shl-int/2addr", "1 <<<= 2"}, - { "shl-int", "1 = (int) 2 << 3"}, - { "shl-long", "1 = (long) 2 << 3"}, - { "move/from16", "1 = 2"}, - { "move-exception", "1 = exception"}, - { "move-result", "1 = result"}, - { "move-result-wide", "1 = (wide) result"}, - { "move-result-object", "1 = (object) result"}, - { "const-wide/high16", "1 = 2"}, - { "const/16", "1 = 2"}, - { "const-wide/16", "1 = 2"}, - { "const-wide/32", "1 = 2"}, - { "const-class", "1 = (class) 2"}, - { "const/high16", "1 = 2"}, - { "const", "1 = 2"}, - { "rem-long", "1 = (long) 2 % 3"}, - { "rem-double", "1 = (double) 2 % 3"}, - { "rem-float", "1 = (float) 2 % 3"}, - { "rem-long/2addr", "1 %= 2"}, - { "rem-float/2addr", "1 %= (float) 2"}, - { "rem-double/2addr", "1 %= (double) 2"}, - { "instance-of", "1 = insteanceof (2) == 3"}, - { "aput", "2[3] = 1"}, - { "aput-byte", "2[3] = (byte) 1"}, - { "aput-short", "2[3] = (short) 1"}, - { "aput-object", "2[3] = (object) 1"}, - { "aput-wide", "2[3] = (wide) 1"}, - { "aput-char", "2[3] = (char) 1"}, - { "aput-boolean", "2[3] = (bool) 1"}, - { "aget", "1 = 2[3]"}, - { "aget-wide", "1 = (wide) 2[3]"}, - { "aget-char", "1 = (char) 2[3]"}, - { "aget-boolean", "1 = (boolean) 2[3]"}, - { "sget", "1 = 2"}, - { "sget-char", "1 = (char) 2"}, - { "sget-short", "1 = (short) 2"}, - { "sget-boolean", "1 = (bool) 2"}, - { "sget-object", "1 = (object) 2"}, - { "iput", "2[3] = 1"}, - { "iput-object", "2[3] = (object) 1"}, - { "iput-byte", "2[3] = (byte) 1"}, - { "iput-char", "2[3] = (char) 1"}, - { "iput-boolean", "2[3] = (bool) 1"}, - { "sput-boolean", "2[3] = (bool) 1"}, - { "sput-char", "2[3] = (char) 1"}, - { "iput-int", "2[3] = (int) 1"}, - { "iget", "1 = 2[3]"}, - { "sget-byte", "1 = (byte) 2 [3]"}, - { "iget-byte", "1 = (byte) 2 [3]"}, - { "iget-char", "1 = (char) 2 [3]"}, - { "iget-short", "1 = (short) 2 [3]"}, - { "iget-wide", "1 = (wide) 2 [3]"}, - { "iget-object", "1 = (2) 3"}, - { "iget-boolean", "1 = (bool) 2 [3]"}, - { "+iget-wide-volatile", "1 = (wide-volatile) 2 [3]"}, - { "if-eq", "if (1 == 2) goto 3"}, - { "if-lt", "if (1 < 2) goto 3"}, - { "if-ne", "if (1 != 2) goto 3"}, - { "if-eqz", "if (!1) goto 2"}, - { "if-ge", "if (1 > zero) goto 2"}, - { "if-le", "if (1 <= 2) goto 3"}, - { "if-gtz", "if (1 > 0) goto 2"}, - { "filled-new-array", "1 = new Array(2)"}, - { "neg-long", "1 = -2"}, - { "neg-double", "1 = -2"}, - { "neg-float", "1 = -2"}, - { "not-int", "1 = !2"}, - { "packed-switch", "switch 2"}, - { "sparse-switch", "switch 2"}, - { "invoke-direct", "call 2 1"}, - { "invoke-direct/range", "call 2 1"}, - { "invoke-interface", "call 2 1"}, - { "invoke-static", "call 2 1"}, - { "invoke-super", "call super 2 1"}, - { "invoke-super/range", "call super 2 1"}, + { "rsub-int", "1 = 2 - 3" }, + { "float-to-double", "1 = (double)(float) 2" }, + { "float-to-long", "1 = (long)(float) 2" }, + { "float-to-int", "1 = (int)(float) 2" }, + { "long-to-float", "1 = (float)(long) 2" }, + { "long-to-int", "1 = (int)(long) 2" }, + { "long-to-double", "1 = (double) 2" }, + { "double-to-long", "1 = (long) 2" }, + { "double-to-int", "1 = (int) 2" }, + { "int-to-double", "1 = (double) 2" }, + { "int-to-long", "1 = (long) 2" }, + { "int-to-byte", "1 = (byte) 2" }, + { "aget-byte", "1 = (byte) 2[3]" }, + { "aget-short", "1 = (short) 2[3]" }, + { "aget-object", "1 = (object) 2[3]" }, + { "sput-wide", "1 = 2" }, + { "sput-object", "1 = 2" }, + { "add-long", "1 = 2 + 3" }, + { "add-double", "1 = 2 + 3" }, + { "mul-long", "1 = 2 * 3" }, + { "const-string/jumbo", "1 = (jumbo-string) 2" }, + { "const-string", "1 = (string) 2" }, + { "const-wide", "1 = (wide) 2" }, + { "const/4", "1 = (wide) 2" }, + { "cmp-int", "1 = (2 == 3)" }, + { "cmp-long", "1 = (2 == 3)" }, + { "cmpl-double", "1 = (double)(2 == 3)" }, + { "cmpl-float", "1 = (float)(2 == 3)" }, + { "cmpl-int", "1 = (int)(2 == 3)" }, + { "cmpg-double", "1 = (2 == 3)" }, + { "cmpg-float", "1 = (2 == 3)" }, + { "or-int/2addr", "1 |= 2" }, + { "or-long", "1 |= 2" }, + { "and-long/2addr", "1 &= (long) 2" }, + { "and-int", "1 &= (int) 2" }, + { "and-byte", "1 &= (byte) 2" }, + { "sub-float/2addr", "1 -= 2" }, + { "sub-float", "1 = 2 - 3" }, + { "sub-int", "1 = (int) 2 - 3" }, + { "sub-long", "1 = (long) 2 - 3" }, + { "sub-long/2addr", "1 -= (long) 2" }, + { "sub-int/2addr", "1 -= 2" }, + { "move", "1 = 2" }, + { "move/16", "1 = 2" }, + { "move-object", "1 = (object) 2" }, + { "move-object/16", "1 = (object) 2" }, + { "move-object/from16", "1 = (object) 2" }, + { "move-wide/from16", "1 = (wide) 2" }, + { "array-length", "1 = Array.length (2)" }, + { "new-array", "1 = new array (2, 3)" }, + { "new-instance", "1 = new 2" }, + { "shr-long/2addr", "1 >>= 2" }, + { "shr-long", "1 = (long) 2 >> 3" }, + { "shr-int", "1 = (int) 2 >> 3" }, + { "ushr-int", "1 = (int) 2 >>> 3" }, + { "ushr-int/2addr", "1 >>>= 2" }, + { "ushr-long", "1 = (long) 2 >>> 3" }, + { "ushl-int/2addr", "1 <<<= 2" }, + { "shl-int/2addr", "1 <<<= 2" }, + { "shl-int", "1 = (int) 2 << 3" }, + { "shl-long", "1 = (long) 2 << 3" }, + { "move/from16", "1 = 2" }, + { "move-exception", "1 = exception" }, + { "move-result", "1 = result" }, + { "move-result-wide", "1 = (wide) result" }, + { "move-result-object", "1 = (object) result" }, + { "const-wide/high16", "1 = 2" }, + { "const/16", "1 = 2" }, + { "const-wide/16", "1 = 2" }, + { "const-wide/32", "1 = 2" }, + { "const-class", "1 = (class) 2" }, + { "const/high16", "1 = 2" }, + { "const", "1 = 2" }, + { "rem-long", "1 = (long) 2 % 3" }, + { "rem-double", "1 = (double) 2 % 3" }, + { "rem-float", "1 = (float) 2 % 3" }, + { "rem-long/2addr", "1 %= 2" }, + { "rem-float/2addr", "1 %= (float) 2" }, + { "rem-double/2addr", "1 %= (double) 2" }, + { "instance-of", "1 = insteanceof (2) == 3" }, + { "aput", "2[3] = 1" }, + { "aput-byte", "2[3] = (byte) 1" }, + { "aput-short", "2[3] = (short) 1" }, + { "aput-object", "2[3] = (object) 1" }, + { "aput-wide", "2[3] = (wide) 1" }, + { "aput-char", "2[3] = (char) 1" }, + { "aput-boolean", "2[3] = (bool) 1" }, + { "aget", "1 = 2[3]" }, + { "aget-wide", "1 = (wide) 2[3]" }, + { "aget-char", "1 = (char) 2[3]" }, + { "aget-boolean", "1 = (boolean) 2[3]" }, + { "sget", "1 = 2" }, + { "sget-char", "1 = (char) 2" }, + { "sget-short", "1 = (short) 2" }, + { "sget-boolean", "1 = (bool) 2" }, + { "sget-object", "1 = (object) 2" }, + { "iput", "2[3] = 1" }, + { "iput-object", "2[3] = (object) 1" }, + { "iput-byte", "2[3] = (byte) 1" }, + { "iput-char", "2[3] = (char) 1" }, + { "iput-boolean", "2[3] = (bool) 1" }, + { "sput-boolean", "2[3] = (bool) 1" }, + { "sput-char", "2[3] = (char) 1" }, + { "iput-int", "2[3] = (int) 1" }, + { "iget", "1 = 2[3]" }, + { "sget-byte", "1 = (byte) 2 [3]" }, + { "iget-byte", "1 = (byte) 2 [3]" }, + { "iget-char", "1 = (char) 2 [3]" }, + { "iget-short", "1 = (short) 2 [3]" }, + { "iget-wide", "1 = (wide) 2 [3]" }, + { "iget-object", "1 = (2) 3" }, + { "iget-boolean", "1 = (bool) 2 [3]" }, + { "+iget-wide-volatile", "1 = (wide-volatile) 2 [3]" }, + { "if-eq", "if (1 == 2) goto 3" }, + { "if-lt", "if (1 < 2) goto 3" }, + { "if-ne", "if (1 != 2) goto 3" }, + { "if-eqz", "if (!1) goto 2" }, + { "if-ge", "if (1 > zero) goto 2" }, + { "if-le", "if (1 <= 2) goto 3" }, + { "if-gtz", "if (1 > 0) goto 2" }, + { "filled-new-array", "1 = new Array(2)" }, + { "neg-long", "1 = -2" }, + { "neg-double", "1 = -2" }, + { "neg-float", "1 = -2" }, + { "not-int", "1 = !2" }, + { "packed-switch", "switch 2" }, + { "sparse-switch", "switch 2" }, + { "invoke-direct", "call 2 1" }, + { "invoke-direct/range", "call 2 1" }, + { "invoke-interface", "call 2 1" }, + { "invoke-static", "call 2 1" }, + { "invoke-super", "call super 2 1" }, + { "invoke-super/range", "call super 2 1" }, { "invoke-polymorphic", "call polymorphic 2 1" }, - { "invoke-virtual/range", "call 2 1"}, - { "invoke-virtual", "call 2 1"}, - { "+invoke-virtual-quick", "call 2 1"}, - { "+invoke-interface/range", "call 2 1"}, - { "invoke-interface/range", "call 2 1"}, - { "div-float/2addr", "1 /= (float) 2"}, - { "div-double/2addr", "1 /= (double) 2"}, - { "div-double", "1 = (double) 2 / 3"}, - { "div-float", "1 = 2 / 3"}, - { "div-int/lit8", "1 = 2 / 3"}, - { "div-int/lit16", "1 = 2 / 3"}, - { "div-int/2addr", "1 /= 2"}, - { "div-int", "1 = (int)(2 / 3)"}, - { "goto/16", "goto 1"}, - { "goto/32", "goto 1"}, - { "or-int", "1 = (int)(2 | 3)"}, - { "xor-int", "1 = (int)(2 ^ 3)"}, - { "xor-int/2addr", "1 ^= 2"}, - { "xor-byte", "1 = (byte)(2 ^ 3)"}, - { "xor-short", "1 = (short)(2 ^ 3)"}, - { "sub-int", "1 = (int)(2 - 3)"}, - { "if-nez", "if (1) goto 2"}, - { "if-ltz", "if (1 <=) goto 2"}, - { "mul-int", "1 = (int)(2 * 3)"}, - { "mul-int/lit8", "1 = (2 * 3)"}, - { "check-cast", "if (1 instanceof 2)"}, - { "add-int", "1 = (int)(2 + 3)"}, - { "add-int/lit8", "1 = 2 + 3"}, - { "add-int/lit16", "1 = 2 + 3"}, - { "add-int/2addr", "1 += 2"}, - { "add-double", "1 = (double)(2 + 3)"}, - { "add-double/2addr", "1 += (double)2"}, - { "mul-float/2addr", "1 *= 2"}, - { "mul-float", "1 = 2 * 3"}, - { "xor-long", "1 = (long)(2 ^ 3)"}, - { "mul-double", "1 = 2 * 3"}, - { "move-wide", "1 = 2"}, - { "move-wide/16", "1 = 2"}, - { "return-wide", "return (wide) 1"}, - { "return-object", "return (object) 1"}, - // { "sget", "1 = 2[3]"}, + { "invoke-virtual/range", "call 2 1" }, + { "invoke-virtual", "call 2 1" }, + { "+invoke-virtual-quick", "call 2 1" }, + { "+invoke-interface/range", "call 2 1" }, + { "invoke-interface/range", "call 2 1" }, + { "div-float/2addr", "1 /= (float) 2" }, + { "div-double/2addr", "1 /= (double) 2" }, + { "div-double", "1 = (double) 2 / 3" }, + { "div-float", "1 = 2 / 3" }, + { "div-int/lit8", "1 = 2 / 3" }, + { "div-int/lit16", "1 = 2 / 3" }, + { "div-int/2addr", "1 /= 2" }, + { "div-int", "1 = (int)(2 / 3)" }, + { "goto/16", "goto 1" }, + { "goto/32", "goto 1" }, + { "or-int", "1 = (int)(2 | 3)" }, + { "xor-int", "1 = (int)(2 ^ 3)" }, + { "xor-int/2addr", "1 ^= 2" }, + { "xor-byte", "1 = (byte)(2 ^ 3)" }, + { "xor-short", "1 = (short)(2 ^ 3)" }, + { "sub-int", "1 = (int)(2 - 3)" }, + { "if-nez", "if (1) goto 2" }, + { "if-ltz", "if (1 <=) goto 2" }, + { "mul-int", "1 = (int)(2 * 3)" }, + { "mul-int/lit8", "1 = (2 * 3)" }, + { "check-cast", "if (1 instanceof 2)" }, + { "add-int", "1 = (int)(2 + 3)" }, + { "add-int/lit8", "1 = 2 + 3" }, + { "add-int/lit16", "1 = 2 + 3" }, + { "add-int/2addr", "1 += 2" }, + { "add-double", "1 = (double)(2 + 3)" }, + { "add-double/2addr", "1 += (double)2" }, + { "mul-float/2addr", "1 *= 2" }, + { "mul-float", "1 = 2 * 3" }, + { "xor-long", "1 = (long)(2 ^ 3)" }, + { "mul-double", "1 = 2 * 3" }, + { "move-wide", "1 = 2" }, + { "move-wide/16", "1 = 2" }, + { "return-wide", "return (wide) 1" }, + { "return-object", "return (object) 1" }, + // { "sget", "1 = 2[3]" }, { NULL } }; diff --git a/libr/parse/p/parse_m68k_pseudo.c b/libr/parse/p/parse_m68k_pseudo.c index de3d22710b..0fce0749f6 100644 --- a/libr/parse/p/parse_m68k_pseudo.c +++ b/libr/parse/p/parse_m68k_pseudo.c @@ -61,7 +61,7 @@ static int replace(int argc, const char *argv[], char *newstr) { { "lsr", "2 >>= 1", 2}, { "lsl", "2 <<= 1", 2}, { "andi", "2 &= 1", 2}, - { "nop", ""}, + { "nop", "" }, // { NULL } }; diff --git a/libr/parse/p/parse_sh_pseudo.c b/libr/parse/p/parse_sh_pseudo.c index 8e6f80e969..53dcd00fdd 100644 --- a/libr/parse/p/parse_sh_pseudo.c +++ b/libr/parse/p/parse_sh_pseudo.c @@ -16,111 +16,111 @@ static int replace(int argc, const char *argv[], char *newstr) { const char *op; const char *str; } ops[] = { - { "add", "B += A"}, - { "addc", "B += A + t"}, - { "addv", "B += A; t = int_overflow (B)"}, - { "and", "B &= A"}, - { "and.b", "B &= A"}, - { "bf", "if (!t) goto A"}, - { "bf.s", "if (!t) goto A"}, - { "bra", "goto A"}, - { "brk", "_break_exception ()"}, - { "bsr", "A ()"}, - { "bsrf", "A ()"}, - { "bt", "if (t) goto A"}, - { "bt.s", "if (t) goto A"}, - { "clrmac", "_clrmac ()"}, - { "clrs", "_clrs ()"}, - { "clrt", "_clrt ()"}, - { "cmp/eq", "t = B == A ? 1 : 0"}, - { "cmp/ge", "t = B >= A ? 1 : 0"}, - { "cmp/gt", "t = B > A ? 1 : 0"}, - { "cmp/hi", "t = (unsigned) B > (unsigned) A ? 1 : 0"}, - { "cmp/hs", "t = (unsigned) B >= (unsigned) A ? 1 : 0"}, - { "cmp/pl", "t = A > 0 ? 1 : 0"}, - { "cmp/pz", "t = A >= 0 ? 1 : 0"}, - { "cmp/str", "t = A ^ B ? 1 : 0"}, - { "div1", "B /= A"}, - { "dmuls.l", "mac = B * A"}, - { "dmulu.l", "mac = (unsigned) B * (unsigned) A"}, - { "dt", "A--; t = !A ? 1 : 0"}, - { "exts.b", "B = (int) A"}, - { "extu.b", "B = (unsigned int) A"}, - { "exts.w", "B = (int) A"}, - { "extu.w", "B = (unsigned int) A"}, - { "fabs", "A = abs (A)"}, - { "fadd", "B += A"}, - { "fcmp/eq", "t = B == A ? 1 : 0"}, - { "fcmp/gt", "t = B > A ? 1 : 0"}, - { "fcnvds", "B = A"}, - { "fdiv", "B /= A"}, - { "flds", "B = A"}, - { "fldi0", "A = 0.0f"}, - { "fldi1", "A = 1.0f"}, - { "float", "B = A"}, - { "fmac", "C += A * B"}, - { "fmov", "B = A"}, - { "fmov.s", "B = A"}, - { "fmul", "B *= A"}, - { "fneg", "A = -A"}, - { "fsqrt", "A = sqrt (A)"}, - { "fsts", "B = A"}, - { "fsub", "B -= A"}, - { "ftrc", "B = trunc (A)"}, - { "ftrv", "B *= A"}, - { "jmp", "goto A"}, - { "jsr", "A ()"}, - { "ldr", "B = A"}, - { "ldr.l", "B = A"}, - { "lds", "B = A"}, - { "lds.l", "B = A"}, - { "mov", "B = A"}, - { "mov.b", "B = A"}, - { "mov.l", "B = A"}, - { "mov.w", "B = A"}, - { "movca.l", "B = A"}, - { "movt", "A = t"}, - { "muls.w", "macl = A * B"}, - { "mulu.w", "macl = (unsigned) A * (unsigned) B"}, - { "neg", "A = -A"}, - { "negc", "A = (-A) - t"}, - { "nop", ""}, - { "not", "A = !A"}, - { "or", "B |= A"}, - { "rotcl", "t = A & 0x80000000 ? 0 : 1; A = (A << 1) | t"}, - { "rotl", "A = (A << 1) | (A >> 31)"}, - { "rotr", "A = (A << 31) | (A >> 1)"}, - { "rte", "_rte ()"}, - { "rts", "return"}, - { "sets", "s = 1"}, - { "sett", "t = 1"}, - { "shad", "B = A >= 0 ? B << A : B >> (31 - A)"}, - { "shal", "A <<= 1"}, - { "shar", "A >>= 1"}, - { "shld", "B = A >= 0 ? B << A : B >> (31 - A)"}, - { "shll", "A <<= 1"}, - { "shll2", "A <<= 2"}, - { "shll8", "A <<= 8"}, - { "shll16", "A <<= 16"}, - { "shlr", "A >>= 1"}, - { "shlr2", "A >>= 2"}, - { "shlr8", "A >>= 8"}, - { "shlr16", "A >>= 16"}, - { "sleep", "_halt ()"}, - { "stc", "B = A"}, - { "stc.l", "B = A"}, - { "sts", "B = A"}, - { "sts.l", "B = A"}, - { "sub", "B -= A"}, - { "subc", "B -= A - t"}, - { "subv", "B -= A; t = int_underflow (B)"}, - { "swap.b", "swap_byte (B, A)"}, - { "swap.w", "swap_word (B, A)"}, - { "tas.b", "test_and_set (A)"}, - { "trapa", "trap (A)"}, - { "tst", "t = B & A ? 0 : 1"}, - { "xor", "B ^= A"}, - { "xor.b", "B ^= A"}, + { "add", "B += A" }, + { "addc", "B += A + t" }, + { "addv", "B += A; t = int_overflow (B)" }, + { "and", "B &= A" }, + { "and.b", "B &= A" }, + { "bf", "if (!t) goto A" }, + { "bf.s", "if (!t) goto A" }, + { "bra", "goto A" }, + { "brk", "_break_exception ()" }, + { "bsr", "A ()" }, + { "bsrf", "A ()" }, + { "bt", "if (t) goto A" }, + { "bt.s", "if (t) goto A" }, + { "clrmac", "_clrmac ()" }, + { "clrs", "_clrs ()" }, + { "clrt", "_clrt ()" }, + { "cmp/eq", "t = B == A ? 1 : 0" }, + { "cmp/ge", "t = B >= A ? 1 : 0" }, + { "cmp/gt", "t = B > A ? 1 : 0" }, + { "cmp/hi", "t = (unsigned) B > (unsigned) A ? 1 : 0" }, + { "cmp/hs", "t = (unsigned) B >= (unsigned) A ? 1 : 0" }, + { "cmp/pl", "t = A > 0 ? 1 : 0" }, + { "cmp/pz", "t = A >= 0 ? 1 : 0" }, + { "cmp/str", "t = A ^ B ? 1 : 0" }, + { "div1", "B /= A" }, + { "dmuls.l", "mac = B * A" }, + { "dmulu.l", "mac = (unsigned) B * (unsigned) A" }, + { "dt", "A--; t = !A ? 1 : 0" }, + { "exts.b", "B = (int) A" }, + { "extu.b", "B = (unsigned int) A" }, + { "exts.w", "B = (int) A" }, + { "extu.w", "B = (unsigned int) A" }, + { "fabs", "A = abs (A)" }, + { "fadd", "B += A" }, + { "fcmp/eq", "t = B == A ? 1 : 0" }, + { "fcmp/gt", "t = B > A ? 1 : 0" }, + { "fcnvds", "B = A" }, + { "fdiv", "B /= A" }, + { "flds", "B = A" }, + { "fldi0", "A = 0.0f" }, + { "fldi1", "A = 1.0f" }, + { "float", "B = A" }, + { "fmac", "C += A * B" }, + { "fmov", "B = A" }, + { "fmov.s", "B = A" }, + { "fmul", "B *= A" }, + { "fneg", "A = -A" }, + { "fsqrt", "A = sqrt (A)" }, + { "fsts", "B = A" }, + { "fsub", "B -= A" }, + { "ftrc", "B = trunc (A)" }, + { "ftrv", "B *= A" }, + { "jmp", "goto A" }, + { "jsr", "A ()" }, + { "ldr", "B = A" }, + { "ldr.l", "B = A" }, + { "lds", "B = A" }, + { "lds.l", "B = A" }, + { "mov", "B = A" }, + { "mov.b", "B = A" }, + { "mov.l", "B = A" }, + { "mov.w", "B = A" }, + { "movca.l", "B = A" }, + { "movt", "A = t" }, + { "muls.w", "macl = A * B" }, + { "mulu.w", "macl = (unsigned) A * (unsigned) B" }, + { "neg", "A = -A" }, + { "negc", "A = (-A) - t" }, + { "nop", "" }, + { "not", "A = !A" }, + { "or", "B |= A" }, + { "rotcl", "t = A & 0x80000000 ? 0 : 1; A = (A << 1) | t" }, + { "rotl", "A = (A << 1) | (A >> 31)" }, + { "rotr", "A = (A << 31) | (A >> 1)" }, + { "rte", "_rte ()" }, + { "rts", "return" }, + { "sets", "s = 1" }, + { "sett", "t = 1" }, + { "shad", "B = A >= 0 ? B << A : B >> (31 - A)" }, + { "shal", "A <<= 1" }, + { "shar", "A >>= 1" }, + { "shld", "B = A >= 0 ? B << A : B >> (31 - A)" }, + { "shll", "A <<= 1" }, + { "shll2", "A <<= 2" }, + { "shll8", "A <<= 8" }, + { "shll16", "A <<= 16" }, + { "shlr", "A >>= 1" }, + { "shlr2", "A >>= 2" }, + { "shlr8", "A >>= 8" }, + { "shlr16", "A >>= 16" }, + { "sleep", "_halt ()" }, + { "stc", "B = A" }, + { "stc.l", "B = A" }, + { "sts", "B = A" }, + { "sts.l", "B = A" }, + { "sub", "B -= A" }, + { "subc", "B -= A - t" }, + { "subv", "B -= A; t = int_underflow (B)" }, + { "swap.b", "swap_byte (B, A)" }, + { "swap.w", "swap_word (B, A)" }, + { "tas.b", "test_and_set (A)" }, + { "trapa", "trap (A)" }, + { "tst", "t = B & A ? 0 : 1" }, + { "xor", "B ^= A" }, + { "xor.b", "B ^= A" }, { NULL } }; diff --git a/libr/parse/p/parse_tms320_pseudo.c b/libr/parse/p/parse_tms320_pseudo.c index 89da962f19..67959cc0f3 100644 --- a/libr/parse/p/parse_tms320_pseudo.c +++ b/libr/parse/p/parse_tms320_pseudo.c @@ -14,84 +14,84 @@ static int replace(int argc, const char *argv[], char *newstr) { const char *op; const char *str; } ops[] = { - {3, "add", "3 = 1 + 2"}, // add b12, b1, b9 -> b9 = b12 + b1 - {3, "addu", "3 = 1 + 2"}, - {3, "addw", "3 = 1 + 2"}, - {3, "addaw", "3 = 1 + 2"}, - {3, "addab", "3 = 1 + 2"}, - {3, "addah", "3 = 1 + 2"}, - {2, "addk", "2 += 1"}, // addk 123, b0 -> b0 += 123 - {3, "sadd", "3 = 1 + 2"}, // sadd b12, b1, b9 -> b9 = b12 + b1 - {3, "sadd2", "3 = 1 + 2"}, // sadd2 b12, b1, b9 -> b9 = b12 + b1 - {3, "sub", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1 - {3, "subu", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1 - {3, "sub2", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1 - {3, "subab", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1 - {3, "ssub", "3 = 1 - 2"}, // ssub b12, b1, b9 -> b9 = b12 - b1 - {2, "mv", "2 = 1"}, - {2, "mvk", "2 = 1"}, // mvk 1, a0 -> a0 = 1 - {2, "mvklh", "2 = (half) 1"},// mvk 1, a0 -> a0 = 1 - {3, "band", "3 = 1 & 2"}, // - {1, "zero", "1 = zero"}, - {3, "andn", "4 = 1 ~ 2"}, // - {3, "cmpgtu", "3 = 1 cmpgtu 2"}, // - {3, "cmpeq", "3 = 1 == 2"}, // - {3, "cmpge", "3 = 1 >= 2"}, // - {3, "cmplt", "3 = 1 <= 2"}, // - {3, "smpylh", "3 = 1 * 2"}, // - {3, "smpy", "3 = 1 * 2"}, // - {3, "smpyh", "3 = 1 * 2"}, // - {3, "mpyu4", "3 = 1 * 2"}, // - {3, "avg2", "3 = 1 avg 2"}, // - {3, "pack2", "3 = 1 pack 2"}, // - {3, "smpy", "3 = 1 * 2"}, // - {3, "max2", "3 = max(1, 2)"}, // - {3, "mpy", "3 = 1 * 2"}, // - {3, "mpy2", "3 = 1 * 2"}, // - {3, "mpyu", "3 = 1 * 2"}, // - {3, "mpyh", "3 = 1 * 2"}, // - {3, "mpyhl", "3 = 1 * 2"}, // - {3, "mpyhl", "3 = 1 * 2"}, // - {3, "mpylh", "3 = 1 * 2"}, // - {3, "mpysu", "3 = 1 * 2"}, // - {3, "smpyhl", "3 = 1 * 2"}, // - {3, "mpyhlu", "3 = 1 * 2"}, // - {3, "mpyhslu", "3 = 1 * 2"}, // - {3, "mpyluhs", "3 = 1 * 2"}, // - {3, "mpyhi", "3 = 1 * 2"}, // - {3, "mpyhu", "3 = 1 * 2"}, // - {3, "mpyhus", "3 = 1 * 2"}, // - {3, "mpyhsu", "3 = 1 * 2"}, // - {3, "mpyhul", "3 = 1 * 2"}, // - {3, "mpyhuls", "3 = 1 * 2"}, // - {3, "mpyhir", "3 = 1 * 2"}, // - {3, "mpyli", "3 = 1 * 2"}, // - {3, "mpylir", "3 = 1 * 2"}, // - {4, "ext", "4 = 2 ext 1 .. 3"}, // - {4, "extu", "4 = 2 ext 1 .. 3"}, // - {0, "reti", "ret"}, // reti -> ret - {2, "lddw", "2 = (word)1"}, // lddw - {2, "ldhu", "2 = (half)1"}, // ldhu - {2, "ldb", "2 = (byte)1"}, // ldb - {2, "ldbu", "2 = (byte)1"}, // ldbu - {2, "ldndw", "2 = 1"}, // ldbu - {2, "ldnw", "2 = 1"}, // ldbu - {2, "ldw", "2 = (word)1"}, // ldw - {2, "ldh", "2 = (half)1"}, // ldw - {2, "stb", "2 = (byte)1"}, // stb - {2, "stw", "2 = (word)1"}, // stw - {2, "sth", "2 = (half)1"}, // stw - {2, "stnw", "2 = (word)1"}, // stw - {2, "stdw", "2 = (half)1"}, // stw - {2, "stndw", "2 = (half)1"}, // stw - {3, "or", "3 = 2 | 1"}, - {3, "shl", "3 = (2 & Oxffffff) << 1"}, - {3, "shr", "3 = (2 & Oxffffff) << 1"}, - {3, "shlmb", "3 = << 1"}, - {4, "set", "4 = 2 .bitset 1 .. 2"}, // set a29,0x1a, 1, a19 - {4, "clr", "4 = 2 .bitclear 1 .. 2"}, // clr a29,0x1a, 1, a19 - {0, "invalid", ""}, - {0, "nop", ""}, + {3, "add", "3 = 1 + 2" }, // add b12, b1, b9 -> b9 = b12 + b1 + {3, "addu", "3 = 1 + 2" }, + {3, "addw", "3 = 1 + 2" }, + {3, "addaw", "3 = 1 + 2" }, + {3, "addab", "3 = 1 + 2" }, + {3, "addah", "3 = 1 + 2" }, + {2, "addk", "2 += 1" }, // addk 123, b0 -> b0 += 123 + {3, "sadd", "3 = 1 + 2" }, // sadd b12, b1, b9 -> b9 = b12 + b1 + {3, "sadd2", "3 = 1 + 2" }, // sadd2 b12, b1, b9 -> b9 = b12 + b1 + {3, "sub", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1 + {3, "subu", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1 + {3, "sub2", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1 + {3, "subab", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1 + {3, "ssub", "3 = 1 - 2" }, // ssub b12, b1, b9 -> b9 = b12 - b1 + {2, "mv", "2 = 1" }, + {2, "mvk", "2 = 1" }, // mvk 1, a0 -> a0 = 1 + {2, "mvklh", "2 = (half) 1" },// mvk 1, a0 -> a0 = 1 + {3, "band", "3 = 1 & 2" }, // + {1, "zero", "1 = zero" }, + {3, "andn", "4 = 1 ~ 2" }, // + {3, "cmpgtu", "3 = 1 cmpgtu 2" }, // + {3, "cmpeq", "3 = 1 == 2" }, // + {3, "cmpge", "3 = 1 >= 2" }, // + {3, "cmplt", "3 = 1 <= 2" }, // + {3, "smpylh", "3 = 1 * 2" }, // + {3, "smpy", "3 = 1 * 2" }, // + {3, "smpyh", "3 = 1 * 2" }, // + {3, "mpyu4", "3 = 1 * 2" }, // + {3, "avg2", "3 = 1 avg 2" }, // + {3, "pack2", "3 = 1 pack 2" }, // + {3, "smpy", "3 = 1 * 2" }, // + {3, "max2", "3 = max(1, 2)" }, // + {3, "mpy", "3 = 1 * 2" }, // + {3, "mpy2", "3 = 1 * 2" }, // + {3, "mpyu", "3 = 1 * 2" }, // + {3, "mpyh", "3 = 1 * 2" }, // + {3, "mpyhl", "3 = 1 * 2" }, // + {3, "mpyhl", "3 = 1 * 2" }, // + {3, "mpylh", "3 = 1 * 2" }, // + {3, "mpysu", "3 = 1 * 2" }, // + {3, "smpyhl", "3 = 1 * 2" }, // + {3, "mpyhlu", "3 = 1 * 2" }, // + {3, "mpyhslu", "3 = 1 * 2" }, // + {3, "mpyluhs", "3 = 1 * 2" }, // + {3, "mpyhi", "3 = 1 * 2" }, // + {3, "mpyhu", "3 = 1 * 2" }, // + {3, "mpyhus", "3 = 1 * 2" }, // + {3, "mpyhsu", "3 = 1 * 2" }, // + {3, "mpyhul", "3 = 1 * 2" }, // + {3, "mpyhuls", "3 = 1 * 2" }, // + {3, "mpyhir", "3 = 1 * 2" }, // + {3, "mpyli", "3 = 1 * 2" }, // + {3, "mpylir", "3 = 1 * 2" }, // + {4, "ext", "4 = 2 ext 1 .. 3" }, // + {4, "extu", "4 = 2 ext 1 .. 3" }, // + {0, "reti", "ret" }, // reti -> ret + {2, "lddw", "2 = (word)1" }, // lddw + {2, "ldhu", "2 = (half)1" }, // ldhu + {2, "ldb", "2 = (byte)1" }, // ldb + {2, "ldbu", "2 = (byte)1" }, // ldbu + {2, "ldndw", "2 = 1" }, // ldbu + {2, "ldnw", "2 = 1" }, // ldbu + {2, "ldw", "2 = (word)1" }, // ldw + {2, "ldh", "2 = (half)1" }, // ldw + {2, "stb", "2 = (byte)1" }, // stb + {2, "stw", "2 = (word)1" }, // stw + {2, "sth", "2 = (half)1" }, // stw + {2, "stnw", "2 = (word)1" }, // stw + {2, "stdw", "2 = (half)1" }, // stw + {2, "stndw", "2 = (half)1" }, // stw + {3, "or", "3 = 2 | 1" }, + {3, "shl", "3 = (2 & Oxffffff) << 1" }, + {3, "shr", "3 = (2 & Oxffffff) << 1" }, + {3, "shlmb", "3 = << 1" }, + {4, "set", "4 = 2 .bitset 1 .. 2" }, // set a29,0x1a, 1, a19 + {4, "clr", "4 = 2 .bitclear 1 .. 2" }, // clr a29,0x1a, 1, a19 + {0, "invalid", "" }, + {0, "nop", "" }, {0, NULL} }; if (!newstr) { diff --git a/libr/parse/p/parse_v850_pseudo.c b/libr/parse/p/parse_v850_pseudo.c index 94dec89e4a..9bc566d9f0 100644 --- a/libr/parse/p/parse_v850_pseudo.c +++ b/libr/parse/p/parse_v850_pseudo.c @@ -14,55 +14,55 @@ static int replace(int argc, const char *argv[], char *newstr) { const char *op; const char *str; } ops[] = { - {0, "ei", "enable-interrupts"}, - {0, "di", "disable-interrupts"}, - {0, "reti", "ret"}, - {2, "ld.hu", "2 = 1"}, - {1, "zxb", "1 = O"}, - {1, "zxh", "1 = O"}, - {1, "zxw", "1 = O"}, - {2, "set1", "2 |= (I << 2)"}, - {2, "clr1", "2 &= ~(I << 2)"}, - {2, "sld.w", "2 = (word) 1"}, - {2, "sld.h", "2 = (half) 1"}, - {2, "sld.b", "2 = (byte) 1"}, - {2, "ld.bu", "2 = 1"}, - {2, "ld.w", "2 = (word) 1"}, - {2, "ld.h", "2 = (half) 1"}, - {2, "ld.b", "2 = (byte) 1"}, - {2, "st.h", "2 = (half) 1"}, - {2, "st.w", "2 = (word) 1"}, - {2, "st.b", "2 = (byte) 1"}, - {2, "sst.w", "2 = (word) 1"}, - {2, "sst.h", "2 = (half) 1"}, - {2, "sst.b", "2 = (byte) 1"}, - {2, "stsr", "2 = 1"}, - {2, "ldsr", "2 = 1"}, - {2, "and", "3 = 2 & 1"}, - {3, "andi", "3 = 2 & 1"}, - {2, "add", "2 += 1"}, - {3, "addi", "3 = 2 + 1"}, - {2, "sub", "2 -= 1"}, - {2, "divh", "2 /= 1"}, - {3, "divh", "3 = 2 / 1"}, - {2, "mulh", "2 *= 1"}, - {3, "mul", "3 = 2 * 1"}, - {3, "mulf.s", "3 = 2 * 1"}, - {2, "shl", "2 <<= 1"}, - {2, "shr", "2 >>= 1"}, - {2, "xor", "2 ^= 1"}, - {3, "xori", "3 = 1 ^ 2"}, - {2, "tst", "2 == 1"}, - {2, "tst1", "2 == 1"}, - {1, "jr", "goto 1"}, - {1, "jmp", "goto 1"}, - {2, "cmp", "2 == 1"}, - {4, "cmov", "4 == 1 ? 2 : 3"}, - {2, "mov", "2 = 1"}, - {3, "movhi", "3 = (1 << XX) + 2"}, - {3, "movea", "3 = 1 & 2"}, - {3, "ori", "3 = 1 | 2"}, - {2, "jarl", "call 1 # 2"}, + {0, "ei", "enable-interrupts" }, + {0, "di", "disable-interrupts" }, + {0, "reti", "ret" }, + {2, "ld.hu", "2 = 1" }, + {1, "zxb", "1 = O" }, + {1, "zxh", "1 = O" }, + {1, "zxw", "1 = O" }, + {2, "set1", "2 |= (I << 2)" }, + {2, "clr1", "2 &= ~(I << 2)" }, + {2, "sld.w", "2 = (word) 1" }, + {2, "sld.h", "2 = (half) 1" }, + {2, "sld.b", "2 = (byte) 1" }, + {2, "ld.bu", "2 = 1" }, + {2, "ld.w", "2 = (word) 1" }, + {2, "ld.h", "2 = (half) 1" }, + {2, "ld.b", "2 = (byte) 1" }, + {2, "st.h", "2 = (half) 1" }, + {2, "st.w", "2 = (word) 1" }, + {2, "st.b", "2 = (byte) 1" }, + {2, "sst.w", "2 = (word) 1" }, + {2, "sst.h", "2 = (half) 1" }, + {2, "sst.b", "2 = (byte) 1" }, + {2, "stsr", "2 = 1" }, + {2, "ldsr", "2 = 1" }, + {2, "and", "3 = 2 & 1" }, + {3, "andi", "3 = 2 & 1" }, + {2, "add", "2 += 1" }, + {3, "addi", "3 = 2 + 1" }, + {2, "sub", "2 -= 1" }, + {2, "divh", "2 /= 1" }, + {3, "divh", "3 = 2 / 1" }, + {2, "mulh", "2 *= 1" }, + {3, "mul", "3 = 2 * 1" }, + {3, "mulf.s", "3 = 2 * 1" }, + {2, "shl", "2 <<= 1" }, + {2, "shr", "2 >>= 1" }, + {2, "xor", "2 ^= 1" }, + {3, "xori", "3 = 1 ^ 2" }, + {2, "tst", "2 == 1" }, + {2, "tst1", "2 == 1" }, + {1, "jr", "goto 1" }, + {1, "jmp", "goto 1" }, + {2, "cmp", "2 == 1" }, + {4, "cmov", "4 == 1 ? 2 : 3" }, + {2, "mov", "2 = 1" }, + {3, "movhi", "3 = (1 << XX) + 2" }, + {3, "movea", "3 = 1 & 2" }, + {3, "ori", "3 = 1 | 2" }, + {2, "jarl", "call 1 # 2" }, {0, NULL} }; if (!newstr) { diff --git a/libr/parse/p/parse_z80_pseudo.c b/libr/parse/p/parse_z80_pseudo.c index ca7d424cbb..d2079b9f31 100644 --- a/libr/parse/p/parse_z80_pseudo.c +++ b/libr/parse/p/parse_z80_pseudo.c @@ -11,29 +11,29 @@ static int replace(int argc, const char *argv[], char *newstr) { const char *op; const char *str; } ops[] = { - { "adc", "1 = 1 + 2"}, - { "add", "1 = 1 + 2"}, - { "and", "1 = 1 & 2"}, - { "cpl", "1 = ~1"}, - { "ex", "swap(1, 2)"}, - { "in", "1 = [2]"}, - { "jp", "goto [1]"}, - { "jp", "goto 1"}, - { "jr", "goto +1"}, - { "ld", "1 = 2"}, - { "ldd", "1 = 2--"}, - { "neg", "1 = -1"}, - { "nop", ""}, - { "or", "1 = 1 | 2"}, - { "pop", "pop 1"}, - { "push", "push 1"}, - { "rr", "1 = 1 << 2"}, - { "sbc", "1 = 1 - 2"}, - { "sla", "1 = 1 << 2"}, - { "sra", "1 = 1 >> 2"}, - { "srl", "1 = 1 >> 2"}, - { "sub", "1 = 1 - 2"}, - { "xor", "1 = 1 ^ 2"}, + { "adc", "1 = 1 + 2" }, + { "add", "1 = 1 + 2" }, + { "and", "1 = 1 & 2" }, + { "cpl", "1 = ~1" }, + { "ex", "swap(1, 2)" }, + { "in", "1 = [2]" }, + { "jp", "goto [1]" }, + { "jp", "goto 1" }, + { "jr", "goto +1" }, + { "ld", "1 = 2" }, + { "ldd", "1 = 2--" }, + { "neg", "1 = -1" }, + { "nop", "" }, + { "or", "1 = 1 | 2" }, + { "pop", "pop 1" }, + { "push", "push 1" }, + { "rr", "1 = 1 << 2" }, + { "sbc", "1 = 1 - 2" }, + { "sla", "1 = 1 << 2" }, + { "sra", "1 = 1 >> 2" }, + { "srl", "1 = 1 >> 2" }, + { "sub", "1 = 1 - 2" }, + { "xor", "1 = 1 ^ 2" }, { NULL } }; diff --git a/libr/syscall/d/par.sh b/libr/syscall/d/par.sh old mode 100755 new mode 100644 index 886d0364a8..f709277439 --- a/libr/syscall/d/par.sh +++ b/libr/syscall/d/par.sh @@ -1,2 +1,2 @@ #!/bin/sh -grep '{ "'|tr '{",}' ' ' |sed -e 's,NULL,,g' | awk '{ print $1"="$2","$3","$4","$5}' +grep '{ "'|tr '{ ",}' ' ' |sed -e 's,NULL,,g' | awk '{ print $1"="$2","$3","$4","$5}' diff --git a/libr/syscall/ioports.c b/libr/syscall/ioports.c index ece9c99e6f..935feec217 100644 --- a/libr/syscall/ioports.c +++ b/libr/syscall/ioports.c @@ -11,67 +11,67 @@ RSyscallPort sysport_x86[] = { RSyscallPort sysport_avr[] = { { 0x3f, "SREG: flags" }, { 0x3e, "SPH: Stack higher bits SP8-SP10" }, - { 0x3d, "SPL: Stack lower bits SP0-SP7"}, - { 0x3c, "OCR0: Timer/Counter0 Output Compare Register."}, + { 0x3d, "SPL: Stack lower bits SP0-SP7" }, + { 0x3c, "OCR0: Timer/Counter0 Output Compare Register." }, { 0x3b, "GICR: General Interrupt Control Register" }, - { 0x3a, "GIFR: General Interrupt Flag Register"}, - { 0x39, "TIMSK: Timer/Counter Interrupt Mask"}, - { 0x38, "TIFR: Timer/Counter Interrupt Flag Register"}, - { 0x37, "SPMCR: Store Program Memory Control Register"}, - { 0x36, "TWCR: I2C (Two-wire) Control Register"}, - { 0x35, "MCUCR: MCU (Power Management) Control Register"}, + { 0x3a, "GIFR: General Interrupt Flag Register" }, + { 0x39, "TIMSK: Timer/Counter Interrupt Mask" }, + { 0x38, "TIFR: Timer/Counter Interrupt Flag Register" }, + { 0x37, "SPMCR: Store Program Memory Control Register" }, + { 0x36, "TWCR: I2C (Two-wire) Control Register" }, + { 0x35, "MCUCR: MCU (Power Management) Control Register" }, { 0x34, "MCUCSR: MCU Control and Status Register. Watchdog, Brown-out, Power-on..." }, - { 0x33, "TCCR0: Timer/Counter Control Register 0"}, - { 0x32, "TCNT0: Timer/Counter Register 0 (8 bits)"}, - { 0x31, "OSCCAL: (Internal) Oscillator Calibration Register"}, - { 0x30, "SFIOR: Special Function IO Register"}, - { 0x2f, "TCCR1A: Timer/Counter Control Register 1A (16 bits). Used for (fast) PWM."}, - { 0x2e, "TCCR1B: Timer/Counter Control Register 1B (16 bits). PWM mode select."}, - { 0x2d, "TCNT1H: Timer/Counter1 Register High byte."}, - { 0x2c, "TCNT1L: Timer/Counter1 Register Low byte."}, - { 0x2b, "OCR1AH: Timer/Counter1 Output Compare Register A High byte."}, - { 0x2a, "OCR1AL: Timer/Counter1 Output Compare Register A Low byte."}, - { 0x29, "OCR1BH: Timer/Counter1 Output Compare Register B High byte."}, - { 0x28, "OCR1BL: Timer/Counter1 Output Compare Register B Low byte."}, - { 0x27, "ICR1H: Timer/Counter1 Input Capture Register High byte."}, - { 0x26, "ICR1L: Timer/Counter1 Input Capture Register Low byte."}, - { 0x25, "TCCR2: Timer/Counter2 Control Register (8 bits)."}, - { 0x24, "TCNT2: Timer/Counter2 (8 bits)."}, - { 0x23, "OCR2: Timer/Counter2 Output Compare Register."}, - { 0x22, "ASSR: Asynchronous Operation of the Timer/Counter."}, - { 0x21, "WDTCR: Watchdog Timer Control Register."}, - { 0x20, "UBRRH, UCSRC: USART Baud Rate Registers, High byte and Control. A.k.a setting serial port speed."}, - { 0x1f, "EEARH: EEPROM Address Register High byte."}, - { 0x1e, "EEARL: EEPROM Address Register Low byte."}, - { 0x1d, "EEDR: EEPROM Data Register."}, - { 0x1c, "EECR: EEPROM Control Register."}, - { 0x1b, "PORTA: Output pins/pullups address for port A."}, - { 0x1a, "DDRA: Data Direction Register for Port A."}, - { 0x19, "PINA: Input Pins Address for Port A."}, - { 0x18, "PORTB: Output pins/pullups address for port B."}, - { 0x17, "DDRB: Data Direction Register for Port B."}, - { 0x16, "PINB: Input Pins Address for Port B."}, - { 0x15, "PORTC: Output pins/pullups address for port C."}, - { 0x14, "DDRC: Data Direction Register for Port C."}, - { 0x13, "PINC: Input Pins Address for Port C."}, - { 0x12, "PORTD: Output pins/pullups address for port D."}, - { 0x11, "DDRD: Data Direction Register for Port D."}, - { 0x10, "PIND: Input Pins Address for Port D."}, - { 0x0f, "SPDR: SPI Data Register."}, - { 0x0e, "SPSR: SPI Status Register."}, - { 0x0d, "SPCR: SPI Control Register."}, - { 0x0c, "UDR: USART I/O Data Register."}, - { 0x0b, "UCSRA: USART Control and Status Register A."}, - { 0x0a, "UCSRB: USART Control and Status Register B."}, - { 0x09, "UBRRL: USART Baud Rate Registers Low byte. A.k.a setting serial port speed."}, - { 0x08, "ACSR: Analog Comparator Control and Status Register."}, - { 0x07, "ADMUX: ADC Multiplexer Selection Register."}, - { 0x06, "ADCSRA: ADC Control and Status Register A."}, - { 0x05, "ADCH: ADC Data Register High byte."}, - { 0x04, "ADCL: ADC Data Register Low byte."}, - { 0x03, "TWDR: I2C (Two-wire) Serial Interface Data Register."}, - { 0x02, "TWAR: I2C (Two-wire) Serial Interface (Slave) Address Register."}, - { 0x01, "TWSR: I2C (Two-wire) Serial Interface Status Register."}, - { 0x00, "TWBR: I2C (Two-wire) Serial Interface Bit Rate Register."}, + { 0x33, "TCCR0: Timer/Counter Control Register 0" }, + { 0x32, "TCNT0: Timer/Counter Register 0 (8 bits)" }, + { 0x31, "OSCCAL: (Internal) Oscillator Calibration Register" }, + { 0x30, "SFIOR: Special Function IO Register" }, + { 0x2f, "TCCR1A: Timer/Counter Control Register 1A (16 bits). Used for (fast) PWM." }, + { 0x2e, "TCCR1B: Timer/Counter Control Register 1B (16 bits). PWM mode select." }, + { 0x2d, "TCNT1H: Timer/Counter1 Register High byte." }, + { 0x2c, "TCNT1L: Timer/Counter1 Register Low byte." }, + { 0x2b, "OCR1AH: Timer/Counter1 Output Compare Register A High byte." }, + { 0x2a, "OCR1AL: Timer/Counter1 Output Compare Register A Low byte." }, + { 0x29, "OCR1BH: Timer/Counter1 Output Compare Register B High byte." }, + { 0x28, "OCR1BL: Timer/Counter1 Output Compare Register B Low byte." }, + { 0x27, "ICR1H: Timer/Counter1 Input Capture Register High byte." }, + { 0x26, "ICR1L: Timer/Counter1 Input Capture Register Low byte." }, + { 0x25, "TCCR2: Timer/Counter2 Control Register (8 bits)." }, + { 0x24, "TCNT2: Timer/Counter2 (8 bits)." }, + { 0x23, "OCR2: Timer/Counter2 Output Compare Register." }, + { 0x22, "ASSR: Asynchronous Operation of the Timer/Counter." }, + { 0x21, "WDTCR: Watchdog Timer Control Register." }, + { 0x20, "UBRRH, UCSRC: USART Baud Rate Registers, High byte and Control. A.k.a setting serial port speed." }, + { 0x1f, "EEARH: EEPROM Address Register High byte." }, + { 0x1e, "EEARL: EEPROM Address Register Low byte." }, + { 0x1d, "EEDR: EEPROM Data Register." }, + { 0x1c, "EECR: EEPROM Control Register." }, + { 0x1b, "PORTA: Output pins/pullups address for port A." }, + { 0x1a, "DDRA: Data Direction Register for Port A." }, + { 0x19, "PINA: Input Pins Address for Port A." }, + { 0x18, "PORTB: Output pins/pullups address for port B." }, + { 0x17, "DDRB: Data Direction Register for Port B." }, + { 0x16, "PINB: Input Pins Address for Port B." }, + { 0x15, "PORTC: Output pins/pullups address for port C." }, + { 0x14, "DDRC: Data Direction Register for Port C." }, + { 0x13, "PINC: Input Pins Address for Port C." }, + { 0x12, "PORTD: Output pins/pullups address for port D." }, + { 0x11, "DDRD: Data Direction Register for Port D." }, + { 0x10, "PIND: Input Pins Address for Port D." }, + { 0x0f, "SPDR: SPI Data Register." }, + { 0x0e, "SPSR: SPI Status Register." }, + { 0x0d, "SPCR: SPI Control Register." }, + { 0x0c, "UDR: USART I/O Data Register." }, + { 0x0b, "UCSRA: USART Control and Status Register A." }, + { 0x0a, "UCSRB: USART Control and Status Register B." }, + { 0x09, "UBRRL: USART Baud Rate Registers Low byte. A.k.a setting serial port speed." }, + { 0x08, "ACSR: Analog Comparator Control and Status Register." }, + { 0x07, "ADMUX: ADC Multiplexer Selection Register." }, + { 0x06, "ADCSRA: ADC Control and Status Register A." }, + { 0x05, "ADCH: ADC Data Register High byte." }, + { 0x04, "ADCL: ADC Data Register Low byte." }, + { 0x03, "TWDR: I2C (Two-wire) Serial Interface Data Register." }, + { 0x02, "TWAR: I2C (Two-wire) Serial Interface (Slave) Address Register." }, + { 0x01, "TWSR: I2C (Two-wire) Serial Interface Status Register." }, + { 0x00, "TWBR: I2C (Two-wire) Serial Interface Bit Rate Register." }, { 0, NULL } }; diff --git a/libr/util/asn1_oids.h b/libr/util/asn1_oids.h index 80245202c2..afcde6bf28 100644 --- a/libr/util/asn1_oids.h +++ b/libr/util/asn1_oids.h @@ -5,2358 +5,2358 @@ extern "C" { #endif -struct r_oid_list_t { - const char* oid; - const char* name; +const struct r_oid_list_t { + const char* const oid; + const char* const name; } X509OIDList [] = { - {"0.2.262.1.10", "Telesec"}, - {"0.2.262.1.10.0", "extension"}, - {"0.2.262.1.10.1", "mechanism"}, - {"0.2.262.1.10.1.0", "authentication"}, - {"0.2.262.1.10.1.0.1", "passwordAuthentication"}, - {"0.2.262.1.10.1.0.2", "protectedPasswordAuthentication"}, - {"0.2.262.1.10.1.0.3", "oneWayX509Authentication"}, - {"0.2.262.1.10.1.0.4", "twoWayX509Authentication"}, - {"0.2.262.1.10.1.0.5", "threeWayX509Authentication"}, - {"0.2.262.1.10.1.0.6", "oneWayISO9798Authentication"}, - {"0.2.262.1.10.1.0.7", "twoWayISO9798Authentication"}, - {"0.2.262.1.10.1.0.8", "telekomAuthentication"}, - {"0.2.262.1.10.1.1", "signature"}, - {"0.2.262.1.10.1.1.1", "md4WithRSAAndISO9697"}, - {"0.2.262.1.10.1.1.2", "md4WithRSAAndTelesecSignatureStandard"}, - {"0.2.262.1.10.1.1.3", "md5WithRSAAndISO9697"}, - {"0.2.262.1.10.1.1.4", "md5WithRSAAndTelesecSignatureStandard"}, - {"0.2.262.1.10.1.1.5", "ripemd160WithRSAAndTelekomSignatureStandard"}, - {"0.2.262.1.10.1.1.9", "hbciRsaSignature"}, - {"0.2.262.1.10.1.2", "encryption"}, - {"0.2.262.1.10.1.2.0", "none"}, - {"0.2.262.1.10.1.2.1", "rsaTelesec"}, - {"0.2.262.1.10.1.2.2", "des"}, - {"0.2.262.1.10.1.2.2.1", "desECB"}, - {"0.2.262.1.10.1.2.2.2", "desCBC"}, - {"0.2.262.1.10.1.2.2.3", "desOFB"}, - {"0.2.262.1.10.1.2.2.4", "desCFB8"}, - {"0.2.262.1.10.1.2.2.5", "desCFB64"}, - {"0.2.262.1.10.1.2.3", "des3"}, - {"0.2.262.1.10.1.2.3.1", "des3ECB"}, - {"0.2.262.1.10.1.2.3.2", "des3CBC"}, - {"0.2.262.1.10.1.2.3.3", "des3OFB"}, - {"0.2.262.1.10.1.2.3.4", "des3CFB8"}, - {"0.2.262.1.10.1.2.3.5", "des3CFB64"}, - {"0.2.262.1.10.1.2.4", "magenta"}, - {"0.2.262.1.10.1.2.5", "idea"}, - {"0.2.262.1.10.1.2.5.1", "ideaECB"}, - {"0.2.262.1.10.1.2.5.2", "ideaCBC"}, - {"0.2.262.1.10.1.2.5.3", "ideaOFB"}, - {"0.2.262.1.10.1.2.5.4", "ideaCFB8"}, - {"0.2.262.1.10.1.2.5.5", "ideaCFB64"}, - {"0.2.262.1.10.1.3", "oneWayFunction"}, - {"0.2.262.1.10.1.3.1", "md4"}, - {"0.2.262.1.10.1.3.2", "md5"}, - {"0.2.262.1.10.1.3.3", "sqModNX509"}, - {"0.2.262.1.10.1.3.4", "sqModNISO"}, - {"0.2.262.1.10.1.3.5", "ripemd128"}, - {"0.2.262.1.10.1.3.6", "hashUsingBlockCipher"}, - {"0.2.262.1.10.1.3.7", "mac"}, - {"0.2.262.1.10.1.3.8", "ripemd160"}, - {"0.2.262.1.10.1.4", "fecFunction"}, - {"0.2.262.1.10.1.4.1", "reedSolomon"}, - {"0.2.262.1.10.10", "notification"}, - {"0.2.262.1.10.11", "snmp-mibs"}, - {"0.2.262.1.10.11.1", "securityApplication"}, - {"0.2.262.1.10.12", "certAndCrlExtensionDefinitions"}, - {"0.2.262.1.10.12.0", "liabilityLimitationFlag"}, - {"0.2.262.1.10.12.1", "telesecCertIdExt"}, - {"0.2.262.1.10.12.2", "Telesec.policyIdentifier"}, - {"0.2.262.1.10.12.3", "telesecPolicyQualifierID"}, - {"0.2.262.1.10.12.4", "telesecCRLFilteredExt"}, - {"0.2.262.1.10.12.5", "telesecCRLFilterExt"}, - {"0.2.262.1.10.12.6", "telesecNamingAuthorityExt"}, - {"0.2.262.1.10.2", "module"}, - {"0.2.262.1.10.2.0", "algorithms"}, - {"0.2.262.1.10.2.1", "attributeTypes"}, - {"0.2.262.1.10.2.10", "electronicOrder"}, - {"0.2.262.1.10.2.11", "telesecTtpAsymmetricApplication"}, - {"0.2.262.1.10.2.12", "telesecTtpBasisApplication"}, - {"0.2.262.1.10.2.13", "telesecTtpMessages"}, - {"0.2.262.1.10.2.14", "telesecTtpTimeStampApplication"}, - {"0.2.262.1.10.2.2", "certificateTypes"}, - {"0.2.262.1.10.2.3", "messageTypes"}, - {"0.2.262.1.10.2.4", "plProtocol"}, - {"0.2.262.1.10.2.5", "smeAndComponentsOfSme"}, - {"0.2.262.1.10.2.6", "fec"}, - {"0.2.262.1.10.2.7", "usefulDefinitions"}, - {"0.2.262.1.10.2.8", "stefiles"}, - {"0.2.262.1.10.2.9", "sadmib"}, - {"0.2.262.1.10.3", "objectClass"}, - {"0.2.262.1.10.3.0", "telesecOtherName"}, - {"0.2.262.1.10.3.1", "directory"}, - {"0.2.262.1.10.3.2", "directoryType"}, - {"0.2.262.1.10.3.3", "directoryGroup"}, - {"0.2.262.1.10.3.4", "directoryUser"}, - {"0.2.262.1.10.3.5", "symmetricKeyEntry"}, - {"0.2.262.1.10.4", "package"}, - {"0.2.262.1.10.5", "parameter"}, - {"0.2.262.1.10.6", "nameBinding"}, - {"0.2.262.1.10.7", "attribute"}, - {"0.2.262.1.10.7.0", "applicationGroupIdentifier"}, - {"0.2.262.1.10.7.1", "certificateType"}, - {"0.2.262.1.10.7.10", "subject"}, - {"0.2.262.1.10.7.11", "timeOfRevocation"}, - {"0.2.262.1.10.7.12", "userGroupReference"}, - {"0.2.262.1.10.7.13", "validity"}, - {"0.2.262.1.10.7.14", "zert93"}, - {"0.2.262.1.10.7.15", "securityMessEnv"}, - {"0.2.262.1.10.7.16", "anonymizedPublicKeyDirectory"}, - {"0.2.262.1.10.7.17", "telesecGivenName"}, - {"0.2.262.1.10.7.18", "nameAdditions"}, - {"0.2.262.1.10.7.19", "telesecPostalCode"}, - {"0.2.262.1.10.7.2", "telesecCertificate"}, - {"0.2.262.1.10.7.20", "nameDistinguisher"}, - {"0.2.262.1.10.7.21", "telesecCertificateList"}, - {"0.2.262.1.10.7.22", "teletrustCertificateList"}, - {"0.2.262.1.10.7.23", "x509CertificateList"}, - {"0.2.262.1.10.7.24", "timeOfIssue"}, - {"0.2.262.1.10.7.25", "physicalCardNumber"}, - {"0.2.262.1.10.7.26", "fileType"}, - {"0.2.262.1.10.7.27", "ctlFileIsArchive"}, - {"0.2.262.1.10.7.28", "emailAddress"}, - {"0.2.262.1.10.7.29", "certificateTemplateList"}, - {"0.2.262.1.10.7.3", "certificateNumber"}, - {"0.2.262.1.10.7.30", "directoryName"}, - {"0.2.262.1.10.7.31", "directoryTypeName"}, - {"0.2.262.1.10.7.32", "directoryGroupName"}, - {"0.2.262.1.10.7.33", "directoryUserName"}, - {"0.2.262.1.10.7.34", "revocationFlag"}, - {"0.2.262.1.10.7.35", "symmetricKeyEntryName"}, - {"0.2.262.1.10.7.36", "glNumber"}, - {"0.2.262.1.10.7.37", "goNumber"}, - {"0.2.262.1.10.7.38", "gKeyData"}, - {"0.2.262.1.10.7.39", "zKeyData"}, - {"0.2.262.1.10.7.4", "certificateRevocationList"}, - {"0.2.262.1.10.7.40", "ktKeyData"}, - {"0.2.262.1.10.7.41", "ktKeyNumber"}, - {"0.2.262.1.10.7.5", "creationDate"}, - {"0.2.262.1.10.7.51", "timeOfRevocationGen"}, - {"0.2.262.1.10.7.52", "liabilityText"}, - {"0.2.262.1.10.7.6", "issuer"}, - {"0.2.262.1.10.7.7", "namingAuthority"}, - {"0.2.262.1.10.7.8", "publicKeyDirectory"}, - {"0.2.262.1.10.7.9", "securityDomain"}, - {"0.2.262.1.10.8", "attributeGroup"}, - {"0.2.262.1.10.9", "action"}, - {"0.4.0.127.0.7", "bsi"}, - {"0.4.0.127.0.7.1", "bsiEcc"}, - {"0.4.0.127.0.7.1.1", "bsifieldType"}, - {"0.4.0.127.0.7.1.1.1", "bsiPrimeField"}, - {"0.4.0.127.0.7.1.1.2", "bsiCharacteristicTwoField"}, - {"0.4.0.127.0.7.1.1.2.2", "bsiECTLVKeyFormat"}, - {"0.4.0.127.0.7.1.1.2.2.1", "bsiECTLVPublicKey"}, - {"0.4.0.127.0.7.1.1.2.3", "bsiCharacteristicTwoBasis"}, - {"0.4.0.127.0.7.1.1.2.3.1", "bsiGnBasis"}, - {"0.4.0.127.0.7.1.1.2.3.2", "bsiTpBasis"}, - {"0.4.0.127.0.7.1.1.2.3.3", "bsiPpBasis"}, - {"0.4.0.127.0.7.1.1.4.1", "bsiEcdsaSignatures"}, - {"0.4.0.127.0.7.1.1.4.1.1", "bsiEcdsaWithSHA1"}, - {"0.4.0.127.0.7.1.1.4.1.2", "bsiEcdsaWithSHA224"}, - {"0.4.0.127.0.7.1.1.4.1.3", "bsiEcdsaWithSHA256"}, - {"0.4.0.127.0.7.1.1.4.1.4", "bsiEcdsaWithSHA384"}, - {"0.4.0.127.0.7.1.1.4.1.5", "bsiEcdsaWithSHA512"}, - {"0.4.0.127.0.7.1.1.4.1.6", "bsiEcdsaWithRIPEMD160"}, - {"0.4.0.127.0.7.1.1.5.1.1", "bsiEckaEgX963KDF"}, - {"0.4.0.127.0.7.1.1.5.1.1.1", "bsiEckaEgX963KDFWithSHA1"}, - {"0.4.0.127.0.7.1.1.5.1.1.2", "bsiEckaEgX963KDFWithSHA224"}, - {"0.4.0.127.0.7.1.1.5.1.1.3", "bsiEckaEgX963KDFWithSHA256"}, - {"0.4.0.127.0.7.1.1.5.1.1.4", "bsiEckaEgX963KDFWithSHA384"}, - {"0.4.0.127.0.7.1.1.5.1.1.5", "bsiEckaEgX963KDFWithSHA512"}, - {"0.4.0.127.0.7.1.1.5.1.1.6", "bsiEckaEgX963KDFWithRIPEMD160"}, - {"0.4.0.127.0.7.1.1.5.1.2", "bsiEckaEgSessionKDF"}, - {"0.4.0.127.0.7.1.1.5.1.2.1", "bsiEckaEgSessionKDFWith3DES"}, - {"0.4.0.127.0.7.1.1.5.1.2.2", "bsiEckaEgSessionKDFWithAES128"}, - {"0.4.0.127.0.7.1.1.5.1.2.3", "bsiEckaEgSessionKDFWithAES192"}, - {"0.4.0.127.0.7.1.1.5.1.2.4", "bsiEckaEgSessionKDFWithAES256"}, - {"0.4.0.127.0.7.1.1.5.2", "bsiEckaDH"}, - {"0.4.0.127.0.7.1.1.5.2.1", "bsiEckaDHX963KDF"}, - {"0.4.0.127.0.7.1.1.5.2.1.1", "bsiEckaDHX963KDFWithSHA1"}, - {"0.4.0.127.0.7.1.1.5.2.1.2", "bsiEckaDHX963KDFWithSHA224"}, - {"0.4.0.127.0.7.1.1.5.2.1.3", "bsiEckaDHX963KDFWithSHA256"}, - {"0.4.0.127.0.7.1.1.5.2.1.4", "bsiEckaDHX963KDFWithSHA384"}, - {"0.4.0.127.0.7.1.1.5.2.1.5", "bsiEckaDHX963KDFWithSHA512"}, - {"0.4.0.127.0.7.1.1.5.2.1.6", "bsiEckaDHX963KDFWithRIPEMD160"}, - {"0.4.0.127.0.7.1.1.5.2.2", "bsiEckaDHSessionKDF"}, - {"0.4.0.127.0.7.1.1.5.2.2.1", "bsiEckaDHSessionKDFWith3DES"}, - {"0.4.0.127.0.7.1.1.5.2.2.2", "bsiEckaDHSessionKDFWithAES128"}, - {"0.4.0.127.0.7.1.1.5.2.2.3", "bsiEckaDHSessionKDFWithAES192"}, - {"0.4.0.127.0.7.1.1.5.2.2.4", "bsiEckaDHSessionKDFWithAES256"}, - {"0.4.0.127.0.7.1.2", "bsiEcKeyType"}, - {"0.4.0.127.0.7.1.2.1", "bsiEcPublicKey"}, - {"0.4.0.127.0.7.1.5.1", "bsiKaeg"}, - {"0.4.0.127.0.7.1.5.1.1", "bsiKaegWithX963KDF"}, - {"0.4.0.127.0.7.1.5.1.2", "bsiKaegWith3DESKDF"}, - {"0.4.0.127.0.7.2.2.1", "bsiPK"}, - {"0.4.0.127.0.7.2.2.1.1", "bsiPK_DH"}, - {"0.4.0.127.0.7.2.2.1.2", "bsiPK_ECDH"}, - {"0.4.0.127.0.7.2.2.2", "bsiTA"}, - {"0.4.0.127.0.7.2.2.2.1", "bsiTA_RSA"}, - {"0.4.0.127.0.7.2.2.2.1.1", "bsiTA_RSAv1_5_SHA1"}, - {"0.4.0.127.0.7.2.2.2.1.2", "bsiTA_RSAv1_5_SHA256"}, - {"0.4.0.127.0.7.2.2.2.1.3", "bsiTA_RSAPSS_SHA1"}, - {"0.4.0.127.0.7.2.2.2.1.4", "bsiTA_RSAPSS_SHA256"}, - {"0.4.0.127.0.7.2.2.2.1.5", "bsiTA_RSAv1_5_SHA512"}, - {"0.4.0.127.0.7.2.2.2.1.6", "bsiTA_RSAPSS_SHA512"}, - {"0.4.0.127.0.7.2.2.2.2", "bsiTA_ECDSA"}, - {"0.4.0.127.0.7.2.2.2.2.1", "bsiTA_ECDSA_SHA1"}, - {"0.4.0.127.0.7.2.2.2.2.2", "bsiTA_ECDSA_SHA224"}, - {"0.4.0.127.0.7.2.2.2.2.3", "bsiTA_ECDSA_SHA256"}, - {"0.4.0.127.0.7.2.2.2.2.4", "bsiTA_ECDSA_SHA384"}, - {"0.4.0.127.0.7.2.2.2.2.5", "bsiTA_ECDSA_SHA512"}, - {"0.4.0.127.0.7.2.2.3", "bsiCA"}, - {"0.4.0.127.0.7.2.2.3.1", "bsiCA_DH"}, - {"0.4.0.127.0.7.2.2.3.1.1", "bsiCA_DH_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.3.1.2", "bsiCA_DH_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.3.1.3", "bsiCA_DH_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.3.1.4", "bsiCA_DH_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.3.2", "bsiCA_ECDH"}, - {"0.4.0.127.0.7.2.2.3.2.1", "bsiCA_ECDH_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.3.2.2", "bsiCA_ECDH_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.3.2.3", "bsiCA_ECDH_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.3.2.4", "bsiCA_ECDH_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.4", "bsiPACE"}, - {"0.4.0.127.0.7.2.2.4.1", "bsiPACE_DH_GM"}, - {"0.4.0.127.0.7.2.2.4.1.1", "bsiPACE_DH_GM_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.4.1.2", "bsiPACE_DH_GM_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.4.1.3", "bsiPACE_DH_GM_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.4.1.4", "bsiPACE_DH_GM_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.4.2", "bsiPACE_ECDH_GM"}, - {"0.4.0.127.0.7.2.2.4.2.1", "bsiPACE_ECDH_GM_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.4.2.2", "bsiPACE_ECDH_GM_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.4.2.3", "bsiPACE_ECDH_GM_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.4.2.4", "bsiPACE_ECDH_GM_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.4.3", "bsiPACE_DH_IM"}, - {"0.4.0.127.0.7.2.2.4.3.1", "bsiPACE_DH_IM_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.4.3.2", "bsiPACE_DH_IM_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.4.3.3", "bsiPACE_DH_IM_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.4.3.4", "bsiPACE_DH_IM_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.4.4", "bsiPACE_ECDH_IM"}, - {"0.4.0.127.0.7.2.2.4.4.1", "bsiPACE_ECDH_IM_3DES_CBC_CBC"}, - {"0.4.0.127.0.7.2.2.4.4.2", "bsiPACE_ECDH_IM_AES_CBC_CMAC_128"}, - {"0.4.0.127.0.7.2.2.4.4.3", "bsiPACE_ECDH_IM_AES_CBC_CMAC_192"}, - {"0.4.0.127.0.7.2.2.4.4.4", "bsiPACE_ECDH_IM_AES_CBC_CMAC_256"}, - {"0.4.0.127.0.7.2.2.5", "bsiRI"}, - {"0.4.0.127.0.7.2.2.5.1", "bsiRI_DH"}, - {"0.4.0.127.0.7.2.2.5.1.1", "bsiRI_DH_SHA1"}, - {"0.4.0.127.0.7.2.2.5.1.2", "bsiRI_DH_SHA224"}, - {"0.4.0.127.0.7.2.2.5.1.3", "bsiRI_DH_SHA256"}, - {"0.4.0.127.0.7.2.2.5.1.4", "bsiRI_DH_SHA384"}, - {"0.4.0.127.0.7.2.2.5.1.5", "bsiRI_DH_SHA512"}, - {"0.4.0.127.0.7.2.2.5.2", "bsiRI_ECDH"}, - {"0.4.0.127.0.7.2.2.5.2.1", "bsiRI_ECDH_SHA1"}, - {"0.4.0.127.0.7.2.2.5.2.2", "bsiRI_ECDH_SHA224"}, - {"0.4.0.127.0.7.2.2.5.2.3", "bsiRI_ECDH_SHA256"}, - {"0.4.0.127.0.7.2.2.5.2.4", "bsiRI_ECDH_SHA384"}, - {"0.4.0.127.0.7.2.2.5.2.5", "bsiRI_ECDH_SHA512"}, - {"0.4.0.127.0.7.2.2.6", "bsiCardInfo"}, - {"0.4.0.127.0.7.2.2.7", "bsiEidSecurity"}, - {"0.4.0.127.0.7.2.2.8", "bsiPT"}, - {"0.4.0.127.0.7.3.1.2", "bsiEACRoles"}, - {"0.4.0.127.0.7.3.1.2.1", "bsiEACRolesIS"}, - {"0.4.0.127.0.7.3.1.2.2", "bsiEACRolesAT"}, - {"0.4.0.127.0.7.3.1.2.3", "bsiEACRolesST"}, - {"0.4.0.127.0.7.3.1.3", "bsiTAv2ce"}, - {"0.4.0.127.0.7.3.1.3.1", "bsiTAv2ceDescription"}, - {"0.4.0.127.0.7.3.1.3.1.1", "bsiTAv2ceDescriptionPlainText"}, - {"0.4.0.127.0.7.3.1.3.1.2", "bsiTAv2ceDescriptionIA5String"}, - {"0.4.0.127.0.7.3.1.3.1.3", "bsiTAv2ceDescriptionOctetString"}, - {"0.4.0.127.0.7.3.1.3.2", "bsiTAv2ceTerminalSector"}, - {"0.4.0.127.0.7.3.1.4", "bsiAuxData"}, - {"0.4.0.127.0.7.3.1.4.1", "bsiAuxDataBirthday"}, - {"0.4.0.127.0.7.3.1.4.2", "bsiAuxDataExpireDate"}, - {"0.4.0.127.0.7.3.1.4.3", "bsiAuxDataCommunityID"}, - {"0.4.0.127.0.7.3.1.5", "bsiDefectList"}, - {"0.4.0.127.0.7.3.1.5.1", "bsiDefectAuthDefect"}, - {"0.4.0.127.0.7.3.1.5.1.1", "bsiDefectCertRevoked"}, - {"0.4.0.127.0.7.3.1.5.1.2", "bsiDefectCertReplaced"}, - {"0.4.0.127.0.7.3.1.5.1.3", "bsiDefectChipAuthKeyRevoked"}, - {"0.4.0.127.0.7.3.1.5.1.4", "bsiDefectActiveAuthKeyRevoked"}, - {"0.4.0.127.0.7.3.1.5.2", "bsiDefectEPassportDefect"}, - {"0.4.0.127.0.7.3.1.5.2.1", "bsiDefectEPassportDGMalformed"}, - {"0.4.0.127.0.7.3.1.5.2.2", "bsiDefectSODInvalid"}, - {"0.4.0.127.0.7.3.1.5.3", "bsiDefectEIDDefect"}, - {"0.4.0.127.0.7.3.1.5.3.1", "bsiDefectEIDDGMalformed"}, - {"0.4.0.127.0.7.3.1.5.3.2", "bsiDefectEIDIntegrity"}, - {"0.4.0.127.0.7.3.1.5.4", "bsiDefectDocumentDefect"}, - {"0.4.0.127.0.7.3.1.5.4.1", "bsiDefectCardSecurityMalformed"}, - {"0.4.0.127.0.7.3.1.5.4.2", "bsiDefectChipSecurityMalformed"}, - {"0.4.0.127.0.7.3.1.5.4.3", "bsiDefectPowerDownReq"}, - {"0.4.0.127.0.7.3.1.6", "bsiListContentDescription"}, - {"0.4.0.127.0.7.3.2.1", "bsiSecurityObject"}, - {"0.4.0.127.0.7.3.2.2", "bsiBlackList"}, - {"0.4.0.1862", "etsiQcsProfile"}, - {"0.4.0.1862.1", "etsiQcs"}, - {"0.4.0.1862.1.1", "etsiQcsCompliance"}, - {"0.4.0.1862.1.2", "etsiQcsLimitValue"}, - {"0.4.0.1862.1.3", "etsiQcsRetentionPeriod"}, - {"0.4.0.1862.1.4", "etsiQcsQcSSCD"}, - {"0.9.2342.19200300.100.1.1", "userID"}, - {"0.9.2342.19200300.100.1.25", "domainComponent"}, - {"0.9.2342.19200300.100.1.3", "rfc822Mailbox"}, - {"1.0.10118.3.0.49", "ripemd160"}, - {"1.0.10118.3.0.50", "ripemd128"}, - {"1.0.10118.3.0.55", "whirlpool"}, - {"1.2.3.4.9999", "timeStamp" }, - {"1.2.36.1.3.1.1.1", "qgpki"}, - {"1.2.36.1.3.1.1.1.1", "qgpkiPolicies"}, - {"1.2.36.1.3.1.1.1.1.1", "qgpkiMedIntermedCA"}, - {"1.2.36.1.3.1.1.1.1.1.1", "qgpkiMedIntermedIndividual"}, - {"1.2.36.1.3.1.1.1.1.1.2", "qgpkiMedIntermedDeviceControl"}, - {"1.2.36.1.3.1.1.1.1.1.3", "qgpkiMedIntermedDevice"}, - {"1.2.36.1.3.1.1.1.1.1.4", "qgpkiMedIntermedAuthorisedParty"}, - {"1.2.36.1.3.1.1.1.1.1.5", "qgpkiMedIntermedDeviceSystem"}, - {"1.2.36.1.3.1.1.1.1.2", "qgpkiMedIssuingCA"}, - {"1.2.36.1.3.1.1.1.1.2.1", "qgpkiMedIssuingIndividual"}, - {"1.2.36.1.3.1.1.1.1.2.2", "qgpkiMedIssuingDeviceControl"}, - {"1.2.36.1.3.1.1.1.1.2.3", "qgpkiMedIssuingDevice"}, - {"1.2.36.1.3.1.1.1.1.2.4", "qgpkiMedIssuingAuthorisedParty"}, - {"1.2.36.1.3.1.1.1.1.2.5", "qgpkiMedIssuingClientAuth"}, - {"1.2.36.1.3.1.1.1.1.2.6", "qgpkiMedIssuingServerAuth"}, - {"1.2.36.1.3.1.1.1.1.2.7", "qgpkiMedIssuingDataProt"}, - {"1.2.36.1.3.1.1.1.1.2.8", "qgpkiMedIssuingTokenAuth"}, - {"1.2.36.1.3.1.1.1.1.3", "qgpkiBasicIntermedCA"}, - {"1.2.36.1.3.1.1.1.1.3.1", "qgpkiBasicIntermedDeviceSystem"}, - {"1.2.36.1.3.1.1.1.1.4", "qgpkiBasicIssuingCA"}, - {"1.2.36.1.3.1.1.1.1.4.1", "qgpkiBasicIssuingClientAuth"}, - {"1.2.36.1.3.1.1.1.1.4.2", "qgpkiBasicIssuingServerAuth"}, - {"1.2.36.1.3.1.1.1.1.4.3", "qgpkiBasicIssuingDataSigning"}, - {"1.2.36.1.3.1.1.1.2", "qgpkiAssuranceLevel"}, - {"1.2.36.1.3.1.1.1.2.1", "qgpkiAssuranceRudimentary"}, - {"1.2.36.1.3.1.1.1.2.2", "qgpkiAssuranceBasic"}, - {"1.2.36.1.3.1.1.1.2.3", "qgpkiAssuranceMedium"}, - {"1.2.36.1.3.1.1.1.2.4", "qgpkiAssuranceHigh"}, - {"1.2.36.1.3.1.1.1.3", "qgpkiCertFunction"}, - {"1.2.36.1.3.1.1.1.3.1", "qgpkiFunctionIndividual"}, - {"1.2.36.1.3.1.1.1.3.2", "qgpkiFunctionDevice"}, - {"1.2.36.1.3.1.1.1.3.3", "qgpkiFunctionAuthorisedParty"}, - {"1.2.36.1.3.1.1.1.3.4", "qgpkiFunctionDeviceControl"}, - {"1.2.36.1.3.1.2", "qpspki"}, - {"1.2.36.1.3.1.2.1", "qpspkiPolicies"}, - {"1.2.36.1.3.1.2.1.2", "qpspkiPolicyBasic"}, - {"1.2.36.1.3.1.2.1.3", "qpspkiPolicyMedium"}, - {"1.2.36.1.3.1.2.1.4", "qpspkiPolicyHigh"}, - {"1.2.36.1.3.1.3.2", "qtmrpki"}, - {"1.2.36.1.3.1.3.2.1", "qtmrpkiPolicies"}, - {"1.2.36.1.3.1.3.2.2", "qtmrpkiPurpose"}, - {"1.2.36.1.3.1.3.2.2.1", "qtmrpkiIndividual"}, - {"1.2.36.1.3.1.3.2.2.2", "qtmrpkiDeviceControl"}, - {"1.2.36.1.3.1.3.2.2.3", "qtmrpkiDevice"}, - {"1.2.36.1.3.1.3.2.2.4", "qtmrpkiAuthorisedParty"}, - {"1.2.36.1.3.1.3.2.2.5", "qtmrpkiDeviceSystem"}, - {"1.2.36.1.3.1.3.2.3", "qtmrpkiDevice"}, - {"1.2.36.1.3.1.3.2.3.1", "qtmrpkiDriverLicense"}, - {"1.2.36.1.3.1.3.2.3.2", "qtmrpkiIndustryAuthority"}, - {"1.2.36.1.3.1.3.2.3.3", "qtmrpkiMarineLicense"}, - {"1.2.36.1.3.1.3.2.3.4", "qtmrpkiAdultProofOfAge"}, - {"1.2.36.1.3.1.3.2.3.5", "qtmrpkiSam"}, - {"1.2.36.1.3.1.3.2.4", "qtmrpkiAuthorisedParty"}, - {"1.2.36.1.3.1.3.2.4.1", "qtmrpkiTransportInspector"}, - {"1.2.36.1.3.1.3.2.4.2", "qtmrpkiPoliceOfficer"}, - {"1.2.36.1.3.1.3.2.4.3", "qtmrpkiSystem"}, - {"1.2.36.1.3.1.3.2.4.4", "qtmrpkiLiquorLicensingInspector"}, - {"1.2.36.1.3.1.3.2.4.5", "qtmrpkiMarineEnforcementOfficer"}, - {"1.2.36.1.333.1", "australianBusinessNumber"}, - {"1.2.36.68980861.1.1.10", "signetPilot"}, - {"1.2.36.68980861.1.1.11", "signetIntraNet"}, - {"1.2.36.68980861.1.1.2", "signetPersonal"}, - {"1.2.36.68980861.1.1.20", "signetPolicy"}, - {"1.2.36.68980861.1.1.3", "signetBusiness"}, - {"1.2.36.68980861.1.1.4", "signetLegal"}, - {"1.2.36.75878867.1.100.1.1", "certificatesAustraliaPolicy"}, - {"1.2.392.200011.61.1.1.1", "mitsubishiSecurityAlgorithm"}, - {"1.2.392.200011.61.1.1.1.1", "misty1-cbc"}, - {"1.2.410.200004.1", "kisaAlgorithm"}, - {"1.2.410.200004.1.1", "kcdsa"}, - {"1.2.410.200004.1.10", "pbeWithHAS160AndSEED-ECB"}, - {"1.2.410.200004.1.11", "pbeWithHAS160AndSEED-CBC"}, - {"1.2.410.200004.1.12", "pbeWithHAS160AndSEED-CFB"}, - {"1.2.410.200004.1.13", "pbeWithHAS160AndSEED-OFB"}, - {"1.2.410.200004.1.14", "pbeWithSHA1AndSEED-ECB"}, - {"1.2.410.200004.1.15", "pbeWithSHA1AndSEED-CBC"}, - {"1.2.410.200004.1.16", "pbeWithSHA1AndSEED-CFB"}, - {"1.2.410.200004.1.17", "pbeWithSHA1AndSEED-OFB"}, - {"1.2.410.200004.1.2", "has160"}, - {"1.2.410.200004.1.20", "rsaWithHAS160"}, - {"1.2.410.200004.1.21", "kcdsa1"}, - {"1.2.410.200004.1.3", "seedECB"}, - {"1.2.410.200004.1.4", "seedCBC"}, - {"1.2.410.200004.1.5", "seedOFB"}, - {"1.2.410.200004.1.6", "seedCFB"}, - {"1.2.410.200004.1.7", "seedMAC"}, - {"1.2.410.200004.1.8", "kcdsaWithHAS160"}, - {"1.2.410.200004.1.9", "kcdsaWithSHA1"}, - {"1.2.410.200004.10", "npki"}, - {"1.2.410.200004.10.1", "npkiAttribute"}, - {"1.2.410.200004.10.1.1", "npkiIdentifyData"}, - {"1.2.410.200004.10.1.1.1", "npkiVID"}, - {"1.2.410.200004.10.1.1.2", "npkiEncryptedVID"}, - {"1.2.410.200004.10.1.1.3", "npkiRandomNum"}, - {"1.2.410.200004.10.1.1.4", "npkiVID"}, - {"1.2.410.200004.2", "npkiCP"}, - {"1.2.410.200004.2.1", "npkiSignaturePolicy"}, - {"1.2.410.200004.3", "npkiKP"}, - {"1.2.410.200004.4", "npkiAT"}, - {"1.2.410.200004.5", "npkiLCA"}, - {"1.2.410.200004.5.1", "npkiSignKorea"}, - {"1.2.410.200004.5.2", "npkiSignGate"}, - {"1.2.410.200004.5.3", "npkiNcaSign"}, - {"1.2.410.200004.6", "npkiON"}, - {"1.2.410.200004.7", "npkiAPP"}, - {"1.2.410.200004.7.1", "npkiSMIME"}, - {"1.2.410.200004.7.1.1", "npkiSMIMEAlgo"}, - {"1.2.410.200004.7.1.1.1", "npkiCmsSEEDWrap"}, - {"1.2.410.200046.1.1", "aria1AlgorithmModes"}, - {"1.2.410.200046.1.1.1", "aria128-ecb"}, - {"1.2.410.200046.1.1.10", "aria192-ctr"}, - {"1.2.410.200046.1.1.11", "aria256-ecb"}, - {"1.2.410.200046.1.1.12", "aria256-cbc"}, - {"1.2.410.200046.1.1.13", "aria256-cfb"}, - {"1.2.410.200046.1.1.14", "aria256-ofb"}, - {"1.2.410.200046.1.1.15", "aria256-ctr"}, - {"1.2.410.200046.1.1.2", "aria128-cbc"}, - {"1.2.410.200046.1.1.21", "aria128-cmac"}, - {"1.2.410.200046.1.1.22", "aria192-cmac"}, - {"1.2.410.200046.1.1.23", "aria256-cmac"}, - {"1.2.410.200046.1.1.3", "aria128-cfb"}, - {"1.2.410.200046.1.1.31", "aria128-ocb2"}, - {"1.2.410.200046.1.1.32", "aria192-ocb2"}, - {"1.2.410.200046.1.1.33", "aria256-ocb2"}, - {"1.2.410.200046.1.1.34", "aria128-gcm"}, - {"1.2.410.200046.1.1.35", "aria192-gcm"}, - {"1.2.410.200046.1.1.36", "aria256-gcm"}, - {"1.2.410.200046.1.1.37", "aria128-ccm"}, - {"1.2.410.200046.1.1.38", "aria192-ccm"}, - {"1.2.410.200046.1.1.39", "aria256-ccm"}, - {"1.2.410.200046.1.1.4", "aria128-ofb"}, - {"1.2.410.200046.1.1.40", "aria128-keywrap"}, - {"1.2.410.200046.1.1.41", "aria192-keywrap"}, - {"1.2.410.200046.1.1.42", "aria256-keywrap"}, - {"1.2.410.200046.1.1.43", "aria128-keywrapWithPad"}, - {"1.2.410.200046.1.1.44", "aria192-keywrapWithPad"}, - {"1.2.410.200046.1.1.45", "aria256-keywrapWithPad"}, - {"1.2.410.200046.1.1.5", "aria128-ctr"}, - {"1.2.410.200046.1.1.6", "aria192-ecb"}, - {"1.2.410.200046.1.1.7", "aria192-cbc"}, - {"1.2.410.200046.1.1.8", "aria192-cfb"}, - {"1.2.410.200046.1.1.9", "aria192-ofb"}, - {"1.2.643.2.2.10", "hmacGost"}, - {"1.2.643.2.2.13.0", "gostWrap"}, - {"1.2.643.2.2.13.1", "cryptoProWrap"}, - {"1.2.643.2.2.14.0", "nullMeshing"}, - {"1.2.643.2.2.14.1", "cryptoProMeshing"}, - {"1.2.643.2.2.19", "gostPublicKey"}, - {"1.2.643.2.2.20", "gost94PublicKey"}, - {"1.2.643.2.2.21", "gostCipher"}, - {"1.2.643.2.2.3", "gostSignature"}, - {"1.2.643.2.2.30.0", "testDigestParams"}, - {"1.2.643.2.2.30.1", "cryptoProDigestA"}, - {"1.2.643.2.2.31.0", "testCipherParams"}, - {"1.2.643.2.2.31.1", "cryptoProCipherA"}, - {"1.2.643.2.2.31.2", "cryptoProCipherB"}, - {"1.2.643.2.2.31.3", "cryptoProCipherC"}, - {"1.2.643.2.2.31.4", "cryptoProCipherD"}, - {"1.2.643.2.2.31.5", "oscar11Cipher"}, - {"1.2.643.2.2.31.6", "oscar10Cipher"}, - {"1.2.643.2.2.31.7", "ric1Cipher"}, - {"1.2.643.2.2.35.0", "testSignParams"}, - {"1.2.643.2.2.35.1", "cryptoProSignA"}, - {"1.2.643.2.2.35.2", "cryptoProSignB"}, - {"1.2.643.2.2.35.3", "cryptoProSignC"}, - {"1.2.643.2.2.36.0", "cryptoProSignXA"}, - {"1.2.643.2.2.36.1", "cryptoProSignXB"}, - {"1.2.643.2.2.4", "gost94Signature"}, - {"1.2.643.2.2.9", "gostDigest"}, - {"1.2.643.2.2.96", "cryptoProECDHWrap"}, - {"1.2.752.34.1", "seis-cp"}, - {"1.2.752.34.1.1", "SEIS.high-assurance.policyIdentifier"}, - {"1.2.752.34.1.2", "SEIS.GAK.policyIdentifier"}, - {"1.2.752.34.2", "SEIS.pe"}, - {"1.2.752.34.3", "SEIS.at"}, - {"1.2.752.34.3.1", "SEIS.at-personalIdentifier"}, - {"1.2.840.10040.1", "module"}, - {"1.2.840.10040.1.1", "x9f1-cert-mgmt"}, - {"1.2.840.10040.2", "holdinstruction"}, - {"1.2.840.10040.2.1", "holdinstruction-none"}, - {"1.2.840.10040.2.2", "callissuer"}, - {"1.2.840.10040.2.3", "reject"}, - {"1.2.840.10040.2.4", "pickupToken"}, - {"1.2.840.10040.3", "attribute"}, - {"1.2.840.10040.3.1", "countersignature"}, - {"1.2.840.10040.3.2", "attribute-cert"}, - {"1.2.840.10040.4", "algorithm"}, - {"1.2.840.10040.4.1", "dsa"}, - {"1.2.840.10040.4.2", "dsa-match"}, - {"1.2.840.10040.4.3", "dsaWithSha1"}, - {"1.2.840.10045.1", "fieldType"}, - {"1.2.840.10045.1.1", "prime-field"}, - {"1.2.840.10045.1.2", "characteristic-two-field"}, - {"1.2.840.10045.1.2.3", "characteristic-two-basis"}, - {"1.2.840.10045.1.2.3.1", "onBasis"}, - {"1.2.840.10045.1.2.3.2", "tpBasis"}, - {"1.2.840.10045.1.2.3.3", "ppBasis"}, - {"1.2.840.10045.2", "publicKeyType"}, - {"1.2.840.10045.2.1", "ecPublicKey"}, - {"1.2.840.10045.2.2", "ecPublicKeyRestricted" }, - {"1.2.840.10045.3.0.1", "c2pnb163v1"}, - {"1.2.840.10045.3.0.10", "c2pnb208w1"}, - {"1.2.840.10045.3.0.11", "c2tnb239v1"}, - {"1.2.840.10045.3.0.12", "c2tnb239v2"}, - {"1.2.840.10045.3.0.13", "c2tnb239v3"}, - {"1.2.840.10045.3.0.16", "c2pnb272w1"}, - {"1.2.840.10045.3.0.18", "c2tnb359v1"}, - {"1.2.840.10045.3.0.19", "c2pnb368w1"}, - {"1.2.840.10045.3.0.2", "c2pnb163v2"}, - {"1.2.840.10045.3.0.20", "c2tnb431r1"}, - {"1.2.840.10045.3.0.3", "c2pnb163v3"}, - {"1.2.840.10045.3.0.5", "c2tnb191v1"}, - {"1.2.840.10045.3.0.6", "c2tnb191v2"}, - {"1.2.840.10045.3.0.7", "c2tnb191v3"}, - {"1.2.840.10045.3.1.1", "prime192v1"}, - {"1.2.840.10045.3.1.2", "prime192v2"}, - {"1.2.840.10045.3.1.3", "prime192v3"}, - {"1.2.840.10045.3.1.4", "prime239v1"}, - {"1.2.840.10045.3.1.5", "prime239v2"}, - {"1.2.840.10045.3.1.6", "prime239v3"}, - {"1.2.840.10045.3.1.7", "prime256v1"}, - {"1.2.840.10045.4.1", "ecdsaWithSHA1"}, - {"1.2.840.10045.4.2", "ecdsaWithRecommended"}, - {"1.2.840.10045.4.3", "ecdsaWithSpecified"}, - {"1.2.840.10045.4.3.1", "ecdsaWithSHA224"}, - {"1.2.840.10045.4.3.2", "ecdsaWithSHA256"}, - {"1.2.840.10045.4.3.3", "ecdsaWithSHA384"}, - {"1.2.840.10045.4.3.4", "ecdsaWithSHA512"}, - {"1.2.840.10046.1", "fieldType"}, - {"1.2.840.10046.1.1", "gf-prime"}, - {"1.2.840.10046.2", "numberType"}, - {"1.2.840.10046.2.1", "dhPublicKey"}, - {"1.2.840.10046.3", "scheme"}, - {"1.2.840.10046.3.1", "dhStatic"}, - {"1.2.840.10046.3.2", "dhEphem"}, - {"1.2.840.10046.3.3", "dhHybrid1"}, - {"1.2.840.10046.3.4", "dhHybrid2"}, - {"1.2.840.10046.3.5", "mqv2"}, - {"1.2.840.10046.3.6", "mqv1"}, - {"1.2.840.10065.2.2", "?"}, - {"1.2.840.10065.2.3", "healthcareLicense"}, - {"1.2.840.10065.2.3.1.1", "license?"}, - {"1.2.840.10070.", "iec62351"}, - {"1.2.840.10070.8", "iec62351_8"}, - {"1.2.840.10070.8.1", "iecUserRoles"}, - {"1.2.840.113533.7", "nsn"}, - {"1.2.840.113533.7.65", "nsn-ce"}, - {"1.2.840.113533.7.65.0", "entrustVersInfo"}, - {"1.2.840.113533.7.65.1", "clearance" }, - {"1.2.840.113533.7.65.2", "noCRL" }, - {"1.2.840.113533.7.66", "nsn-alg"}, - {"1.2.840.113533.7.66.0", "cast40CBC" }, - {"1.2.840.113533.7.66.1", "cast64CBC" }, - {"1.2.840.113533.7.66.10", "cast5CBC"}, - {"1.2.840.113533.7.66.11", "cast5MAC"}, - {"1.2.840.113533.7.66.12", "pbeWithMD5AndCAST5-CBC"}, - {"1.2.840.113533.7.66.13", "passwordBasedMac"}, - {"1.2.840.113533.7.66.2", "cast64MAC" }, - {"1.2.840.113533.7.66.3", "cast3CBC"}, - {"1.2.840.113533.7.67", "nsn-oc"}, - {"1.2.840.113533.7.67.0", "entrustUser"}, - {"1.2.840.113533.7.67.1", "entrustCA" }, - {"1.2.840.113533.7.68", "nsn-at"}, - {"1.2.840.113533.7.68.0", "entrustCAInfo"}, - {"1.2.840.113533.7.68.10", "attributeCertificate"}, - {"1.2.840.113533.7.68.16", "entrustPwordPolicy" }, - {"1.2.840.113533.7.68.29", "entrustUserRole" }, - {"1.2.840.113533.7.77.0", "entrustRoleMap" }, - {"1.2.840.113533.7.77.1", "entrustPasswordRules" }, - {"1.2.840.113533.7.77.10", "entrustEncKeyType" }, - {"1.2.840.113533.7.77.11", "entrustBusCtrlPolOids" }, - {"1.2.840.113533.7.77.12", "entrustBusCtrlFlags" }, - {"1.2.840.113533.7.77.13", "entrustPCertLifetime" }, - {"1.2.840.113533.7.77.14", "entrustDNEncoding" }, - {"1.2.840.113533.7.77.15", "entrustCertConsistencyChecking" }, - {"1.2.840.113533.7.77.16", "entrustUserEncAlgm" }, - {"1.2.840.113533.7.77.17", "entrustCRLGracePeriod" }, - {"1.2.840.113533.7.77.18", "entrustSkipRLChecks" }, - {"1.2.840.113533.7.77.19", "entrustHTTPProxySetting" }, - {"1.2.840.113533.7.77.20", "entrustOfflineProfileUse" }, - {"1.2.840.113533.7.77.21", "entrustAllowServerLogin" }, - {"1.2.840.113533.7.77.22", "entrustEnforceIdentityUse" }, - {"1.2.840.113533.7.77.23", "entrustAllowPKCS12Export" }, - {"1.2.840.113533.7.77.24", "entrustPKCS12ExportMinimumHashCount" }, - {"1.2.840.113533.7.77.25", "entrustClientNKeyType" }, - {"1.2.840.113533.7.77.26", "entrustAllowed3rdPartySymmetricAlgms" }, - {"1.2.840.113533.7.77.27", "entrustPreventManualAppRegistration" }, - {"1.2.840.113533.7.77.28", "entrustPasswordMaxAttempts" }, - {"1.2.840.113533.7.77.29", "entrustPasswordMinTime" }, - {"1.2.840.113533.7.77.3", "entrustAllowedSymmetricAlgms" }, - {"1.2.840.113533.7.77.30", "entrustPasswordMinSuspend" }, - {"1.2.840.113533.7.77.31", "entrustAllowCAPIExport" }, - {"1.2.840.113533.7.77.32", "entrustICEAdminPolicy" }, - {"1.2.840.113533.7.77.33", "entrustEnableCacheUsage" }, - {"1.2.840.113533.7.77.34", "entrustUserEncAlgm2" }, - {"1.2.840.113533.7.77.35", "entrustSecureDeliveryServiceSMTP" }, - {"1.2.840.113533.7.77.36", "entrustContentScannerServiceSMTP" }, - {"1.2.840.113533.7.77.37", "entrustExpressSearchSourceOrder" }, - {"1.2.840.113533.7.77.38", "entrustCAPIPolicy" }, - {"1.2.840.113533.7.77.39", "entrustSearchbaseSearchOrder" }, - {"1.2.840.113533.7.77.4", "entrustAllowedHashAlgms" }, - {"1.2.840.113533.7.77.40", "entrustCRLGracePercentage" }, - {"1.2.840.113533.7.77.49", "entrustPublicTokenCerts" }, - {"1.2.840.113533.7.77.5", "entrustCSetFlags" }, - {"1.2.840.113533.7.77.50", "entrustProtectKeyTransfer" }, - {"1.2.840.113533.7.77.57", "entrustAllowTokenSpilloverFile" }, - {"1.2.840.113533.7.77.58", "entrustMaximumTokenKeyHistory" }, - {"1.2.840.113533.7.77.59", "entrustSelfRevokePolicy" }, - {"1.2.840.113533.7.77.6", "entrustMessageOfTheDay" }, - {"1.2.840.113533.7.77.60", "entrustAllowPSSwitch" }, - {"1.2.840.113533.7.77.61", "entrustManagementClient" }, - {"1.2.840.113533.7.77.62", "entrustForceOriginalCDPolicyCompliance" }, - {"1.2.840.113533.7.77.63", "entrustAllExportable" }, - {"1.2.840.113533.7.77.64", "entrustProtocolSymmetricEncAlgs" }, - {"1.2.840.113533.7.77.65", "entrustProtocolSigningAlgs" }, - {"1.2.840.113533.7.77.7", "entrustAttrName" }, - {"1.2.840.113533.7.77.8", "entrustApplicationFlags" }, - {"1.2.840.113533.7.77.9", "entrustSignKeyType" }, - {"1.2.840.113549.1.1", "pkcs-1"}, - {"1.2.840.113549.1.1.1", "rsaEncryption"}, - {"1.2.840.113549.1.1.10", "rsaPSS"}, - {"1.2.840.113549.1.1.11", "sha256WithRSAEncryption"}, - {"1.2.840.113549.1.1.12", "sha384WithRSAEncryption"}, - {"1.2.840.113549.1.1.13", "sha512WithRSAEncryption"}, - {"1.2.840.113549.1.1.14", "sha224WithRSAEncryption"}, - {"1.2.840.113549.1.1.2", "md2WithRSAEncryption"}, - {"1.2.840.113549.1.1.3", "md4WithRSAEncryption"}, - {"1.2.840.113549.1.1.4", "md5WithRSAEncryption"}, - {"1.2.840.113549.1.1.5", "sha1WithRSAEncryption"}, - {"1.2.840.113549.1.1.6", "rsaOAEPEncryptionSET"}, - {"1.2.840.113549.1.1.7", "rsaOAEP"}, - {"1.2.840.113549.1.1.8", "pkcs1-MGF"}, - {"1.2.840.113549.1.1.9", "rsaOAEP-pSpecified"}, - {"1.2.840.113549.1.12", "pkcs-12"}, - {"1.2.840.113549.1.12.1", "pkcs-12-PbeIds"}, - {"1.2.840.113549.1.12.1.1", "pbeWithSHAAnd128BitRC4"}, - {"1.2.840.113549.1.12.1.2", "pbeWithSHAAnd40BitRC4"}, - {"1.2.840.113549.1.12.1.3", "pbeWithSHAAnd3-KeyTripleDES-CBC"}, - {"1.2.840.113549.1.12.1.4", "pbeWithSHAAnd2-KeyTripleDES-CBC"}, - {"1.2.840.113549.1.12.1.5", "pbeWithSHAAnd128BitRC2-CBC"}, - {"1.2.840.113549.1.12.1.6", "pbeWithSHAAnd40BitRC2-CBC"}, - {"1.2.840.113549.1.12.10", "pkcs-12Version1"}, - {"1.2.840.113549.1.12.10.1", "pkcs-12BadIds"}, - {"1.2.840.113549.1.12.10.1.1", "pkcs-12-keyBag"}, - {"1.2.840.113549.1.12.10.1.2", "pkcs-12-pkcs-8ShroudedKeyBag"}, - {"1.2.840.113549.1.12.10.1.3", "pkcs-12-certBag"}, - {"1.2.840.113549.1.12.10.1.4", "pkcs-12-crlBag"}, - {"1.2.840.113549.1.12.10.1.5", "pkcs-12-secretBag"}, - {"1.2.840.113549.1.12.10.1.6", "pkcs-12-safeContentsBag"}, - {"1.2.840.113549.1.12.2", "pkcs-12-ESPVKID"}, - {"1.2.840.113549.1.12.2.1", "pkcs-12-PKCS8KeyShrouding"}, - {"1.2.840.113549.1.12.3", "pkcs-12-BagIds"}, - {"1.2.840.113549.1.12.3.1", "pkcs-12-keyBagId"}, - {"1.2.840.113549.1.12.3.2", "pkcs-12-certAndCRLBagId"}, - {"1.2.840.113549.1.12.3.3", "pkcs-12-secretBagId"}, - {"1.2.840.113549.1.12.3.4", "pkcs-12-safeContentsId"}, - {"1.2.840.113549.1.12.3.5", "pkcs-12-pkcs-8ShroudedKeyBagId"}, - {"1.2.840.113549.1.12.4", "pkcs-12-CertBagID"}, - {"1.2.840.113549.1.12.4.1", "pkcs-12-X509CertCRLBagID"}, - {"1.2.840.113549.1.12.4.2", "pkcs-12-SDSICertBagID"}, - {"1.2.840.113549.1.12.5", "pkcs-12-OID"}, - {"1.2.840.113549.1.12.5.1", "pkcs-12-PBEID"}, - {"1.2.840.113549.1.12.5.1.1", "pkcs-12-PBEWithSha1And128BitRC4"}, - {"1.2.840.113549.1.12.5.1.2", "pkcs-12-PBEWithSha1And40BitRC4"}, - {"1.2.840.113549.1.12.5.1.3", "pkcs-12-PBEWithSha1AndTripleDESCBC"}, - {"1.2.840.113549.1.12.5.1.4", "pkcs-12-PBEWithSha1And128BitRC2CBC"}, - {"1.2.840.113549.1.12.5.1.5", "pkcs-12-PBEWithSha1And40BitRC2CBC"}, - {"1.2.840.113549.1.12.5.1.6", "pkcs-12-PBEWithSha1AndRC4"}, - {"1.2.840.113549.1.12.5.1.7", "pkcs-12-PBEWithSha1AndRC2CBC"}, - {"1.2.840.113549.1.12.5.2", "pkcs-12-EnvelopingID"}, - {"1.2.840.113549.1.12.5.2.1", "pkcs-12-RSAEncryptionWith128BitRC4"}, - {"1.2.840.113549.1.12.5.2.2", "pkcs-12-RSAEncryptionWith40BitRC4"}, - {"1.2.840.113549.1.12.5.2.3", "pkcs-12-RSAEncryptionWithTripleDES"}, - {"1.2.840.113549.1.12.5.3", "pkcs-12-SignatureID"}, - {"1.2.840.113549.1.12.5.3.1", "pkcs-12-RSASignatureWithSHA1Digest"}, - {"1.2.840.113549.1.15.1", "pkcs15modules"}, - {"1.2.840.113549.1.15.2", "pkcs15attributes"}, - {"1.2.840.113549.1.15.3", "pkcs15contentType"}, - {"1.2.840.113549.1.15.3.1", "pkcs15content"}, - {"1.2.840.113549.1.2", "bsafeRsaEncr"}, - {"1.2.840.113549.1.3", "pkcs-3"}, - {"1.2.840.113549.1.3.1", "dhKeyAgreement"}, - {"1.2.840.113549.1.5", "pkcs-5"}, - {"1.2.840.113549.1.5.1", "pbeWithMD2AndDES-CBC"}, - {"1.2.840.113549.1.5.10", "pbeWithSHAAndDES-CBC"}, - {"1.2.840.113549.1.5.12", "pkcs5PBKDF2"}, - {"1.2.840.113549.1.5.13", "pkcs5PBES2"}, - {"1.2.840.113549.1.5.14", "pkcs5PBMAC1"}, - {"1.2.840.113549.1.5.3", "pbeWithMD5AndDES-CBC"}, - {"1.2.840.113549.1.5.4", "pbeWithMD2AndRC2-CBC"}, - {"1.2.840.113549.1.5.6", "pbeWithMD5AndRC2-CBC"}, - {"1.2.840.113549.1.5.9", "pbeWithMD5AndXOR"}, - {"1.2.840.113549.1.7", "pkcs-7"}, - {"1.2.840.113549.1.7.1", "pkcs-7-data"}, - {"1.2.840.113549.1.7.2", "pkcs-7-signedData"}, - {"1.2.840.113549.1.7.3", "pkcs-7-envelopedData"}, - {"1.2.840.113549.1.7.4", "pkcs-7-signedAndEnvelopedData"}, - {"1.2.840.113549.1.7.5", "pkcs-7-digestedData"}, - {"1.2.840.113549.1.7.6", "pkcs-7-encryptedData"}, - {"1.2.840.113549.1.7.7", "pkcs-7-dataWithAttributes"}, - {"1.2.840.113549.1.7.8", "pkcs-7-encryptedPrivateKeyInfo"}, - {"1.2.840.113549.1.9", "pkcs-9"}, - {"1.2.840.113549.1.9.1", "emailAddress"}, - {"1.2.840.113549.1.9.10", "issuerAndSerialNumber"}, - {"1.2.840.113549.1.9.11", "passwordCheck"}, - {"1.2.840.113549.1.9.12", "publicKey"}, - {"1.2.840.113549.1.9.13", "signingDescription"}, - {"1.2.840.113549.1.9.14", "extensionRequest"}, - {"1.2.840.113549.1.9.15", "sMIMECapabilities"}, - {"1.2.840.113549.1.9.15.1", "preferSignedData"}, - {"1.2.840.113549.1.9.15.2", "canNotDecryptAny"}, - {"1.2.840.113549.1.9.15.3", "receiptRequest"}, - {"1.2.840.113549.1.9.15.4", "receipt"}, - {"1.2.840.113549.1.9.15.5", "contentHints"}, - {"1.2.840.113549.1.9.15.6", "mlExpansionHistory"}, - {"1.2.840.113549.1.9.16", "id-sMIME"}, - {"1.2.840.113549.1.9.16.0", "id-mod"}, - {"1.2.840.113549.1.9.16.0.1", "id-mod-cms"}, - {"1.2.840.113549.1.9.16.0.2", "id-mod-ess"}, - {"1.2.840.113549.1.9.16.0.3", "id-mod-oid"}, - {"1.2.840.113549.1.9.16.0.4", "id-mod-msg-v3"}, - {"1.2.840.113549.1.9.16.0.5", "id-mod-ets-eSignature-88"}, - {"1.2.840.113549.1.9.16.0.6", "id-mod-ets-eSignature-97"}, - {"1.2.840.113549.1.9.16.0.7", "id-mod-ets-eSigPolicy-88"}, - {"1.2.840.113549.1.9.16.0.8", "id-mod-ets-eSigPolicy-88"}, - {"1.2.840.113549.1.9.16.1", "contentType"}, - {"1.2.840.113549.1.9.16.1.1", "receipt"}, - {"1.2.840.113549.1.9.16.1.10", "scvpCertValRequest"}, - {"1.2.840.113549.1.9.16.1.11", "scvpCertValResponse"}, - {"1.2.840.113549.1.9.16.1.12", "scvpValPolRequest"}, - {"1.2.840.113549.1.9.16.1.13", "scvpValPolResponse"}, - {"1.2.840.113549.1.9.16.1.14", "attrCertEncAttrs"}, - {"1.2.840.113549.1.9.16.1.15", "tSReq"}, - {"1.2.840.113549.1.9.16.1.16", "firmwarePackage"}, - {"1.2.840.113549.1.9.16.1.17", "firmwareLoadReceipt"}, - {"1.2.840.113549.1.9.16.1.18", "firmwareLoadError"}, - {"1.2.840.113549.1.9.16.1.19", "contentCollection"}, - {"1.2.840.113549.1.9.16.1.2", "authData"}, - {"1.2.840.113549.1.9.16.1.20", "contentWithAttrs"}, - {"1.2.840.113549.1.9.16.1.21", "encKeyWithID"}, - {"1.2.840.113549.1.9.16.1.22", "encPEPSI"}, - {"1.2.840.113549.1.9.16.1.23", "authEnvelopedData"}, - {"1.2.840.113549.1.9.16.1.24", "routeOriginAttest"}, - {"1.2.840.113549.1.9.16.1.25", "symmetricKeyPackage"}, - {"1.2.840.113549.1.9.16.1.26", "rpkiManifest"}, - {"1.2.840.113549.1.9.16.1.27", "asciiTextWithCRLF"}, - {"1.2.840.113549.1.9.16.1.28", "xml"}, - {"1.2.840.113549.1.9.16.1.29", "pdf"}, - {"1.2.840.113549.1.9.16.1.3", "publishCert"}, - {"1.2.840.113549.1.9.16.1.30", "postscript"}, - {"1.2.840.113549.1.9.16.1.31", "timestampedData"}, - {"1.2.840.113549.1.9.16.1.32", "asAdjacencyAttest"}, - {"1.2.840.113549.1.9.16.1.33", "rpkiTrustAnchor"}, - {"1.2.840.113549.1.9.16.1.34", "trustAnchorList"}, - {"1.2.840.113549.1.9.16.1.4", "tSTInfo"}, - {"1.2.840.113549.1.9.16.1.5", "tDTInfo"}, - {"1.2.840.113549.1.9.16.1.6", "contentInfo"}, - {"1.2.840.113549.1.9.16.1.7", "dVCSRequestData"}, - {"1.2.840.113549.1.9.16.1.8", "dVCSResponseData"}, - {"1.2.840.113549.1.9.16.1.9", "compressedData"}, - {"1.2.840.113549.1.9.16.11", "capabilities"}, - {"1.2.840.113549.1.9.16.11.1", "preferBinaryInside"}, - {"1.2.840.113549.1.9.16.2", "authenticatedAttributes"}, - {"1.2.840.113549.1.9.16.2.1", "receiptRequest"}, - {"1.2.840.113549.1.9.16.2.10", "contentReference"}, - {"1.2.840.113549.1.9.16.2.11", "encrypKeyPref"}, - {"1.2.840.113549.1.9.16.2.12", "signingCertificate"}, - {"1.2.840.113549.1.9.16.2.13", "smimeEncryptCerts"}, - {"1.2.840.113549.1.9.16.2.14", "timeStampToken"}, - {"1.2.840.113549.1.9.16.2.15", "sigPolicyId"}, - {"1.2.840.113549.1.9.16.2.16", "commitmentType"}, - {"1.2.840.113549.1.9.16.2.17", "signerLocation"}, - {"1.2.840.113549.1.9.16.2.18", "signerAttr"}, - {"1.2.840.113549.1.9.16.2.19", "otherSigCert"}, - {"1.2.840.113549.1.9.16.2.2", "securityLabel"}, - {"1.2.840.113549.1.9.16.2.20", "contentTimestamp"}, - {"1.2.840.113549.1.9.16.2.21", "certificateRefs"}, - {"1.2.840.113549.1.9.16.2.22", "revocationRefs"}, - {"1.2.840.113549.1.9.16.2.23", "certValues"}, - {"1.2.840.113549.1.9.16.2.24", "revocationValues"}, - {"1.2.840.113549.1.9.16.2.25", "escTimeStamp"}, - {"1.2.840.113549.1.9.16.2.26", "certCRLTimestamp"}, - {"1.2.840.113549.1.9.16.2.27", "archiveTimeStamp"}, - {"1.2.840.113549.1.9.16.2.28", "signatureType"}, - {"1.2.840.113549.1.9.16.2.29", "dvcsDvc"}, - {"1.2.840.113549.1.9.16.2.3", "mlExpandHistory"}, - {"1.2.840.113549.1.9.16.2.30", "cekReference"}, - {"1.2.840.113549.1.9.16.2.31", "maxCEKDecrypts"}, - {"1.2.840.113549.1.9.16.2.32", "kekDerivationAlg"}, - {"1.2.840.113549.1.9.16.2.33", "intendedRecipients"}, - {"1.2.840.113549.1.9.16.2.34", "cmcUnsignedData"}, - {"1.2.840.113549.1.9.16.2.35", "fwPackageID"}, - {"1.2.840.113549.1.9.16.2.36", "fwTargetHardwareIDs"}, - {"1.2.840.113549.1.9.16.2.37", "fwDecryptKeyID"}, - {"1.2.840.113549.1.9.16.2.38", "fwImplCryptAlgs"}, - {"1.2.840.113549.1.9.16.2.39", "fwWrappedFirmwareKey"}, - {"1.2.840.113549.1.9.16.2.4", "contentHint"}, - {"1.2.840.113549.1.9.16.2.40", "fwCommunityIdentifiers"}, - {"1.2.840.113549.1.9.16.2.41", "fwPkgMessageDigest"}, - {"1.2.840.113549.1.9.16.2.42", "fwPackageInfo"}, - {"1.2.840.113549.1.9.16.2.43", "fwImplCompressAlgs"}, - {"1.2.840.113549.1.9.16.2.44", "etsAttrCertificateRefs"}, - {"1.2.840.113549.1.9.16.2.45", "etsAttrRevocationRefs"}, - {"1.2.840.113549.1.9.16.2.46", "binarySigningTime"}, - {"1.2.840.113549.1.9.16.2.47", "signingCertificateV2"}, - {"1.2.840.113549.1.9.16.2.48", "etsArchiveTimeStampV2"}, - {"1.2.840.113549.1.9.16.2.49", "erInternal"}, - {"1.2.840.113549.1.9.16.2.5", "msgSigDigest"}, - {"1.2.840.113549.1.9.16.2.50", "erExternal"}, - {"1.2.840.113549.1.9.16.2.51", "multipleSignatures"}, - {"1.2.840.113549.1.9.16.2.6", "encapContentType"}, - {"1.2.840.113549.1.9.16.2.7", "contentIdentifier"}, - {"1.2.840.113549.1.9.16.2.8", "macValue"}, - {"1.2.840.113549.1.9.16.2.9", "equivalentLabels"}, - {"1.2.840.113549.1.9.16.3.1", "esDHwith3DES"}, - {"1.2.840.113549.1.9.16.3.10", "ssDH"}, - {"1.2.840.113549.1.9.16.3.11", "hmacWith3DESwrap"}, - {"1.2.840.113549.1.9.16.3.12", "hmacWithAESwrap"}, - {"1.2.840.113549.1.9.16.3.13", "md5XorExperiment"}, - {"1.2.840.113549.1.9.16.3.14", "rsaKEM"}, - {"1.2.840.113549.1.9.16.3.15", "authEnc128"}, - {"1.2.840.113549.1.9.16.3.16", "authEnc256"}, - {"1.2.840.113549.1.9.16.3.2", "esDHwithRC2"}, - {"1.2.840.113549.1.9.16.3.3", "3desWrap"}, - {"1.2.840.113549.1.9.16.3.4", "rc2Wrap"}, - {"1.2.840.113549.1.9.16.3.5", "esDH"}, - {"1.2.840.113549.1.9.16.3.6", "cms3DESwrap"}, - {"1.2.840.113549.1.9.16.3.7", "cmsRC2wrap"}, - {"1.2.840.113549.1.9.16.3.8", "zlib"}, - {"1.2.840.113549.1.9.16.3.9", "pwriKEK"}, - {"1.2.840.113549.1.9.16.4.1", "certDist-ldap"}, - {"1.2.840.113549.1.9.16.5.1", "sigPolicyQualifier-spuri.x"}, - {"1.2.840.113549.1.9.16.5.2", "sigPolicyQualifier-spUserNotice"}, - {"1.2.840.113549.1.9.16.6.1", "proofOfOrigin"}, - {"1.2.840.113549.1.9.16.6.2", "proofOfReceipt"}, - {"1.2.840.113549.1.9.16.6.3", "proofOfDelivery"}, - {"1.2.840.113549.1.9.16.6.4", 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{"2.16.840.1.101.3.2", "pki"}, - {"2.16.840.1.101.3.2.1", "NIST.policyIdentifier"}, - {"2.16.840.1.101.3.2.1.3.1", "fbcaRudimentaryPolicy"}, - {"2.16.840.1.101.3.2.1.3.2", "fbcaBasicPolicy"}, - {"2.16.840.1.101.3.2.1.3.3", "fbcaMediumPolicy"}, - {"2.16.840.1.101.3.2.1.3.4", "fbcaHighPolicy"}, - {"2.16.840.1.101.3.2.1.48.1", "nistTestPolicy1"}, - {"2.16.840.1.101.3.2.1.48.2", "nistTestPolicy2"}, - {"2.16.840.1.101.3.2.1.48.3", "nistTestPolicy3"}, - {"2.16.840.1.101.3.2.1.48.4", "nistTestPolicy4"}, - {"2.16.840.1.101.3.2.1.48.5", "nistTestPolicy5"}, - {"2.16.840.1.101.3.2.1.48.6", "nistTestPolicy6"}, - {"2.16.840.1.101.3.2.2", "gak"}, - {"2.16.840.1.101.3.2.2.1", "kRAKey"}, - {"2.16.840.1.101.3.2.3", "extensions"}, - {"2.16.840.1.101.3.2.3.1", "kRTechnique"}, - {"2.16.840.1.101.3.2.3.2", "kRecoveryCapable"}, - {"2.16.840.1.101.3.2.3.3", "kR"}, - {"2.16.840.1.101.3.2.4", "keyRecoverySchemes"}, - {"2.16.840.1.101.3.2.5", "krapola"}, - {"2.16.840.1.101.3.3", "arpa"}, - {"2.16.840.1.101.3.4", "nistAlgorithm"}, - {"2.16.840.1.101.3.4.1", "aes"}, - {"2.16.840.1.101.3.4.1.1", "aes128-ECB"}, - {"2.16.840.1.101.3.4.1.2", "aes128-CBC"}, - {"2.16.840.1.101.3.4.1.21", "aes192-ECB"}, - {"2.16.840.1.101.3.4.1.22", "aes192-CBC"}, - {"2.16.840.1.101.3.4.1.23", "aes192-OFB"}, - {"2.16.840.1.101.3.4.1.24", "aes192-CFB"}, - {"2.16.840.1.101.3.4.1.25", "aes192-wrap"}, - {"2.16.840.1.101.3.4.1.26", "aes192-GCM"}, - {"2.16.840.1.101.3.4.1.27", "aes192-CCM"}, - {"2.16.840.1.101.3.4.1.28", "aes192-wrap-pad"}, - {"2.16.840.1.101.3.4.1.3", "aes128-OFB"}, - {"2.16.840.1.101.3.4.1.4", "aes128-CFB"}, - {"2.16.840.1.101.3.4.1.41", "aes256-ECB"}, - {"2.16.840.1.101.3.4.1.42", "aes256-CBC"}, - {"2.16.840.1.101.3.4.1.43", "aes256-OFB"}, - {"2.16.840.1.101.3.4.1.44", "aes256-CFB"}, - {"2.16.840.1.101.3.4.1.45", "aes256-wrap"}, - {"2.16.840.1.101.3.4.1.46", "aes256-GCM"}, - {"2.16.840.1.101.3.4.1.47", "aes256-CCM"}, - {"2.16.840.1.101.3.4.1.48", "aes256-wrap-pad"}, - {"2.16.840.1.101.3.4.1.5", "aes128-wrap"}, - {"2.16.840.1.101.3.4.1.6", "aes128-GCM"}, - {"2.16.840.1.101.3.4.1.7", "aes128-CCM"}, - {"2.16.840.1.101.3.4.1.8", "aes128-wrap-pad"}, - {"2.16.840.1.101.3.4.2", "hashAlgos"}, - {"2.16.840.1.101.3.4.2.1", "sha-256"}, - {"2.16.840.1.101.3.4.2.2", "sha-384"}, - {"2.16.840.1.101.3.4.2.3", "sha-512"}, - {"2.16.840.1.101.3.4.2.4", "sha-224"}, - {"2.16.840.1.101.3.4.3.1", "dsaWithSha224"}, - {"2.16.840.1.101.3.4.3.2", "dsaWithSha256"}, - {"2.16.840.1.113719.1.2.8", "novellAlgorithm"}, - {"2.16.840.1.113719.1.2.8.130", "md4Packet"}, - {"2.16.840.1.113719.1.2.8.131", "rsaEncryptionBsafe1"}, - {"2.16.840.1.113719.1.2.8.132", "nwPassword"}, - {"2.16.840.1.113719.1.2.8.133", "novellObfuscate-1"}, - {"2.16.840.1.113719.1.2.8.22", "desCbcIV8"}, - {"2.16.840.1.113719.1.2.8.23", "desCbcPadIV8"}, - {"2.16.840.1.113719.1.2.8.24", "desEDE2CbcIV8"}, - {"2.16.840.1.113719.1.2.8.25", "desEDE2CbcPadIV8"}, - {"2.16.840.1.113719.1.2.8.26", "desEDE3CbcIV8"}, - {"2.16.840.1.113719.1.2.8.27", "desEDE3CbcPadIV8"}, - {"2.16.840.1.113719.1.2.8.28", "rc5CbcPad"}, - {"2.16.840.1.113719.1.2.8.29", "md2WithRSAEncryptionBSafe1"}, - {"2.16.840.1.113719.1.2.8.30", "md5WithRSAEncryptionBSafe1"}, - {"2.16.840.1.113719.1.2.8.31", "sha1WithRSAEncryptionBSafe1"}, - {"2.16.840.1.113719.1.2.8.32", "lmDigest"}, - {"2.16.840.1.113719.1.2.8.40", "md2"}, - {"2.16.840.1.113719.1.2.8.50", "md5"}, - {"2.16.840.1.113719.1.2.8.51", "ikeHmacWithSHA1-RSA"}, - {"2.16.840.1.113719.1.2.8.52", "ikeHmacWithMD5-RSA"}, - {"2.16.840.1.113719.1.2.8.69", "rc2CbcPad"}, - {"2.16.840.1.113719.1.2.8.82", "sha-1"}, - {"2.16.840.1.113719.1.2.8.92", "rc2BSafe1Cbc"}, - {"2.16.840.1.113719.1.2.8.95", "md4"}, - {"2.16.840.1.113719.1.9", "pki"}, - {"2.16.840.1.113719.1.9.4", "pkiAttributeType"}, - {"2.16.840.1.113719.1.9.4.1", "securityAttributes"}, - {"2.16.840.1.113719.1.9.4.2", "relianceLimit"}, - {"2.16.840.1.113730", "netscape" }, - {"2.16.840.1.113730.1", "cert-extension"}, - {"2.16.840.1.113730.1.1", "netscape-cert-type"}, - {"2.16.840.1.113730.1.10", "EntityLogo"}, - {"2.16.840.1.113730.1.11", "UserPicture"}, - {"2.16.840.1.113730.1.12", "netscape-ssl-server-name"}, - {"2.16.840.1.113730.1.13", "netscape-comment"}, - {"2.16.840.1.113730.1.2", "netscape-base-url"}, - {"2.16.840.1.113730.1.3", "netscape-revocation-url"}, - {"2.16.840.1.113730.1.4", "netscape-ca-revocation-url"}, - {"2.16.840.1.113730.1.7", "netscape-cert-renewal-url"}, - {"2.16.840.1.113730.1.8", "netscape-ca-policy-url"}, - {"2.16.840.1.113730.1.9", "HomePage-url"}, - {"2.16.840.1.113730.2", "data-type"}, - {"2.16.840.1.113730.2.1", "dataGIF"}, - {"2.16.840.1.113730.2.2", "dataJPEG"}, - {"2.16.840.1.113730.2.3", "dataURL"}, - {"2.16.840.1.113730.2.4", "dataHTML"}, - {"2.16.840.1.113730.2.5", "certSequence"}, - {"2.16.840.1.113730.2.6", "certURL"}, - {"2.16.840.1.113730.3", "directory"}, - {"2.16.840.1.113730.3.1", "ldapDefinitions"}, - {"2.16.840.1.113730.3.1.1", "carLicense"}, - {"2.16.840.1.113730.3.1.2", "departmentNumber"}, - {"2.16.840.1.113730.3.1.3", "employeeNumber"}, - {"2.16.840.1.113730.3.1.4", "employeeType"}, - {"2.16.840.1.113730.3.2.2", "inetOrgPerson"}, - {"2.16.840.1.113730.4.1", "serverGatedCrypto"}, - {"2.16.840.1.113733.1", "pki"}, - {"2.16.840.1.113733.1.9", "pkcs7Attribute"}, - {"2.16.840.1.113733.1.9.2", "messageType"}, - {"2.16.840.1.113733.1.9.3", "pkiStatus"}, - {"2.16.840.1.113733.1.9.4", "failInfo"}, - {"2.16.840.1.113733.1.9.5", "senderNonce"}, - {"2.16.840.1.113733.1.9.6", "recipientNonce"}, - {"2.16.840.1.113733.1.9.7", "transID"}, - {"2.16.840.1.113733.1.9.8", "extensionReq"}, - {"2.16.840.1.113741.2", "intelCDSA"}, - {"2.16.840.1.114027.10.4", "entrustAdminServicesClients" }, - {"2.16.840.1.114027.10.5", "entrustAdminServicesServer" }, - {"2.16.840.1.114027.80.2.1", "id-PKIXCMP-stdECDHwithX963SHA1" }, - {"2.16.840.1.114027.80.2.1", "id-PKIXCMP-stdECDHwithX963SHA1" }, - {"2.16.840.1.114412.1", "digiCertNonEVCerts"}, - {"2.16.840.1.114412.1.1", "digiCertOVCert"}, - {"2.16.840.1.114412.1.11", "digiCertFederatedDeviceCert"}, - {"2.16.840.1.114412.1.2", "digiCertDVCert"}, - {"2.16.840.1.114412.1.3.0.1", "digiCertGlobalCAPolicy"}, - {"2.16.840.1.114412.1.3.0.2", "digiCertHighAssuranceEVCAPolicy"}, - {"2.16.840.1.114412.1.3.0.3", "digiCertGlobalRootCAPolicy"}, - {"2.16.840.1.114412.1.3.0.4", "digiCertAssuredIDRootCAPolicy"}, - {"2.16.840.1.114412.2.2", "digiCertEVCert"}, - {"2.16.840.1.114412.2.3", "digiCertObjectSigningCert"}, - {"2.16.840.1.114412.2.3.1", "digiCertCodeSigningCert"}, - {"2.16.840.1.114412.2.3.11", "digiCertKernelCodeSigningCert"}, - {"2.16.840.1.114412.2.3.2", "digiCertEVCodeSigningCert"}, - {"2.16.840.1.114412.2.3.21", "digiCertDocumentSigningCert"}, - {"2.16.840.1.114412.2.4", "digiCertClientCert"}, - {"2.16.840.1.114412.2.4.1.1", "digiCertLevel1PersonalClientCert"}, - {"2.16.840.1.114412.2.4.1.2", "digiCertLevel1EnterpriseClientCert"}, - {"2.16.840.1.114412.2.4.2", "digiCertLevel2ClientCert"}, - {"2.16.840.1.114412.2.4.3.1", "digiCertLevel3USClientCert"}, - {"2.16.840.1.114412.2.4.3.2", "digiCertLevel3CBPClientCert"}, - {"2.16.840.1.114412.2.4.4.1", "digiCertLevel4USClientCert"}, - {"2.16.840.1.114412.2.4.4.2", "digiCertLevel4CBPClientCert"}, - {"2.16.840.1.114412.2.4.5.1", "digiCertPIVHardwareCert"}, - {"2.16.840.1.114412.2.4.5.2", "digiCertPIVCardAuthCert"}, - {"2.16.840.1.114412.2.4.5.3", "digiCertPIVContentSigningCert"}, - {"2.16.840.1.114412.31.4.31.1", "digiCertGridHostCert"}, - {"2.16.840.1.114412.4.31", "digiCertGridClassicCert"}, - {"2.16.840.1.114412.4.31.5", "digiCertGridIntegratedCert"}, - {"2.23.133", "tCPA"}, - {"2.23.133.1", "tcpaSpecVersion"}, - {"2.23.133.2", "tcpaAttribute"}, - {"2.23.133.2.1", "tcpaTpmManufacturer"}, - {"2.23.133.2.10", "tcpaSecurityQualities"}, - {"2.23.133.2.11", "tcpaTpmProtectionProfile"}, - {"2.23.133.2.12", "tcpaTpmSecurityTarget"}, - {"2.23.133.2.13", "tcpaFoundationProtectionProfile"}, - {"2.23.133.2.14", "tcpaFoundationSecurityTarget"}, - {"2.23.133.2.15", "tcpaTpmIdLabel"}, - {"2.23.133.2.2", "tcpaTpmModel"}, - {"2.23.133.2.3", "tcpaTpmVersion"}, - {"2.23.133.2.4", "tcpaPlatformManufacturer"}, - {"2.23.133.2.5", "tcpaPlatformModel"}, - {"2.23.133.2.6", "tcpaPlatformVersion"}, - {"2.23.133.2.7", "tcpaComponentManufacturer"}, - {"2.23.133.2.8", "tcpaComponentModel"}, - {"2.23.133.2.9", "tcpaComponentVersion"}, - {"2.23.133.3", "tcpaProtocol"}, - {"2.23.133.3.1", "tcpaPrttTpmIdProtocol"}, - {"2.23.134.1.2.1.8.210", "postSignumCommercialServerPolicy"}, - {"2.23.134.1.2.2.3", "postSignumPublicCA."}, - {"2.23.134.1.4.2.1", "postSignumRootQCA.."}, - {"2.23.136.1.1.1", "mRTDSignatureData"}, - {"2.23.136.1.1.3", "id-icao-cscaMasterListSigningKey" }, - {"2.23.42.0", "contentType"}, - {"2.23.42.0.0", "panData"}, - {"2.23.42.0.1", "panToken"}, - {"2.23.42.0.2", "panOnly"}, - {"2.23.42.1", "msgExt"}, - {"2.23.42.10", "national"}, - {"2.23.42.10.392", "Japan"}, - {"2.23.42.2", "field"}, - {"2.23.42.2.0", "fullName"}, - {"2.23.42.2.1", "givenName"}, - {"2.23.42.2.10", "amount"}, - {"2.23.42.2.11", "accountNumber"}, - {"2.23.42.2.12", "passPhrase"}, - {"2.23.42.2.2", "familyName"}, - {"2.23.42.2.3", "birthFamilyName"}, - {"2.23.42.2.4", "placeName"}, - {"2.23.42.2.5", "identificationNumber"}, - {"2.23.42.2.6", "month"}, - {"2.23.42.2.7", "date"}, - {"2.23.42.2.7.11", "accountNumber" }, - {"2.23.42.2.7.12", "passPhrase" }, - {"2.23.42.2.8", "address"}, - {"2.23.42.2.9", "telephone"}, - {"2.23.42.3", "attribute"}, - {"2.23.42.3.0", "cert"}, - {"2.23.42.3.0.0", "rootKeyThumb"}, - {"2.23.42.3.0.1", "additionalPolicy"}, - {"2.23.42.4", "algorithm"}, - {"2.23.42.5", "policy"}, - {"2.23.42.5.0", "root"}, - {"2.23.42.6", "module"}, - {"2.23.42.7", "certExt"}, - {"2.23.42.7.0", "hashedRootKey"}, - {"2.23.42.7.1", "certificateType"}, - {"2.23.42.7.2", "merchantData"}, - {"2.23.42.7.3", "cardCertRequired"}, - {"2.23.42.7.4", "tunneling"}, - {"2.23.42.7.5", "setExtensions"}, - {"2.23.42.7.6", "setQualifier"}, - {"2.23.42.8", "brand"}, - {"2.23.42.8.1", "IATA-ATA"}, - {"2.23.42.8.30", "Diners"}, - {"2.23.42.8.34", "AmericanExpress"}, - {"2.23.42.8.4", "VISA"}, - {"2.23.42.8.5", "MasterCard"}, - {"2.23.42.8.6011", "Novus"}, - {"2.23.42.9", "vendor"}, - {"2.23.42.9.0", "GlobeSet"}, - {"2.23.42.9.1", "IBM"}, - {"2.23.42.9.10", "Griffin"}, - {"2.23.42.9.11", "Certicom"}, - {"2.23.42.9.12", "OSS"}, - {"2.23.42.9.13", "TenthMountain"}, - {"2.23.42.9.14", "Antares"}, - {"2.23.42.9.15", "ECC"}, - {"2.23.42.9.16", "Maithean"}, - {"2.23.42.9.17", "Netscape"}, - {"2.23.42.9.18", "Verisign"}, - {"2.23.42.9.19", "BlueMoney"}, - {"2.23.42.9.2", "CyberCash"}, - {"2.23.42.9.20", "Lacerte"}, - {"2.23.42.9.21", "Fujitsu"}, - {"2.23.42.9.22", "eLab"}, - {"2.23.42.9.23", "Entrust"}, - {"2.23.42.9.24", "VIAnet"}, - {"2.23.42.9.25", "III"}, - {"2.23.42.9.26", "OpenMarket"}, - {"2.23.42.9.27", "Lexem"}, - {"2.23.42.9.28", "Intertrader"}, - {"2.23.42.9.29", "Persimmon"}, - {"2.23.42.9.3", "Terisa"}, - {"2.23.42.9.30", "NABLE"}, - {"2.23.42.9.31", "espace-net"}, - {"2.23.42.9.32", "Hitachi"}, - {"2.23.42.9.33", "Microsoft"}, - {"2.23.42.9.34", "NEC"}, - {"2.23.42.9.35", "Mitsubishi"}, - {"2.23.42.9.36", "NCR"}, - {"2.23.42.9.37", "e-COMM"}, - {"2.23.42.9.38", "Gemplus"}, - {"2.23.42.9.4", "RSADSI"}, - {"2.23.42.9.5", "VeriFone"}, - {"2.23.42.9.6", "TrinTech"}, - {"2.23.42.9.7", "BankGate"}, - {"2.23.42.9.8", "GTE"}, - {"2.23.42.9.9", "CompuSource"}, - {"2.23.43.1.4", "wTLS-ECC"}, - {"2.23.43.1.4.1", "wTLS-ECC-curve1"}, - {"2.23.43.1.4.6", "wTLS-ECC-curve6"}, - {"2.23.43.1.4.8", "wTLS-ECC-curve8"}, - {"2.23.43.1.4.9", "wTLS-ECC-curve9"}, - {"2.5.29.1", "authorityKeyIdentifier"}, - {"2.5.29.10", "basicConstraints"}, - {"2.5.29.11", "nameConstraints"}, - {"2.5.29.12", "policyConstraints"}, - {"2.5.29.13", "basicConstraints"}, - {"2.5.29.14", "subjectKeyIdentifier"}, - {"2.5.29.15", "keyUsage"}, - {"2.5.29.16", "privateKeyUsagePeriod"}, - {"2.5.29.17", "subjectAltName"}, - {"2.5.29.18", "issuerAltName"}, - {"2.5.29.19", "basicConstraints"}, - {"2.5.29.2", "keyAttributes"}, - {"2.5.29.20", "cRLNumber"}, - {"2.5.29.21", "cRLReason"}, - {"2.5.29.22", "expirationDate"}, - {"2.5.29.23", "instructionCode"}, - {"2.5.29.24", "invalidityDate"}, - {"2.5.29.25", "cRLDistributionPoints"}, - {"2.5.29.26", "issuingDistributionPoint"}, - {"2.5.29.27", "deltaCRLIndicator"}, - {"2.5.29.28", "issuingDistributionPoint"}, - {"2.5.29.29", "certificateIssuer"}, - {"2.5.29.3", "certificatePolicies"}, - {"2.5.29.30", "nameConstraints"}, - {"2.5.29.31", "cRLDistributionPoints"}, - {"2.5.29.32", "certificatePolicies"}, - {"2.5.29.32.0", "anyPolicy"}, - {"2.5.29.33", "policyMappings"}, - {"2.5.29.34", "policyConstraints"}, - {"2.5.29.35", "authorityKeyIdentifier"}, - {"2.5.29.36", "policyConstraints"}, - {"2.5.29.37", "extKeyUsage"}, - {"2.5.29.37.0", "anyExtendedKeyUsage"}, - {"2.5.29.38", "authorityAttributeIdentifier"}, - {"2.5.29.39", "roleSpecCertIdentifier"}, - {"2.5.29.4", "keyUsageRestriction"}, - {"2.5.29.40", "cRLStreamIdentifier"}, - {"2.5.29.41", "basicAttConstraints"}, - {"2.5.29.42", "delegatedNameConstraints"}, - {"2.5.29.43", "timeSpecification"}, - {"2.5.29.44", "cRLScope"}, - {"2.5.29.45", "statusReferrals"}, - {"2.5.29.46", "freshestCRL"}, - {"2.5.29.47", "orderedList"}, - {"2.5.29.48", "attributeDescriptor"}, - {"2.5.29.49", "userNotice"}, - {"2.5.29.5", "policyMapping"}, - {"2.5.29.50", "sOAIdentifier"}, - {"2.5.29.51", "baseUpdateTime"}, - {"2.5.29.52", "acceptableCertPolicies"}, - {"2.5.29.53", "deltaInfo"}, - {"2.5.29.54", "inhibitAnyPolicy"}, - {"2.5.29.55", "targetInformation"}, - {"2.5.29.56", "noRevAvail"}, - {"2.5.29.57", "acceptablePrivilegePolicies"}, - {"2.5.29.58", "toBeRevoked"}, - {"2.5.29.59", "revokedGroups"}, - {"2.5.29.6", "subtreesConstraint"}, - {"2.5.29.60", "expiredCertsOnCRL"}, - {"2.5.29.61", "indirectIssuer"}, - {"2.5.29.62", "noAssertion"}, - {"2.5.29.63", "aAissuingDistributionPoint"}, - {"2.5.29.64", "issuedOnBehalfOf"}, - {"2.5.29.65", "singleUse"}, - {"2.5.29.66", "groupAC"}, - {"2.5.29.67", "allowedAttAss"}, - {"2.5.29.68", "attributeMappings"}, - {"2.5.29.69", "holderNameConstraints"}, - {"2.5.29.7", "subjectAltName"}, - {"2.5.29.8", "issuerAltName"}, - {"2.5.29.9", "subjectDirectoryAttributes"}, - {"2.5.4.0", "objectClass"}, - {"2.5.4.1", "aliasedEntryName"}, - {"2.5.4.10", "organizationName"}, - {"2.5.4.10.1", "collectiveOrganizationName"}, - {"2.5.4.11", "organizationalUnitName"}, - {"2.5.4.11.1", "collectiveOrganizationalUnitName"}, - {"2.5.4.12", "title"}, - {"2.5.4.13", "description"}, - {"2.5.4.14", "searchGuide"}, - {"2.5.4.15", "businessCategory"}, - {"2.5.4.16", "postalAddress"}, - {"2.5.4.16.1", "collectivePostalAddress"}, - {"2.5.4.17", "postalCode"}, - {"2.5.4.17.1", "collectivePostalCode"}, - {"2.5.4.18", "postOfficeBox"}, - {"2.5.4.18.1", "collectivePostOfficeBox"}, - {"2.5.4.19", "physicalDeliveryOfficeName"}, - {"2.5.4.19.1", "collectivePhysicalDeliveryOfficeName"}, - {"2.5.4.2", "knowledgeInformation"}, - {"2.5.4.20", "telephoneNumber"}, - {"2.5.4.20.1", "collectiveTelephoneNumber"}, - {"2.5.4.21", "telexNumber"}, - {"2.5.4.21.1", "collectiveTelexNumber"}, - {"2.5.4.22", "teletexTerminalIdentifier"}, - {"2.5.4.22.1", "collectiveTeletexTerminalIdentifier"}, - {"2.5.4.23", "facsimileTelephoneNumber"}, - {"2.5.4.23.1", "collectiveFacsimileTelephoneNumber"}, - {"2.5.4.24", "x121Address"}, - {"2.5.4.25", "internationalISDNNumber"}, - {"2.5.4.25.1", "collectiveInternationalISDNNumber"}, - {"2.5.4.26", "registeredAddress"}, - {"2.5.4.27", "destinationIndicator"}, - {"2.5.4.28", "preferredDeliveryMehtod"}, - {"2.5.4.29", "presentationAddress"}, - {"2.5.4.3", "commonName"}, - {"2.5.4.30", "supportedApplicationContext"}, - {"2.5.4.31", "member"}, - {"2.5.4.32", "owner"}, - {"2.5.4.33", "roleOccupant"}, - {"2.5.4.34", "seeAlso"}, - {"2.5.4.35", "userPassword"}, - {"2.5.4.36", "userCertificate"}, - {"2.5.4.37", "caCertificate"}, - {"2.5.4.38", "authorityRevocationList"}, - {"2.5.4.39", "certificateRevocationList"}, - {"2.5.4.4", "surname"}, - {"2.5.4.40", "crossCertificatePair"}, - {"2.5.4.41", "name"}, - {"2.5.4.42", "givenName"}, - {"2.5.4.43", "initials"}, - {"2.5.4.44", "generationQualifier"}, - {"2.5.4.45", "uniqueIdentifier"}, - {"2.5.4.46", "dnQualifier"}, - {"2.5.4.47", "enhancedSearchGuide"}, - {"2.5.4.48", "protocolInformation"}, - {"2.5.4.49", "distinguishedName"}, - {"2.5.4.5", "serialNumber"}, - {"2.5.4.50", "uniqueMember"}, - {"2.5.4.51", "houseIdentifier"}, - {"2.5.4.52", "supportedAlgorithms"}, - {"2.5.4.53", "deltaRevocationList"}, - {"2.5.4.54", "dmdName"}, - {"2.5.4.55", "clearance"}, - {"2.5.4.56", "defaultDirQop"}, - {"2.5.4.57", "attributeIntegrityInfo"}, - {"2.5.4.58", "attributeCertificate"}, - {"2.5.4.59", "attributeCertificateRevocationList"}, - {"2.5.4.6", "countryName"}, - {"2.5.4.60", "confKeyInfo"}, - {"2.5.4.61", "aACertificate"}, - {"2.5.4.62", "attributeDescriptorCertificate"}, - {"2.5.4.63", "attributeAuthorityRevocationList"}, - {"2.5.4.64", "familyInformation"}, - {"2.5.4.65", "pseudonym"}, - {"2.5.4.66", "communicationsService"}, - {"2.5.4.67", "communicationsNetwork"}, - {"2.5.4.68", "certificationPracticeStmt"}, - {"2.5.4.69", "certificatePolicy"}, - {"2.5.4.7", "localityName"}, - {"2.5.4.7.1", "collectiveLocalityName"}, - {"2.5.4.70", "pkiPath"}, - {"2.5.4.71", "privPolicy"}, - {"2.5.4.72", "role"}, - {"2.5.4.73", "delegationPath"}, - {"2.5.4.74", "protPrivPolicy"}, - {"2.5.4.75", "xMLPrivilegeInfo"}, - {"2.5.4.76", "xmlPrivPolicy"}, - {"2.5.4.8", "stateOrProvinceName"}, - {"2.5.4.8.1", "collectiveStateOrProvinceName"}, - {"2.5.4.82", "permission"}, - {"2.5.4.9", "streetAddress"}, - {"2.5.4.9.1", "collectiveStreetAddress"}, - {"2.5.6.0", "top"}, - {"2.5.6.1", "alias"}, - {"2.5.6.10", "residentialPerson"}, - {"2.5.6.11", "applicationProcess"}, - {"2.5.6.12", "applicationEntity"}, - {"2.5.6.13", "dSA"}, - {"2.5.6.14", "device"}, - {"2.5.6.15", "strongAuthenticationUser"}, - {"2.5.6.16", "certificateAuthority"}, - {"2.5.6.17", "groupOfUniqueNames"}, - {"2.5.6.19", "cRLDistributionPoint" }, - {"2.5.6.2", "country"}, - {"2.5.6.21", "pkiUser"}, - {"2.5.6.22", "pkiCA"}, - {"2.5.6.3", "locality"}, - {"2.5.6.4", "organization"}, - {"2.5.6.5", "organizationalUnit"}, - {"2.5.6.6", "person"}, - {"2.5.6.7", "organizationalPerson"}, - {"2.5.6.8", "organizationalRole"}, - {"2.5.6.9", "groupOfNames"}, - {"2.5.8", "X.500-Algorithms" }, - {"2.5.8.1", "X.500-Alg-Encryption" }, - {"2.5.8.1.1", "rsa"}, - {"2.5.8.2.1", "sqMod_n" }, - {"2.5.8.3.1", "sqMod_nWithRSA" }, - {"2.54.1775.2", "hashedRootKey"}, - {"2.54.1775.3", "certificateType"}, - {"2.54.1775.4", "merchantData"}, - {"2.54.1775.5", "cardCertRequired"}, - {"2.54.1775.6", "tunneling"}, - {"2.54.1775.7", "setQualifier"}, - {"2.54.1775.99", "setData"}, + { "0.2.262.1.10", "Telesec" }, + { "0.2.262.1.10.0", "extension" }, + { "0.2.262.1.10.1", "mechanism" }, + { "0.2.262.1.10.1.0", "authentication" }, + { "0.2.262.1.10.1.0.1", "passwordAuthentication" }, + { "0.2.262.1.10.1.0.2", "protectedPasswordAuthentication" }, + { "0.2.262.1.10.1.0.3", "oneWayX509Authentication" }, + { "0.2.262.1.10.1.0.4", "twoWayX509Authentication" }, + { "0.2.262.1.10.1.0.5", "threeWayX509Authentication" }, + { "0.2.262.1.10.1.0.6", "oneWayISO9798Authentication" }, + { "0.2.262.1.10.1.0.7", "twoWayISO9798Authentication" }, + { "0.2.262.1.10.1.0.8", "telekomAuthentication" }, + { "0.2.262.1.10.1.1", "signature" }, + { "0.2.262.1.10.1.1.1", "md4WithRSAAndISO9697" }, + { "0.2.262.1.10.1.1.2", "md4WithRSAAndTelesecSignatureStandard" }, + { "0.2.262.1.10.1.1.3", "md5WithRSAAndISO9697" }, + { "0.2.262.1.10.1.1.4", "md5WithRSAAndTelesecSignatureStandard" }, + { "0.2.262.1.10.1.1.5", "ripemd160WithRSAAndTelekomSignatureStandard" }, + { "0.2.262.1.10.1.1.9", "hbciRsaSignature" }, + { "0.2.262.1.10.1.2", "encryption" }, + { "0.2.262.1.10.1.2.0", "none" }, + { "0.2.262.1.10.1.2.1", "rsaTelesec" }, + { "0.2.262.1.10.1.2.2", "des" }, + { "0.2.262.1.10.1.2.2.1", "desECB" }, + { "0.2.262.1.10.1.2.2.2", "desCBC" }, + { "0.2.262.1.10.1.2.2.3", "desOFB" }, + { "0.2.262.1.10.1.2.2.4", "desCFB8" }, + { "0.2.262.1.10.1.2.2.5", "desCFB64" }, + { "0.2.262.1.10.1.2.3", "des3" }, + { "0.2.262.1.10.1.2.3.1", "des3ECB" }, + { "0.2.262.1.10.1.2.3.2", "des3CBC" }, + { "0.2.262.1.10.1.2.3.3", "des3OFB" }, + { "0.2.262.1.10.1.2.3.4", "des3CFB8" }, + { "0.2.262.1.10.1.2.3.5", "des3CFB64" }, + { "0.2.262.1.10.1.2.4", "magenta" }, + { "0.2.262.1.10.1.2.5", "idea" }, + { "0.2.262.1.10.1.2.5.1", "ideaECB" }, + { "0.2.262.1.10.1.2.5.2", "ideaCBC" }, + { "0.2.262.1.10.1.2.5.3", "ideaOFB" }, + { "0.2.262.1.10.1.2.5.4", "ideaCFB8" }, + { "0.2.262.1.10.1.2.5.5", "ideaCFB64" }, + { "0.2.262.1.10.1.3", "oneWayFunction" }, + { "0.2.262.1.10.1.3.1", "md4" }, + { "0.2.262.1.10.1.3.2", "md5" }, + { "0.2.262.1.10.1.3.3", "sqModNX509" }, + { "0.2.262.1.10.1.3.4", "sqModNISO" }, + { "0.2.262.1.10.1.3.5", "ripemd128" }, + { "0.2.262.1.10.1.3.6", "hashUsingBlockCipher" }, + { "0.2.262.1.10.1.3.7", "mac" }, + { "0.2.262.1.10.1.3.8", "ripemd160" }, + { "0.2.262.1.10.1.4", "fecFunction" }, + { "0.2.262.1.10.1.4.1", "reedSolomon" }, + { "0.2.262.1.10.10", "notification" }, + { "0.2.262.1.10.11", "snmp-mibs" }, + { "0.2.262.1.10.11.1", "securityApplication" }, + { "0.2.262.1.10.12", "certAndCrlExtensionDefinitions" }, + { "0.2.262.1.10.12.0", "liabilityLimitationFlag" }, + { "0.2.262.1.10.12.1", "telesecCertIdExt" }, + { "0.2.262.1.10.12.2", "Telesec.policyIdentifier" }, + { "0.2.262.1.10.12.3", "telesecPolicyQualifierID" }, + { "0.2.262.1.10.12.4", "telesecCRLFilteredExt" }, + { "0.2.262.1.10.12.5", "telesecCRLFilterExt" }, + { "0.2.262.1.10.12.6", "telesecNamingAuthorityExt" }, + { "0.2.262.1.10.2", "module" }, + { "0.2.262.1.10.2.0", "algorithms" }, + { "0.2.262.1.10.2.1", "attributeTypes" }, + { "0.2.262.1.10.2.10", "electronicOrder" }, + { "0.2.262.1.10.2.11", "telesecTtpAsymmetricApplication" }, + { "0.2.262.1.10.2.12", "telesecTtpBasisApplication" }, + { "0.2.262.1.10.2.13", "telesecTtpMessages" }, + { "0.2.262.1.10.2.14", "telesecTtpTimeStampApplication" }, + { "0.2.262.1.10.2.2", "certificateTypes" }, + { "0.2.262.1.10.2.3", "messageTypes" }, + { "0.2.262.1.10.2.4", "plProtocol" }, + { "0.2.262.1.10.2.5", "smeAndComponentsOfSme" }, + { "0.2.262.1.10.2.6", "fec" }, + { "0.2.262.1.10.2.7", "usefulDefinitions" }, + { "0.2.262.1.10.2.8", "stefiles" }, + { "0.2.262.1.10.2.9", "sadmib" }, + { "0.2.262.1.10.3", "objectClass" }, + { "0.2.262.1.10.3.0", "telesecOtherName" }, + { "0.2.262.1.10.3.1", "directory" }, + { "0.2.262.1.10.3.2", "directoryType" }, + { "0.2.262.1.10.3.3", "directoryGroup" }, + { "0.2.262.1.10.3.4", "directoryUser" }, + { "0.2.262.1.10.3.5", "symmetricKeyEntry" }, + { "0.2.262.1.10.4", "package" }, + { "0.2.262.1.10.5", "parameter" }, + { "0.2.262.1.10.6", "nameBinding" }, + { "0.2.262.1.10.7", "attribute" }, + { "0.2.262.1.10.7.0", "applicationGroupIdentifier" }, + { "0.2.262.1.10.7.1", "certificateType" }, + { "0.2.262.1.10.7.10", "subject" }, + { "0.2.262.1.10.7.11", "timeOfRevocation" }, + { "0.2.262.1.10.7.12", "userGroupReference" }, + { "0.2.262.1.10.7.13", "validity" }, + { "0.2.262.1.10.7.14", "zert93" }, + { "0.2.262.1.10.7.15", "securityMessEnv" }, + { "0.2.262.1.10.7.16", "anonymizedPublicKeyDirectory" }, + { "0.2.262.1.10.7.17", "telesecGivenName" }, + { "0.2.262.1.10.7.18", "nameAdditions" }, + { "0.2.262.1.10.7.19", "telesecPostalCode" }, + { "0.2.262.1.10.7.2", "telesecCertificate" }, + { "0.2.262.1.10.7.20", "nameDistinguisher" }, + { "0.2.262.1.10.7.21", "telesecCertificateList" }, + { "0.2.262.1.10.7.22", "teletrustCertificateList" }, + { "0.2.262.1.10.7.23", "x509CertificateList" }, + { "0.2.262.1.10.7.24", "timeOfIssue" }, + { "0.2.262.1.10.7.25", "physicalCardNumber" }, + { "0.2.262.1.10.7.26", "fileType" }, + { "0.2.262.1.10.7.27", "ctlFileIsArchive" }, + { "0.2.262.1.10.7.28", "emailAddress" }, + { "0.2.262.1.10.7.29", "certificateTemplateList" }, + { "0.2.262.1.10.7.3", "certificateNumber" }, + { "0.2.262.1.10.7.30", "directoryName" }, + { "0.2.262.1.10.7.31", "directoryTypeName" }, + { "0.2.262.1.10.7.32", "directoryGroupName" }, + { "0.2.262.1.10.7.33", "directoryUserName" }, + { "0.2.262.1.10.7.34", "revocationFlag" }, + { "0.2.262.1.10.7.35", "symmetricKeyEntryName" }, + { "0.2.262.1.10.7.36", "glNumber" }, + { "0.2.262.1.10.7.37", "goNumber" }, + { "0.2.262.1.10.7.38", "gKeyData" }, + { "0.2.262.1.10.7.39", "zKeyData" }, + { "0.2.262.1.10.7.4", "certificateRevocationList" }, + { "0.2.262.1.10.7.40", "ktKeyData" }, + { "0.2.262.1.10.7.41", "ktKeyNumber" }, + { "0.2.262.1.10.7.5", "creationDate" }, + { "0.2.262.1.10.7.51", "timeOfRevocationGen" }, + { "0.2.262.1.10.7.52", "liabilityText" }, + { "0.2.262.1.10.7.6", "issuer" }, + { "0.2.262.1.10.7.7", "namingAuthority" }, + { "0.2.262.1.10.7.8", "publicKeyDirectory" }, + { "0.2.262.1.10.7.9", "securityDomain" }, + { "0.2.262.1.10.8", "attributeGroup" }, + { "0.2.262.1.10.9", "action" }, + { "0.4.0.127.0.7", "bsi" }, + { "0.4.0.127.0.7.1", "bsiEcc" }, + { "0.4.0.127.0.7.1.1", "bsifieldType" }, + { "0.4.0.127.0.7.1.1.1", "bsiPrimeField" }, + { "0.4.0.127.0.7.1.1.2", "bsiCharacteristicTwoField" }, + { "0.4.0.127.0.7.1.1.2.2", "bsiECTLVKeyFormat" }, + { "0.4.0.127.0.7.1.1.2.2.1", "bsiECTLVPublicKey" }, + { "0.4.0.127.0.7.1.1.2.3", "bsiCharacteristicTwoBasis" }, + { "0.4.0.127.0.7.1.1.2.3.1", "bsiGnBasis" }, + { "0.4.0.127.0.7.1.1.2.3.2", "bsiTpBasis" }, + { "0.4.0.127.0.7.1.1.2.3.3", "bsiPpBasis" }, + { "0.4.0.127.0.7.1.1.4.1", "bsiEcdsaSignatures" }, + { "0.4.0.127.0.7.1.1.4.1.1", "bsiEcdsaWithSHA1" }, + { "0.4.0.127.0.7.1.1.4.1.2", "bsiEcdsaWithSHA224" }, + { "0.4.0.127.0.7.1.1.4.1.3", "bsiEcdsaWithSHA256" }, + { "0.4.0.127.0.7.1.1.4.1.4", "bsiEcdsaWithSHA384" }, + { "0.4.0.127.0.7.1.1.4.1.5", "bsiEcdsaWithSHA512" }, + { "0.4.0.127.0.7.1.1.4.1.6", "bsiEcdsaWithRIPEMD160" }, + { "0.4.0.127.0.7.1.1.5.1.1", "bsiEckaEgX963KDF" }, + { "0.4.0.127.0.7.1.1.5.1.1.1", "bsiEckaEgX963KDFWithSHA1" }, + { "0.4.0.127.0.7.1.1.5.1.1.2", "bsiEckaEgX963KDFWithSHA224" }, + { "0.4.0.127.0.7.1.1.5.1.1.3", "bsiEckaEgX963KDFWithSHA256" }, + { "0.4.0.127.0.7.1.1.5.1.1.4", "bsiEckaEgX963KDFWithSHA384" }, + { "0.4.0.127.0.7.1.1.5.1.1.5", "bsiEckaEgX963KDFWithSHA512" }, + { "0.4.0.127.0.7.1.1.5.1.1.6", "bsiEckaEgX963KDFWithRIPEMD160" }, + { "0.4.0.127.0.7.1.1.5.1.2", "bsiEckaEgSessionKDF" }, + { "0.4.0.127.0.7.1.1.5.1.2.1", "bsiEckaEgSessionKDFWith3DES" }, + { "0.4.0.127.0.7.1.1.5.1.2.2", "bsiEckaEgSessionKDFWithAES128" }, + { "0.4.0.127.0.7.1.1.5.1.2.3", "bsiEckaEgSessionKDFWithAES192" }, + { "0.4.0.127.0.7.1.1.5.1.2.4", "bsiEckaEgSessionKDFWithAES256" }, + { "0.4.0.127.0.7.1.1.5.2", "bsiEckaDH" }, + { "0.4.0.127.0.7.1.1.5.2.1", "bsiEckaDHX963KDF" }, + { "0.4.0.127.0.7.1.1.5.2.1.1", "bsiEckaDHX963KDFWithSHA1" }, + { "0.4.0.127.0.7.1.1.5.2.1.2", "bsiEckaDHX963KDFWithSHA224" }, + { "0.4.0.127.0.7.1.1.5.2.1.3", "bsiEckaDHX963KDFWithSHA256" }, + { "0.4.0.127.0.7.1.1.5.2.1.4", "bsiEckaDHX963KDFWithSHA384" }, + { "0.4.0.127.0.7.1.1.5.2.1.5", "bsiEckaDHX963KDFWithSHA512" }, + { "0.4.0.127.0.7.1.1.5.2.1.6", "bsiEckaDHX963KDFWithRIPEMD160" }, + { "0.4.0.127.0.7.1.1.5.2.2", "bsiEckaDHSessionKDF" }, + { "0.4.0.127.0.7.1.1.5.2.2.1", "bsiEckaDHSessionKDFWith3DES" }, + { "0.4.0.127.0.7.1.1.5.2.2.2", "bsiEckaDHSessionKDFWithAES128" }, + { "0.4.0.127.0.7.1.1.5.2.2.3", "bsiEckaDHSessionKDFWithAES192" }, + { "0.4.0.127.0.7.1.1.5.2.2.4", "bsiEckaDHSessionKDFWithAES256" }, + { "0.4.0.127.0.7.1.2", "bsiEcKeyType" }, + { "0.4.0.127.0.7.1.2.1", "bsiEcPublicKey" }, + { "0.4.0.127.0.7.1.5.1", "bsiKaeg" }, + { "0.4.0.127.0.7.1.5.1.1", "bsiKaegWithX963KDF" }, + { "0.4.0.127.0.7.1.5.1.2", "bsiKaegWith3DESKDF" }, + { "0.4.0.127.0.7.2.2.1", "bsiPK" }, + { "0.4.0.127.0.7.2.2.1.1", "bsiPK_DH" }, + { "0.4.0.127.0.7.2.2.1.2", "bsiPK_ECDH" }, + { "0.4.0.127.0.7.2.2.2", "bsiTA" }, + { "0.4.0.127.0.7.2.2.2.1", "bsiTA_RSA" }, + { "0.4.0.127.0.7.2.2.2.1.1", "bsiTA_RSAv1_5_SHA1" }, + { "0.4.0.127.0.7.2.2.2.1.2", "bsiTA_RSAv1_5_SHA256" }, + { "0.4.0.127.0.7.2.2.2.1.3", "bsiTA_RSAPSS_SHA1" }, + { "0.4.0.127.0.7.2.2.2.1.4", "bsiTA_RSAPSS_SHA256" }, + { "0.4.0.127.0.7.2.2.2.1.5", "bsiTA_RSAv1_5_SHA512" }, + { "0.4.0.127.0.7.2.2.2.1.6", "bsiTA_RSAPSS_SHA512" }, + { "0.4.0.127.0.7.2.2.2.2", "bsiTA_ECDSA" }, + { "0.4.0.127.0.7.2.2.2.2.1", "bsiTA_ECDSA_SHA1" }, + { "0.4.0.127.0.7.2.2.2.2.2", "bsiTA_ECDSA_SHA224" }, + { "0.4.0.127.0.7.2.2.2.2.3", "bsiTA_ECDSA_SHA256" }, + { "0.4.0.127.0.7.2.2.2.2.4", "bsiTA_ECDSA_SHA384" }, + { "0.4.0.127.0.7.2.2.2.2.5", "bsiTA_ECDSA_SHA512" }, + { "0.4.0.127.0.7.2.2.3", "bsiCA" }, + { "0.4.0.127.0.7.2.2.3.1", "bsiCA_DH" }, + { "0.4.0.127.0.7.2.2.3.1.1", "bsiCA_DH_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.3.1.2", "bsiCA_DH_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.3.1.3", "bsiCA_DH_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.3.1.4", "bsiCA_DH_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.3.2", "bsiCA_ECDH" }, + { "0.4.0.127.0.7.2.2.3.2.1", "bsiCA_ECDH_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.3.2.2", "bsiCA_ECDH_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.3.2.3", "bsiCA_ECDH_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.3.2.4", "bsiCA_ECDH_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.4", "bsiPACE" }, + { "0.4.0.127.0.7.2.2.4.1", "bsiPACE_DH_GM" }, + { "0.4.0.127.0.7.2.2.4.1.1", "bsiPACE_DH_GM_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.4.1.2", "bsiPACE_DH_GM_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.4.1.3", "bsiPACE_DH_GM_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.4.1.4", "bsiPACE_DH_GM_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.4.2", "bsiPACE_ECDH_GM" }, + { "0.4.0.127.0.7.2.2.4.2.1", "bsiPACE_ECDH_GM_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.4.2.2", "bsiPACE_ECDH_GM_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.4.2.3", "bsiPACE_ECDH_GM_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.4.2.4", "bsiPACE_ECDH_GM_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.4.3", "bsiPACE_DH_IM" }, + { "0.4.0.127.0.7.2.2.4.3.1", "bsiPACE_DH_IM_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.4.3.2", "bsiPACE_DH_IM_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.4.3.3", "bsiPACE_DH_IM_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.4.3.4", "bsiPACE_DH_IM_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.4.4", "bsiPACE_ECDH_IM" }, + { "0.4.0.127.0.7.2.2.4.4.1", "bsiPACE_ECDH_IM_3DES_CBC_CBC" }, + { "0.4.0.127.0.7.2.2.4.4.2", "bsiPACE_ECDH_IM_AES_CBC_CMAC_128" }, + { "0.4.0.127.0.7.2.2.4.4.3", "bsiPACE_ECDH_IM_AES_CBC_CMAC_192" }, + { "0.4.0.127.0.7.2.2.4.4.4", "bsiPACE_ECDH_IM_AES_CBC_CMAC_256" }, + { "0.4.0.127.0.7.2.2.5", "bsiRI" }, + { "0.4.0.127.0.7.2.2.5.1", "bsiRI_DH" }, + { "0.4.0.127.0.7.2.2.5.1.1", "bsiRI_DH_SHA1" }, + { "0.4.0.127.0.7.2.2.5.1.2", "bsiRI_DH_SHA224" }, + { "0.4.0.127.0.7.2.2.5.1.3", "bsiRI_DH_SHA256" }, + { "0.4.0.127.0.7.2.2.5.1.4", "bsiRI_DH_SHA384" }, + { "0.4.0.127.0.7.2.2.5.1.5", "bsiRI_DH_SHA512" }, + { "0.4.0.127.0.7.2.2.5.2", "bsiRI_ECDH" }, + { "0.4.0.127.0.7.2.2.5.2.1", "bsiRI_ECDH_SHA1" }, + { "0.4.0.127.0.7.2.2.5.2.2", "bsiRI_ECDH_SHA224" }, + { "0.4.0.127.0.7.2.2.5.2.3", "bsiRI_ECDH_SHA256" }, + { "0.4.0.127.0.7.2.2.5.2.4", "bsiRI_ECDH_SHA384" }, + { "0.4.0.127.0.7.2.2.5.2.5", "bsiRI_ECDH_SHA512" }, + { "0.4.0.127.0.7.2.2.6", "bsiCardInfo" }, + { "0.4.0.127.0.7.2.2.7", "bsiEidSecurity" }, + { "0.4.0.127.0.7.2.2.8", "bsiPT" }, + { "0.4.0.127.0.7.3.1.2", "bsiEACRoles" }, + { "0.4.0.127.0.7.3.1.2.1", "bsiEACRolesIS" }, + { "0.4.0.127.0.7.3.1.2.2", "bsiEACRolesAT" }, + { "0.4.0.127.0.7.3.1.2.3", "bsiEACRolesST" }, + { "0.4.0.127.0.7.3.1.3", "bsiTAv2ce" }, + { "0.4.0.127.0.7.3.1.3.1", "bsiTAv2ceDescription" }, + { "0.4.0.127.0.7.3.1.3.1.1", "bsiTAv2ceDescriptionPlainText" }, + { "0.4.0.127.0.7.3.1.3.1.2", "bsiTAv2ceDescriptionIA5String" }, + { "0.4.0.127.0.7.3.1.3.1.3", "bsiTAv2ceDescriptionOctetString" }, + { "0.4.0.127.0.7.3.1.3.2", "bsiTAv2ceTerminalSector" }, + { "0.4.0.127.0.7.3.1.4", "bsiAuxData" }, + { "0.4.0.127.0.7.3.1.4.1", "bsiAuxDataBirthday" }, + { "0.4.0.127.0.7.3.1.4.2", "bsiAuxDataExpireDate" }, + { "0.4.0.127.0.7.3.1.4.3", "bsiAuxDataCommunityID" }, + { "0.4.0.127.0.7.3.1.5", "bsiDefectList" }, + { "0.4.0.127.0.7.3.1.5.1", "bsiDefectAuthDefect" }, + { "0.4.0.127.0.7.3.1.5.1.1", "bsiDefectCertRevoked" }, + { "0.4.0.127.0.7.3.1.5.1.2", "bsiDefectCertReplaced" }, + { "0.4.0.127.0.7.3.1.5.1.3", "bsiDefectChipAuthKeyRevoked" }, + { "0.4.0.127.0.7.3.1.5.1.4", "bsiDefectActiveAuthKeyRevoked" }, + { "0.4.0.127.0.7.3.1.5.2", "bsiDefectEPassportDefect" }, + { "0.4.0.127.0.7.3.1.5.2.1", "bsiDefectEPassportDGMalformed" }, + { "0.4.0.127.0.7.3.1.5.2.2", "bsiDefectSODInvalid" }, + { "0.4.0.127.0.7.3.1.5.3", "bsiDefectEIDDefect" }, + { "0.4.0.127.0.7.3.1.5.3.1", "bsiDefectEIDDGMalformed" }, + { "0.4.0.127.0.7.3.1.5.3.2", "bsiDefectEIDIntegrity" }, + { "0.4.0.127.0.7.3.1.5.4", "bsiDefectDocumentDefect" }, + { "0.4.0.127.0.7.3.1.5.4.1", "bsiDefectCardSecurityMalformed" }, + { "0.4.0.127.0.7.3.1.5.4.2", "bsiDefectChipSecurityMalformed" }, + { "0.4.0.127.0.7.3.1.5.4.3", "bsiDefectPowerDownReq" }, + { "0.4.0.127.0.7.3.1.6", "bsiListContentDescription" }, + { "0.4.0.127.0.7.3.2.1", "bsiSecurityObject" }, + { "0.4.0.127.0.7.3.2.2", "bsiBlackList" }, + { "0.4.0.1862", "etsiQcsProfile" }, + { "0.4.0.1862.1", "etsiQcs" }, + { "0.4.0.1862.1.1", "etsiQcsCompliance" }, + { "0.4.0.1862.1.2", "etsiQcsLimitValue" }, + { "0.4.0.1862.1.3", "etsiQcsRetentionPeriod" }, + { "0.4.0.1862.1.4", "etsiQcsQcSSCD" }, + { "0.9.2342.19200300.100.1.1", "userID" }, + { "0.9.2342.19200300.100.1.25", "domainComponent" }, + { "0.9.2342.19200300.100.1.3", "rfc822Mailbox" }, + { "1.0.10118.3.0.49", "ripemd160" }, + { "1.0.10118.3.0.50", "ripemd128" }, + { "1.0.10118.3.0.55", "whirlpool" }, + { "1.2.3.4.9999", "timeStamp" }, + { "1.2.36.1.3.1.1.1", "qgpki" }, + { "1.2.36.1.3.1.1.1.1", "qgpkiPolicies" }, + { "1.2.36.1.3.1.1.1.1.1", "qgpkiMedIntermedCA" }, + { "1.2.36.1.3.1.1.1.1.1.1", "qgpkiMedIntermedIndividual" }, + { "1.2.36.1.3.1.1.1.1.1.2", "qgpkiMedIntermedDeviceControl" }, + { "1.2.36.1.3.1.1.1.1.1.3", "qgpkiMedIntermedDevice" }, + { "1.2.36.1.3.1.1.1.1.1.4", "qgpkiMedIntermedAuthorisedParty" }, + { "1.2.36.1.3.1.1.1.1.1.5", "qgpkiMedIntermedDeviceSystem" }, + { "1.2.36.1.3.1.1.1.1.2", "qgpkiMedIssuingCA" }, + { "1.2.36.1.3.1.1.1.1.2.1", "qgpkiMedIssuingIndividual" }, + { "1.2.36.1.3.1.1.1.1.2.2", "qgpkiMedIssuingDeviceControl" }, + { "1.2.36.1.3.1.1.1.1.2.3", "qgpkiMedIssuingDevice" }, + { "1.2.36.1.3.1.1.1.1.2.4", "qgpkiMedIssuingAuthorisedParty" }, + { "1.2.36.1.3.1.1.1.1.2.5", "qgpkiMedIssuingClientAuth" }, + { "1.2.36.1.3.1.1.1.1.2.6", "qgpkiMedIssuingServerAuth" }, + { "1.2.36.1.3.1.1.1.1.2.7", "qgpkiMedIssuingDataProt" }, + { "1.2.36.1.3.1.1.1.1.2.8", "qgpkiMedIssuingTokenAuth" }, + { "1.2.36.1.3.1.1.1.1.3", "qgpkiBasicIntermedCA" }, + { "1.2.36.1.3.1.1.1.1.3.1", "qgpkiBasicIntermedDeviceSystem" }, + { "1.2.36.1.3.1.1.1.1.4", "qgpkiBasicIssuingCA" }, + { "1.2.36.1.3.1.1.1.1.4.1", "qgpkiBasicIssuingClientAuth" }, + { "1.2.36.1.3.1.1.1.1.4.2", "qgpkiBasicIssuingServerAuth" }, + { "1.2.36.1.3.1.1.1.1.4.3", "qgpkiBasicIssuingDataSigning" }, + { "1.2.36.1.3.1.1.1.2", "qgpkiAssuranceLevel" }, + { "1.2.36.1.3.1.1.1.2.1", "qgpkiAssuranceRudimentary" }, + { "1.2.36.1.3.1.1.1.2.2", "qgpkiAssuranceBasic" }, + { "1.2.36.1.3.1.1.1.2.3", "qgpkiAssuranceMedium" }, + { "1.2.36.1.3.1.1.1.2.4", "qgpkiAssuranceHigh" }, + { "1.2.36.1.3.1.1.1.3", "qgpkiCertFunction" }, + { "1.2.36.1.3.1.1.1.3.1", "qgpkiFunctionIndividual" }, + { "1.2.36.1.3.1.1.1.3.2", "qgpkiFunctionDevice" }, + { "1.2.36.1.3.1.1.1.3.3", "qgpkiFunctionAuthorisedParty" }, + { "1.2.36.1.3.1.1.1.3.4", "qgpkiFunctionDeviceControl" }, + { "1.2.36.1.3.1.2", "qpspki" }, + { "1.2.36.1.3.1.2.1", "qpspkiPolicies" }, + { "1.2.36.1.3.1.2.1.2", "qpspkiPolicyBasic" }, + { "1.2.36.1.3.1.2.1.3", "qpspkiPolicyMedium" }, + { "1.2.36.1.3.1.2.1.4", "qpspkiPolicyHigh" }, + { "1.2.36.1.3.1.3.2", "qtmrpki" }, + { "1.2.36.1.3.1.3.2.1", "qtmrpkiPolicies" }, + { "1.2.36.1.3.1.3.2.2", "qtmrpkiPurpose" }, + { "1.2.36.1.3.1.3.2.2.1", "qtmrpkiIndividual" }, + { "1.2.36.1.3.1.3.2.2.2", "qtmrpkiDeviceControl" }, + { "1.2.36.1.3.1.3.2.2.3", "qtmrpkiDevice" }, + { "1.2.36.1.3.1.3.2.2.4", "qtmrpkiAuthorisedParty" }, + { "1.2.36.1.3.1.3.2.2.5", "qtmrpkiDeviceSystem" }, + { "1.2.36.1.3.1.3.2.3", "qtmrpkiDevice" }, + { "1.2.36.1.3.1.3.2.3.1", "qtmrpkiDriverLicense" }, + { "1.2.36.1.3.1.3.2.3.2", "qtmrpkiIndustryAuthority" }, + { "1.2.36.1.3.1.3.2.3.3", "qtmrpkiMarineLicense" }, + { "1.2.36.1.3.1.3.2.3.4", "qtmrpkiAdultProofOfAge" }, + { "1.2.36.1.3.1.3.2.3.5", "qtmrpkiSam" }, + { "1.2.36.1.3.1.3.2.4", "qtmrpkiAuthorisedParty" }, + { "1.2.36.1.3.1.3.2.4.1", "qtmrpkiTransportInspector" }, + { "1.2.36.1.3.1.3.2.4.2", "qtmrpkiPoliceOfficer" }, + { "1.2.36.1.3.1.3.2.4.3", "qtmrpkiSystem" }, + { "1.2.36.1.3.1.3.2.4.4", "qtmrpkiLiquorLicensingInspector" }, + { "1.2.36.1.3.1.3.2.4.5", "qtmrpkiMarineEnforcementOfficer" }, + { "1.2.36.1.333.1", "australianBusinessNumber" }, + { "1.2.36.68980861.1.1.10", "signetPilot" }, + { "1.2.36.68980861.1.1.11", "signetIntraNet" }, + { "1.2.36.68980861.1.1.2", "signetPersonal" }, + { "1.2.36.68980861.1.1.20", "signetPolicy" }, + { "1.2.36.68980861.1.1.3", "signetBusiness" }, + { "1.2.36.68980861.1.1.4", "signetLegal" }, + { "1.2.36.75878867.1.100.1.1", "certificatesAustraliaPolicy" }, + { "1.2.392.200011.61.1.1.1", "mitsubishiSecurityAlgorithm" }, + { "1.2.392.200011.61.1.1.1.1", "misty1-cbc" }, + { "1.2.410.200004.1", "kisaAlgorithm" }, + { "1.2.410.200004.1.1", "kcdsa" }, + { "1.2.410.200004.1.10", "pbeWithHAS160AndSEED-ECB" }, + { "1.2.410.200004.1.11", "pbeWithHAS160AndSEED-CBC" }, + { "1.2.410.200004.1.12", "pbeWithHAS160AndSEED-CFB" }, + { "1.2.410.200004.1.13", "pbeWithHAS160AndSEED-OFB" }, + { "1.2.410.200004.1.14", "pbeWithSHA1AndSEED-ECB" }, + { "1.2.410.200004.1.15", "pbeWithSHA1AndSEED-CBC" }, + { "1.2.410.200004.1.16", "pbeWithSHA1AndSEED-CFB" }, + { "1.2.410.200004.1.17", "pbeWithSHA1AndSEED-OFB" }, + { "1.2.410.200004.1.2", "has160" }, + { "1.2.410.200004.1.20", "rsaWithHAS160" }, + { "1.2.410.200004.1.21", "kcdsa1" }, + { "1.2.410.200004.1.3", "seedECB" }, + { "1.2.410.200004.1.4", "seedCBC" }, + { "1.2.410.200004.1.5", "seedOFB" }, + { "1.2.410.200004.1.6", "seedCFB" }, + { "1.2.410.200004.1.7", "seedMAC" }, + { "1.2.410.200004.1.8", "kcdsaWithHAS160" }, + { "1.2.410.200004.1.9", "kcdsaWithSHA1" }, + { "1.2.410.200004.10", "npki" }, + { "1.2.410.200004.10.1", "npkiAttribute" }, + { "1.2.410.200004.10.1.1", "npkiIdentifyData" }, + { "1.2.410.200004.10.1.1.1", "npkiVID" }, + { "1.2.410.200004.10.1.1.2", "npkiEncryptedVID" }, + { "1.2.410.200004.10.1.1.3", "npkiRandomNum" }, + { "1.2.410.200004.10.1.1.4", "npkiVID" }, + { "1.2.410.200004.2", "npkiCP" }, + { "1.2.410.200004.2.1", "npkiSignaturePolicy" }, + { "1.2.410.200004.3", "npkiKP" }, + { "1.2.410.200004.4", "npkiAT" }, + { "1.2.410.200004.5", "npkiLCA" }, + { "1.2.410.200004.5.1", "npkiSignKorea" }, + { "1.2.410.200004.5.2", "npkiSignGate" }, + { "1.2.410.200004.5.3", "npkiNcaSign" }, + { "1.2.410.200004.6", "npkiON" }, + { "1.2.410.200004.7", "npkiAPP" }, + { "1.2.410.200004.7.1", "npkiSMIME" }, + { "1.2.410.200004.7.1.1", "npkiSMIMEAlgo" }, + { "1.2.410.200004.7.1.1.1", "npkiCmsSEEDWrap" }, + { "1.2.410.200046.1.1", "aria1AlgorithmModes" }, + { "1.2.410.200046.1.1.1", "aria128-ecb" }, + { "1.2.410.200046.1.1.10", "aria192-ctr" }, + { "1.2.410.200046.1.1.11", "aria256-ecb" }, + { "1.2.410.200046.1.1.12", "aria256-cbc" }, + { "1.2.410.200046.1.1.13", "aria256-cfb" }, + { "1.2.410.200046.1.1.14", "aria256-ofb" }, + { "1.2.410.200046.1.1.15", "aria256-ctr" }, + { "1.2.410.200046.1.1.2", "aria128-cbc" }, + { "1.2.410.200046.1.1.21", "aria128-cmac" }, + { "1.2.410.200046.1.1.22", "aria192-cmac" }, + { "1.2.410.200046.1.1.23", "aria256-cmac" }, + { "1.2.410.200046.1.1.3", "aria128-cfb" }, + { "1.2.410.200046.1.1.31", "aria128-ocb2" }, + { "1.2.410.200046.1.1.32", "aria192-ocb2" }, + { "1.2.410.200046.1.1.33", "aria256-ocb2" }, + { "1.2.410.200046.1.1.34", "aria128-gcm" }, + { "1.2.410.200046.1.1.35", "aria192-gcm" }, + { "1.2.410.200046.1.1.36", "aria256-gcm" }, + { "1.2.410.200046.1.1.37", "aria128-ccm" }, + { "1.2.410.200046.1.1.38", "aria192-ccm" }, + { "1.2.410.200046.1.1.39", "aria256-ccm" }, + { "1.2.410.200046.1.1.4", "aria128-ofb" }, + { "1.2.410.200046.1.1.40", "aria128-keywrap" }, + { "1.2.410.200046.1.1.41", "aria192-keywrap" }, + { "1.2.410.200046.1.1.42", "aria256-keywrap" }, + { "1.2.410.200046.1.1.43", "aria128-keywrapWithPad" }, + { "1.2.410.200046.1.1.44", "aria192-keywrapWithPad" }, + { "1.2.410.200046.1.1.45", "aria256-keywrapWithPad" }, + { "1.2.410.200046.1.1.5", "aria128-ctr" }, + { "1.2.410.200046.1.1.6", "aria192-ecb" }, + { "1.2.410.200046.1.1.7", "aria192-cbc" }, + { "1.2.410.200046.1.1.8", "aria192-cfb" }, + { "1.2.410.200046.1.1.9", "aria192-ofb" }, + { "1.2.643.2.2.10", "hmacGost" }, + { "1.2.643.2.2.13.0", "gostWrap" }, + { "1.2.643.2.2.13.1", "cryptoProWrap" }, + { "1.2.643.2.2.14.0", "nullMeshing" }, + { "1.2.643.2.2.14.1", "cryptoProMeshing" }, + { "1.2.643.2.2.19", "gostPublicKey" }, + { "1.2.643.2.2.20", "gost94PublicKey" }, + { "1.2.643.2.2.21", "gostCipher" }, + { "1.2.643.2.2.3", "gostSignature" }, + { "1.2.643.2.2.30.0", "testDigestParams" }, + { "1.2.643.2.2.30.1", "cryptoProDigestA" }, + { "1.2.643.2.2.31.0", "testCipherParams" }, + { "1.2.643.2.2.31.1", "cryptoProCipherA" }, + { "1.2.643.2.2.31.2", "cryptoProCipherB" }, + { "1.2.643.2.2.31.3", "cryptoProCipherC" }, + { "1.2.643.2.2.31.4", "cryptoProCipherD" }, + { "1.2.643.2.2.31.5", "oscar11Cipher" }, + { "1.2.643.2.2.31.6", "oscar10Cipher" }, + { "1.2.643.2.2.31.7", "ric1Cipher" }, + { "1.2.643.2.2.35.0", "testSignParams" }, + { "1.2.643.2.2.35.1", "cryptoProSignA" }, + { "1.2.643.2.2.35.2", "cryptoProSignB" }, + { "1.2.643.2.2.35.3", "cryptoProSignC" }, + { "1.2.643.2.2.36.0", "cryptoProSignXA" }, + { "1.2.643.2.2.36.1", "cryptoProSignXB" }, + { "1.2.643.2.2.4", "gost94Signature" }, + { "1.2.643.2.2.9", "gostDigest" }, + { "1.2.643.2.2.96", "cryptoProECDHWrap" }, + { "1.2.752.34.1", "seis-cp" }, + { "1.2.752.34.1.1", "SEIS.high-assurance.policyIdentifier" }, + { "1.2.752.34.1.2", "SEIS.GAK.policyIdentifier" }, + { "1.2.752.34.2", "SEIS.pe" }, + { "1.2.752.34.3", "SEIS.at" }, + { "1.2.752.34.3.1", "SEIS.at-personalIdentifier" }, + { "1.2.840.10040.1", "module" }, + { "1.2.840.10040.1.1", "x9f1-cert-mgmt" }, + { "1.2.840.10040.2", "holdinstruction" }, + { "1.2.840.10040.2.1", "holdinstruction-none" }, + { "1.2.840.10040.2.2", "callissuer" }, + { "1.2.840.10040.2.3", "reject" }, + { "1.2.840.10040.2.4", "pickupToken" }, + { "1.2.840.10040.3", "attribute" }, + { "1.2.840.10040.3.1", "countersignature" }, + { "1.2.840.10040.3.2", "attribute-cert" }, + { "1.2.840.10040.4", "algorithm" }, + { "1.2.840.10040.4.1", "dsa" }, + { "1.2.840.10040.4.2", "dsa-match" }, + { "1.2.840.10040.4.3", "dsaWithSha1" }, + { "1.2.840.10045.1", "fieldType" }, + { "1.2.840.10045.1.1", "prime-field" }, + { "1.2.840.10045.1.2", "characteristic-two-field" }, + { "1.2.840.10045.1.2.3", "characteristic-two-basis" }, + { "1.2.840.10045.1.2.3.1", "onBasis" }, + { "1.2.840.10045.1.2.3.2", "tpBasis" }, + { "1.2.840.10045.1.2.3.3", "ppBasis" }, + { "1.2.840.10045.2", "publicKeyType" }, + { "1.2.840.10045.2.1", "ecPublicKey" }, + { "1.2.840.10045.2.2", "ecPublicKeyRestricted" }, + { "1.2.840.10045.3.0.1", "c2pnb163v1" }, + { "1.2.840.10045.3.0.10", "c2pnb208w1" }, + { "1.2.840.10045.3.0.11", "c2tnb239v1" }, + { "1.2.840.10045.3.0.12", "c2tnb239v2" }, + { "1.2.840.10045.3.0.13", "c2tnb239v3" }, + { "1.2.840.10045.3.0.16", "c2pnb272w1" }, + { "1.2.840.10045.3.0.18", "c2tnb359v1" }, + { "1.2.840.10045.3.0.19", "c2pnb368w1" }, + { "1.2.840.10045.3.0.2", "c2pnb163v2" }, + { "1.2.840.10045.3.0.20", "c2tnb431r1" }, + { "1.2.840.10045.3.0.3", "c2pnb163v3" }, + { "1.2.840.10045.3.0.5", "c2tnb191v1" }, + { "1.2.840.10045.3.0.6", "c2tnb191v2" }, + { "1.2.840.10045.3.0.7", "c2tnb191v3" }, + { "1.2.840.10045.3.1.1", "prime192v1" }, + { "1.2.840.10045.3.1.2", "prime192v2" }, + { "1.2.840.10045.3.1.3", "prime192v3" }, + { "1.2.840.10045.3.1.4", "prime239v1" }, + { "1.2.840.10045.3.1.5", "prime239v2" }, + { "1.2.840.10045.3.1.6", "prime239v3" }, + { "1.2.840.10045.3.1.7", "prime256v1" }, + { "1.2.840.10045.4.1", "ecdsaWithSHA1" }, + { "1.2.840.10045.4.2", "ecdsaWithRecommended" }, + { "1.2.840.10045.4.3", "ecdsaWithSpecified" }, + { "1.2.840.10045.4.3.1", "ecdsaWithSHA224" }, + { "1.2.840.10045.4.3.2", "ecdsaWithSHA256" }, + { "1.2.840.10045.4.3.3", "ecdsaWithSHA384" }, + { "1.2.840.10045.4.3.4", "ecdsaWithSHA512" }, + { "1.2.840.10046.1", "fieldType" }, + { "1.2.840.10046.1.1", "gf-prime" }, + { "1.2.840.10046.2", "numberType" }, + { "1.2.840.10046.2.1", "dhPublicKey" }, + { "1.2.840.10046.3", "scheme" }, + { "1.2.840.10046.3.1", "dhStatic" }, + { "1.2.840.10046.3.2", "dhEphem" }, + { "1.2.840.10046.3.3", "dhHybrid1" }, + { "1.2.840.10046.3.4", "dhHybrid2" }, + { "1.2.840.10046.3.5", "mqv2" }, + { "1.2.840.10046.3.6", "mqv1" }, + { "1.2.840.10065.2.2", "?" }, + { "1.2.840.10065.2.3", "healthcareLicense" }, + { "1.2.840.10065.2.3.1.1", "license?" }, + { "1.2.840.10070.", "iec62351" }, + { "1.2.840.10070.8", "iec62351_8" }, + { "1.2.840.10070.8.1", "iecUserRoles" }, + { "1.2.840.113533.7", "nsn" }, + { "1.2.840.113533.7.65", "nsn-ce" }, + { "1.2.840.113533.7.65.0", "entrustVersInfo" }, + { "1.2.840.113533.7.65.1", "clearance" }, + { "1.2.840.113533.7.65.2", "noCRL" }, + { "1.2.840.113533.7.66", "nsn-alg" }, + { "1.2.840.113533.7.66.0", "cast40CBC" }, + { "1.2.840.113533.7.66.1", "cast64CBC" }, + { "1.2.840.113533.7.66.10", "cast5CBC" }, + { "1.2.840.113533.7.66.11", "cast5MAC" }, + { "1.2.840.113533.7.66.12", "pbeWithMD5AndCAST5-CBC" }, + { "1.2.840.113533.7.66.13", "passwordBasedMac" }, + { "1.2.840.113533.7.66.2", "cast64MAC" }, + { "1.2.840.113533.7.66.3", "cast3CBC" }, + { "1.2.840.113533.7.67", "nsn-oc" }, + { "1.2.840.113533.7.67.0", "entrustUser" }, + { "1.2.840.113533.7.67.1", "entrustCA" }, + { "1.2.840.113533.7.68", "nsn-at" }, + { "1.2.840.113533.7.68.0", "entrustCAInfo" }, + { "1.2.840.113533.7.68.10", "attributeCertificate" }, + { "1.2.840.113533.7.68.16", "entrustPwordPolicy" }, + { "1.2.840.113533.7.68.29", "entrustUserRole" }, + { "1.2.840.113533.7.77.0", "entrustRoleMap" }, + { "1.2.840.113533.7.77.1", "entrustPasswordRules" }, + { "1.2.840.113533.7.77.10", "entrustEncKeyType" }, + { "1.2.840.113533.7.77.11", "entrustBusCtrlPolOids" }, + { "1.2.840.113533.7.77.12", "entrustBusCtrlFlags" }, + { "1.2.840.113533.7.77.13", "entrustPCertLifetime" }, + { "1.2.840.113533.7.77.14", "entrustDNEncoding" }, + { "1.2.840.113533.7.77.15", "entrustCertConsistencyChecking" }, + { "1.2.840.113533.7.77.16", "entrustUserEncAlgm" }, + { "1.2.840.113533.7.77.17", "entrustCRLGracePeriod" }, + { "1.2.840.113533.7.77.18", "entrustSkipRLChecks" }, + { "1.2.840.113533.7.77.19", "entrustHTTPProxySetting" }, + { "1.2.840.113533.7.77.20", "entrustOfflineProfileUse" }, + { "1.2.840.113533.7.77.21", "entrustAllowServerLogin" }, + { "1.2.840.113533.7.77.22", "entrustEnforceIdentityUse" }, + { "1.2.840.113533.7.77.23", "entrustAllowPKCS12Export" }, + { "1.2.840.113533.7.77.24", "entrustPKCS12ExportMinimumHashCount" }, + { "1.2.840.113533.7.77.25", "entrustClientNKeyType" }, + { "1.2.840.113533.7.77.26", "entrustAllowed3rdPartySymmetricAlgms" }, + { "1.2.840.113533.7.77.27", "entrustPreventManualAppRegistration" }, + { "1.2.840.113533.7.77.28", "entrustPasswordMaxAttempts" }, + { "1.2.840.113533.7.77.29", "entrustPasswordMinTime" }, + { "1.2.840.113533.7.77.3", "entrustAllowedSymmetricAlgms" }, + { "1.2.840.113533.7.77.30", "entrustPasswordMinSuspend" }, + { "1.2.840.113533.7.77.31", "entrustAllowCAPIExport" }, + { "1.2.840.113533.7.77.32", "entrustICEAdminPolicy" }, + { "1.2.840.113533.7.77.33", "entrustEnableCacheUsage" }, + { "1.2.840.113533.7.77.34", "entrustUserEncAlgm2" }, + { "1.2.840.113533.7.77.35", "entrustSecureDeliveryServiceSMTP" }, + { "1.2.840.113533.7.77.36", "entrustContentScannerServiceSMTP" }, + { "1.2.840.113533.7.77.37", "entrustExpressSearchSourceOrder" }, + { "1.2.840.113533.7.77.38", "entrustCAPIPolicy" }, + { "1.2.840.113533.7.77.39", "entrustSearchbaseSearchOrder" }, + { "1.2.840.113533.7.77.4", "entrustAllowedHashAlgms" }, + { "1.2.840.113533.7.77.40", "entrustCRLGracePercentage" }, + { "1.2.840.113533.7.77.49", "entrustPublicTokenCerts" }, + { "1.2.840.113533.7.77.5", "entrustCSetFlags" }, + { "1.2.840.113533.7.77.50", "entrustProtectKeyTransfer" }, + { "1.2.840.113533.7.77.57", "entrustAllowTokenSpilloverFile" }, + { "1.2.840.113533.7.77.58", "entrustMaximumTokenKeyHistory" }, + { "1.2.840.113533.7.77.59", "entrustSelfRevokePolicy" }, + { "1.2.840.113533.7.77.6", "entrustMessageOfTheDay" }, + { "1.2.840.113533.7.77.60", "entrustAllowPSSwitch" }, + { "1.2.840.113533.7.77.61", "entrustManagementClient" }, + { "1.2.840.113533.7.77.62", "entrustForceOriginalCDPolicyCompliance" }, + { "1.2.840.113533.7.77.63", "entrustAllExportable" }, + { "1.2.840.113533.7.77.64", "entrustProtocolSymmetricEncAlgs" }, + { "1.2.840.113533.7.77.65", "entrustProtocolSigningAlgs" }, + { "1.2.840.113533.7.77.7", "entrustAttrName" }, + { "1.2.840.113533.7.77.8", "entrustApplicationFlags" }, + { "1.2.840.113533.7.77.9", "entrustSignKeyType" }, + { "1.2.840.113549.1.1", "pkcs-1" }, + { "1.2.840.113549.1.1.1", "rsaEncryption" }, + { "1.2.840.113549.1.1.10", "rsaPSS" }, + { "1.2.840.113549.1.1.11", "sha256WithRSAEncryption" }, + { "1.2.840.113549.1.1.12", "sha384WithRSAEncryption" }, + { "1.2.840.113549.1.1.13", "sha512WithRSAEncryption" }, + { "1.2.840.113549.1.1.14", "sha224WithRSAEncryption" }, + { "1.2.840.113549.1.1.2", "md2WithRSAEncryption" }, + { "1.2.840.113549.1.1.3", "md4WithRSAEncryption" }, + { "1.2.840.113549.1.1.4", "md5WithRSAEncryption" }, + { "1.2.840.113549.1.1.5", "sha1WithRSAEncryption" }, + { "1.2.840.113549.1.1.6", "rsaOAEPEncryptionSET" }, + { "1.2.840.113549.1.1.7", "rsaOAEP" }, + { "1.2.840.113549.1.1.8", "pkcs1-MGF" }, + { "1.2.840.113549.1.1.9", "rsaOAEP-pSpecified" }, + { "1.2.840.113549.1.12", "pkcs-12" }, + { "1.2.840.113549.1.12.1", "pkcs-12-PbeIds" }, + { "1.2.840.113549.1.12.1.1", "pbeWithSHAAnd128BitRC4" }, + { "1.2.840.113549.1.12.1.2", "pbeWithSHAAnd40BitRC4" }, + { "1.2.840.113549.1.12.1.3", "pbeWithSHAAnd3-KeyTripleDES-CBC" }, + { "1.2.840.113549.1.12.1.4", "pbeWithSHAAnd2-KeyTripleDES-CBC" }, + { "1.2.840.113549.1.12.1.5", "pbeWithSHAAnd128BitRC2-CBC" }, + { "1.2.840.113549.1.12.1.6", "pbeWithSHAAnd40BitRC2-CBC" }, + { "1.2.840.113549.1.12.10", "pkcs-12Version1" }, + { "1.2.840.113549.1.12.10.1", "pkcs-12BadIds" }, + { "1.2.840.113549.1.12.10.1.1", "pkcs-12-keyBag" }, + { "1.2.840.113549.1.12.10.1.2", "pkcs-12-pkcs-8ShroudedKeyBag" }, + { "1.2.840.113549.1.12.10.1.3", "pkcs-12-certBag" }, + { "1.2.840.113549.1.12.10.1.4", "pkcs-12-crlBag" }, + { "1.2.840.113549.1.12.10.1.5", "pkcs-12-secretBag" }, + { "1.2.840.113549.1.12.10.1.6", "pkcs-12-safeContentsBag" }, + { "1.2.840.113549.1.12.2", "pkcs-12-ESPVKID" }, + { "1.2.840.113549.1.12.2.1", "pkcs-12-PKCS8KeyShrouding" }, + { "1.2.840.113549.1.12.3", "pkcs-12-BagIds" }, + { "1.2.840.113549.1.12.3.1", "pkcs-12-keyBagId" }, + { "1.2.840.113549.1.12.3.2", "pkcs-12-certAndCRLBagId" }, + { "1.2.840.113549.1.12.3.3", "pkcs-12-secretBagId" }, + { "1.2.840.113549.1.12.3.4", "pkcs-12-safeContentsId" }, + { "1.2.840.113549.1.12.3.5", "pkcs-12-pkcs-8ShroudedKeyBagId" }, + { "1.2.840.113549.1.12.4", "pkcs-12-CertBagID" }, + { "1.2.840.113549.1.12.4.1", "pkcs-12-X509CertCRLBagID" }, + { "1.2.840.113549.1.12.4.2", "pkcs-12-SDSICertBagID" }, + { "1.2.840.113549.1.12.5", "pkcs-12-OID" }, + { "1.2.840.113549.1.12.5.1", "pkcs-12-PBEID" }, + { "1.2.840.113549.1.12.5.1.1", "pkcs-12-PBEWithSha1And128BitRC4" }, + { "1.2.840.113549.1.12.5.1.2", "pkcs-12-PBEWithSha1And40BitRC4" }, + { "1.2.840.113549.1.12.5.1.3", "pkcs-12-PBEWithSha1AndTripleDESCBC" }, + { "1.2.840.113549.1.12.5.1.4", "pkcs-12-PBEWithSha1And128BitRC2CBC" }, + { "1.2.840.113549.1.12.5.1.5", "pkcs-12-PBEWithSha1And40BitRC2CBC" }, + { "1.2.840.113549.1.12.5.1.6", "pkcs-12-PBEWithSha1AndRC4" }, + { "1.2.840.113549.1.12.5.1.7", "pkcs-12-PBEWithSha1AndRC2CBC" }, + { "1.2.840.113549.1.12.5.2", "pkcs-12-EnvelopingID" }, + { "1.2.840.113549.1.12.5.2.1", "pkcs-12-RSAEncryptionWith128BitRC4" }, + { "1.2.840.113549.1.12.5.2.2", "pkcs-12-RSAEncryptionWith40BitRC4" }, + { "1.2.840.113549.1.12.5.2.3", "pkcs-12-RSAEncryptionWithTripleDES" }, + { "1.2.840.113549.1.12.5.3", "pkcs-12-SignatureID" }, + { "1.2.840.113549.1.12.5.3.1", "pkcs-12-RSASignatureWithSHA1Digest" }, + { "1.2.840.113549.1.15.1", "pkcs15modules" }, + { "1.2.840.113549.1.15.2", "pkcs15attributes" }, + { "1.2.840.113549.1.15.3", "pkcs15contentType" }, + { "1.2.840.113549.1.15.3.1", "pkcs15content" }, + { "1.2.840.113549.1.2", "bsafeRsaEncr" }, + { "1.2.840.113549.1.3", "pkcs-3" }, + { "1.2.840.113549.1.3.1", "dhKeyAgreement" }, + { "1.2.840.113549.1.5", "pkcs-5" }, + { "1.2.840.113549.1.5.1", "pbeWithMD2AndDES-CBC" }, + { "1.2.840.113549.1.5.10", "pbeWithSHAAndDES-CBC" }, + { "1.2.840.113549.1.5.12", "pkcs5PBKDF2" }, + { "1.2.840.113549.1.5.13", "pkcs5PBES2" }, + { "1.2.840.113549.1.5.14", "pkcs5PBMAC1" }, + { "1.2.840.113549.1.5.3", "pbeWithMD5AndDES-CBC" }, + { "1.2.840.113549.1.5.4", "pbeWithMD2AndRC2-CBC" }, + { "1.2.840.113549.1.5.6", "pbeWithMD5AndRC2-CBC" }, + { "1.2.840.113549.1.5.9", "pbeWithMD5AndXOR" }, + { "1.2.840.113549.1.7", "pkcs-7" }, + { "1.2.840.113549.1.7.1", "pkcs-7-data" }, + { "1.2.840.113549.1.7.2", "pkcs-7-signedData" }, + { "1.2.840.113549.1.7.3", "pkcs-7-envelopedData" }, + { "1.2.840.113549.1.7.4", "pkcs-7-signedAndEnvelopedData" }, + { "1.2.840.113549.1.7.5", "pkcs-7-digestedData" }, + { "1.2.840.113549.1.7.6", "pkcs-7-encryptedData" }, + { "1.2.840.113549.1.7.7", "pkcs-7-dataWithAttributes" }, + { "1.2.840.113549.1.7.8", "pkcs-7-encryptedPrivateKeyInfo" }, + { "1.2.840.113549.1.9", "pkcs-9" }, + { "1.2.840.113549.1.9.1", "emailAddress" }, + { "1.2.840.113549.1.9.10", "issuerAndSerialNumber" }, + { "1.2.840.113549.1.9.11", "passwordCheck" }, + { "1.2.840.113549.1.9.12", "publicKey" }, + { "1.2.840.113549.1.9.13", "signingDescription" }, + { "1.2.840.113549.1.9.14", "extensionRequest" }, + { "1.2.840.113549.1.9.15", "sMIMECapabilities" }, + { "1.2.840.113549.1.9.15.1", "preferSignedData" }, + { "1.2.840.113549.1.9.15.2", "canNotDecryptAny" }, + { "1.2.840.113549.1.9.15.3", "receiptRequest" }, + { "1.2.840.113549.1.9.15.4", "receipt" }, + { "1.2.840.113549.1.9.15.5", "contentHints" }, + { "1.2.840.113549.1.9.15.6", "mlExpansionHistory" }, + { "1.2.840.113549.1.9.16", "id-sMIME" }, + { "1.2.840.113549.1.9.16.0", "id-mod" }, + { "1.2.840.113549.1.9.16.0.1", "id-mod-cms" }, + { "1.2.840.113549.1.9.16.0.2", "id-mod-ess" }, + { "1.2.840.113549.1.9.16.0.3", "id-mod-oid" }, + { "1.2.840.113549.1.9.16.0.4", "id-mod-msg-v3" }, + { "1.2.840.113549.1.9.16.0.5", "id-mod-ets-eSignature-88" }, + { "1.2.840.113549.1.9.16.0.6", "id-mod-ets-eSignature-97" }, + { "1.2.840.113549.1.9.16.0.7", "id-mod-ets-eSigPolicy-88" }, + { "1.2.840.113549.1.9.16.0.8", "id-mod-ets-eSigPolicy-88" }, + { "1.2.840.113549.1.9.16.1", "contentType" }, + { "1.2.840.113549.1.9.16.1.1", "receipt" }, + { "1.2.840.113549.1.9.16.1.10", "scvpCertValRequest" }, + { "1.2.840.113549.1.9.16.1.11", "scvpCertValResponse" }, + { "1.2.840.113549.1.9.16.1.12", "scvpValPolRequest" }, + { "1.2.840.113549.1.9.16.1.13", "scvpValPolResponse" }, + { "1.2.840.113549.1.9.16.1.14", "attrCertEncAttrs" }, + { "1.2.840.113549.1.9.16.1.15", "tSReq" }, + { "1.2.840.113549.1.9.16.1.16", "firmwarePackage" }, + { "1.2.840.113549.1.9.16.1.17", "firmwareLoadReceipt" }, + { "1.2.840.113549.1.9.16.1.18", "firmwareLoadError" }, + { "1.2.840.113549.1.9.16.1.19", "contentCollection" }, + { "1.2.840.113549.1.9.16.1.2", "authData" }, + { "1.2.840.113549.1.9.16.1.20", "contentWithAttrs" }, + { "1.2.840.113549.1.9.16.1.21", "encKeyWithID" }, + { "1.2.840.113549.1.9.16.1.22", "encPEPSI" }, + { "1.2.840.113549.1.9.16.1.23", "authEnvelopedData" }, + { "1.2.840.113549.1.9.16.1.24", "routeOriginAttest" }, + { "1.2.840.113549.1.9.16.1.25", "symmetricKeyPackage" }, + { "1.2.840.113549.1.9.16.1.26", "rpkiManifest" }, + { "1.2.840.113549.1.9.16.1.27", "asciiTextWithCRLF" }, + { "1.2.840.113549.1.9.16.1.28", "xml" }, + { "1.2.840.113549.1.9.16.1.29", "pdf" }, + { "1.2.840.113549.1.9.16.1.3", "publishCert" }, + { "1.2.840.113549.1.9.16.1.30", "postscript" }, + { "1.2.840.113549.1.9.16.1.31", "timestampedData" }, + { "1.2.840.113549.1.9.16.1.32", "asAdjacencyAttest" }, + { "1.2.840.113549.1.9.16.1.33", "rpkiTrustAnchor" }, + { "1.2.840.113549.1.9.16.1.34", "trustAnchorList" }, + { "1.2.840.113549.1.9.16.1.4", "tSTInfo" }, + { "1.2.840.113549.1.9.16.1.5", "tDTInfo" }, + { "1.2.840.113549.1.9.16.1.6", "contentInfo" }, + { "1.2.840.113549.1.9.16.1.7", "dVCSRequestData" }, + { "1.2.840.113549.1.9.16.1.8", "dVCSResponseData" }, + { "1.2.840.113549.1.9.16.1.9", "compressedData" }, + { "1.2.840.113549.1.9.16.11", "capabilities" }, + { "1.2.840.113549.1.9.16.11.1", "preferBinaryInside" }, + { "1.2.840.113549.1.9.16.2", "authenticatedAttributes" }, + { "1.2.840.113549.1.9.16.2.1", "receiptRequest" }, + { "1.2.840.113549.1.9.16.2.10", "contentReference" }, + { "1.2.840.113549.1.9.16.2.11", "encrypKeyPref" }, + { "1.2.840.113549.1.9.16.2.12", "signingCertificate" }, + { "1.2.840.113549.1.9.16.2.13", "smimeEncryptCerts" }, + { "1.2.840.113549.1.9.16.2.14", "timeStampToken" }, + { "1.2.840.113549.1.9.16.2.15", "sigPolicyId" }, + { "1.2.840.113549.1.9.16.2.16", "commitmentType" }, + { "1.2.840.113549.1.9.16.2.17", "signerLocation" }, + { "1.2.840.113549.1.9.16.2.18", "signerAttr" }, + { "1.2.840.113549.1.9.16.2.19", "otherSigCert" }, + { "1.2.840.113549.1.9.16.2.2", "securityLabel" }, + { "1.2.840.113549.1.9.16.2.20", "contentTimestamp" }, + { "1.2.840.113549.1.9.16.2.21", "certificateRefs" }, + { "1.2.840.113549.1.9.16.2.22", "revocationRefs" }, + { "1.2.840.113549.1.9.16.2.23", "certValues" }, + { "1.2.840.113549.1.9.16.2.24", "revocationValues" }, + { "1.2.840.113549.1.9.16.2.25", "escTimeStamp" }, + { "1.2.840.113549.1.9.16.2.26", "certCRLTimestamp" }, + { "1.2.840.113549.1.9.16.2.27", "archiveTimeStamp" }, + { "1.2.840.113549.1.9.16.2.28", "signatureType" }, + { "1.2.840.113549.1.9.16.2.29", "dvcsDvc" }, + { "1.2.840.113549.1.9.16.2.3", "mlExpandHistory" }, + { "1.2.840.113549.1.9.16.2.30", "cekReference" }, + { "1.2.840.113549.1.9.16.2.31", "maxCEKDecrypts" }, + { "1.2.840.113549.1.9.16.2.32", "kekDerivationAlg" }, + { "1.2.840.113549.1.9.16.2.33", "intendedRecipients" }, + { "1.2.840.113549.1.9.16.2.34", "cmcUnsignedData" }, + { "1.2.840.113549.1.9.16.2.35", "fwPackageID" }, + { "1.2.840.113549.1.9.16.2.36", "fwTargetHardwareIDs" }, + { "1.2.840.113549.1.9.16.2.37", "fwDecryptKeyID" }, + { "1.2.840.113549.1.9.16.2.38", "fwImplCryptAlgs" }, + { "1.2.840.113549.1.9.16.2.39", "fwWrappedFirmwareKey" }, + { "1.2.840.113549.1.9.16.2.4", "contentHint" }, + { "1.2.840.113549.1.9.16.2.40", "fwCommunityIdentifiers" }, + { "1.2.840.113549.1.9.16.2.41", "fwPkgMessageDigest" }, + { "1.2.840.113549.1.9.16.2.42", "fwPackageInfo" }, + { "1.2.840.113549.1.9.16.2.43", "fwImplCompressAlgs" }, + { "1.2.840.113549.1.9.16.2.44", "etsAttrCertificateRefs" }, + { "1.2.840.113549.1.9.16.2.45", "etsAttrRevocationRefs" }, + { "1.2.840.113549.1.9.16.2.46", "binarySigningTime" }, + { "1.2.840.113549.1.9.16.2.47", "signingCertificateV2" }, + { "1.2.840.113549.1.9.16.2.48", "etsArchiveTimeStampV2" }, + { "1.2.840.113549.1.9.16.2.49", "erInternal" }, + { "1.2.840.113549.1.9.16.2.5", "msgSigDigest" }, + { "1.2.840.113549.1.9.16.2.50", "erExternal" }, + { "1.2.840.113549.1.9.16.2.51", "multipleSignatures" }, + { "1.2.840.113549.1.9.16.2.6", "encapContentType" }, + { "1.2.840.113549.1.9.16.2.7", "contentIdentifier" }, + { "1.2.840.113549.1.9.16.2.8", "macValue" }, + { "1.2.840.113549.1.9.16.2.9", "equivalentLabels" }, + { "1.2.840.113549.1.9.16.3.1", "esDHwith3DES" }, + { "1.2.840.113549.1.9.16.3.10", "ssDH" }, + { "1.2.840.113549.1.9.16.3.11", "hmacWith3DESwrap" }, + { "1.2.840.113549.1.9.16.3.12", "hmacWithAESwrap" }, + { "1.2.840.113549.1.9.16.3.13", "md5XorExperiment" }, + { "1.2.840.113549.1.9.16.3.14", "rsaKEM" }, + { "1.2.840.113549.1.9.16.3.15", "authEnc128" }, + { "1.2.840.113549.1.9.16.3.16", "authEnc256" }, + { "1.2.840.113549.1.9.16.3.2", "esDHwithRC2" }, + { "1.2.840.113549.1.9.16.3.3", "3desWrap" }, + { "1.2.840.113549.1.9.16.3.4", "rc2Wrap" }, + { "1.2.840.113549.1.9.16.3.5", "esDH" }, + { "1.2.840.113549.1.9.16.3.6", "cms3DESwrap" }, + { "1.2.840.113549.1.9.16.3.7", "cmsRC2wrap" }, + { "1.2.840.113549.1.9.16.3.8", "zlib" }, + { "1.2.840.113549.1.9.16.3.9", "pwriKEK" }, + { "1.2.840.113549.1.9.16.4.1", "certDist-ldap" }, + { "1.2.840.113549.1.9.16.5.1", "sigPolicyQualifier-spuri.x" }, + { "1.2.840.113549.1.9.16.5.2", "sigPolicyQualifier-spUserNotice" }, + { "1.2.840.113549.1.9.16.6.1", "proofOfOrigin" }, + { "1.2.840.113549.1.9.16.6.2", "proofOfReceipt" }, + { "1.2.840.113549.1.9.16.6.3", "proofOfDelivery" }, + { "1.2.840.113549.1.9.16.6.4", "proofOfSender" }, + { "1.2.840.113549.1.9.16.6.5", "proofOfApproval" }, + { "1.2.840.113549.1.9.16.6.6", "proofOfCreation" }, + { "1.2.840.113549.1.9.16.8.1", "glUseKEK" }, + { "1.2.840.113549.1.9.16.8.10", "glFailInfo" }, + { "1.2.840.113549.1.9.16.8.11", "glaQueryRequest" }, + { "1.2.840.113549.1.9.16.8.12", "glaQueryResponse" }, + { "1.2.840.113549.1.9.16.8.13", "glProvideCert" }, + { "1.2.840.113549.1.9.16.8.14", "glUpdateCert" }, + { "1.2.840.113549.1.9.16.8.15", "glKey" }, + { "1.2.840.113549.1.9.16.8.2", "glDelete" }, + { "1.2.840.113549.1.9.16.8.3", "glAddMember" }, + { "1.2.840.113549.1.9.16.8.4", "glDeleteMember" }, + { "1.2.840.113549.1.9.16.8.5", "glRekey" }, + { "1.2.840.113549.1.9.16.8.6", "glAddOwner" }, + { "1.2.840.113549.1.9.16.8.7", "glRemoveOwner" }, + { "1.2.840.113549.1.9.16.8.8", "glkCompromise" }, + { "1.2.840.113549.1.9.16.8.9", "glkRefresh" }, + { "1.2.840.113549.1.9.16.9", "signatureTypeIdentifier" }, + { "1.2.840.113549.1.9.16.9.1", "originatorSig" }, + { "1.2.840.113549.1.9.16.9.2", "domainSig" }, + { "1.2.840.113549.1.9.16.9.3", "additionalAttributesSig" }, + { "1.2.840.113549.1.9.16.9.4", "reviewSig" }, + { "1.2.840.113549.1.9.2", "unstructuredName" }, + { "1.2.840.113549.1.9.20", "friendlyName.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.21", "localKeyID.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.22", "certTypes.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.22.1", "x509Certificate.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.22.2", "sdsiCertificate.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.23", "crlTypes.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.23.1", "x509Crl.(for.PKCS.#12)" }, + { "1.2.840.113549.1.9.24", "pkcs9objectClass" }, + { "1.2.840.113549.1.9.25", "pkcs9attributes" }, + { "1.2.840.113549.1.9.25.1", "pkcs15Token" }, + { "1.2.840.113549.1.9.25.2", "encryptedPrivateKeyInfo" }, + { "1.2.840.113549.1.9.25.3", "randomNonce" }, + { "1.2.840.113549.1.9.25.4", "sequenceNumber" }, + { "1.2.840.113549.1.9.25.5", "pkcs7PDU" }, + { "1.2.840.113549.1.9.26", "pkcs9syntax" }, + { "1.2.840.113549.1.9.27", "pkcs9matchingRules" }, + { "1.2.840.113549.1.9.3", "contentType" }, + { "1.2.840.113549.1.9.4", "messageDigest" }, + { "1.2.840.113549.1.9.5", "signingTime" }, + { "1.2.840.113549.1.9.6", "countersignature" }, + { "1.2.840.113549.1.9.7", "challengePassword" }, + { "1.2.840.113549.1.9.8", "unstructuredAddress" }, + { "1.2.840.113549.1.9.9", "extendedCertificateAttributes" }, + { "1.2.840.113549.2", "digestAlgorithm" }, + { "1.2.840.113549.2.10", "hmacWithSHA384" }, + { "1.2.840.113549.2.11", "hmacWithSHA512" }, + { "1.2.840.113549.2.2", "md2" }, + { "1.2.840.113549.2.4", "md4" }, + { "1.2.840.113549.2.5", "md5" }, + { "1.2.840.113549.2.7", "hmacWithSHA1" }, + { "1.2.840.113549.2.8", "hmacWithSHA224" }, + { "1.2.840.113549.2.9", "hmacWithSHA256" }, + { "1.2.840.113549.3", "encryptionAlgorithm" }, + { "1.2.840.113549.3.10", "desCDMF" }, + { "1.2.840.113549.3.2", "rc2CBC" }, + { "1.2.840.113549.3.3", "rc2ECB" }, + { "1.2.840.113549.3.4", "rc4" }, + { "1.2.840.113549.3.5", "rc4WithMAC" }, + { "1.2.840.113549.3.6", "desx-CBC" }, + { "1.2.840.113549.3.7", "des-EDE3-CBC" }, + { "1.2.840.113549.3.8", "rc5CBC" }, + { "1.2.840.113549.3.9", "rc5-CBCPad" }, + { "1.2.840.113556.1.2.241", "deliveryMechanism" }, + { "1.2.840.113556.1.2.281", "ntSecurityDescriptor" }, + { "1.2.840.113556.1.3.0", "site-Addressing" }, + { "1.2.840.113556.1.3.13", "classSchema" }, + { "1.2.840.113556.1.3.14", "attributeSchema" }, + { "1.2.840.113556.1.3.17", "mailbox-Agent" }, + { "1.2.840.113556.1.3.22", "mailbox" }, + { "1.2.840.113556.1.3.23", "container" }, + { "1.2.840.113556.1.3.46", "mailRecipient" }, + { "1.2.840.113556.1.4.1327", "pKIDefaultKeySpec" }, + { "1.2.840.113556.1.4.1328", "pKIKeyUsage" }, + { "1.2.840.113556.1.4.1329", "pKIMaxIssuingDepth" }, + { "1.2.840.113556.1.4.1330", "pKICriticalExtensions" }, + { "1.2.840.113556.1.4.1331", "pKIExpirationPeriod" }, + { "1.2.840.113556.1.4.1332", "pKIOverlapPeriod" }, + { "1.2.840.113556.1.4.1333", "pKIExtendedKeyUsage" }, + { "1.2.840.113556.1.4.1334", "pKIDefaultCSPs" }, + { "1.2.840.113556.1.4.1335", "pKIEnrollmentAccess" }, + { "1.2.840.113556.1.4.1429", "msPKI-RA-Signature" }, + { "1.2.840.113556.1.4.1430", "msPKI-Enrollment-Flag" }, + { "1.2.840.113556.1.4.1431", "msPKI-Private-Key-Flag" }, + { "1.2.840.113556.1.4.1432", "msPKI-Certificate-Name-Flag" }, + { "1.2.840.113556.1.4.1433", "msPKI-Minimal-Key-Size" }, + { "1.2.840.113556.1.4.1434", "msPKI-Template-Schema-Version" }, + { "1.2.840.113556.1.4.1435", "msPKI-Template-Minor-Revision" }, + { "1.2.840.113556.1.4.1436", "msPKI-Cert-Template-OID" }, + { "1.2.840.113556.1.4.1437", "msPKI-Supersede-Templates" }, + { "1.2.840.113556.1.4.1438", "msPKI-RA-Policies" }, + { "1.2.840.113556.1.4.1439", "msPKI-Certificate-Policy" }, + { "1.2.840.113556.1.4.145", "revision" }, + { "1.2.840.113556.1.4.1674", "msPKI-Certificate-Application-Policy" }, + { "1.2.840.113556.1.4.1675", "msPKI-RA-Application-Policies" }, + { "1.2.840.113556.4.3", "microsoftExcel" }, + { "1.2.840.113556.4.4", "titledWithOID" }, + { "1.2.840.113556.4.5", "microsoftPowerPoint" }, + { "1.2.840.113583.1", "adobeAcrobat" }, + { "1.2.840.113583.1.1", "acrobatSecurity" }, + { "1.2.840.113583.1.1.1", "pdfPassword" }, + { "1.2.840.113583.1.1.10", "pdfPPLKLiteCredential" }, + { "1.2.840.113583.1.1.2", "pdfDefaultSigningCredential" }, + { "1.2.840.113583.1.1.3", "pdfDefaultEncryptionCredential" }, + { "1.2.840.113583.1.1.4", "pdfPasswordTimeout" }, + { "1.2.840.113583.1.1.5", "pdfAuthenticDocumentsTrust" }, + { "1.2.840.113583.1.1.6", "pdfDynamicContentTrust" }, + { "1.2.840.113583.1.1.7", "pdfUbiquityTrust" }, + { "1.2.840.113583.1.1.8", "pdfRevocationInfoArchival" }, + { "1.2.840.113583.1.1.9", "pdfX509Extension" }, + { "1.2.840.113583.1.1.9.1", "pdfTimeStamp" }, + { "1.2.840.113583.1.1.9.2", "pdfArchiveRevInfo" }, + { "1.2.840.113583.1.2.", "acrobatCPS" }, + { "1.2.840.113583.1.2.1", "pdfAuthenticDocumentsCPS" }, + { "1.2.840.113583.1.2.2", "pdfTestCPS" }, + { "1.2.840.113583.1.2.3", "pdfUbiquityCPS" }, + { "1.2.840.113583.1.2.4", "pdfAdhocCPS" }, + { "1.2.840.113583.1.7", "acrobatUbiquity" }, + { "1.2.840.113583.1.7.1", "pdfUbiquitySubRights" }, + { "1.2.840.113583.1.9", "acrobatExtension" }, + { "1.2.840.113628.114.1.7", "adobePKCS7" }, + { "1.2.840.113635.100", "appleDataSecurity" }, + { "1.2.840.113635.100.1", "appleTrustPolicy" }, + { "1.2.840.113635.100.1.1", "appleISignTP" }, + { "1.2.840.113635.100.1.10", "appleSWUpdateSigningPolicy" }, + { "1.2.840.113635.100.1.11", "appleIPSecPolicy" }, + { "1.2.840.113635.100.1.12", "appleIChatPolicy" }, + { "1.2.840.113635.100.1.13", "appleResourceSignPolicy" }, + { "1.2.840.113635.100.1.14", "applePKINITClientPolicy" }, + { "1.2.840.113635.100.1.15", "applePKINITServerPolicy" }, + { "1.2.840.113635.100.1.16", "appleCodeSigningPolicy" }, + { "1.2.840.113635.100.1.17", "applePackageSigningPolicy" }, + { "1.2.840.113635.100.1.2", "appleX509Basic" }, + { "1.2.840.113635.100.1.3", "appleSSLPolicy" }, + { "1.2.840.113635.100.1.4", "appleLocalCertGenPolicy" }, + { "1.2.840.113635.100.1.5", "appleCSRGenPolicy" }, + { "1.2.840.113635.100.1.6", "appleCRLPolicy" }, + { "1.2.840.113635.100.1.7", "appleOCSPPolicy" }, + { "1.2.840.113635.100.1.8", "appleSMIMEPolicy" }, + { "1.2.840.113635.100.1.9", "appleEAPPolicy" }, + { "1.2.840.113635.100.2", "appleSecurityAlgorithm" }, + { "1.2.840.113635.100.2.1", "appleFEE" }, + { "1.2.840.113635.100.2.2", "appleASC" }, + { "1.2.840.113635.100.2.3", "appleFEE_MD5" }, + { "1.2.840.113635.100.2.4", "appleFEE_SHA1" }, + { "1.2.840.113635.100.2.5", "appleFEED" }, + { "1.2.840.113635.100.2.6", "appleFEEDEXP" }, + { "1.2.840.113635.100.2.7", "appleECDSA" }, + { "1.2.840.113635.100.3", "appleDotMacCertificate" }, + { "1.2.840.113635.100.3.1", "appleDotMacCertificateRequest" }, + { "1.2.840.113635.100.3.2", "appleDotMacCertificateExtension" }, + { "1.2.840.113635.100.3.3", "appleDotMacCertificateRequestValues" }, + { "1.2.840.113635.100.4", "appleExtendedKeyUsage" }, + { "1.2.840.113635.100.4.1", "appleCodeSigning" }, + { "1.2.840.113635.100.4.1.1", "appleCodeSigningDevelopment" }, + { "1.2.840.113635.100.4.1.2", "appleSoftwareUpdateSigning" }, + { "1.2.840.113635.100.4.1.3", "appleCodeSigningThirdParty" }, + { "1.2.840.113635.100.4.1.4", "appleResourceSigning" }, + { "1.2.840.113635.100.4.2", "appleIChatSigning" }, + { "1.2.840.113635.100.4.3", "appleIChatEncryption" }, + { "1.2.840.113635.100.4.4", "appleSystemIdentity" }, + { "1.2.840.113635.100.4.5", "appleCryptoEnv" }, + { "1.2.840.113635.100.4.5.1", "appleCryptoProductionEnv" }, + { "1.2.840.113635.100.4.5.2", "appleCryptoMaintenanceEnv" }, + { "1.2.840.113635.100.4.5.3", "appleCryptoTestEnv" }, + { "1.2.840.113635.100.4.5.4", "appleCryptoDevelopmentEnv" }, + { "1.2.840.113635.100.4.6", "appleCryptoQoS" }, + { "1.2.840.113635.100.4.6.1", "appleCryptoTier0QoS" }, + { "1.2.840.113635.100.4.6.2", "appleCryptoTier1QoS" }, + { "1.2.840.113635.100.4.6.3", "appleCryptoTier2QoS" }, + { "1.2.840.113635.100.4.6.4", "appleCryptoTier3QoS" }, + { "1.2.840.113635.100.4.8", "SafariDeveloper" }, + { "1.2.840.113635.100.4.9", "ThirdPartyMacDeveloperInstaller" }, + { "1.2.840.113635.100.4.13", "DeveloperIdInstaller" }, + { "1.2.840.113635.100.5", "appleCertificatePolicies" }, + { "1.2.840.113635.100.5.1", "appleCertificatePolicyID" }, + { "1.2.840.113635.100.5.2", "appleDotMacCertificatePolicyID" }, + { "1.2.840.113635.100.5.3", "appleADCCertificatePolicyID" }, + { "1.2.840.113635.100.6", "appleCertificateExtensions" }, + { "1.2.840.113635.100.6.1", "appleCertificateExtensionCodeSigning" }, + { "1.2.840.113635.100.6.1.1", "appleCertificateExtensionAppleSigning" }, + { "1.2.840.113635.100.6.1.2", "appleCertificateExtensionADCDeveloperSigning" }, + { "1.2.840.113635.100.6.1.3", "appleCertificateExtensionADCAppleSigning" }, + { "1.2.840.113635.100.6.1.4", "appleCertificateSubmission" }, + { "1.2.840.113635.100.6.1.5", "appleSafariDeveloper" }, + { "1.2.840.113635.100.6.1.6", "appleIPhoneOsVpnSigning" }, + { "1.2.840.113635.100.6.1.7", "appleMacAppSigningDevelopment" }, + { "1.2.840.113635.100.6.1.8", "appleMacAppSigningSubmission" }, + { "1.2.840.113635.100.6.1.9", "appleMacAppStoreCodeSigning" }, + { "1.2.840.113635.100.6.1.10", "appleMacAppStoreInstallerSigning" }, + { "1.2.840.113635.100.6.1.12", "appleMacDeveloper" }, + { "1.2.840.113635.100.6.1.13", "appleDeveloperIdApplication" }, + { "1.2.840.113635.100.6.1.33", "appleDeveloperIdDate" }, + { "1.2.840.113635.100.6.1.14", "appleDeveloperIdInstaller" }, + { "1.2.840.113635.100.6.1.16", "applePayPassbookSigning" }, + { "1.2.840.113635.100.6.1.17", "appleWebsitePushNotificationSigning" }, + { "1.2.840.113635.100.6.1.18", "appleDeveloperIdKernel" }, + { "1.2.840.113635.100.6.1.25.1", "appleTestFlight" }, + { "1.2.840.113635.100.6.2.1", "appleWorldwideDeveloperRelations" }, + { "1.2.840.113635.100.6.2.3", "appleApplicationIntegration" }, + { "1.2.840.113635.100.6.2.6", "appleDeveloperId" }, + { "1.2.840.113635.100.6.2.9", "appleTimestamp" }, + { "1.2.840.113635.100.6.2.11", "appleDeveloperAuthentication" }, + { "1.2.840.113635.100.6.2.14", "appleApplicationIntegrationG3" }, + { "1.2.840.113635.100.6.2.15", "appleWorldwideDeveloperRelationsG2" }, + { "1.2.840.113635.100.6.2.19", "appleSoftwareUpdateCertification" }, + { "1.2.840.114021.1.6.1", "Identrus.unknown.policyIdentifier" }, + { "1.2.840.114021.4.1", "identrusOCSP" }, + { "1.3.101.1.4", "thawte-ce" }, + { "1.3.101.1.4.1", "strongExtranet" }, + { "1.3.12.2.1011.7.1", "decEncryptionAlgorithm" }, + { "1.3.12.2.1011.7.1.2", "decDEA" }, + { "1.3.12.2.1011.7.2", "decHashAlgorithm" }, + { "1.3.12.2.1011.7.2.1", "decMD2" }, + { "1.3.12.2.1011.7.2.2", "decMD4" }, + { "1.3.12.2.1011.7.3", "decSignatureAlgorithm" }, + { "1.3.12.2.1011.7.3.1", "decMD2withRSA" }, + { "1.3.12.2.1011.7.3.2", "decMD4withRSA" }, + { "1.3.12.2.1011.7.3.3", "decDEAMAC" }, + { "1.3.132.0.1", "sect163k1" }, + { "1.3.132.0.10", "secp256k1" }, + { "1.3.132.0.15", "sect163r2" }, + { "1.3.132.0.16", "sect283k1" }, + { "1.3.132.0.17", "sect283r1" }, + { "1.3.132.0.2", "sect163r1" }, + { "1.3.132.0.22", "sect131r1" }, + { "1.3.132.0.23", "sect131r2" }, + { "1.3.132.0.24", "sect193r1" }, + { "1.3.132.0.25", "sect193r2" }, + { "1.3.132.0.26", "sect233k1" }, + { "1.3.132.0.27", "sect233r1" }, + { "1.3.132.0.28", "secp128r1" }, + { "1.3.132.0.29", "secp128r2" }, + { "1.3.132.0.3", "sect239k1" }, + { "1.3.132.0.30", "secp160r2" }, + { "1.3.132.0.31", "secp192k1" }, + { "1.3.132.0.32", "secp224k1" }, + { "1.3.132.0.33", "secp224r1" }, + { "1.3.132.0.34", "secp384r1" }, + { "1.3.132.0.35", "secp521r1" }, + { "1.3.132.0.36", "sect409k1" }, + { "1.3.132.0.37", "sect409r1" }, + { "1.3.132.0.38", "sect571k1" }, + { "1.3.132.0.39", "sect571r1" }, + { "1.3.132.0.4", "sect113r1" }, + { "1.3.132.0.5", "sect113r2" }, + { "1.3.132.0.6", "secp112r1" }, + { "1.3.132.0.7", "secp112r2" }, + { "1.3.132.0.8", "secp160r1" }, + { "1.3.132.0.9", "secp160k1" }, + { "1.3.132.1.11.0", "dhSinglePass-stdDH-sha224kdf-scheme" }, + { "1.3.132.1.11.1", "dhSinglePass-stdDH-sha256kdf-scheme" }, + { "1.3.132.1.11.2", "dhSinglePass-stdDH-sha384kdf-scheme" }, + { "1.3.132.1.11.3", "dhSinglePass-stdDH-sha512kdf-scheme" }, + { "1.3.132.1.12", "ecDH" }, + { "1.3.132.1.13", "ecMQV" }, + { "1.3.132.1.14.0", "dhSinglePass-cofactorDH-sha224kdf-scheme" }, + { "1.3.132.1.14.1", "dhSinglePass-cofactorDH-sha256kdf-scheme" }, + { "1.3.132.1.14.2", "dhSinglePass-cofactorDH-sha384kdf-scheme" }, + { "1.3.132.1.14.3", "dhSinglePass-cofactorDH-sha512kdf-scheme" }, + { "1.3.132.1.15.0", "mqvSinglePass-sha224kdf-scheme" }, + { "1.3.132.1.15.1", "mqvSinglePass-sha256kdf-scheme" }, + { "1.3.132.1.15.2", "mqvSinglePass-sha384kdf-scheme" }, + { "1.3.132.1.15.3", "mqvSinglePass-sha512kdf-scheme" }, + { "1.3.133.16.840.63.0.16", "mqvSinglePass-sha1kdf-scheme" }, + { "1.3.133.16.840.63.0.2", "dhSinglePass-stdDH-sha1kdf-scheme" }, + { "1.3.133.16.840.63.0.3", "dhSinglePass-cofactorDH-sha1kdf-scheme" }, + { "1.3.133.16.840.9.84", "x984" }, + { "1.3.133.16.840.9.84.0", "x984Module" }, + { "1.3.133.16.840.9.84.0.1", "x984Biometrics" }, + { "1.3.133.16.840.9.84.0.2", "x984CMS" }, + { "1.3.133.16.840.9.84.0.3", "x984Identifiers" }, + { "1.3.133.16.840.9.84.1", "x984Biometric" }, + { "1.3.133.16.840.9.84.1", "x984ProcessingAlgorithm" }, + { "1.3.133.16.840.9.84.1.0", "biometricUnknownType" }, + { "1.3.133.16.840.9.84.1.1", "biometricBodyOdor" }, + { "1.3.133.16.840.9.84.1.10", "biometricPalm" }, + { "1.3.133.16.840.9.84.1.11", "biometricRetina" }, + { "1.3.133.16.840.9.84.1.12", "biometricSignature" }, + { "1.3.133.16.840.9.84.1.13", "biometricSpeechPattern" }, + { "1.3.133.16.840.9.84.1.14", "biometricThermalImage" }, + { "1.3.133.16.840.9.84.1.15", "biometricVeinPattern" }, + { "1.3.133.16.840.9.84.1.16", "biometricThermalFaceImage" }, + { "1.3.133.16.840.9.84.1.17", "biometricThermalHandImage" }, + { "1.3.133.16.840.9.84.1.18", "biometricLipMovement" }, + { "1.3.133.16.840.9.84.1.19", "biometricGait" }, + { "1.3.133.16.840.9.84.1.2", "biometricDNA" }, + { "1.3.133.16.840.9.84.1.3", "biometricEarShape" }, + { "1.3.133.16.840.9.84.1.4", "biometricFacialFeatures" }, + { "1.3.133.16.840.9.84.1.5", "biometricFingerImage" }, + { "1.3.133.16.840.9.84.1.6", "biometricFingerGeometry" }, + { "1.3.133.16.840.9.84.1.7", "biometricHandGeometry" }, + { "1.3.133.16.840.9.84.1.8", "biometricIrisFeatures" }, + { "1.3.133.16.840.9.84.1.9", "biometricKeystrokeDynamics" }, + { "1.3.133.16.840.9.84.3", "x984MatchingMethod" }, + { "1.3.133.16.840.9.84.4", "x984FormatOwner" }, + { "1.3.133.16.840.9.84.4.0", "x984CbeffOwner" }, + { "1.3.133.16.840.9.84.4.1", "x984IbiaOwner" }, + { "1.3.133.16.840.9.84.4.1", "x984X9Owner" }, + { "1.3.133.16.840.9.84.4.1.1", "ibiaOwnerSAFLINK" }, + { "1.3.133.16.840.9.84.4.1.10", "ibiaOwnerSecuGen" }, + { "1.3.133.16.840.9.84.4.1.11", "ibiaOwnerPreciseBiometric" }, + { "1.3.133.16.840.9.84.4.1.12", "ibiaOwnerIdentix" }, + { "1.3.133.16.840.9.84.4.1.13", "ibiaOwnerDERMALOG" }, + { "1.3.133.16.840.9.84.4.1.14", "ibiaOwnerLOGICO" }, + { "1.3.133.16.840.9.84.4.1.15", "ibiaOwnerNIST" }, + { "1.3.133.16.840.9.84.4.1.16", "ibiaOwnerA3Vision" }, + { "1.3.133.16.840.9.84.4.1.17", "ibiaOwnerNEC" }, + { "1.3.133.16.840.9.84.4.1.18", "ibiaOwnerSTMicroelectronics" }, + { "1.3.133.16.840.9.84.4.1.2", "ibiaOwnerBioscrypt" }, + { "1.3.133.16.840.9.84.4.1.3", "ibiaOwnerVisionics" }, + { "1.3.133.16.840.9.84.4.1.4", "ibiaOwnerInfineonTechnologiesAG" }, + { "1.3.133.16.840.9.84.4.1.5", "ibiaOwnerIridianTechnologies" }, + { "1.3.133.16.840.9.84.4.1.6", "ibiaOwnerVeridicom" }, + { "1.3.133.16.840.9.84.4.1.7", "ibiaOwnerCyberSIGN" }, + { "1.3.133.16.840.9.84.4.1.8", "ibiaOwnereCryp" }, + { "1.3.133.16.840.9.84.4.1.9", "ibiaOwnerFingerprintCardsAB" }, + { "1.3.14.2.26.5", "sha" }, + { "1.3.14.3.2.1.1", "rsa" }, + { "1.3.14.3.2.10", "desMAC" }, + { "1.3.14.3.2.11", "rsaSignature" }, + { "1.3.14.3.2.12", "dsa" }, + { "1.3.14.3.2.13", "dsaWithSHA" }, + { "1.3.14.3.2.14", "mdc2WithRSASignature" }, + { "1.3.14.3.2.15", "shaWithRSASignature" }, + { "1.3.14.3.2.16", "dhWithCommonModulus" }, + { "1.3.14.3.2.17", "desEDE" }, + { "1.3.14.3.2.18", "sha" }, + { "1.3.14.3.2.19", "mdc-2" }, + { "1.3.14.3.2.2", "md4WitRSA" }, + { "1.3.14.3.2.2.1", "sqmod-N" }, + { "1.3.14.3.2.20", "dsaCommon" }, + { "1.3.14.3.2.21", "dsaCommonWithSHA" }, + { "1.3.14.3.2.22", "rsaKeyTransport" }, + { "1.3.14.3.2.23", "keyed-hash-seal" }, + { "1.3.14.3.2.24", "md2WithRSASignature" }, + { "1.3.14.3.2.25", "md5WithRSASignature" }, + { "1.3.14.3.2.26", "sha1" }, + { "1.3.14.3.2.27", "dsaWithSHA1" }, + { "1.3.14.3.2.28", "dsaWithCommonSHA1" }, + { "1.3.14.3.2.29", "sha-1WithRSAEncryption" }, + { "1.3.14.3.2.3", "md5WithRSA" }, + { "1.3.14.3.2.3.1", "sqmod-NwithRSA" }, + { "1.3.14.3.2.4", "md4WithRSAEncryption" }, + { "1.3.14.3.2.6", "desECB" }, + { "1.3.14.3.2.7", "desCBC" }, + { "1.3.14.3.2.8", "desOFB" }, + { "1.3.14.3.2.9", "desCFB" }, + { "1.3.14.3.3.1", "simple-strong-auth-mechanism" }, + { "1.3.14.7.2.1.1", "ElGamal" }, + { "1.3.14.7.2.3.1", "md2WithRSA" }, + { "1.3.14.7.2.3.2", "md2WithElGamal" }, + { "1.3.36.1", "document" }, + { "1.3.36.1.1", "finalVersion" }, + { "1.3.36.1.2", "draft" }, + { "1.3.36.2", "sio" }, + { "1.3.36.2.1", "sedu" }, + { "1.3.36.3", "algorithm" }, + { "1.3.36.3.1", "encryptionAlgorithm" }, + { "1.3.36.3.1.1", "des" }, + { "1.3.36.3.1.1.1", "desECB_pad" }, + { "1.3.36.3.1.1.1.1", "desECB_ISOpad" }, + { "1.3.36.3.1.1.2.1", "desCBC_pad" }, + { "1.3.36.3.1.1.2.1.1", "desCBC_ISOpad" }, + { "1.3.36.3.1.2", "idea" }, + { "1.3.36.3.1.2.1", "ideaECB" }, + { "1.3.36.3.1.2.1.1", "ideaECB_pad" }, + { "1.3.36.3.1.2.1.1.1", "ideaECB_ISOpad" }, + { "1.3.36.3.1.2.2", "ideaCBC" }, + { "1.3.36.3.1.2.2.1", "ideaCBC_pad" }, + { "1.3.36.3.1.2.2.1.1", "ideaCBC_ISOpad" }, + { "1.3.36.3.1.2.3", "ideaOFB" }, + { "1.3.36.3.1.2.4", "ideaCFB" }, + { "1.3.36.3.1.3", "des_3" }, + { "1.3.36.3.1.3.1.1", "des_3ECB_pad" }, + { "1.3.36.3.1.3.1.1.1", "des_3ECB_ISOpad" }, + { "1.3.36.3.1.3.2.1", "des_3CBC_pad" }, + { "1.3.36.3.1.3.2.1.1", "des_3CBC_ISOpad" }, + { "1.3.36.3.1.4", "rsaEncryption" }, + { "1.3.36.3.1.4.512.17", "rsaEncryptionWithlmod512expe17" }, + { "1.3.36.3.1.5", "bsi-1" }, + { "1.3.36.3.1.5.1", "bsi_1ECB_pad" }, + { "1.3.36.3.1.5.2", "bsi_1CBC_pad" }, + { "1.3.36.3.1.5.2.1", "bsi_1CBC_PEMpad" }, + { "1.3.36.3.2", "hashAlgorithm" }, + { "1.3.36.3.2.1", "ripemd160" }, + { "1.3.36.3.2.2", "ripemd128" }, + { "1.3.36.3.2.3", "ripemd256" }, + { "1.3.36.3.2.4", "mdc2singleLength" }, + { "1.3.36.3.2.5", "mdc2doubleLength" }, + { "1.3.36.3.3", "signatureAlgorithm" }, + { "1.3.36.3.3.1", "rsaSignature" }, + { "1.3.36.3.3.1.1", "rsaSignatureWithsha1" }, + { "1.3.36.3.3.1.1.1024.11", "rsaSignatureWithsha1_l1024_l11" }, + { "1.3.36.3.3.1.1.1024.2", "rsaSignatureWithsha1_l1024_l2" }, + { "1.3.36.3.3.1.1.1024.3", "rsaSignatureWithsha1_l1024_l3" }, + { "1.3.36.3.3.1.1.1024.5", "rsaSignatureWithsha1_l1024_l5" }, + { "1.3.36.3.3.1.1.1024.9", "rsaSignatureWithsha1_l1024_l9" }, + { "1.3.36.3.3.1.1.512.11", "rsaSignatureWithsha1_l512_l11" }, + { "1.3.36.3.3.1.1.512.2", "rsaSignatureWithsha1_l512_l2" }, + { "1.3.36.3.3.1.1.512.3", "rsaSignatureWithsha1_l512_l3" }, + { "1.3.36.3.3.1.1.512.5", "rsaSignatureWithsha1_l512_l5" }, + { "1.3.36.3.3.1.1.512.9", "rsaSignatureWithsha1_l512_l9" }, + { "1.3.36.3.3.1.1.640.11", "rsaSignatureWithsha1_l640_l11" }, + { "1.3.36.3.3.1.1.640.2", "rsaSignatureWithsha1_l640_l2" }, + { "1.3.36.3.3.1.1.640.3", "rsaSignatureWithsha1_l640_l3" }, + { "1.3.36.3.3.1.1.640.5", "rsaSignatureWithsha1_l640_l5" }, + { "1.3.36.3.3.1.1.640.9", "rsaSignatureWithsha1_l640_l9" }, + { "1.3.36.3.3.1.1.768.11", "rsaSignatureWithsha1_l768_l11" }, + { "1.3.36.3.3.1.1.768.2", "rsaSignatureWithsha1_l768_l2" }, + { "1.3.36.3.3.1.1.768.3", "rsaSignatureWithsha1_l768_l3" }, + { "1.3.36.3.3.1.1.768.5", "rsaSignatureWithsha1_l768_l5" }, + { "1.3.36.3.3.1.1.768.9", "rsaSignatureWithsha1_l768_l9" }, + { "1.3.36.3.3.1.1.896.11", "rsaSignatureWithsha1_l896_l11" }, + { "1.3.36.3.3.1.1.896.2", "rsaSignatureWithsha1_l896_l2" }, + { "1.3.36.3.3.1.1.896.3", "rsaSignatureWithsha1_l896_l3" }, + { "1.3.36.3.3.1.1.896.5", "rsaSignatureWithsha1_l896_l5" }, + { "1.3.36.3.3.1.1.896.9", "rsaSignatureWithsha1_l896_l9" }, + { "1.3.36.3.3.1.2", "rsaSignatureWithripemd160" }, + { "1.3.36.3.3.1.2.1024.11", "rsaSignatureWithripemd160_l1024_l11" }, + { "1.3.36.3.3.1.2.1024.2", "rsaSignatureWithripemd160_l1024_l2" }, + { "1.3.36.3.3.1.2.1024.3", "rsaSignatureWithripemd160_l1024_l3" }, + { "1.3.36.3.3.1.2.1024.5", "rsaSignatureWithripemd160_l1024_l5" }, + { "1.3.36.3.3.1.2.1024.9", "rsaSignatureWithripemd160_l1024_l9" }, + { "1.3.36.3.3.1.2.512.11", "rsaSignatureWithripemd160_l512_l11" }, + { "1.3.36.3.3.1.2.512.2", "rsaSignatureWithripemd160_l512_l2" }, + { "1.3.36.3.3.1.2.512.3", "rsaSignatureWithripemd160_l512_l3" }, + { "1.3.36.3.3.1.2.512.5", "rsaSignatureWithripemd160_l512_l5" }, + { "1.3.36.3.3.1.2.512.9", "rsaSignatureWithripemd160_l512_l9" }, + { "1.3.36.3.3.1.2.640.11", "rsaSignatureWithripemd160_l640_l11" }, + { "1.3.36.3.3.1.2.640.2", "rsaSignatureWithripemd160_l640_l2" }, + { "1.3.36.3.3.1.2.640.3", "rsaSignatureWithripemd160_l640_l3" }, + { "1.3.36.3.3.1.2.640.5", "rsaSignatureWithripemd160_l640_l5" }, + { "1.3.36.3.3.1.2.640.9", "rsaSignatureWithripemd160_l640_l9" }, + { "1.3.36.3.3.1.2.768.11", "rsaSignatureWithripemd160_l768_l11" }, + { "1.3.36.3.3.1.2.768.2", "rsaSignatureWithripemd160_l768_l2" }, + { "1.3.36.3.3.1.2.768.3", "rsaSignatureWithripemd160_l768_l3" }, + { "1.3.36.3.3.1.2.768.5", "rsaSignatureWithripemd160_l768_l5" }, + { "1.3.36.3.3.1.2.768.9", "rsaSignatureWithripemd160_l768_l9" }, + { "1.3.36.3.3.1.2.896.11", "rsaSignatureWithripemd160_l896_l11" }, + { "1.3.36.3.3.1.2.896.2", "rsaSignatureWithripemd160_l896_l2" }, + { "1.3.36.3.3.1.2.896.3", "rsaSignatureWithripemd160_l896_l3" }, + { "1.3.36.3.3.1.2.896.5", "rsaSignatureWithripemd160_l896_l5" }, + { "1.3.36.3.3.1.2.896.9", "rsaSignatureWithripemd160_l896_l9" }, + { "1.3.36.3.3.1.3", "rsaSignatureWithrimpemd128" }, + { "1.3.36.3.3.1.4", "rsaSignatureWithrimpemd256" }, + { "1.3.36.3.3.2", "ecsieSign" }, + { "1.3.36.3.3.2.1", "ecsieSignWithsha1" }, + { "1.3.36.3.3.2.2", "ecsieSignWithripemd160" }, + { "1.3.36.3.3.2.3", "ecsieSignWithmd2" }, + { "1.3.36.3.3.2.4", "ecsieSignWithmd5" }, + { "1.3.36.3.3.2.8.1.1.1", "brainpoolP160r1" }, + { "1.3.36.3.3.2.8.1.1.10", "brainpoolP320t1" }, + { "1.3.36.3.3.2.8.1.1.11", "brainpoolP384r1" }, + { "1.3.36.3.3.2.8.1.1.12", "brainpoolP384t1" }, + { "1.3.36.3.3.2.8.1.1.13", "brainpoolP512r1" }, + { "1.3.36.3.3.2.8.1.1.14", "brainpoolP512t1" }, + { "1.3.36.3.3.2.8.1.1.2", "brainpoolP160t1" }, + { "1.3.36.3.3.2.8.1.1.3", "brainpoolP192r1" }, + { "1.3.36.3.3.2.8.1.1.4", "brainpoolP192t1" }, + { "1.3.36.3.3.2.8.1.1.5", "brainpoolP224r1" }, + { "1.3.36.3.3.2.8.1.1.6", "brainpoolP224t1" }, + { "1.3.36.3.3.2.8.1.1.7", "brainpoolP256r1" }, + { "1.3.36.3.3.2.8.1.1.8", "brainpoolP256t1" }, + { "1.3.36.3.3.2.8.1.1.9", "brainpoolP320r1" }, + { "1.3.36.3.4", "signatureScheme" }, + { "1.3.36.3.4.1", "sigS_ISO9796-1" }, + { "1.3.36.3.4.2", "sigS_ISO9796-2" }, + { "1.3.36.3.4.2.1", "sigS_ISO9796-2Withred" }, + { "1.3.36.3.4.2.2", "sigS_ISO9796-2Withrsa" }, + { "1.3.36.3.4.2.3", "sigS_ISO9796-2Withrnd" }, + { "1.3.36.4", "attribute" }, + { "1.3.36.5", "policy" }, + { "1.3.36.6", "api" }, + { "1.3.36.6.1", "manufacturer-specific_api" }, + { "1.3.36.6.1.1", "utimaco-api" }, + { "1.3.36.6.2", "functionality-specific_api" }, + { "1.3.36.7", "keymgmnt" }, + { "1.3.36.7.1", "keyagree" }, + { "1.3.36.7.1.1", "bsiPKE" }, + { "1.3.36.7.2", "keytrans" }, + { "1.3.36.7.2.1", "encISO9796-2Withrsa" }, + { "1.3.36.8.1.1", "Teletrust.SigGConform.policyIdentifier" }, + { "1.3.36.8.2.1", "directoryService" }, + { "1.3.36.8.3.1", "dateOfCertGen" }, + { "1.3.36.8.3.10", "requestedCertificate" }, + { "1.3.36.8.3.11", "namingAuthorities" }, + { "1.3.36.8.3.11.1", "rechtWirtschaftSteuern" }, + { "1.3.36.8.3.11.1.1", "rechtsanwaeltin" }, + { "1.3.36.8.3.11.1.10", "notarVertreterin" }, + { "1.3.36.8.3.11.1.11", "notarVertreter" }, + { "1.3.36.8.3.11.1.12", "notariatsVerwalterin" }, + { "1.3.36.8.3.11.1.13", "notariatsVerwalter" }, + { "1.3.36.8.3.11.1.14", "wirtschaftsPrueferin" }, + { "1.3.36.8.3.11.1.15", "wirtschaftsPruefer" }, + { "1.3.36.8.3.11.1.16", "vereidigteBuchprueferin" }, + { "1.3.36.8.3.11.1.17", "vereidigterBuchpruefer" }, + { "1.3.36.8.3.11.1.18", "patentAnwaeltin" }, + { "1.3.36.8.3.11.1.19", "patentAnwalt" }, + { "1.3.36.8.3.11.1.2", "rechtsanwalt" }, + { "1.3.36.8.3.11.1.3", "rechtsBeistand" }, + { "1.3.36.8.3.11.1.4", "steuerBeraterin" }, + { "1.3.36.8.3.11.1.5", "steuerBerater" }, + { "1.3.36.8.3.11.1.6", "steuerBevollmaechtigte" }, + { "1.3.36.8.3.11.1.7", "steuerBevollmaechtigter" }, + { "1.3.36.8.3.11.1.8", "notarin" }, + { "1.3.36.8.3.11.1.9", "notar" }, + { "1.3.36.8.3.12", "certInDirSince" }, + { "1.3.36.8.3.13", "certHash" }, + { "1.3.36.8.3.14", "nameAtBirth" }, + { "1.3.36.8.3.15", "additionalInformation" }, + { "1.3.36.8.3.2", "procuration" }, + { "1.3.36.8.3.3", "admission" }, + { "1.3.36.8.3.4", "monetaryLimit" }, + { "1.3.36.8.3.5", "declarationOfMajority" }, + { "1.3.36.8.3.6", "integratedCircuitCardSerialNumber" }, + { "1.3.36.8.3.7", "pKReference" }, + { "1.3.36.8.3.8", "restriction" }, + { "1.3.36.8.3.9", "retrieveIfAllowed" }, + { "1.3.36.8.4.1", "personalData" }, + { "1.3.36.8.4.8", "restriction" }, + { "1.3.36.8.5.1.1.1", "rsaIndicateSHA1" }, + { "1.3.36.8.5.1.1.2", "rsaIndicateRIPEMD160" }, + { "1.3.36.8.5.1.1.3", "rsaWithSHA1" }, + { "1.3.36.8.5.1.1.4", "rsaWithRIPEMD160" }, + { "1.3.36.8.5.1.2.1", "dsaExtended" }, + { "1.3.36.8.5.1.2.2", "dsaWithRIPEMD160" }, + { "1.3.36.8.6.1", "cert" }, + { "1.3.36.8.6.10", "autoGen" }, + { "1.3.36.8.6.2", "certRef" }, + { "1.3.36.8.6.3", "attrCert" }, + { "1.3.36.8.6.4", "attrRef" }, + { "1.3.36.8.6.5", "fileName" }, + { "1.3.36.8.6.6", "storageTime" }, + { "1.3.36.8.6.7", "fileSize" }, + { "1.3.36.8.6.8", "location" }, + { "1.3.36.8.6.9", "sigNumber" }, + { "1.3.36.8.7.1.1", "ptAdobeILL" }, + { "1.3.36.8.7.1.10", "ptCorelPHT" }, + { "1.3.36.8.7.1.11", "ptDraw" }, + { "1.3.36.8.7.1.12", "ptDVI" }, + { "1.3.36.8.7.1.13", "ptEPS" }, + { "1.3.36.8.7.1.14", "ptExcel" }, + { "1.3.36.8.7.1.15", "ptGEM" }, + { "1.3.36.8.7.1.16", "ptGIF" }, + { "1.3.36.8.7.1.17", "ptHPGL" }, + { "1.3.36.8.7.1.18", "ptJPEG" }, + { "1.3.36.8.7.1.19", "ptKodak" }, + { "1.3.36.8.7.1.2", "ptAmiPro" }, + { "1.3.36.8.7.1.20", "ptLaTeX" }, + { "1.3.36.8.7.1.21", "ptLotus" }, + { "1.3.36.8.7.1.22", "ptLotusPIC" }, + { "1.3.36.8.7.1.23", "ptMacPICT" }, + { "1.3.36.8.7.1.24", "ptMacWord" }, + { "1.3.36.8.7.1.25", "ptMSWfD" }, + { "1.3.36.8.7.1.26", "ptMSWord" }, + { "1.3.36.8.7.1.27", "ptMSWord2" }, + { "1.3.36.8.7.1.28", "ptMSWord6" }, + { "1.3.36.8.7.1.29", "ptMSWord8" }, + { "1.3.36.8.7.1.3", "ptAutoCAD" }, + { "1.3.36.8.7.1.30", "ptPDF" }, + { "1.3.36.8.7.1.31", "ptPIF" }, + { "1.3.36.8.7.1.32", "ptPostscript" }, + { "1.3.36.8.7.1.33", "ptRTF" }, + { "1.3.36.8.7.1.34", "ptSCITEX" }, + { "1.3.36.8.7.1.35", "ptTAR" }, + { "1.3.36.8.7.1.36", "ptTarga" }, + { "1.3.36.8.7.1.37", "ptTeX" }, + { "1.3.36.8.7.1.38", "ptText" }, + { "1.3.36.8.7.1.39", "ptTIFF" }, + { "1.3.36.8.7.1.4", "ptBinary" }, + { "1.3.36.8.7.1.40", "ptTIFF-FC" }, + { "1.3.36.8.7.1.41", "ptUID" }, + { "1.3.36.8.7.1.42", "ptUUEncode" }, + { "1.3.36.8.7.1.43", "ptWMF" }, + { "1.3.36.8.7.1.44", "ptWordPerfect" }, + { "1.3.36.8.7.1.45", "ptWPGrph" }, + { "1.3.36.8.7.1.5", "ptBMP" }, + { "1.3.36.8.7.1.6", "ptCGM" }, + { "1.3.36.8.7.1.7", "ptCorelCRT" }, + { "1.3.36.8.7.1.8", "ptCorelDRW" }, + { "1.3.36.8.7.1.9", "ptCorelEXC" }, + { "1.3.6.1.4.1.11591", "gnu" }, + { "1.3.6.1.4.1.11591.1", "gnuRadius" }, + { "1.3.6.1.4.1.11591.12", "gnuDigestAlgorithm" }, + { "1.3.6.1.4.1.11591.12.2", "tiger" }, + { "1.3.6.1.4.1.11591.13", "gnuEncryptionAlgorithm" }, + { "1.3.6.1.4.1.11591.13.2", "serpent" }, + { "1.3.6.1.4.1.11591.13.2.1", "serpent128_ECB" }, + { "1.3.6.1.4.1.11591.13.2.2", "serpent128_CBC" }, + { "1.3.6.1.4.1.11591.13.2.21", "serpent192_ECB" }, + { "1.3.6.1.4.1.11591.13.2.22", "serpent192_CBC" }, + { "1.3.6.1.4.1.11591.13.2.23", "serpent192_OFB" }, + { "1.3.6.1.4.1.11591.13.2.24", "serpent192_CFB" }, + { "1.3.6.1.4.1.11591.13.2.3", "serpent128_OFB" }, + { "1.3.6.1.4.1.11591.13.2.4", "serpent128_CFB" }, + { "1.3.6.1.4.1.11591.13.2.41", "serpent256_ECB" }, + { "1.3.6.1.4.1.11591.13.2.42", "serpent256_CBC" }, + { "1.3.6.1.4.1.11591.13.2.43", "serpent256_OFB" }, + { "1.3.6.1.4.1.11591.13.2.44", "serpent256_CFB" }, + { "1.3.6.1.4.1.11591.3", "gnuRadar" }, + { "1.3.6.1.4.1.16334.509.1.1", "Northrop.Grumman.extKeyUsage?" }, + { "1.3.6.1.4.1.16334.509.2.1", "ngcClass1" }, + { "1.3.6.1.4.1.16334.509.2.2", "ngcClass2" }, + { "1.3.6.1.4.1.16334.509.2.3", "ngcClass3" }, + { "1.3.6.1.4.1.188.7.1.1", "ascom" }, + { "1.3.6.1.4.1.188.7.1.1.1", "ideaECB" }, + { "1.3.6.1.4.1.188.7.1.1.2", "ideaCBC" }, + { "1.3.6.1.4.1.188.7.1.1.3", "ideaCFB" }, + { "1.3.6.1.4.1.188.7.1.1.4", "ideaOFB" }, + { "1.3.6.1.4.1.23629.1.4.2.1.1", "safenetUsageLimit" }, + { "1.3.6.1.4.1.23629.1.4.2.1.2", "safenetEndDate" }, + { "1.3.6.1.4.1.23629.1.4.2.1.3", "safenetStartDate" }, + { "1.3.6.1.4.1.23629.1.4.2.1.4", "safenetAdminCert" }, + { "1.3.6.1.4.1.23629.1.4.2.2.1", "safenetKeyDigest" }, + { "1.3.6.1.4.1.2428.10.1.1", "UNINETT.policyIdentifier" }, + { "1.3.6.1.4.1.2712.10", "ICE-TEL.policyIdentifier" }, + { "1.3.6.1.4.1.2786.1.1.1", "ICE-TEL.Italian.policyIdentifier" }, + { "1.3.6.1.4.1.3029.1.1.1", "blowfishECB" }, + { "1.3.6.1.4.1.3029.1.1.2", "blowfishCBC" }, + { "1.3.6.1.4.1.3029.1.1.3", "blowfishCFB" }, + { "1.3.6.1.4.1.3029.1.1.4", "blowfishOFB" }, + { "1.3.6.1.4.1.3029.1.2.1", "elgamal" }, + { "1.3.6.1.4.1.3029.1.2.1.1", "elgamalWithSHA-1" }, + { "1.3.6.1.4.1.3029.1.2.1.2", "elgamalWithRIPEMD-160" }, + { "1.3.6.1.4.1.3029.3.1.1", "cryptlibPresenceCheck" }, + { "1.3.6.1.4.1.3029.3.1.2", "pkiBoot" }, + { "1.3.6.1.4.1.3029.3.1.4", "crlExtReason" }, + { "1.3.6.1.4.1.3029.3.1.5", "keyFeatures" }, + { "1.3.6.1.4.1.3029.4.1", "cryptlibContent" }, + { "1.3.6.1.4.1.3029.4.1.1", "cryptlibConfigData" }, + { "1.3.6.1.4.1.3029.4.1.2", "cryptlibUserIndex" }, + { "1.3.6.1.4.1.3029.4.1.3", "cryptlibUserInfo" }, + { "1.3.6.1.4.1.3029.4.1.4", "rtcsRequest" }, + { "1.3.6.1.4.1.3029.4.1.5", "rtcsResponse" }, + { "1.3.6.1.4.1.3029.4.1.6", "rtcsResponseExt" }, + { "1.3.6.1.4.1.3029.42.11172.1", "mpeg-1" }, + { "1.3.6.1.4.1.3029.88.89.90.90.89", "xYZZY.policyIdentifier" }, + { "1.3.6.1.4.1.311.10.1", "certTrustList" }, + { "1.3.6.1.4.1.311.10.1.1", "sortedCtl" }, + { "1.3.6.1.4.1.311.10.10.1", "cmcAddAttributes" }, + { "1.3.6.1.4.1.311.10.11", "certPropIdPrefix" }, + { "1.3.6.1.4.1.311.10.11.20", "certKeyIdentifierPropId" }, + { "1.3.6.1.4.1.311.10.11.28", "certIssuerSerialNumberMd5HashPropId" }, + { "1.3.6.1.4.1.311.10.11.29", "certSubjectNameMd5HashPropId" }, + { "1.3.6.1.4.1.311.10.11.4", "certMd5HashPropId" }, + { "1.3.6.1.4.1.311.10.12.1", "anyApplicationPolicy" }, + { "1.3.6.1.4.1.311.10.2", "nextUpdateLocation" }, + { "1.3.6.1.4.1.311.10.3.1", "certTrustListSigning" }, + { "1.3.6.1.4.1.311.10.3.10", "qualifiedSubordination" }, + { "1.3.6.1.4.1.311.10.3.11", "keyRecovery" }, + { "1.3.6.1.4.1.311.10.3.12", "documentSigning" }, + { "1.3.6.1.4.1.311.10.3.13", "lifetimeSigning" }, + { "1.3.6.1.4.1.311.10.3.14", "mobileDeviceSoftware" }, + { "1.3.6.1.4.1.311.10.3.15", "smartDisplay" }, + { "1.3.6.1.4.1.311.10.3.16", "cspSignature" }, + { "1.3.6.1.4.1.311.10.3.2", "timeStampSigning" }, + { "1.3.6.1.4.1.311.10.3.3", "serverGatedCrypto" }, + { "1.3.6.1.4.1.311.10.3.3.1", "serialized" }, + { "1.3.6.1.4.1.311.10.3.4", "encryptedFileSystem" }, + { "1.3.6.1.4.1.311.10.3.4.1", "efsRecovery" }, + { "1.3.6.1.4.1.311.10.3.5", "whqlCrypto" }, + { "1.3.6.1.4.1.311.10.3.6", "nt5Crypto" }, + { "1.3.6.1.4.1.311.10.3.7", "oemWHQLCrypto" }, + { "1.3.6.1.4.1.311.10.3.8", "embeddedNTCrypto" }, + { "1.3.6.1.4.1.311.10.3.9", "rootListSigner" }, + { "1.3.6.1.4.1.311.10.4.1", "yesnoTrustAttr" }, + { "1.3.6.1.4.1.311.10.5.1", "drm" }, + { "1.3.6.1.4.1.311.10.5.2", "drmIndividualization" }, + { "1.3.6.1.4.1.311.10.6.1", "licenses" }, + { "1.3.6.1.4.1.311.10.6.2", "licenseServer" }, + { "1.3.6.1.4.1.311.10.7.1", "keyidRdn" }, + { "1.3.6.1.4.1.311.10.8.1", "removeCertificate" }, + { "1.3.6.1.4.1.311.10.9.1", "crossCertDistPoints" }, + { "1.3.6.1.4.1.311.12", "catalog" }, + { "1.3.6.1.4.1.311.12.1.1", "catalogList" }, + { "1.3.6.1.4.1.311.12.1.2", "catalogListMember" }, + { "1.3.6.1.4.1.311.12.2.1", "catalogNameValueObjID" }, + { "1.3.6.1.4.1.311.12.2.2", "catalogMemberInfoObjID" }, + { "1.3.6.1.4.1.311.13.1", "renewalCertificate" }, + { "1.3.6.1.4.1.311.13.2.1", "enrolmentNameValuePair" }, + { "1.3.6.1.4.1.311.13.2.2", "enrolmentCSP" }, + { "1.3.6.1.4.1.311.13.2.3", "osVersion" }, + { "1.3.6.1.4.1.311.16.4", "microsoftRecipientInfo" }, + { "1.3.6.1.4.1.311.17.1", "pkcs12KeyProviderNameAttr" }, + { "1.3.6.1.4.1.311.17.2", "localMachineKeyset" }, + { "1.3.6.1.4.1.311.17.3", "pkcs12ExtendedAttributes" }, + { "1.3.6.1.4.1.311.2.1.10", "spcAgencyInfo" }, + { "1.3.6.1.4.1.311.2.1.11", "spcStatementType" }, + { "1.3.6.1.4.1.311.2.1.12", "spcSpOpusInfo" }, + { "1.3.6.1.4.1.311.2.1.14", "certReqExtensions" }, + { "1.3.6.1.4.1.311.2.1.15", "spcPEImageData" }, + { "1.3.6.1.4.1.311.2.1.18", "spcRawFileData" }, + { "1.3.6.1.4.1.311.2.1.19", "spcStructuredStorageData" }, + { "1.3.6.1.4.1.311.2.1.20", "spcJavaClassData.(type.1)" }, + { "1.3.6.1.4.1.311.2.1.21", "individualCodeSigning" }, + { "1.3.6.1.4.1.311.2.1.22", "commercialCodeSigning" }, + { "1.3.6.1.4.1.311.2.1.25", "spcLink.(type.2)" }, + { "1.3.6.1.4.1.311.2.1.26", "spcMinimalCriteriaInfo" }, + { "1.3.6.1.4.1.311.2.1.27", "spcFinancialCriteriaInfo" }, + { "1.3.6.1.4.1.311.2.1.28", "spcLink.(type.3)" }, + { "1.3.6.1.4.1.311.2.1.29", "spcHashInfoObjID" }, + { "1.3.6.1.4.1.311.2.1.30", "spcSipInfoObjID" }, + { "1.3.6.1.4.1.311.2.1.4", "spcIndirectDataContext" }, + { "1.3.6.1.4.1.311.2.2", "ctl" }, + { "1.3.6.1.4.1.311.2.2.1", "ctlTrustedCodesigningCAList" }, + { "1.3.6.1.4.1.311.2.2.2", "ctlTrustedClientAuthCAList" }, + { "1.3.6.1.4.1.311.2.2.3", "ctlTrustedServerAuthCAList" }, + { "1.3.6.1.4.1.311.20.1", "autoEnrollCtlUsage" }, + { "1.3.6.1.4.1.311.20.2", "enrollCerttypeExtension" }, + { "1.3.6.1.4.1.311.20.2.1", "enrollmentAgent" }, + { "1.3.6.1.4.1.311.20.2.2", "smartcardLogon" }, + { "1.3.6.1.4.1.311.20.2.3", "universalPrincipalName" }, + { "1.3.6.1.4.1.311.20.3", "certManifold" }, + { "1.3.6.1.4.1.311.21.1", "cAKeyCertIndexPair" }, + { "1.3.6.1.4.1.311.21.10", "applicationCertPolicies" }, + { "1.3.6.1.4.1.311.21.11", "applicationPolicyMappings" }, + { "1.3.6.1.4.1.311.21.12", "applicationPolicyConstraints" }, + { "1.3.6.1.4.1.311.21.13", "archivedKey" }, + { "1.3.6.1.4.1.311.21.14", "crlSelfCDP" }, + { "1.3.6.1.4.1.311.21.15", "requireCertChainPolicy" }, + { "1.3.6.1.4.1.311.21.16", "archivedKeyCertHash" }, + { "1.3.6.1.4.1.311.21.17", "issuedCertHash" }, + { "1.3.6.1.4.1.311.21.19", "dsEmailReplication" }, + { "1.3.6.1.4.1.311.21.2", "certSrvPreviousCertHash" }, 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"1.3.6.1.4.1.311.61.1.1", "kernelModeCodeSigning" }, + { "1.3.6.1.4.1.311.88", "capiCom" }, + { "1.3.6.1.4.1.311.88.1", "capiComVersion" }, + { "1.3.6.1.4.1.311.88.2", "capiComAttribute" }, + { "1.3.6.1.4.1.311.88.2.1", "capiComDocumentName" }, + { "1.3.6.1.4.1.311.88.2.2", "capiComDocumentDescription" }, + { "1.3.6.1.4.1.311.88.3", "capiComEncryptedData" }, + { "1.3.6.1.4.1.311.88.3.1", "capiComEncryptedContent" }, + { "1.3.6.1.4.1.3401.8.1.1", "pgpExtension" }, + { "1.3.6.1.4.1.3576.7", "eciaAscX12Edi" }, + { "1.3.6.1.4.1.3576.7.1", "plainEDImessage" }, + { "1.3.6.1.4.1.3576.7.2", "signedEDImessage" }, + { "1.3.6.1.4.1.3576.7.5", "integrityEDImessage" }, + { "1.3.6.1.4.1.3576.7.65", "iaReceiptMessage" }, + { "1.3.6.1.4.1.3576.7.97", "iaStatusMessage" }, + { "1.3.6.1.4.1.3576.8", "eciaEdifact" }, + { "1.3.6.1.4.1.3576.9", "eciaNonEdi" }, + { "1.3.6.1.4.1.4146", "Globalsign" }, + { "1.3.6.1.4.1.4146.1", "globalsignPolicy" }, + { "1.3.6.1.4.1.4146.1.10", "globalsignDVPolicy" }, + { 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"2.16.840.1.101.2.1.2.74", "forwardedCSPMsgBodyPart" }, + { "2.16.840.1.101.2.1.2.75", "cspForwardedMessageParameters" }, + { "2.16.840.1.101.2.1.2.76", "mspMMP2" }, + { "2.16.840.1.101.2.1.3.1", "sdnsSecurityPolicy" }, + { "2.16.840.1.101.2.1.3.10", "siSecurityPolicy" }, + { "2.16.840.1.101.2.1.3.10.0", "siNASP" }, + { "2.16.840.1.101.2.1.3.10.1", "siELCO" }, + { "2.16.840.1.101.2.1.3.10.10", "siREL_UK" }, + { "2.16.840.1.101.2.1.3.10.11", "siREL-NZ" }, + { "2.16.840.1.101.2.1.3.10.12", "siGeneric" }, + { "2.16.840.1.101.2.1.3.10.2", "siTK" }, + { "2.16.840.1.101.2.1.3.10.3", "siDSAP" }, + { "2.16.840.1.101.2.1.3.10.4", "siSSSS" }, + { "2.16.840.1.101.2.1.3.10.5", "siDNASP" }, + { "2.16.840.1.101.2.1.3.10.6", "siBYEMAN" }, + { "2.16.840.1.101.2.1.3.10.7", "siREL-US" }, + { "2.16.840.1.101.2.1.3.10.8", "siREL-AUS" }, + { "2.16.840.1.101.2.1.3.10.9", "siREL-CAN" }, + { "2.16.840.1.101.2.1.3.11", "genser" }, + { "2.16.840.1.101.2.1.3.11.0", "genserNations" }, + { "2.16.840.1.101.2.1.3.11.1", "genserComsec" }, + { "2.16.840.1.101.2.1.3.11.2", "genserAcquisition" }, + { "2.16.840.1.101.2.1.3.11.3", "genserSecurityCategories" }, + { "2.16.840.1.101.2.1.3.11.3.0", "genserTagSetName" }, + { "2.16.840.1.101.2.1.3.12", "defaultSecurityPolicy" }, + { "2.16.840.1.101.2.1.3.13", "capcoMarkings" }, + { "2.16.840.1.101.2.1.3.13.0", "capcoSecurityCategories" }, + { "2.16.840.1.101.2.1.3.13.0.1", "capcoTagSetName1" }, + { "2.16.840.1.101.2.1.3.13.0.2", "capcoTagSetName2" }, + { "2.16.840.1.101.2.1.3.13.0.3", "capcoTagSetName3" }, + { "2.16.840.1.101.2.1.3.13.0.4", "capcoTagSetName4" }, + { "2.16.840.1.101.2.1.3.2", "sdnsPRBAC" }, + { "2.16.840.1.101.2.1.3.3", "mosaicPRBAC" }, + { "2.16.840.1.101.2.1.5.1", "sdnsKeyManagementCertificate" }, + { "2.16.840.1.101.2.1.5.10", "auxiliaryVector" }, + { "2.16.840.1.101.2.1.5.11", "mlReceiptPolicy" }, + { "2.16.840.1.101.2.1.5.12", "mlMembership" }, + { "2.16.840.1.101.2.1.5.13", "mlAdministrators" }, + { "2.16.840.1.101.2.1.5.14", "alid" }, + { "2.16.840.1.101.2.1.5.2", "sdnsUserSignatureCertificate" }, + { "2.16.840.1.101.2.1.5.20", "janUKMs" }, + { "2.16.840.1.101.2.1.5.21", "febUKMs" }, + { "2.16.840.1.101.2.1.5.22", "marUKMs" }, + { "2.16.840.1.101.2.1.5.23", "aprUKMs" }, + { "2.16.840.1.101.2.1.5.24", "mayUKMs" }, + { "2.16.840.1.101.2.1.5.25", "junUKMs" }, + { "2.16.840.1.101.2.1.5.26", "julUKMs" }, + { "2.16.840.1.101.2.1.5.27", "augUKMs" }, + { "2.16.840.1.101.2.1.5.28", "sepUKMs" }, + { "2.16.840.1.101.2.1.5.29", "octUKMs" }, + { "2.16.840.1.101.2.1.5.3", "sdnsKMandSigCertificate" }, + { "2.16.840.1.101.2.1.5.30", "novUKMs" }, + { "2.16.840.1.101.2.1.5.31", "decUKMs" }, + { "2.16.840.1.101.2.1.5.4", "fortezzaKeyManagementCertificate" }, + { "2.16.840.1.101.2.1.5.40", "metaSDNSckl" }, + { "2.16.840.1.101.2.1.5.41", "sdnsCKL" }, + { "2.16.840.1.101.2.1.5.42", "metaSDNSsignatureCKL" }, + { "2.16.840.1.101.2.1.5.43", "sdnsSignatureCKL" }, + { "2.16.840.1.101.2.1.5.44", "sdnsCertificateRevocationList" }, + { "2.16.840.1.101.2.1.5.45", "fortezzaCertificateRevocationList" }, + { "2.16.840.1.101.2.1.5.46", "fortezzaCKL" }, + { "2.16.840.1.101.2.1.5.47", "alExemptedAddressProcessor" }, + { "2.16.840.1.101.2.1.5.48", "guard" }, + { "2.16.840.1.101.2.1.5.49", "algorithmsSupported" }, + { "2.16.840.1.101.2.1.5.5", "fortezzaKMandSigCertificate" }, + { "2.16.840.1.101.2.1.5.50", "suiteAKeyManagementCertificate" }, + { "2.16.840.1.101.2.1.5.51", "suiteAKMandSigCertificate" }, + { "2.16.840.1.101.2.1.5.52", "suiteAUserSignatureCertificate" }, + { "2.16.840.1.101.2.1.5.53", "prbacInfo" }, + { "2.16.840.1.101.2.1.5.54", "prbacCAConstraints" }, + { "2.16.840.1.101.2.1.5.55", "sigOrKMPrivileges" }, + { "2.16.840.1.101.2.1.5.56", "commPrivileges" }, + { "2.16.840.1.101.2.1.5.57", "labeledAttribute" }, + { "2.16.840.1.101.2.1.5.58", "policyInformationFile" }, + { "2.16.840.1.101.2.1.5.59", "secPolicyInformationFile" }, + { "2.16.840.1.101.2.1.5.6", "fortezzaUserSignatureCertificate" }, + { "2.16.840.1.101.2.1.5.60", "cAClearanceConstraint" }, + { "2.16.840.1.101.2.1.5.7", "fortezzaCASignatureCertificate" }, + { "2.16.840.1.101.2.1.5.8", "sdnsCASignatureCertificate" }, + { "2.16.840.1.101.2.1.7.1", "cspExtns" }, + { "2.16.840.1.101.2.1.7.1.0", "cspCsExtn" }, + { "2.16.840.1.101.2.1.8.1", "mISSISecurityCategories" }, + { "2.16.840.1.101.2.1.8.2", "standardSecurityLabelPrivileges" }, + { "2.16.840.1.101.3.1", "slabel" }, + { "2.16.840.1.101.3.2", "pki" }, + { "2.16.840.1.101.3.2.1", "NIST.policyIdentifier" }, + { "2.16.840.1.101.3.2.1.3.1", "fbcaRudimentaryPolicy" }, + { "2.16.840.1.101.3.2.1.3.2", "fbcaBasicPolicy" }, + { "2.16.840.1.101.3.2.1.3.3", "fbcaMediumPolicy" }, + { "2.16.840.1.101.3.2.1.3.4", "fbcaHighPolicy" }, + { "2.16.840.1.101.3.2.1.48.1", "nistTestPolicy1" }, + { "2.16.840.1.101.3.2.1.48.2", "nistTestPolicy2" }, + { "2.16.840.1.101.3.2.1.48.3", "nistTestPolicy3" }, + { "2.16.840.1.101.3.2.1.48.4", "nistTestPolicy4" }, + { "2.16.840.1.101.3.2.1.48.5", "nistTestPolicy5" }, + { "2.16.840.1.101.3.2.1.48.6", "nistTestPolicy6" }, + { "2.16.840.1.101.3.2.2", "gak" }, + { "2.16.840.1.101.3.2.2.1", "kRAKey" }, + { "2.16.840.1.101.3.2.3", "extensions" }, + { "2.16.840.1.101.3.2.3.1", "kRTechnique" }, + { "2.16.840.1.101.3.2.3.2", "kRecoveryCapable" }, + { "2.16.840.1.101.3.2.3.3", "kR" }, + { "2.16.840.1.101.3.2.4", "keyRecoverySchemes" }, + { "2.16.840.1.101.3.2.5", "krapola" }, + { "2.16.840.1.101.3.3", "arpa" }, + { "2.16.840.1.101.3.4", "nistAlgorithm" }, + { "2.16.840.1.101.3.4.1", "aes" }, + { "2.16.840.1.101.3.4.1.1", "aes128-ECB" }, + { "2.16.840.1.101.3.4.1.2", "aes128-CBC" }, + { "2.16.840.1.101.3.4.1.21", "aes192-ECB" }, + { "2.16.840.1.101.3.4.1.22", "aes192-CBC" }, + { "2.16.840.1.101.3.4.1.23", "aes192-OFB" }, + { "2.16.840.1.101.3.4.1.24", "aes192-CFB" }, + { "2.16.840.1.101.3.4.1.25", "aes192-wrap" }, + { "2.16.840.1.101.3.4.1.26", "aes192-GCM" }, + { "2.16.840.1.101.3.4.1.27", "aes192-CCM" }, + { "2.16.840.1.101.3.4.1.28", "aes192-wrap-pad" }, + { "2.16.840.1.101.3.4.1.3", "aes128-OFB" }, + { "2.16.840.1.101.3.4.1.4", "aes128-CFB" }, + { "2.16.840.1.101.3.4.1.41", "aes256-ECB" }, + { "2.16.840.1.101.3.4.1.42", "aes256-CBC" }, + { "2.16.840.1.101.3.4.1.43", "aes256-OFB" }, + { "2.16.840.1.101.3.4.1.44", "aes256-CFB" }, + { "2.16.840.1.101.3.4.1.45", "aes256-wrap" }, + { "2.16.840.1.101.3.4.1.46", "aes256-GCM" }, + { "2.16.840.1.101.3.4.1.47", "aes256-CCM" }, + { "2.16.840.1.101.3.4.1.48", "aes256-wrap-pad" }, + { "2.16.840.1.101.3.4.1.5", "aes128-wrap" }, + { "2.16.840.1.101.3.4.1.6", "aes128-GCM" }, + { "2.16.840.1.101.3.4.1.7", "aes128-CCM" }, + { "2.16.840.1.101.3.4.1.8", "aes128-wrap-pad" }, + { "2.16.840.1.101.3.4.2", "hashAlgos" }, + { "2.16.840.1.101.3.4.2.1", "sha-256" }, + { "2.16.840.1.101.3.4.2.2", "sha-384" }, + { "2.16.840.1.101.3.4.2.3", "sha-512" }, + { "2.16.840.1.101.3.4.2.4", "sha-224" }, + { "2.16.840.1.101.3.4.3.1", "dsaWithSha224" }, + { "2.16.840.1.101.3.4.3.2", "dsaWithSha256" }, + { "2.16.840.1.113719.1.2.8", "novellAlgorithm" }, + { "2.16.840.1.113719.1.2.8.130", "md4Packet" }, + { "2.16.840.1.113719.1.2.8.131", "rsaEncryptionBsafe1" }, + { "2.16.840.1.113719.1.2.8.132", "nwPassword" }, + { "2.16.840.1.113719.1.2.8.133", "novellObfuscate-1" }, + { "2.16.840.1.113719.1.2.8.22", "desCbcIV8" }, + { "2.16.840.1.113719.1.2.8.23", "desCbcPadIV8" }, + { "2.16.840.1.113719.1.2.8.24", "desEDE2CbcIV8" }, + { "2.16.840.1.113719.1.2.8.25", "desEDE2CbcPadIV8" }, + { "2.16.840.1.113719.1.2.8.26", "desEDE3CbcIV8" }, + { "2.16.840.1.113719.1.2.8.27", "desEDE3CbcPadIV8" }, + { "2.16.840.1.113719.1.2.8.28", "rc5CbcPad" }, + { "2.16.840.1.113719.1.2.8.29", "md2WithRSAEncryptionBSafe1" }, + { "2.16.840.1.113719.1.2.8.30", "md5WithRSAEncryptionBSafe1" }, + { "2.16.840.1.113719.1.2.8.31", "sha1WithRSAEncryptionBSafe1" }, + { "2.16.840.1.113719.1.2.8.32", "lmDigest" }, + { "2.16.840.1.113719.1.2.8.40", "md2" }, + { "2.16.840.1.113719.1.2.8.50", "md5" }, + { "2.16.840.1.113719.1.2.8.51", "ikeHmacWithSHA1-RSA" }, + { "2.16.840.1.113719.1.2.8.52", "ikeHmacWithMD5-RSA" }, + { "2.16.840.1.113719.1.2.8.69", "rc2CbcPad" }, + { "2.16.840.1.113719.1.2.8.82", "sha-1" }, + { "2.16.840.1.113719.1.2.8.92", "rc2BSafe1Cbc" }, + { "2.16.840.1.113719.1.2.8.95", "md4" }, + { "2.16.840.1.113719.1.9", "pki" }, + { "2.16.840.1.113719.1.9.4", "pkiAttributeType" }, + { "2.16.840.1.113719.1.9.4.1", "securityAttributes" }, + { "2.16.840.1.113719.1.9.4.2", "relianceLimit" }, + { "2.16.840.1.113730", "netscape" }, + { "2.16.840.1.113730.1", "cert-extension" }, + { "2.16.840.1.113730.1.1", "netscape-cert-type" }, + { "2.16.840.1.113730.1.10", "EntityLogo" }, + { "2.16.840.1.113730.1.11", "UserPicture" }, + { "2.16.840.1.113730.1.12", "netscape-ssl-server-name" }, + { "2.16.840.1.113730.1.13", "netscape-comment" }, + { "2.16.840.1.113730.1.2", "netscape-base-url" }, + { "2.16.840.1.113730.1.3", "netscape-revocation-url" }, + { "2.16.840.1.113730.1.4", "netscape-ca-revocation-url" }, + { "2.16.840.1.113730.1.7", "netscape-cert-renewal-url" }, + { "2.16.840.1.113730.1.8", "netscape-ca-policy-url" }, + { "2.16.840.1.113730.1.9", "HomePage-url" }, + { "2.16.840.1.113730.2", "data-type" }, + { "2.16.840.1.113730.2.1", "dataGIF" }, + { "2.16.840.1.113730.2.2", "dataJPEG" }, + { "2.16.840.1.113730.2.3", "dataURL" }, + { "2.16.840.1.113730.2.4", "dataHTML" }, + { "2.16.840.1.113730.2.5", "certSequence" }, + { "2.16.840.1.113730.2.6", "certURL" }, + { "2.16.840.1.113730.3", "directory" }, + { "2.16.840.1.113730.3.1", "ldapDefinitions" }, + { "2.16.840.1.113730.3.1.1", "carLicense" }, + { "2.16.840.1.113730.3.1.2", "departmentNumber" }, + { "2.16.840.1.113730.3.1.3", "employeeNumber" }, + { "2.16.840.1.113730.3.1.4", "employeeType" }, + { "2.16.840.1.113730.3.2.2", "inetOrgPerson" }, + { "2.16.840.1.113730.4.1", "serverGatedCrypto" }, + { "2.16.840.1.113733.1", "pki" }, + { "2.16.840.1.113733.1.9", "pkcs7Attribute" }, + { "2.16.840.1.113733.1.9.2", "messageType" }, + { "2.16.840.1.113733.1.9.3", "pkiStatus" }, + { "2.16.840.1.113733.1.9.4", "failInfo" }, + { "2.16.840.1.113733.1.9.5", "senderNonce" }, + { "2.16.840.1.113733.1.9.6", "recipientNonce" }, + { "2.16.840.1.113733.1.9.7", "transID" }, + { "2.16.840.1.113733.1.9.8", "extensionReq" }, + { "2.16.840.1.113741.2", "intelCDSA" }, + { "2.16.840.1.114027.10.4", "entrustAdminServicesClients" }, + { "2.16.840.1.114027.10.5", "entrustAdminServicesServer" }, + { "2.16.840.1.114027.80.2.1", "id-PKIXCMP-stdECDHwithX963SHA1" }, + { "2.16.840.1.114027.80.2.1", "id-PKIXCMP-stdECDHwithX963SHA1" }, + { "2.16.840.1.114412.1", "digiCertNonEVCerts" }, + { "2.16.840.1.114412.1.1", "digiCertOVCert" }, + { "2.16.840.1.114412.1.11", "digiCertFederatedDeviceCert" }, + { "2.16.840.1.114412.1.2", "digiCertDVCert" }, + { "2.16.840.1.114412.1.3.0.1", "digiCertGlobalCAPolicy" }, + { "2.16.840.1.114412.1.3.0.2", "digiCertHighAssuranceEVCAPolicy" }, + { "2.16.840.1.114412.1.3.0.3", "digiCertGlobalRootCAPolicy" }, + { "2.16.840.1.114412.1.3.0.4", "digiCertAssuredIDRootCAPolicy" }, + { "2.16.840.1.114412.2.2", "digiCertEVCert" }, + { "2.16.840.1.114412.2.3", "digiCertObjectSigningCert" }, + { "2.16.840.1.114412.2.3.1", "digiCertCodeSigningCert" }, + { "2.16.840.1.114412.2.3.11", "digiCertKernelCodeSigningCert" }, + { "2.16.840.1.114412.2.3.2", "digiCertEVCodeSigningCert" }, + { "2.16.840.1.114412.2.3.21", "digiCertDocumentSigningCert" }, + { "2.16.840.1.114412.2.4", "digiCertClientCert" }, + { "2.16.840.1.114412.2.4.1.1", "digiCertLevel1PersonalClientCert" }, + { "2.16.840.1.114412.2.4.1.2", "digiCertLevel1EnterpriseClientCert" }, + { "2.16.840.1.114412.2.4.2", "digiCertLevel2ClientCert" }, + { "2.16.840.1.114412.2.4.3.1", "digiCertLevel3USClientCert" }, + { "2.16.840.1.114412.2.4.3.2", "digiCertLevel3CBPClientCert" }, + { "2.16.840.1.114412.2.4.4.1", "digiCertLevel4USClientCert" }, + { "2.16.840.1.114412.2.4.4.2", "digiCertLevel4CBPClientCert" }, + { "2.16.840.1.114412.2.4.5.1", "digiCertPIVHardwareCert" }, + { "2.16.840.1.114412.2.4.5.2", "digiCertPIVCardAuthCert" }, + { "2.16.840.1.114412.2.4.5.3", "digiCertPIVContentSigningCert" }, + { "2.16.840.1.114412.31.4.31.1", "digiCertGridHostCert" }, + { "2.16.840.1.114412.4.31", "digiCertGridClassicCert" }, + { "2.16.840.1.114412.4.31.5", "digiCertGridIntegratedCert" }, + { "2.23.133", "tCPA" }, + { "2.23.133.1", "tcpaSpecVersion" }, + { "2.23.133.2", "tcpaAttribute" }, + { "2.23.133.2.1", "tcpaTpmManufacturer" }, + { "2.23.133.2.10", "tcpaSecurityQualities" }, + { "2.23.133.2.11", "tcpaTpmProtectionProfile" }, + { "2.23.133.2.12", "tcpaTpmSecurityTarget" }, + { "2.23.133.2.13", "tcpaFoundationProtectionProfile" }, + { "2.23.133.2.14", "tcpaFoundationSecurityTarget" }, + { "2.23.133.2.15", "tcpaTpmIdLabel" }, + { "2.23.133.2.2", "tcpaTpmModel" }, + { "2.23.133.2.3", "tcpaTpmVersion" }, + { "2.23.133.2.4", "tcpaPlatformManufacturer" }, + { "2.23.133.2.5", "tcpaPlatformModel" }, + { "2.23.133.2.6", "tcpaPlatformVersion" }, + { "2.23.133.2.7", "tcpaComponentManufacturer" }, + { "2.23.133.2.8", "tcpaComponentModel" }, + { "2.23.133.2.9", "tcpaComponentVersion" }, + { "2.23.133.3", "tcpaProtocol" }, + { "2.23.133.3.1", "tcpaPrttTpmIdProtocol" }, + { "2.23.134.1.2.1.8.210", "postSignumCommercialServerPolicy" }, + { "2.23.134.1.2.2.3", "postSignumPublicCA." }, + { "2.23.134.1.4.2.1", "postSignumRootQCA.." }, + { "2.23.136.1.1.1", "mRTDSignatureData" }, + { "2.23.136.1.1.3", "id-icao-cscaMasterListSigningKey" }, + { "2.23.42.0", "contentType" }, + { "2.23.42.0.0", "panData" }, + { "2.23.42.0.1", "panToken" }, + { "2.23.42.0.2", "panOnly" }, + { "2.23.42.1", "msgExt" }, + { "2.23.42.10", "national" }, + { "2.23.42.10.392", "Japan" }, + { "2.23.42.2", "field" }, + { "2.23.42.2.0", "fullName" }, + { "2.23.42.2.1", "givenName" }, + { "2.23.42.2.10", "amount" }, + { "2.23.42.2.11", "accountNumber" }, + { "2.23.42.2.12", "passPhrase" }, + { "2.23.42.2.2", "familyName" }, + { "2.23.42.2.3", "birthFamilyName" }, + { "2.23.42.2.4", "placeName" }, + { "2.23.42.2.5", "identificationNumber" }, + { "2.23.42.2.6", "month" }, + { "2.23.42.2.7", "date" }, + { "2.23.42.2.7.11", "accountNumber" }, + { "2.23.42.2.7.12", "passPhrase" }, + { "2.23.42.2.8", "address" }, + { "2.23.42.2.9", "telephone" }, + { "2.23.42.3", "attribute" }, + { "2.23.42.3.0", "cert" }, + { "2.23.42.3.0.0", "rootKeyThumb" }, + { "2.23.42.3.0.1", "additionalPolicy" }, + { "2.23.42.4", "algorithm" }, + { "2.23.42.5", "policy" }, + { "2.23.42.5.0", "root" }, + { "2.23.42.6", "module" }, + { "2.23.42.7", "certExt" }, + { "2.23.42.7.0", "hashedRootKey" }, + { "2.23.42.7.1", "certificateType" }, + { "2.23.42.7.2", "merchantData" }, + { "2.23.42.7.3", "cardCertRequired" }, + { "2.23.42.7.4", "tunneling" }, + { "2.23.42.7.5", "setExtensions" }, + { "2.23.42.7.6", "setQualifier" }, + { "2.23.42.8", "brand" }, + { "2.23.42.8.1", "IATA-ATA" }, + { "2.23.42.8.30", "Diners" }, + { "2.23.42.8.34", "AmericanExpress" }, + { "2.23.42.8.4", "VISA" }, + { "2.23.42.8.5", "MasterCard" }, + { "2.23.42.8.6011", "Novus" }, + { "2.23.42.9", "vendor" }, + { "2.23.42.9.0", "GlobeSet" }, + { "2.23.42.9.1", "IBM" }, + { "2.23.42.9.10", "Griffin" }, + { "2.23.42.9.11", "Certicom" }, + { "2.23.42.9.12", "OSS" }, + { "2.23.42.9.13", "TenthMountain" }, + { "2.23.42.9.14", "Antares" }, + { "2.23.42.9.15", "ECC" }, + { "2.23.42.9.16", "Maithean" }, + { "2.23.42.9.17", "Netscape" }, + { "2.23.42.9.18", "Verisign" }, + { "2.23.42.9.19", "BlueMoney" }, + { "2.23.42.9.2", "CyberCash" }, + { "2.23.42.9.20", "Lacerte" }, + { "2.23.42.9.21", "Fujitsu" }, + { "2.23.42.9.22", "eLab" }, + { "2.23.42.9.23", "Entrust" }, + { "2.23.42.9.24", "VIAnet" }, + { "2.23.42.9.25", "III" }, + { "2.23.42.9.26", "OpenMarket" }, + { "2.23.42.9.27", "Lexem" }, + { "2.23.42.9.28", "Intertrader" }, + { "2.23.42.9.29", "Persimmon" }, + { "2.23.42.9.3", "Terisa" }, + { "2.23.42.9.30", "NABLE" }, + { "2.23.42.9.31", "espace-net" }, + { "2.23.42.9.32", "Hitachi" }, + { "2.23.42.9.33", "Microsoft" }, + { "2.23.42.9.34", "NEC" }, + { "2.23.42.9.35", "Mitsubishi" }, + { "2.23.42.9.36", "NCR" }, + { "2.23.42.9.37", "e-COMM" }, + { "2.23.42.9.38", "Gemplus" }, + { "2.23.42.9.4", "RSADSI" }, + { "2.23.42.9.5", "VeriFone" }, + { "2.23.42.9.6", "TrinTech" }, + { "2.23.42.9.7", "BankGate" }, + { "2.23.42.9.8", "GTE" }, + { "2.23.42.9.9", "CompuSource" }, + { "2.23.43.1.4", "wTLS-ECC" }, + { "2.23.43.1.4.1", "wTLS-ECC-curve1" }, + { "2.23.43.1.4.6", "wTLS-ECC-curve6" }, + { "2.23.43.1.4.8", "wTLS-ECC-curve8" }, + { "2.23.43.1.4.9", "wTLS-ECC-curve9" }, + { "2.5.29.1", "authorityKeyIdentifier" }, + { "2.5.29.10", "basicConstraints" }, + { "2.5.29.11", "nameConstraints" }, + { "2.5.29.12", "policyConstraints" }, + { "2.5.29.13", "basicConstraints" }, + { "2.5.29.14", "subjectKeyIdentifier" }, + { "2.5.29.15", "keyUsage" }, + { "2.5.29.16", "privateKeyUsagePeriod" }, + { "2.5.29.17", "subjectAltName" }, + { "2.5.29.18", "issuerAltName" }, + { "2.5.29.19", "basicConstraints" }, + { "2.5.29.2", "keyAttributes" }, + { "2.5.29.20", "cRLNumber" }, + { "2.5.29.21", "cRLReason" }, + { "2.5.29.22", "expirationDate" }, + { "2.5.29.23", "instructionCode" }, + { "2.5.29.24", "invalidityDate" }, + { "2.5.29.25", "cRLDistributionPoints" }, + { "2.5.29.26", "issuingDistributionPoint" }, + { "2.5.29.27", "deltaCRLIndicator" }, + { "2.5.29.28", "issuingDistributionPoint" }, + { "2.5.29.29", "certificateIssuer" }, + { "2.5.29.3", "certificatePolicies" }, + { "2.5.29.30", "nameConstraints" }, + { "2.5.29.31", "cRLDistributionPoints" }, + { "2.5.29.32", "certificatePolicies" }, + { "2.5.29.32.0", "anyPolicy" }, + { "2.5.29.33", "policyMappings" }, + { "2.5.29.34", "policyConstraints" }, + { "2.5.29.35", "authorityKeyIdentifier" }, + { "2.5.29.36", "policyConstraints" }, + { "2.5.29.37", "extKeyUsage" }, + { "2.5.29.37.0", "anyExtendedKeyUsage" }, + { "2.5.29.38", "authorityAttributeIdentifier" }, + { "2.5.29.39", "roleSpecCertIdentifier" }, + { "2.5.29.4", "keyUsageRestriction" }, + { "2.5.29.40", "cRLStreamIdentifier" }, + { "2.5.29.41", "basicAttConstraints" }, + { "2.5.29.42", "delegatedNameConstraints" }, + { "2.5.29.43", "timeSpecification" }, + { "2.5.29.44", "cRLScope" }, + { "2.5.29.45", "statusReferrals" }, + { "2.5.29.46", "freshestCRL" }, + { "2.5.29.47", "orderedList" }, + { "2.5.29.48", "attributeDescriptor" }, + { "2.5.29.49", "userNotice" }, + { "2.5.29.5", "policyMapping" }, + { "2.5.29.50", "sOAIdentifier" }, + { "2.5.29.51", "baseUpdateTime" }, + { "2.5.29.52", "acceptableCertPolicies" }, + { "2.5.29.53", "deltaInfo" }, + { "2.5.29.54", "inhibitAnyPolicy" }, + { "2.5.29.55", "targetInformation" }, + { "2.5.29.56", "noRevAvail" }, + { "2.5.29.57", "acceptablePrivilegePolicies" }, + { "2.5.29.58", "toBeRevoked" }, + { "2.5.29.59", "revokedGroups" }, + { "2.5.29.6", "subtreesConstraint" }, + { "2.5.29.60", "expiredCertsOnCRL" }, + { "2.5.29.61", "indirectIssuer" }, + { "2.5.29.62", "noAssertion" }, + { "2.5.29.63", "aAissuingDistributionPoint" }, + { "2.5.29.64", "issuedOnBehalfOf" }, + { "2.5.29.65", "singleUse" }, + { "2.5.29.66", "groupAC" }, + { "2.5.29.67", "allowedAttAss" }, + { "2.5.29.68", "attributeMappings" }, + { "2.5.29.69", "holderNameConstraints" }, + { "2.5.29.7", "subjectAltName" }, + { "2.5.29.8", "issuerAltName" }, + { "2.5.29.9", "subjectDirectoryAttributes" }, + { "2.5.4.0", "objectClass" }, + { "2.5.4.1", "aliasedEntryName" }, + { "2.5.4.10", "organizationName" }, + { "2.5.4.10.1", "collectiveOrganizationName" }, + { "2.5.4.11", "organizationalUnitName" }, + { "2.5.4.11.1", "collectiveOrganizationalUnitName" }, + { "2.5.4.12", "title" }, + { "2.5.4.13", "description" }, + { "2.5.4.14", "searchGuide" }, + { "2.5.4.15", "businessCategory" }, + { "2.5.4.16", "postalAddress" }, + { "2.5.4.16.1", "collectivePostalAddress" }, + { "2.5.4.17", "postalCode" }, + { "2.5.4.17.1", "collectivePostalCode" }, + { "2.5.4.18", "postOfficeBox" }, + { "2.5.4.18.1", "collectivePostOfficeBox" }, + { "2.5.4.19", "physicalDeliveryOfficeName" }, + { "2.5.4.19.1", "collectivePhysicalDeliveryOfficeName" }, + { "2.5.4.2", "knowledgeInformation" }, + { "2.5.4.20", "telephoneNumber" }, + { "2.5.4.20.1", "collectiveTelephoneNumber" }, + { "2.5.4.21", "telexNumber" }, + { "2.5.4.21.1", "collectiveTelexNumber" }, + { "2.5.4.22", "teletexTerminalIdentifier" }, + { "2.5.4.22.1", "collectiveTeletexTerminalIdentifier" }, + { "2.5.4.23", "facsimileTelephoneNumber" }, + { "2.5.4.23.1", "collectiveFacsimileTelephoneNumber" }, + { "2.5.4.24", "x121Address" }, + { "2.5.4.25", "internationalISDNNumber" }, + { "2.5.4.25.1", "collectiveInternationalISDNNumber" }, + { "2.5.4.26", "registeredAddress" }, + { "2.5.4.27", "destinationIndicator" }, + { "2.5.4.28", "preferredDeliveryMehtod" }, + { "2.5.4.29", "presentationAddress" }, + { "2.5.4.3", "commonName" }, + { "2.5.4.30", "supportedApplicationContext" }, + { "2.5.4.31", "member" }, + { "2.5.4.32", "owner" }, + { "2.5.4.33", "roleOccupant" }, + { "2.5.4.34", "seeAlso" }, + { "2.5.4.35", "userPassword" }, + { "2.5.4.36", "userCertificate" }, + { "2.5.4.37", "caCertificate" }, + { "2.5.4.38", "authorityRevocationList" }, + { "2.5.4.39", "certificateRevocationList" }, + { "2.5.4.4", "surname" }, + { "2.5.4.40", "crossCertificatePair" }, + { "2.5.4.41", "name" }, + { "2.5.4.42", "givenName" }, + { "2.5.4.43", "initials" }, + { "2.5.4.44", "generationQualifier" }, + { "2.5.4.45", "uniqueIdentifier" }, + { "2.5.4.46", "dnQualifier" }, + { "2.5.4.47", "enhancedSearchGuide" }, + { "2.5.4.48", "protocolInformation" }, + { "2.5.4.49", "distinguishedName" }, + { "2.5.4.5", "serialNumber" }, + { "2.5.4.50", "uniqueMember" }, + { "2.5.4.51", "houseIdentifier" }, + { "2.5.4.52", "supportedAlgorithms" }, + { "2.5.4.53", "deltaRevocationList" }, + { "2.5.4.54", "dmdName" }, + { "2.5.4.55", "clearance" }, + { "2.5.4.56", "defaultDirQop" }, + { "2.5.4.57", "attributeIntegrityInfo" }, + { "2.5.4.58", "attributeCertificate" }, + { "2.5.4.59", "attributeCertificateRevocationList" }, + { "2.5.4.6", "countryName" }, + { "2.5.4.60", "confKeyInfo" }, + { "2.5.4.61", "aACertificate" }, + { "2.5.4.62", "attributeDescriptorCertificate" }, + { "2.5.4.63", "attributeAuthorityRevocationList" }, + { "2.5.4.64", "familyInformation" }, + { "2.5.4.65", "pseudonym" }, + { "2.5.4.66", "communicationsService" }, + { "2.5.4.67", "communicationsNetwork" }, + { "2.5.4.68", "certificationPracticeStmt" }, + { "2.5.4.69", "certificatePolicy" }, + { "2.5.4.7", "localityName" }, + { "2.5.4.7.1", "collectiveLocalityName" }, + { "2.5.4.70", "pkiPath" }, + { "2.5.4.71", "privPolicy" }, + { "2.5.4.72", "role" }, + { "2.5.4.73", "delegationPath" }, + { "2.5.4.74", "protPrivPolicy" }, + { "2.5.4.75", "xMLPrivilegeInfo" }, + { "2.5.4.76", "xmlPrivPolicy" }, + { "2.5.4.8", "stateOrProvinceName" }, + { "2.5.4.8.1", "collectiveStateOrProvinceName" }, + { "2.5.4.82", "permission" }, + { "2.5.4.9", "streetAddress" }, + { "2.5.4.9.1", "collectiveStreetAddress" }, + { "2.5.6.0", "top" }, + { "2.5.6.1", "alias" }, + { "2.5.6.10", "residentialPerson" }, + { "2.5.6.11", "applicationProcess" }, + { "2.5.6.12", "applicationEntity" }, + { "2.5.6.13", "dSA" }, + { "2.5.6.14", "device" }, + { "2.5.6.15", "strongAuthenticationUser" }, + { "2.5.6.16", "certificateAuthority" }, + { "2.5.6.17", "groupOfUniqueNames" }, + { "2.5.6.19", "cRLDistributionPoint" }, + { "2.5.6.2", "country" }, + { "2.5.6.21", "pkiUser" }, + { "2.5.6.22", "pkiCA" }, + { "2.5.6.3", "locality" }, + { "2.5.6.4", "organization" }, + { "2.5.6.5", "organizationalUnit" }, + { "2.5.6.6", "person" }, + { "2.5.6.7", "organizationalPerson" }, + { "2.5.6.8", "organizationalRole" }, + { "2.5.6.9", "groupOfNames" }, + { "2.5.8", "X.500-Algorithms" }, + { "2.5.8.1", "X.500-Alg-Encryption" }, + { "2.5.8.1.1", "rsa" }, + { "2.5.8.2.1", "sqMod_n" }, + { "2.5.8.3.1", "sqMod_nWithRSA" }, + { "2.54.1775.2", "hashedRootKey" }, + { "2.54.1775.3", "certificateType" }, + { "2.54.1775.4", "merchantData" }, + { "2.54.1775.5", "cardCertRequired" }, + { "2.54.1775.6", "tunneling" }, + { "2.54.1775.7", "setQualifier" }, + { "2.54.1775.99", "setData" }, {0, 0} }; diff --git a/libr/util/format.c b/libr/util/format.c index d478c3b645..6c0b115267 100644 --- a/libr/util/format.c +++ b/libr/util/format.c @@ -668,7 +668,7 @@ static void r_print_format_hex(const RPrint* p, int endian, int mode, const char if (elem > -1) { elem--; } - i +=4; + i += 4; } p->cb_printf (" ]"); } @@ -722,7 +722,7 @@ static void r_print_format_int(const RPrint* p, int endian, int mode, const char if (size == -1) { p->cb_printf ("%"PFMT64d, addr); } else { - p->cb_printf ("[ "); + p->cb_printf ("["); while (size--) { updateAddr (buf + i, size - i, endian, &addr, NULL); if (elem == -1 || elem == 0) { @@ -955,7 +955,7 @@ static int r_print_format_10bytes(const RPrint* p, int mode, const char *setval, for (; j < 10; j++) { p->cb_printf (", %d", buf[j]); } - p->cb_printf ("]"); + p->cb_printf (" ]"); return 0; } return 0; @@ -998,7 +998,7 @@ static int r_print_format_hexpairs(const RPrint* p, int endian, int mode, const for (; j < 10; j++) { p->cb_printf (", %d", buf[j]); } - p->cb_printf ("]"); + p->cb_printf (" ]"); if (MUSTSEEJSON) { p->cb_printf ("}"); } diff --git a/libr/util/graph_drawable.c b/libr/util/graph_drawable.c index 7ddc455b20..2063262a07 100644 --- a/libr/util/graph_drawable.c +++ b/libr/util/graph_drawable.c @@ -1,14 +1,15 @@ +/* radare - LGPL - Copyright 2007-2020 - pancake, ret2libc */ + #include #include R_API void r_graph_free_node_info(void *ptr) { - if (!ptr) { - return; + if (ptr) { + RGraphNodeInfo *info = ptr; + free (info->body); + free (info->title); + free (info); } - RGraphNodeInfo *info = ptr; - free (info->body); - free (info->title); - free (info); } R_API RGraphNodeInfo *r_graph_create_node_info(const char *title, const char *body, ut64 offset) { diff --git a/libr/util/print.c b/libr/util/print.c index c1050da21a..5bac00b3d9 100644 --- a/libr/util/print.c +++ b/libr/util/print.c @@ -1650,7 +1650,7 @@ R_API void r_print_c(RPrint *p, const ut8 *str, int len) { p->cb_printf ("\n"); } } - p->cb_printf (" };\n"); + p->cb_printf ("};\n"); } // HACK :D diff --git a/libr/util/print_code.c b/libr/util/print_code.c index 27d3db8701..7176ae9c87 100644 --- a/libr/util/print_code.c +++ b/libr/util/print_code.c @@ -293,7 +293,7 @@ R_API void r_print_code(RPrint *p, ut64 addr, const ut8 *buf, int len, char lang p->cb_printf (" %02x", buf[i] & 0xff); r_print_cursor (p, i, 1, 0); } - p->cb_printf (" }\n"); + p->cb_printf ("}\n"); break; case 'j': // "pcj" p->cb_printf ("["); diff --git a/libr/util/protobuf.c b/libr/util/protobuf.c index 534db8e403..076748efa8 100644 --- a/libr/util/protobuf.c +++ b/libr/util/protobuf.c @@ -207,7 +207,7 @@ static char *decode_buffer(PJ *pj, const ut8* start, const ut8* end, int padcnt, if (mode == 'j' || mode == 'J') { pj_o (pj); } else { - r_strbuf_append (sb, " {\n"); + r_strbuf_append (sb, "{\n"); } padcnt++; break; diff --git a/libr/util/qrcode.c b/libr/util/qrcode.c index 82567c7c23..1e65d286ba 100644 --- a/libr/util/qrcode.c +++ b/libr/util/qrcode.c @@ -994,7 +994,7 @@ static void setModuleBounded(ut8 qrcode[], int x, int y, bool isBlack) { static char qrcode_utf8_expansions[16][7] = { " ","▀ "," ▀","▀▀", "▄ ","█ ","▄▀","█▀", " ▄","▀▄"," █","▀█", - "▄▄","█▄","▄█","██"}; + "▄▄","█▄","▄█","██" }; R_API char *r_qrcode_gen(const ut8 *text, int len, bool utf8, bool inverted) { uint8_t qrcode[qrcodegen_BUFFER_LEN_MAX] = { diff --git a/libr/util/regex/cclass.h b/libr/util/regex/cclass.h index fce1bf0c95..ec3cdcd036 100644 --- a/libr/util/regex/cclass.h +++ b/libr/util/regex/cclass.h @@ -41,17 +41,17 @@ static struct cclass { const char *chars; const char *multis; } cclasses[] = { - { "alnum", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789", ""}, - { "alpha", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz", ""}, - { "blank", " \t", ""}, - { "cntrl", "\007\b\t\n\v\f\r\1\2\3\4\5\6\16\17\20\21\22\23\24\25\26\27\30\31\32\33\34\35\36\37\177", ""}, - { "digit", "0123456789", ""}, - { "graph", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz 0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", ""}, - { "lower", "abcdefghijklmnopqrstuvwxyz", ""}, - { "print", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~ ", ""}, - { "punct", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", ""}, - { "space", "\t\n\v\f\r ", ""}, - { "upper", "ABCDEFGHIJKLMNOPQRSTUVWXYZ", ""}, - { "xdigit", "0123456789ABCDEFabcdef", ""}, + { "alnum", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789", "" }, + { "alpha", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz", "" }, + { "blank", " \t", "" }, + { "cntrl", "\007\b\t\n\v\f\r\1\2\3\4\5\6\16\17\20\21\22\23\24\25\26\27\30\31\32\33\34\35\36\37\177", "" }, + { "digit", "0123456789", "" }, + { "graph", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz 0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", "" }, + { "lower", "abcdefghijklmnopqrstuvwxyz", "" }, + { "print", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~ ", "" }, + { "punct", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", "" }, + { "space", "\t\n\v\f\r ", "" }, + { "upper", "ABCDEFGHIJKLMNOPQRSTUVWXYZ", "" }, + { "xdigit", "0123456789ABCDEFabcdef", "" }, { NULL, NULL, "" } }; diff --git a/libr/util/sstext.c b/libr/util/sstext.c index a0efe62153..70f74d0cf0 100644 --- a/libr/util/sstext.c +++ b/libr/util/sstext.c @@ -9,441 +9,441 @@ typedef struct { // seven segment ascii-art text static const SevenSegments ss_lc[] = { - { '0', {" __ ", + { '0', { " __ ", "| /|", - "|/_|"} + "|/_|" } }, - { '1', {" ", + { '1', { " ", " | ", - " | "} + " | " } }, - { '2', {" __ ", + { '2', { " __ ", " __|", - "|__ "} + "|__ " } }, - { '3', {" __ ", + { '3', { " __ ", " __|", - " __|"} + " __|" } }, - { '4', {" ", + { '4', { " ", "|__|", - " |"} + " |" } }, - { '5', {" __ ", + { '5', { " __ ", "|__ ", - " __|"} + " __|" } }, - { '6', {" __ ", + { '6', { " __ ", "|__ ", - "|__|"} + "|__|" } }, - { '7', {" __ ", + { '7', { " __ ", " |", - " |"} + " |" } }, - { '8', {" __ ", + { '8', { " __ ", "|__|", - "|__|"} + "|__|" } }, - { '9', {" __ ", + { '9', { " __ ", "|__|", - " __|"} + " __|" } }, - { '$', {" __ ", + { '$', { " __ ", "||_ ", - " _||"} + " _||" } }, - { '_', {" ", + { '_', { " ", " ", - " __ "} + " __ " } }, - { '.', {" ", + { '.', { " ", " ", - " _ "} + " _ " } }, - { ',', {" ", + { ',', { " ", " ", - " _ "} + " _ " } }, - { '/', {" ", + { '/', { " ", " / ", - " / "} + " / " } }, - { '%', {" ", + { '%', { " ", " O/ ", - " /O "} + " /O " } }, - { '=', {" ", + { '=', { " ", " __ ", - " __ "} + " __ " } }, - { '"', {" __ ", + { '"', { " __ ", " ", - " "} + " " } }, - { '?', {" __ ", + { '?', { " __ ", " _|", - " _\\ "} + " _\\ " } }, - { '+', {" ", + { '+', { " ", " _|_", - " | "} + " | " } }, - { '-', {" ", + { '-', { " ", " __ ", - " "} + " " } }, - { '*', {" ", + { '*', { " ", "_\\/_", - " /\\ "} + " /\\ " } }, - { '(', {" _ ", + { '(', { " _ ", "| ", - "|_ "} + "|_ " } }, - { ')', {" _ ", + { ')', { " _ ", " |", - " _|"} + " _|" } }, - { '[', {" _ ", + { '[', { " _ ", "| ", - "|_ "} + "|_ " } }, - { ']', {" _ ", + { ']', { " _ ", " |", - " _|"} + " _|" } }, - { '>', {" ", + { '>', { " ", " \\ ", - " / "} + " / " } }, - { ' ', {" ", + { ' ', { " ", " ", - " "} + " " } }, - { 'a', {" _ ", + { 'a', { " _ ", " _|", - " /_|"} + " /_|" } }, - { 'b', {" ", + { 'b', { " ", "|_ ", - "|_\\ "} + "|_\\ " } }, - { 'c', {" ", + { 'c', { " ", " __ ", - "|__ "} + "|__ " } }, - { 'd', {" ", + { 'd', { " ", " _|", - " /_|"} + " /_|" } }, - { 'e', {" _ ", + { 'e', { " _ ", "|_\\ ", - "|__ "} + "|__ " } }, - { 'f', {" __ ", + { 'f', { " __ ", "|_ ", - "| "} + "| " } }, - { 'g', {" __ ", + { 'g', { " __ ", " \\_|", - "|__|"} + "|__|" } }, - { 'h', {" ", + { 'h', { " ", "|_ ", - "| \\ "} + "| \\ " } }, - { 'i', {" ", + { 'i', { " ", " _ ", - " | "} + " | " } }, - { 'j', {" __ ", + { 'j', { " __ ", " | ", - "|_| "} + "|_| " } }, - { 'k', {" ", + { 'k', { " ", "|_/ ", - "| \\ "} + "| \\ " } }, - { 'l', {" ", + { 'l', { " ", " ", - "|___"} + "|___" } }, - { 'm', {" ", + { 'm', { " ", " ", - "|\\/|"} + "|\\/|" } }, - { 'n', {" ", + { 'n', { " ", " __ ", - "| |"} + "| |" } }, - { 'o', {" ", + { 'o', { " ", " __ ", - "|__|"} + "|__|" } }, - { 'p', {" __ ", + { 'p', { " __ ", "|__|", - "| "} + "| " } }, - { 'q', {" __ ", + { 'q', { " __ ", "|__|", - " \\ "} + " \\ " } }, - { 'r', {" __ ", + { 'r', { " __ ", "|__|", - "| \\ "} + "| \\ " } }, - { 's', {" ", + { 's', { " ", " _ ", - " _\\"} + " _\\" } }, - { 't', {" ", + { 't', { " ", "_|_ ", - " |__"} + " |__" } }, - { 'u', {" ", + { 'u', { " ", " ", - "|__|"} + "|__|" } }, - { 'v', {" ", + { 'v', { " ", "| |", - " \\/ "} + " \\/ " } }, - { 'w', {" ", + { 'w', { " ", " ", - "|/\\|"} + "|/\\|" } }, - { 'x', {" ", + { 'x', { " ", " \\/ ", - " /\\ "} + " /\\ " } }, - { 'y', {" ", + { 'y', { " ", " \\_|", - " _|"} + " _|" } }, - { 'z', {" ", + { 'z', { " ", " _ ", - " /_ "} + " /_ " } }, { '\0', {0}} }; static const SevenSegments ss[] = { - { '0', {" __ ", + { '0', { " __ ", "| |", - "|__|"} + "|__|" } }, - { '1', {" ", + { '1', { " ", " | ", - " | "} + " | " } }, - { '2', {" __ ", + { '2', { " __ ", " __|", - "|__ "} + "|__ " } }, - { '3', {" __ ", + { '3', { " __ ", " __|", - " __|"} + " __|" } }, - { '4', {" ", + { '4', { " ", "|__|", - " |"} + " |" } }, - { '5', {" __ ", + { '5', { " __ ", "|__ ", - " __|"} + " __|" } }, - { '6', {" __ ", + { '6', { " __ ", "|__ ", - "|__|"} + "|__|" } }, - { '7', {" __ ", + { '7', { " __ ", " |", - " |"} + " |" } }, - { '8', {" __ ", + { '8', { " __ ", "|__|", - "|__|"} + "|__|" } }, - { '9', {" __ ", + { '9', { " __ ", "|__|", - " __|"} + " __|" } }, - { '$', {" __ ", + { '$', { " __ ", "||_ ", - " _||"} + " _||" } }, - { '_', {" ", + { '_', { " ", " ", - " __ "} + " __ " } }, - { '.', {" ", + { '.', { " ", " ", - " _ "} + " _ " } }, - { ',', {" ", + { ',', { " ", " ", - " _ "} + " _ " } }, - { '/', {" ", + { '/', { " ", " / ", - " / "} + " / " } }, - { '%', {" ", + { '%', { " ", " O/ ", - " /O "} + " /O " } }, - { '=', {" ", + { '=', { " ", " __ ", - " __ "} + " __ " } }, - { '"', {" __ ", + { '"', { " __ ", " ", - " "} + " " } }, - { '?', {" __ ", + { '?', { " __ ", " _|", - " _\\ "} + " _\\ " } }, - { '+', {" ", + { '+', { " ", " _|_", - " | "} + " | " } }, - { '-', {" ", + { '-', { " ", " __ ", - " "} + " " } }, - { '*', {" ", + { '*', { " ", "_\\/_", - " /\\ "} + " /\\ " } }, - { '(', {" _ ", + { '(', { " _ ", "| ", - "|_ "} + "|_ " } }, - { ')', {" _ ", + { ')', { " _ ", " |", - " _|"} + " _|" } }, - { '[', {" _ ", + { '[', { " _ ", "| ", - "|_ "} + "|_ " } }, - { ']', {" _ ", + { ']', { " _ ", " |", - " _|"} + " _|" } }, - { '>', {" ", + { '>', { " ", " \\ ", - " / "} + " / " } }, - { ' ', {" ", + { ' ', { " ", " ", - " "} + " " } }, - { 'a', {" __ ", + { 'a', { " __ ", "|__|", - "| |"} + "| |" } }, - { 'b', {" ", + { 'b', { " ", "|__ ", - "|__|"} + "|__|" } }, - { 'c', {" ", + { 'c', { " ", " __ ", - "|__ "} + "|__ " } }, - { 'd', {" ", + { 'd', { " ", " __|", - "|__|"} + "|__|" } }, - { 'e', {" __ ", + { 'e', { " __ ", "|_ ", - "|__ "} + "|__ " } }, - { 'f', {" __ ", + { 'f', { " __ ", "|_ ", - "| "} + "| " } }, - { 'g', {" __ ", + { 'g', { " __ ", "| _ ", - "|__|"} + "|__|" } }, - { 'h', {" ", + { 'h', { " ", "|__|", - "| |"} + "| |" } }, - { 'i', {" ___", + { 'i', { " ___", " | ", - " _|_"} + " _|_" } }, - { 'j', {" __ ", + { 'j', { " __ ", " | ", - "|_| "} + "|_| " } }, - { 'k', {" ", + { 'k', { " ", "|_/ ", - "| \\ "} + "| \\ " } }, - { 'l', {" ", + { 'l', { " ", "| ", - "|__ "} + "|__ " } }, - { 'm', {" ", + { 'm', { " ", "|\\/|", - "| |"} + "| |" } }, - { 'n', {" ", + { 'n', { " ", "|\\ |", - "| \\|"} + "| \\|" } }, - { 'o', {" __ ", + { 'o', { " __ ", "| |", - "|__|"} + "|__|" } }, - { 'p', {" __ ", + { 'p', { " __ ", "|__|", - "| "} + "| " } }, - { 'q', {" __ ", + { 'q', { " __ ", "|__|", - " \\ "} + " \\ " } }, - { 'r', {" __ ", + { 'r', { " __ ", "|__|", - "| \\ "} + "| \\ " } }, - { 's', {" __ ", + { 's', { " __ ", "|__ ", - " __\\"} + " __\\" } }, - { 't', {" ", + { 't', { " ", "_|_ ", - " |_ "} + " |_ " } }, - { 'u', {" ", + { 'u', { " ", " ", - "|__|"} + "|__|" } }, - { 'v', {" ", + { 'v', { " ", "| |", - " \\/ "} + " \\/ " } }, - { 'w', {" ", + { 'w', { " ", "| |", - "|/\\|"} + "|/\\|" } }, - { 'x', {" ", + { 'x', { " ", " \\/ ", - " /\\ "} + " /\\ " } }, - { 'y', {" ", + { 'y', { " ", "|__|", - " __|"} + " __|" } }, - { 'z', {" __ ", + { 'z', { " __ ", " / ", - " /_ "} + " /_ " } }, { '\0', {0}} }; diff --git a/libr/util/sys.c b/libr/util/sys.c index 2f9ebfd02a..96fe107cd9 100644 --- a/libr/util/sys.c +++ b/libr/util/sys.c @@ -117,28 +117,28 @@ R_LIB_VERSION (r_util); #endif static const struct {const char* name; ut64 bit;} arch_bit_array[] = { - {"x86", R_SYS_ARCH_X86}, - {"arm", R_SYS_ARCH_ARM}, - {"ppc", R_SYS_ARCH_PPC}, - {"m68k", R_SYS_ARCH_M68K}, - {"java", R_SYS_ARCH_JAVA}, - {"mips", R_SYS_ARCH_MIPS}, - {"sparc", R_SYS_ARCH_SPARC}, - {"xap", R_SYS_ARCH_XAP}, - {"tms320", R_SYS_ARCH_TMS320}, - {"msil", R_SYS_ARCH_MSIL}, - {"objd", R_SYS_ARCH_OBJD}, - {"bf", R_SYS_ARCH_BF}, - {"sh", R_SYS_ARCH_SH}, - {"avr", R_SYS_ARCH_AVR}, - {"dalvik", R_SYS_ARCH_DALVIK}, - {"z80", R_SYS_ARCH_Z80}, - {"arc", R_SYS_ARCH_ARC}, - {"i8080", R_SYS_ARCH_I8080}, - {"rar", R_SYS_ARCH_RAR}, - {"lm32", R_SYS_ARCH_LM32}, - {"v850", R_SYS_ARCH_V850}, - {"bpf", R_SYS_ARCH_BPF}, + { "x86", R_SYS_ARCH_X86}, + { "arm", R_SYS_ARCH_ARM}, + { "ppc", R_SYS_ARCH_PPC}, + { "m68k", R_SYS_ARCH_M68K}, + { "java", R_SYS_ARCH_JAVA}, + { "mips", R_SYS_ARCH_MIPS}, + { "sparc", R_SYS_ARCH_SPARC}, + { "xap", R_SYS_ARCH_XAP}, + { "tms320", R_SYS_ARCH_TMS320}, + { "msil", R_SYS_ARCH_MSIL}, + { "objd", R_SYS_ARCH_OBJD}, + { "bf", R_SYS_ARCH_BF}, + { "sh", R_SYS_ARCH_SH}, + { "avr", R_SYS_ARCH_AVR}, + { "dalvik", R_SYS_ARCH_DALVIK}, + { "z80", R_SYS_ARCH_Z80}, + { "arc", R_SYS_ARCH_ARC}, + { "i8080", R_SYS_ARCH_I8080}, + { "rar", R_SYS_ARCH_RAR}, + { "lm32", R_SYS_ARCH_LM32}, + { "v850", R_SYS_ARCH_V850}, + { "bpf", R_SYS_ARCH_BPF}, {NULL, 0} }; @@ -833,7 +833,13 @@ R_API int r_sys_cmdbg(const char *str) { return pid; } int ret = r_sandbox_system (str, 0); - eprintf ("{exit: %d, pid: %d, cmd: \"%s\"}", ret, pid, str); + PJ *pj = pj_new (); + pj_kn (pj, "exit", ret); + pj_kn (pj, "pid", pid); + pj_ks (pj, "cmd", str); + char *s = pj_drain (pj); + eprintf ("%s\n", s); + free (s); exit (0); return -1; #else diff --git a/shlr/java/class.c b/shlr/java/class.c index 5a412a91fb..f48959950e 100644 --- a/shlr/java/class.c +++ b/shlr/java/class.c @@ -1,6 +1,7 @@ -/* Apache 2.0 - Copyright 2007-2022 - pancake and dso - class.c rewrite: Adam Pridgen - */ +/* Apache 2.0 - Copyright 2007-2022 - pancake and dso */ +/* class.c rewrite: Adam Pridgen */ +#define R_LOG_ORIGIN "java.class" + #include #include #include "class.h" @@ -15,12 +16,16 @@ #define MAX_CPITEMS 16 +static const ut16 R_BIN_JAVA_ELEMENT_VALUE_METAS_SZ = 14; +static const ut32 RBIN_JAVA_ATTRS_METAS_SZ = 20; +static R_TH_LOCAL bool R_BIN_JAVA_NULL_TYPE_INITTED = false; +static R_TH_LOCAL RBinJavaObj *R_BIN_JAVA_GLOBAL_BIN = NULL; + R_API char *U(r_bin_java_unmangle_method)(const char *flags, const char *name, const char *params, const char *r_value); R_API int r_bin_java_is_fm_type_private(RBinJavaField *fm_type); R_API int r_bin_java_is_fm_type_protected(RBinJavaField *fm_type); R_API ut32 U(r_bin_java_swap_uint)(ut32 x); -// R_API const char * r_bin_java_get_this_class_name(RBinJavaObj *bin); R_API void U(add_cp_objs_to_sdb)(RBinJavaObj * bin); R_API void U(add_field_infos_to_sdb)(RBinJavaObj * bin); R_API void U(add_method_infos_to_sdb)(RBinJavaObj * bin); @@ -381,9 +386,6 @@ static RBinJavaRefMetas R_BIN_JAVA_REF_METAS[] = { { "NewInvokeSpecial", R_BIN_JAVA_REF_NEWINVOKESPECIAL }, { "InvokeInterface", R_BIN_JAVA_REF_INVOKEINTERFACE } }; -static const ut16 R_BIN_JAVA_ELEMENT_VALUE_METAS_SZ = 14; -static R_TH_LOCAL bool R_BIN_JAVA_NULL_TYPE_INITTED = false; -static R_TH_LOCAL RBinJavaObj *R_BIN_JAVA_GLOBAL_BIN = NULL; static RBinJavaElementValueMetas R_BIN_JAVA_ELEMENT_VALUE_METAS[] = { { "Byte", R_BIN_JAVA_EV_TAG_BYTE, NULL }, @@ -492,8 +494,6 @@ static RBinJavaAttrInfoObjectAllocs RBIN_JAVA_ATTRS_ALLOCS[] = { { r_bin_java_synthetic_attr_new, r_bin_java_synthetic_attr_free, r_bin_java_print_synthetic_attr_summary, r_bin_java_synthetic_attr_calc_size }, { r_bin_java_unknown_attr_new, r_bin_java_unknown_attr_free, r_bin_java_print_unknown_attr_summary, r_bin_java_unknown_attr_calc_size } }; -// R_API ut32 RBIN_JAVA_ATTRS_METAS_SZ = 21; -static ut32 RBIN_JAVA_ATTRS_METAS_SZ = 20; static RBinJavaAttrMetas RBIN_JAVA_ATTRS_METAS[] = { { "AnnotationDefault", R_BIN_JAVA_ATTR_TYPE_ANNOTATION_DEFAULT_ATTR, &RBIN_JAVA_ATTRS_ALLOCS[0] }, { "BootstrapMethods", R_BIN_JAVA_ATTR_TYPE_BOOTSTRAP_METHODS_ATTR, &RBIN_JAVA_ATTRS_ALLOCS[1] }, @@ -1644,80 +1644,59 @@ R_API RBinJavaInterfaceInfo *r_bin_java_read_next_interface_item(RBinJavaObj *bi } return ifobj; } -// R_API void addrow (RBinJavaObj *bin, int addr, int line) { -// int n = bin->lines.count++; -//// XXX. possible memleak -// bin->lines.addr = realloc (bin->lines.addr, sizeof (int)*n+1); -// bin->lines.addr[n] = addr; -// bin->lines.line = realloc (bin->lines.line, sizeof (int)*n+1); -// bin->lines.line[n] = line; -// } -// R_API struct r_bin_java_cp_item_t* r_bin_java_get_item_from_cp_CP(RBinJavaObj *bin, int i) { -// return (i<0||i>bin->cf.cp_count)? &cp_null_item: &bin->cp_items[i]; -// } R_API char *r_bin_java_get_utf8_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) { + r_return_val_if_fail (bin, NULL); /* Search through the Constant Pool list for the given CP Index. If the idx not found by directly going to the list index, the list will be walked and then the IDX will be checked. rvalue: new char* for caller to free. */ - if (bin == NULL) { - return NULL; - } return r_bin_java_get_utf8_from_cp_item_list (bin->cp_list, idx); } R_API ut32 r_bin_java_get_utf8_len_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) { + r_return_val_if_fail (bin, 0); /* Search through the Constant Pool list for the given CP Index. If the idx not found by directly going to the list index, the list will be walked and then the IDX will be checked. rvalue: new char* for caller to free. */ - if (bin == NULL) { - return 0; - } return r_bin_java_get_utf8_len_from_cp_item_list (bin->cp_list, idx); } R_API char *r_bin_java_get_name_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) { + r_return_val_if_fail (bin, NULL); /* Search through the Constant Pool list for the given CP Index. If the idx not found by directly going to the list index, the list will be walked and then the IDX will be checked. rvalue: new char* for caller to free. */ - if (bin == NULL) { - return NULL; - } return r_bin_java_get_name_from_cp_item_list (bin->cp_list, idx); } R_API char *r_bin_java_get_desc_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) { + r_return_val_if_fail (bin, NULL); /* Search through the Constant Pool list for the given CP Index. If the idx not found by directly going to the list index, the list will be walked and then the IDX will be checked. rvalue: new char* for caller to free. */ - if (bin == NULL) { - return NULL; - } return r_bin_java_get_desc_from_cp_item_list (bin->cp_list, idx); } R_API RBinJavaCPTypeObj *r_bin_java_get_item_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) { + r_return_val_if_fail (bin, NULL); /* Search through the Constant Pool list for the given CP Index. If the idx not found by directly going to the list index, the list will be walked and then the IDX will be checked. rvalue: RBinJavaObj* (user does NOT free). */ - if (bin == NULL) { - return NULL; - } if (idx > bin->cp_count || idx == 0) { return r_bin_java_get_java_null_cp (); } @@ -2013,16 +1992,13 @@ R_API RBinJavaAttrInfo *r_bin_java_read_next_attr(RBinJavaObj *bin, const ut64 o const ut8 *a_buf = offset + buf; ut8 attr_idx_len = 6; if (offset + 6 > buf_len) { - eprintf ("[X] r_bin_java: Error unable to parse remainder of classfile in Attribute offset " - "(0x%"PFMT64x ") > len of remaining bytes (0x%"PFMT64x ").\n", offset, buf_len); + R_LOG_ERROR ("unable to parse Attribute offset (0x%"PFMT64x ") > len (0x%"PFMT64x ")", offset, buf_len); return NULL; } // ut16 attr_idx, ut32 length of attr. ut32 sz = R_BIN_JAVA_UINT (a_buf, 2) + attr_idx_len; // r_bin_java_read_int (bin, buf_offset+2) + attr_idx_len; if (sz + offset > buf_len) { - eprintf ("[X] r_bin_java: Error unable to parse remainder of classfile in Attribute len " - "(0x%x) + offset (0x%"PFMT64x ") exceeds length of buffer (0x%"PFMT64x ").\n", - sz, offset, buf_len); + R_LOG_ERROR ("Unable to parse class Attribute len (0x%x) + offset (0x%"PFMT64x ") exceeds length of buffer (0x%"PFMT64x ")", sz, offset, buf_len); return NULL; } // when reading the attr bytes, need to also diff --git a/sys/lint.sh b/sys/lint.sh index 23fa5cdc55..7d0875e7c8 100755 --- a/sys/lint.sh +++ b/sys/lint.sh @@ -3,6 +3,9 @@ cd "$(dirname $0)"/.. # (git grep -e '_[a-z][a-z](' libr | grep -v '{'| grep c:) && exit 1 +# TODO : also check for '{0x' +(git grep '\t{"' libr | grep -v strcmp | grep -v format | grep -v '{",' | grep -v esil | grep c:) && exit 1 +(git grep '"},' libr | grep -v strcmp | grep -v format | grep -v '"},' | grep -v '"}{' | grep -v esil | grep -v anal/p | grep c:) && exit 1 (git grep '^\ \ \ ' libr | grep -v '/arch/' | grep -v dotnet | grep -v mangl | grep c:) && exit 1 (git grep 'TODO' libr | grep R_LOG_INFO) && exit 1 ( git grep r_config_set libr binr | grep -e '"fal' -e '"tru') && exit 1 diff --git a/test/db/cmd/types b/test/db/cmd/types index cf6c2ee261..406a4b70dc 100644 --- a/test/db/cmd/types +++ b/test/db/cmd/types @@ -1454,10 +1454,10 @@ s sym.range_or pd 1~4h EOF EXPECT=< 0xa} @ rbp-0x4 -| ; var signed int64_t var_14h { > 0x0 && <= 0x9} @ rbp-0x14 -| ; var signed int64_t var_4h { > 0x64 && <= 0xc7} @ rbp-0x4 -| ; var signed int64_t var_4h { > 0xff && <= 0x12b || > 0x14 && <= 0x31 || > 0x6f && <= 0xdd} @ rbp-0x4 +| ; var signed int64_t var_4h { > 0xa } @ rbp-0x4 +| ; var signed int64_t var_14h { > 0x0 && <= 0x9 } @ rbp-0x14 +| ; var signed int64_t var_4h { > 0x64 && <= 0xc7 } @ rbp-0x4 +| ; var signed int64_t var_4h { > 0xff && <= 0x12b || > 0x14 && <= 0x31 || > 0x6f && <= 0xdd } @ rbp-0x4 EOF RUN