Balance spacings in braces ##indent
This commit is contained in:
pancake
GitHub
parent
bf4f6a6504
commit
a06ade1796
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@ -995,7 +995,7 @@ R_API bool r2r_check_cmd_test(R2RProcessOutput *out, R2RCmdTest *test) {
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#define JQ_CMD "jq"
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R_API bool r2r_check_jq_available(void) {
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const char *args[] = {"."};
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const char *args[] = { "." };
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const char *invalid_json = "this is not json lol";
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R2RSubprocess *proc = r2r_subprocess_start (JQ_CMD, args, 1, NULL, NULL, 0);
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if (!proc) {
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@ -1038,7 +1038,7 @@ R_API bool r2r_check_json_test(R2RProcessOutput *out, R2RJsonTest *test) {
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if (!out || out->ret != 0 || !out->out || !out->err || out->timeout) {
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return false;
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}
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const char *args[] = {"."};
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const char *args[] = { "." };
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R2RSubprocess *proc = r2r_subprocess_start (JQ_CMD, args, 1, NULL, NULL, 0);
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r2r_subprocess_stdin_write (proc, (const ut8 *)out->out, strlen (out->out));
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r2r_subprocess_wait (proc, UT64_MAX);
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@ -4034,62 +4034,62 @@ static const struct arc_operand_value arc_reg_names_a700[] =
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{ "memsubsys",0x67,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MEMSUBSYS",0x67,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Interrupt vector base register */
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{"vecbase_ac_build",0x68,AUXREG_AC, ARC_REGISTER_READONLY},
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{"VECBASE_AC_BUILD",0x68,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "vecbase_ac_build",0x68,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "VECBASE_AC_BUILD",0x68,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Peripheral base address register */
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{ "p_base_addr",0x69,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "P_BASE_ADDR",0x69,AUXREG_AC, ARC_REGISTER_READONLY},
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/* MMU BCR . Specifies the associativity of the TLB etc. */
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{"mmu_build",0x6F,AUXREG_AC, ARC_REGISTER_READONLY},
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{"MMU_BUILD",0x6F,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "mmu_build",0x6F,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MMU_BUILD",0x6F,AUXREG_AC, ARC_REGISTER_READONLY},
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/* ARC Angel BCR . Specifies the version of the ARC Angel Dev. Board */
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{ "arcangel_build",0x70,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "ARCANGEL_BUILD",0x70,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Data Cache BCR . Associativity/Line Size/ size of the Data Cache etc. */
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{"dcache_build",0x72,AUXREG_AC, ARC_REGISTER_READONLY},
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{"DCACHE_BUILD",0x72,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "dcache_build",0x72,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "DCACHE_BUILD",0x72,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Information regarding multiple arc debug interfaces */
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{"madi_build",0x73,AUXREG_AC, ARC_REGISTER_READONLY},
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{"MADI_BUILD",0x73,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "madi_build",0x73,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MADI_BUILD",0x73,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for data closely coupled memory */
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{"dccm_build",0x74,AUXREG_AC, ARC_REGISTER_READONLY},
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{"DCCM_BUILD",0x74,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "dccm_build",0x74,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "DCCM_BUILD",0x74,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for timers */
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{"timer_build",0x75,AUXREG_AC, ARC_REGISTER_READONLY},
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{"TIMER_BUILD",0x75,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "timer_build",0x75,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "TIMER_BUILD",0x75,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Actionpoints build */
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{"ap_build",0x76,AUXREG_AC, ARC_REGISTER_READONLY},
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{"AP_BUILD",0x76,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "ap_build",0x76,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "AP_BUILD",0x76,AUXREG_AC, ARC_REGISTER_READONLY},
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/* Instruction Cache BCR */
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{"icache_build",0x77,AUXREG_AC, ARC_REGISTER_READONLY},
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{"ICACHE_BUILD",0x77,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "icache_build",0x77,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "ICACHE_BUILD",0x77,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for Instruction Closely Coupled Memory.
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Used to be BCR for Saturated ADD/SUB.
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*/
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{"iccm_build",0x78,AUXREG_AC, ARC_REGISTER_READONLY},
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{"ICCM_BUILD",0x78,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "iccm_build",0x78,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "ICCM_BUILD",0x78,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for X/Y Memory */
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{"dspram_build",0x79,AUXREG_AC, ARC_REGISTER_READONLY},
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{"DSPRAM_BUILD",0x79,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "dspram_build",0x79,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "DSPRAM_BUILD",0x79,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for MAC / MUL */
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{"mac_build",0x7A,AUXREG_AC, ARC_REGISTER_READONLY},
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{"MAC_BUILD",0x7A,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "mac_build",0x7A,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MAC_BUILD",0x7A,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for old 32 * 32 Multiply */
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{"multiply_build",0x7B,AUXREG_AC, ARC_REGISTER_READONLY},
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{"MULTIPLY_BUILD",0x7B,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "multiply_build",0x7B,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MULTIPLY_BUILD",0x7B,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for swap */
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{"swap_build",0x7C,AUXREG_AC, ARC_REGISTER_READONLY},
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{"SWAP_BUILD",0x7C,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "swap_build",0x7C,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "SWAP_BUILD",0x7C,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR For Norm */
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{"norm_build",0x7D,AUXREG_AC, ARC_REGISTER_READONLY},
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{"NORM_BUILD",0x7D,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "norm_build",0x7D,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "NORM_BUILD",0x7D,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for Min / Max instructions */
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{"minmax_build",0x7E,AUXREG_AC, ARC_REGISTER_READONLY},
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{"MINMAX_BUILD",0x7E,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "minmax_build",0x7E,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "MINMAX_BUILD",0x7E,AUXREG_AC, ARC_REGISTER_READONLY},
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/* BCR for barrel shifter */
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{"barrel_build",0x7F,AUXREG_AC, ARC_REGISTER_READONLY},
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{"BARREL_BUILD",0x7F,AUXREG_AC, ARC_REGISTER_READONLY}
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{ "barrel_build",0x7F,AUXREG_AC, ARC_REGISTER_READONLY},
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{ "BARREL_BUILD",0x7F,AUXREG_AC, ARC_REGISTER_READONLY}
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};
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@ -4611,9 +4611,9 @@ ARC700_rtie_insn (arc_insn insn)
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ld/ldb/ldw r0, [gp, var@sda] 1
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ldw.as r0, [gp, var@sda] 2
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ld_s r0, [gp, var@sda] 10
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ldb_ r0, [gp, var@sda] 11
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ldw_s r0, [gp, var@sda] 12
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ld_s r0, [gp, var@sda] 10
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ldb_ r0, [gp, var@sda] 11
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ldw_s r0, [gp, var@sda] 12
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Any other insn -1
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@ -49,263 +49,263 @@ struct dalvik_opcodes_t {
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};
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static const struct dalvik_opcodes_t dalvik_opcodes[256] = {
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{"nop", 2, fmtop}, /* 0x00 */
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{"move", 2, fmtopvAvB},
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{"move/from16", 4, fmtopvAAvBBBB},
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{"move/16", 6, fmtopvAAAAvBBBB},
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{"move-wide", 2, fmtopvAvB},
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{"move-wide/from16", 4, fmtopvAAvBBBB},
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{"move-wide/16", 6, fmtopvAAAAvBBBB},
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{"move-object", 2, fmtopvAvB},
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{"move-object/from16", 4, fmtopvAAvBBBB},
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{"move-object/16", 6, fmtopvAAAAvBBBB},
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{"move-result", 2, fmtopvAA},
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{"move-result-wide", 2, fmtopvAA},
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{"move-result-object", 2, fmtopvAA},
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{"move-exception", 2, fmtopvAA},
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{"return-void", 2, fmtop},
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{"return", 2, fmtopvAA},
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{"return-wide", 2, fmtopvAA}, /* 0x10 */
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{"return-object", 2, fmtopvAA},
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{"const/4", 2, fmtopvAcB},
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{"const/16", 4, fmtopvAAcBBBB},
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{"const", 6, fmtopvAAcBBBBBBBB},
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{"const/high16", 4, fmtopvAAcBBBB0000},
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{"const-wide/16", 4, fmtopvAAcBBBB},
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{"const-wide/32", 6, fmtopvAAcBBBBBBBB},
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{"const-wide", 10, fmtopvAAcBBBBBBBBBBBBBBBB},
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{"const-wide/high16", 4, fmtopvAAcBBBB0000},
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{"const-string", 4, fmtopvAAtBBBB},
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{"const-string/jumbo", 6, fmtopvAAtBBBBBBBB},
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{"const-class", 4, fmtopvAAtBBBB},
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{"monitor-enter", 2, fmtopvAA},
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{"monitor-exit", 2, fmtopvAA},
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{"check-cast", 4, fmtopvAAtBBBB},
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{"instance-of", 4, fmtopvAvBtCCCC}, /* 0x20 */
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{"array-length", 2, fmtopvAvB},
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{"new-instance", 4, fmtopvAAtBBBB},
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{"new-array", 4, fmtopvAvBtCCCC},
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{"filled-new-array", 6, fmtopvXtBBBB},
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{"filled-new-array/range", 6, fmtopvCCCCmBBBB},
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{"fill-array-data", 6, fmtopvAApBBBBBBBB},
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{"throw", 2, fmtopvAA},
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{"goto", 2, fmtoppAA},
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{"goto/16", 4, fmtoppAAAA},
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{"goto/32", 6, fmtoppAAAAAAAA},
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{"packed-switch", 6, fmtopvAApBBBBBBBB},
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{"sparse-switch", 6, fmtopvAApBBBBBBBB},
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{"cmpl-float", 4, fmtopvAAvBBvCC},
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{"cmpg-float", 4, fmtopvAAvBBvCC},
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{"cmpl-double", 4, fmtopvAAvBBvCC},
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{"cmpg-double", 4, fmtopvAAvBBvCC}, /* 0x30 */
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{"cmp-long", 4, fmtopvAAvBBvCC},
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{"if-eq", 4, fmtopvAvBpCCCC},
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{"if-ne", 4, fmtopvAvBpCCCC},
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{"if-lt", 4, fmtopvAvBpCCCC},
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{"if-ge", 4, fmtopvAvBpCCCC},
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{"if-gt", 4, fmtopvAvBpCCCC},
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{"if-le", 4, fmtopvAvBpCCCC},
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{"if-eqz", 4, fmtopvAApBBBB},
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{"if-nez", 4, fmtopvAApBBBB},
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{"if-ltz", 4, fmtopvAApBBBB},
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{"if-gez", 4, fmtopvAApBBBB},
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{"if-gtz", 4, fmtopvAApBBBB},
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{"if-lez", 4, fmtopvAApBBBB},
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{"UNUSED", 2, fmt00},
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{"UNUSED", 2, fmt00},
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{"UNUSED", 2, fmt00}, /* 0x40 */
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{"UNUSED", 2, fmt00},
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{"UNUSED", 2, fmt00},
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{"UNUSED", 2, fmt00},
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{"aget", 4, fmtopvAAvBBvCC},
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{"aget-wide", 4, fmtopvAAvBBvCC},
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{"aget-object", 4, fmtopvAAvBBvCC},
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{"aget-boolean", 4, fmtopvAAvBBvCC},
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{"aget-byte", 4, fmtopvAAvBBvCC},
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{"aget-char", 4, fmtopvAAvBBvCC},
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{"aget-short", 4, fmtopvAAvBBvCC},
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{"aput", 4, fmtopvAAvBBvCC},
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{"aput-wide", 4, fmtopvAAvBBvCC},
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{"aput-object", 4, fmtopvAAvBBvCC},
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{"aput-boolean", 4, fmtopvAAvBBvCC},
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{"aput-byte", 4, fmtopvAAvBBvCC},
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{"aput-char", 4, fmtopvAAvBBvCC}, /* 0x50 */
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{"aput-short", 4, fmtopvAAvBBvCC},
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{"iget", 4, fmtopvAvBtCCCC},
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{"iget-wide", 4, fmtopvAvBtCCCC},
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{"iget-object", 4, fmtopvAvBtCCCC},
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{"iget-boolean", 4, fmtopvAvBtCCCC},
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{"iget-byte", 4, fmtopvAvBtCCCC},
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{"iget-char", 4, fmtopvAvBtCCCC},
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{"iget-short", 4, fmtopvAvBtCCCC},
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{"iput", 4, fmtopvAvBtCCCC},
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{"iput-wide", 4, fmtopvAvBtCCCC},
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{"iput-object", 4, fmtopvAvBtCCCC},
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{"iput-boolean", 4, fmtopvAvBtCCCC},
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{"iput-byte", 4, fmtopvAvBtCCCC},
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{"iput-char", 4, fmtopvAvBtCCCC},
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{"iput-short", 4, fmtopvAvBtCCCC},
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{"sget", 4, fmtopvAAtBBBB}, /* 0x60 */
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{"sget-wide", 4, fmtopvAAtBBBB},
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{"sget-object", 4, fmtopvAAtBBBB},
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{"sget-boolean", 4, fmtopvAAtBBBB},
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{"sget-byte", 4, fmtopvAAtBBBB},
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{"sget-char", 4, fmtopvAAtBBBB},
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{"sget-short", 4, fmtopvAAtBBBB},
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{"sput", 4, fmtopvAAtBBBB},
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{"sput-wide", 4, fmtopvAAtBBBB},
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{"sput-object", 4, fmtopvAAtBBBB},
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{"sput-boolean", 4, fmtopvAAtBBBB},
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{"sput-byte", 4, fmtopvAAtBBBB},
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{"sput-char", 4, fmtopvAAtBBBB},
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{"sput-short", 4, fmtopvAAtBBBB},
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{"invoke-virtual", 6, fmtopvXtBBBB},
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{"invoke-super", 6, fmtopvXtBBBB},
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{"invoke-direct", 6, fmtopvXtBBBB}, /* 0x70 */
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{"invoke-static", 6, fmtopvXtBBBB},
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{"invoke-interface", 6, fmtopvXtBBBB}, //XXX: Maybe use opt invoke-interface ??
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{"UNUSED", 2, fmt00},
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{"invoke-virtual/range", 6, fmtopvCCCCmBBBB},
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{"invoke-super/range", 6, fmtopvCCCCmBBBB},
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{"invoke-direct/range", 6, fmtopvCCCCmBBBB},
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{"invoke-static/range", 6, fmtopvCCCCmBBBB},
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{"invoke-interface/range", 6, fmtopvCCCCmBBBB},
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{"UNUSED", 2, fmt00},
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{"UNUSED", 2, fmt00},
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{"neg-int", 2, fmtopvAvB},
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{"not-int", 2, fmtopvAvB},
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{"neg-long", 2, fmtopvAvB},
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{"not-long", 2, fmtopvAvB},
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{"neg-float", 2, fmtopvAvB},
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{"neg-double", 2, fmtopvAvB}, /* 0x80 */
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{"int-to-long", 2, fmtopvAvB},
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{"int-to-float", 2, fmtopvAvB},
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{"int-to-double", 2, fmtopvAvB},
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{"long-to-int", 2, fmtopvAvB},
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{"long-to-float", 2, fmtopvAvB},
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{"long-to-double", 2, fmtopvAvB},
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{"float-to-int", 2, fmtopvAvB},
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{"float-to-long", 2, fmtopvAvB},
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{"float-to-double", 2, fmtopvAvB},
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{"double-to-int", 2, fmtopvAvB},
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{"double-to-long", 2, fmtopvAvB},
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{"double-to-float", 2, fmtopvAvB},
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{"int-to-byte", 2, fmtopvAvB},
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{"int-to-char", 2, fmtopvAvB},
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{"int-to-short", 2, fmtopvAvB},
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{"add-int", 4, fmtopvAAvBBvCC}, /* 0x90 */
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{"sub-int", 4, fmtopvAAvBBvCC},
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{"mul-int", 4, fmtopvAAvBBvCC},
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{"div-int", 4, fmtopvAAvBBvCC},
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{"rem-int", 4, fmtopvAAvBBvCC},
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{"and-int", 4, fmtopvAAvBBvCC},
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{"or-int", 4, fmtopvAAvBBvCC},
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{"xor-int", 4, fmtopvAAvBBvCC},
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{"shl-int", 4, fmtopvAAvBBvCC},
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{"shr-int", 4, fmtopvAAvBBvCC},
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{"ushr-int", 4, fmtopvAAvBBvCC},
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{"add-long", 4, fmtopvAAvBBvCC},
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{"sub-long", 4, fmtopvAAvBBvCC},
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{"mul-long", 4, fmtopvAAvBBvCC},
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{"div-long", 4, fmtopvAAvBBvCC},
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{"rem-long", 4, fmtopvAAvBBvCC},
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{"and-long", 4, fmtopvAAvBBvCC}, /* 0xa0 */
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{"or-long", 4, fmtopvAAvBBvCC},
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{"xor-long", 4, fmtopvAAvBBvCC},
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{"shl-long", 4, fmtopvAAvBBvCC},
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{"shr-long", 4, fmtopvAAvBBvCC},
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{"ushr-long", 4, fmtopvAAvBBvCC},
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{"add-float", 4, fmtopvAAvBBvCC},
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{"sub-float", 4, fmtopvAAvBBvCC},
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{"mul-float", 4, fmtopvAAvBBvCC},
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{"div-float", 4, fmtopvAAvBBvCC},
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{"rem-float", 4, fmtopvAAvBBvCC},
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{"add-double", 4, fmtopvAAvBBvCC},
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{"sub-double", 4, fmtopvAAvBBvCC},
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{"mul-double", 4, fmtopvAAvBBvCC},
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{"div-double", 4, fmtopvAAvBBvCC},
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{"rem-double", 4, fmtopvAAvBBvCC},
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{"add-int/2addr", 2, fmtopvAvB}, /* 0xb0 */
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{"sub-int/2addr", 2, fmtopvAvB},
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{"mul-int/2addr", 2, fmtopvAvB},
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{"div-int/2addr", 2, fmtopvAvB},
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{"rem-int/2addr", 2, fmtopvAvB},
|
||||
{"and-int/2addr", 2, fmtopvAvB},
|
||||
{"or-int/2addr", 2, fmtopvAvB},
|
||||
{"xor-int/2addr", 2, fmtopvAvB},
|
||||
{"shl-int/2addr", 2, fmtopvAvB},
|
||||
{"shr-int/2addr", 2, fmtopvAvB},
|
||||
{"ushr-int/2addr", 2, fmtopvAvB},
|
||||
{"add-long/2addr", 2, fmtopvAvB},
|
||||
{"sub-long/2addr", 2, fmtopvAvB},
|
||||
{"mul-long/2addr", 2, fmtopvAvB},
|
||||
{"div-long/2addr", 2, fmtopvAvB},
|
||||
{"rem-long/2addr", 2, fmtopvAvB},
|
||||
{"and-long/2addr", 2, fmtopvAvB}, /* 0xc0 */
|
||||
{"or-long/2addr", 2, fmtopvAvB},
|
||||
{"xor-long/2addr", 2, fmtopvAvB},
|
||||
{"shl-long/2addr", 2, fmtopvAvB},
|
||||
{"shr-long/2addr", 2, fmtopvAvB},
|
||||
{"ushr-long/2addr", 2, fmtopvAvB},
|
||||
{"add-float/2addr", 2, fmtopvAvB},
|
||||
{"sub-float/2addr", 2, fmtopvAvB},
|
||||
{"mul-float/2addr", 2, fmtopvAvB},
|
||||
{"div-float/2addr", 2, fmtopvAvB},
|
||||
{"rem-float/2addr", 2, fmtopvAvB},
|
||||
{"add-double/2addr", 2, fmtopvAvB},
|
||||
{"sub-double/2addr", 2, fmtopvAvB},
|
||||
{"mul-double/2addr", 2, fmtopvAvB},
|
||||
{"div-double/2addr", 2, fmtopvAvB},
|
||||
{"rem-double/2addr", 2, fmtopvAvB},
|
||||
{"add-int/lit16", 4, fmtopvAvBcCCCC}, /* 0xd0 */
|
||||
{"rsub-int", 4, fmtopvAvBcCCCC},
|
||||
{"mul-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"div-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"rem-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"and-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"or-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"xor-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{"add-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"rsub-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"mul-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"div-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"rem-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"and-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"or-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"xor-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"shl-int/lit8", 4, fmtopvAAvBBcCC}, /* 0xe0 */
|
||||
{"shr-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"ushr-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{"+iget-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+iput-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+sget-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+sput-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+iget-object-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+iget-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+iput-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+sget-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"+sput-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{"^breakpoint", 4, fmtopvAvBtCCCC},
|
||||
{"^throw-verification-error", 4, fmtopAAtBBBB},
|
||||
{"+execute-inline", 6, fmtoptinlineI},
|
||||
{"+execute-inline/range", 6, fmtoptinlineIR},
|
||||
//{"+invoke-direct-empty", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range
|
||||
{"+invoke-object-init-range", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range
|
||||
{"return-void-barrier", 2, fmtop},
|
||||
{"+iget-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+iget-wide-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+iget-object-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+iput-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+iput-wide-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+iput-object-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{"+invoke-virtual-quick", 6, fmtoptinvokeVS},
|
||||
{"+invoke-virtual-quick/range", 6, fmtoptinvokeVSR},
|
||||
{"invoke-polymorphic", 8, fmtop45CC},
|
||||
{"invoke-polymorphic/range", 8, fmtop4RCC},
|
||||
{"invoke-custom", 6, fmtopvXtBBBB},
|
||||
{"invoke-custom/range", 6, fmtopvCCCCmBBBB},
|
||||
{"+sput-object-volatile", 4, fmtopvAAtBBBB},
|
||||
{"invalid", 2, fmtop}
|
||||
{ "nop", 2, fmtop}, /* 0x00 */
|
||||
{ "move", 2, fmtopvAvB},
|
||||
{ "move/from16", 4, fmtopvAAvBBBB},
|
||||
{ "move/16", 6, fmtopvAAAAvBBBB},
|
||||
{ "move-wide", 2, fmtopvAvB},
|
||||
{ "move-wide/from16", 4, fmtopvAAvBBBB},
|
||||
{ "move-wide/16", 6, fmtopvAAAAvBBBB},
|
||||
{ "move-object", 2, fmtopvAvB},
|
||||
{ "move-object/from16", 4, fmtopvAAvBBBB},
|
||||
{ "move-object/16", 6, fmtopvAAAAvBBBB},
|
||||
{ "move-result", 2, fmtopvAA},
|
||||
{ "move-result-wide", 2, fmtopvAA},
|
||||
{ "move-result-object", 2, fmtopvAA},
|
||||
{ "move-exception", 2, fmtopvAA},
|
||||
{ "return-void", 2, fmtop},
|
||||
{ "return", 2, fmtopvAA},
|
||||
{ "return-wide", 2, fmtopvAA}, /* 0x10 */
|
||||
{ "return-object", 2, fmtopvAA},
|
||||
{ "const/4", 2, fmtopvAcB},
|
||||
{ "const/16", 4, fmtopvAAcBBBB},
|
||||
{ "const", 6, fmtopvAAcBBBBBBBB},
|
||||
{ "const/high16", 4, fmtopvAAcBBBB0000},
|
||||
{ "const-wide/16", 4, fmtopvAAcBBBB},
|
||||
{ "const-wide/32", 6, fmtopvAAcBBBBBBBB},
|
||||
{ "const-wide", 10, fmtopvAAcBBBBBBBBBBBBBBBB},
|
||||
{ "const-wide/high16", 4, fmtopvAAcBBBB0000},
|
||||
{ "const-string", 4, fmtopvAAtBBBB},
|
||||
{ "const-string/jumbo", 6, fmtopvAAtBBBBBBBB},
|
||||
{ "const-class", 4, fmtopvAAtBBBB},
|
||||
{ "monitor-enter", 2, fmtopvAA},
|
||||
{ "monitor-exit", 2, fmtopvAA},
|
||||
{ "check-cast", 4, fmtopvAAtBBBB},
|
||||
{ "instance-of", 4, fmtopvAvBtCCCC}, /* 0x20 */
|
||||
{ "array-length", 2, fmtopvAvB},
|
||||
{ "new-instance", 4, fmtopvAAtBBBB},
|
||||
{ "new-array", 4, fmtopvAvBtCCCC},
|
||||
{ "filled-new-array", 6, fmtopvXtBBBB},
|
||||
{ "filled-new-array/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "fill-array-data", 6, fmtopvAApBBBBBBBB},
|
||||
{ "throw", 2, fmtopvAA},
|
||||
{ "goto", 2, fmtoppAA},
|
||||
{ "goto/16", 4, fmtoppAAAA},
|
||||
{ "goto/32", 6, fmtoppAAAAAAAA},
|
||||
{ "packed-switch", 6, fmtopvAApBBBBBBBB},
|
||||
{ "sparse-switch", 6, fmtopvAApBBBBBBBB},
|
||||
{ "cmpl-float", 4, fmtopvAAvBBvCC},
|
||||
{ "cmpg-float", 4, fmtopvAAvBBvCC},
|
||||
{ "cmpl-double", 4, fmtopvAAvBBvCC},
|
||||
{ "cmpg-double", 4, fmtopvAAvBBvCC}, /* 0x30 */
|
||||
{ "cmp-long", 4, fmtopvAAvBBvCC},
|
||||
{ "if-eq", 4, fmtopvAvBpCCCC},
|
||||
{ "if-ne", 4, fmtopvAvBpCCCC},
|
||||
{ "if-lt", 4, fmtopvAvBpCCCC},
|
||||
{ "if-ge", 4, fmtopvAvBpCCCC},
|
||||
{ "if-gt", 4, fmtopvAvBpCCCC},
|
||||
{ "if-le", 4, fmtopvAvBpCCCC},
|
||||
{ "if-eqz", 4, fmtopvAApBBBB},
|
||||
{ "if-nez", 4, fmtopvAApBBBB},
|
||||
{ "if-ltz", 4, fmtopvAApBBBB},
|
||||
{ "if-gez", 4, fmtopvAApBBBB},
|
||||
{ "if-gtz", 4, fmtopvAApBBBB},
|
||||
{ "if-lez", 4, fmtopvAApBBBB},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "UNUSED", 2, fmt00}, /* 0x40 */
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "aget", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-wide", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-object", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-boolean", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-byte", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-char", 4, fmtopvAAvBBvCC},
|
||||
{ "aget-short", 4, fmtopvAAvBBvCC},
|
||||
{ "aput", 4, fmtopvAAvBBvCC},
|
||||
{ "aput-wide", 4, fmtopvAAvBBvCC},
|
||||
{ "aput-object", 4, fmtopvAAvBBvCC},
|
||||
{ "aput-boolean", 4, fmtopvAAvBBvCC},
|
||||
{ "aput-byte", 4, fmtopvAAvBBvCC},
|
||||
{ "aput-char", 4, fmtopvAAvBBvCC}, /* 0x50 */
|
||||
{ "aput-short", 4, fmtopvAAvBBvCC},
|
||||
{ "iget", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-wide", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-object", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-boolean", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-byte", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-char", 4, fmtopvAvBtCCCC},
|
||||
{ "iget-short", 4, fmtopvAvBtCCCC},
|
||||
{ "iput", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-wide", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-object", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-boolean", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-byte", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-char", 4, fmtopvAvBtCCCC},
|
||||
{ "iput-short", 4, fmtopvAvBtCCCC},
|
||||
{ "sget", 4, fmtopvAAtBBBB}, /* 0x60 */
|
||||
{ "sget-wide", 4, fmtopvAAtBBBB},
|
||||
{ "sget-object", 4, fmtopvAAtBBBB},
|
||||
{ "sget-boolean", 4, fmtopvAAtBBBB},
|
||||
{ "sget-byte", 4, fmtopvAAtBBBB},
|
||||
{ "sget-char", 4, fmtopvAAtBBBB},
|
||||
{ "sget-short", 4, fmtopvAAtBBBB},
|
||||
{ "sput", 4, fmtopvAAtBBBB},
|
||||
{ "sput-wide", 4, fmtopvAAtBBBB},
|
||||
{ "sput-object", 4, fmtopvAAtBBBB},
|
||||
{ "sput-boolean", 4, fmtopvAAtBBBB},
|
||||
{ "sput-byte", 4, fmtopvAAtBBBB},
|
||||
{ "sput-char", 4, fmtopvAAtBBBB},
|
||||
{ "sput-short", 4, fmtopvAAtBBBB},
|
||||
{ "invoke-virtual", 6, fmtopvXtBBBB},
|
||||
{ "invoke-super", 6, fmtopvXtBBBB},
|
||||
{ "invoke-direct", 6, fmtopvXtBBBB}, /* 0x70 */
|
||||
{ "invoke-static", 6, fmtopvXtBBBB},
|
||||
{ "invoke-interface", 6, fmtopvXtBBBB}, //XXX: Maybe use opt invoke-interface ??
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "invoke-virtual/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "invoke-super/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "invoke-direct/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "invoke-static/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "invoke-interface/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "UNUSED", 2, fmt00},
|
||||
{ "neg-int", 2, fmtopvAvB},
|
||||
{ "not-int", 2, fmtopvAvB},
|
||||
{ "neg-long", 2, fmtopvAvB},
|
||||
{ "not-long", 2, fmtopvAvB},
|
||||
{ "neg-float", 2, fmtopvAvB},
|
||||
{ "neg-double", 2, fmtopvAvB}, /* 0x80 */
|
||||
{ "int-to-long", 2, fmtopvAvB},
|
||||
{ "int-to-float", 2, fmtopvAvB},
|
||||
{ "int-to-double", 2, fmtopvAvB},
|
||||
{ "long-to-int", 2, fmtopvAvB},
|
||||
{ "long-to-float", 2, fmtopvAvB},
|
||||
{ "long-to-double", 2, fmtopvAvB},
|
||||
{ "float-to-int", 2, fmtopvAvB},
|
||||
{ "float-to-long", 2, fmtopvAvB},
|
||||
{ "float-to-double", 2, fmtopvAvB},
|
||||
{ "double-to-int", 2, fmtopvAvB},
|
||||
{ "double-to-long", 2, fmtopvAvB},
|
||||
{ "double-to-float", 2, fmtopvAvB},
|
||||
{ "int-to-byte", 2, fmtopvAvB},
|
||||
{ "int-to-char", 2, fmtopvAvB},
|
||||
{ "int-to-short", 2, fmtopvAvB},
|
||||
{ "add-int", 4, fmtopvAAvBBvCC}, /* 0x90 */
|
||||
{ "sub-int", 4, fmtopvAAvBBvCC},
|
||||
{ "mul-int", 4, fmtopvAAvBBvCC},
|
||||
{ "div-int", 4, fmtopvAAvBBvCC},
|
||||
{ "rem-int", 4, fmtopvAAvBBvCC},
|
||||
{ "and-int", 4, fmtopvAAvBBvCC},
|
||||
{ "or-int", 4, fmtopvAAvBBvCC},
|
||||
{ "xor-int", 4, fmtopvAAvBBvCC},
|
||||
{ "shl-int", 4, fmtopvAAvBBvCC},
|
||||
{ "shr-int", 4, fmtopvAAvBBvCC},
|
||||
{ "ushr-int", 4, fmtopvAAvBBvCC},
|
||||
{ "add-long", 4, fmtopvAAvBBvCC},
|
||||
{ "sub-long", 4, fmtopvAAvBBvCC},
|
||||
{ "mul-long", 4, fmtopvAAvBBvCC},
|
||||
{ "div-long", 4, fmtopvAAvBBvCC},
|
||||
{ "rem-long", 4, fmtopvAAvBBvCC},
|
||||
{ "and-long", 4, fmtopvAAvBBvCC}, /* 0xa0 */
|
||||
{ "or-long", 4, fmtopvAAvBBvCC},
|
||||
{ "xor-long", 4, fmtopvAAvBBvCC},
|
||||
{ "shl-long", 4, fmtopvAAvBBvCC},
|
||||
{ "shr-long", 4, fmtopvAAvBBvCC},
|
||||
{ "ushr-long", 4, fmtopvAAvBBvCC},
|
||||
{ "add-float", 4, fmtopvAAvBBvCC},
|
||||
{ "sub-float", 4, fmtopvAAvBBvCC},
|
||||
{ "mul-float", 4, fmtopvAAvBBvCC},
|
||||
{ "div-float", 4, fmtopvAAvBBvCC},
|
||||
{ "rem-float", 4, fmtopvAAvBBvCC},
|
||||
{ "add-double", 4, fmtopvAAvBBvCC},
|
||||
{ "sub-double", 4, fmtopvAAvBBvCC},
|
||||
{ "mul-double", 4, fmtopvAAvBBvCC},
|
||||
{ "div-double", 4, fmtopvAAvBBvCC},
|
||||
{ "rem-double", 4, fmtopvAAvBBvCC},
|
||||
{ "add-int/2addr", 2, fmtopvAvB}, /* 0xb0 */
|
||||
{ "sub-int/2addr", 2, fmtopvAvB},
|
||||
{ "mul-int/2addr", 2, fmtopvAvB},
|
||||
{ "div-int/2addr", 2, fmtopvAvB},
|
||||
{ "rem-int/2addr", 2, fmtopvAvB},
|
||||
{ "and-int/2addr", 2, fmtopvAvB},
|
||||
{ "or-int/2addr", 2, fmtopvAvB},
|
||||
{ "xor-int/2addr", 2, fmtopvAvB},
|
||||
{ "shl-int/2addr", 2, fmtopvAvB},
|
||||
{ "shr-int/2addr", 2, fmtopvAvB},
|
||||
{ "ushr-int/2addr", 2, fmtopvAvB},
|
||||
{ "add-long/2addr", 2, fmtopvAvB},
|
||||
{ "sub-long/2addr", 2, fmtopvAvB},
|
||||
{ "mul-long/2addr", 2, fmtopvAvB},
|
||||
{ "div-long/2addr", 2, fmtopvAvB},
|
||||
{ "rem-long/2addr", 2, fmtopvAvB},
|
||||
{ "and-long/2addr", 2, fmtopvAvB}, /* 0xc0 */
|
||||
{ "or-long/2addr", 2, fmtopvAvB},
|
||||
{ "xor-long/2addr", 2, fmtopvAvB},
|
||||
{ "shl-long/2addr", 2, fmtopvAvB},
|
||||
{ "shr-long/2addr", 2, fmtopvAvB},
|
||||
{ "ushr-long/2addr", 2, fmtopvAvB},
|
||||
{ "add-float/2addr", 2, fmtopvAvB},
|
||||
{ "sub-float/2addr", 2, fmtopvAvB},
|
||||
{ "mul-float/2addr", 2, fmtopvAvB},
|
||||
{ "div-float/2addr", 2, fmtopvAvB},
|
||||
{ "rem-float/2addr", 2, fmtopvAvB},
|
||||
{ "add-double/2addr", 2, fmtopvAvB},
|
||||
{ "sub-double/2addr", 2, fmtopvAvB},
|
||||
{ "mul-double/2addr", 2, fmtopvAvB},
|
||||
{ "div-double/2addr", 2, fmtopvAvB},
|
||||
{ "rem-double/2addr", 2, fmtopvAvB},
|
||||
{ "add-int/lit16", 4, fmtopvAvBcCCCC}, /* 0xd0 */
|
||||
{ "rsub-int", 4, fmtopvAvBcCCCC},
|
||||
{ "mul-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "div-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "rem-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "and-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "or-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "xor-int/lit16", 4, fmtopvAvBcCCCC},
|
||||
{ "add-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "rsub-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "mul-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "div-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "rem-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "and-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "or-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "xor-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "shl-int/lit8", 4, fmtopvAAvBBcCC}, /* 0xe0 */
|
||||
{ "shr-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "ushr-int/lit8", 4, fmtopvAAvBBcCC},
|
||||
{ "+iget-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+iput-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+sget-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+sput-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+iget-object-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+iget-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+iput-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+sget-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "+sput-wide-volatile", 4, fmtopvAvBtCCCC},
|
||||
{ "^breakpoint", 4, fmtopvAvBtCCCC},
|
||||
{ "^throw-verification-error", 4, fmtopAAtBBBB},
|
||||
{ "+execute-inline", 6, fmtoptinlineI},
|
||||
{ "+execute-inline/range", 6, fmtoptinlineIR},
|
||||
//{ "+invoke-direct-empty", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range
|
||||
{ "+invoke-object-init-range", 6, fmtopvXtBBBB}, /* 0xf0 */ // invoke-object-init-range
|
||||
{ "return-void-barrier", 2, fmtop},
|
||||
{ "+iget-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+iget-wide-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+iget-object-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+iput-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+iput-wide-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+iput-object-quick", 4, fmtoptopvAvBoCCCC},
|
||||
{ "+invoke-virtual-quick", 6, fmtoptinvokeVS},
|
||||
{ "+invoke-virtual-quick/range", 6, fmtoptinvokeVSR},
|
||||
{ "invoke-polymorphic", 8, fmtop45CC},
|
||||
{ "invoke-polymorphic/range", 8, fmtop4RCC},
|
||||
{ "invoke-custom", 6, fmtopvXtBBBB},
|
||||
{ "invoke-custom/range", 6, fmtopvCCCCmBBBB},
|
||||
{ "+sput-object-volatile", 4, fmtopvAAtBBBB},
|
||||
{ "invalid", 2, fmtop}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -632,7 +632,7 @@ static int decode_cmpi(const ut8 *bytes, ebc_command_t *cmd) {
|
|||
char op1c[32];
|
||||
char indx[32] = {0};
|
||||
char immed[32] = {0};
|
||||
char *suff[] = {"eq", "lte", "gte", "ulte", "ugte"};
|
||||
char *suff[] = { "eq", "lte", "gte", "ulte", "ugte" };
|
||||
|
||||
snprintf (op1c, sizeof (op1c)-1, "%sr%u",
|
||||
TEST_BIT(bytes[1], 3) ? "@" : "", op1);
|
||||
|
|
|
|||
|
|
@ -1,294 +1,294 @@
|
|||
/* radare - LGPL - Copyright 2013 - 2014 - condret@runas-racer.com */
|
||||
/* radare - LGPL - Copyright 2013-2022 - condret */
|
||||
|
||||
#define GB_8BIT 1
|
||||
#define GB_16BIT 2
|
||||
#define ARG_8 4
|
||||
#define ARG_16 8
|
||||
#define GB_IO 16 // Most io (Joypad, Sound, Screen ...)
|
||||
#define GB_8BIT 1
|
||||
#define GB_16BIT 2
|
||||
#define ARG_8 4
|
||||
#define ARG_16 8
|
||||
#define GB_IO 16 // Most io (Joypad, Sound, Screen ...)
|
||||
|
||||
|
||||
typedef struct{
|
||||
typedef struct {
|
||||
const char *name;
|
||||
const int type;
|
||||
} gb_opcode;
|
||||
|
||||
static const char *cb_ops[]={ "rlc","rrc","rl","rr","sla","sra","swap","srl",
|
||||
"bit 0,","bit 1,","bit 2,","bit 3,","bit 4,","bit 5,","bit 6,","bit 7,",
|
||||
"res 0,","res 1,","res 2,","res 3,","res 4,","res 5,","res 6,","res 7,",
|
||||
"set 0,","set 1,","set 2,","set 3,","set 4,","set 5,","set 6,","set 7,"};
|
||||
static const char *cb_ops[] = {
|
||||
"rlc", "rrc", "rl", "rr", "sla", "sra", "swap", "srl",
|
||||
"bit 0,", "bit 1,", "bit 2,", "bit 3,", "bit 4,", "bit 5,", "bit 6,", "bit 7,",
|
||||
"res 0,", "res 1,", "res 2,", "res 3,", "res 4,", "res 5,", "res 6,", "res 7,",
|
||||
"set 0,", "set 1,", "set 2,", "set 3,", "set 4,", "set 5,", "set 6,", "set 7,"
|
||||
};
|
||||
|
||||
static const char *cb_regs[]={ "b","c","d","e","h","l","[hl]","a"};
|
||||
static const char *cb_regs[]= { "b", "c", "d", "e", "h", "l", "[hl]", "a" };
|
||||
|
||||
static gb_opcode gb_op[] = {
|
||||
{"nop" ,GB_8BIT}, //0x00
|
||||
{"ld bc, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"ld [bc], a" ,GB_8BIT},
|
||||
{"inc bc" ,GB_8BIT},
|
||||
{"inc b" ,GB_8BIT},
|
||||
{"dec b" ,GB_8BIT},
|
||||
{"ld b, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rlca" ,GB_8BIT},
|
||||
{"ld [0x%04x], sp" ,GB_8BIT+ARG_16}, //word or byte?
|
||||
{"add hl, bc" ,GB_8BIT},
|
||||
{"ld a, [bc]" ,GB_8BIT},
|
||||
{"dec bc" ,GB_8BIT},
|
||||
{"inc c" ,GB_8BIT},
|
||||
{"dec c" ,GB_8BIT},
|
||||
{"ld c, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rrca" ,GB_8BIT},
|
||||
{ "nop", GB_8BIT }, //0x00
|
||||
{ "ld bc, 0x%04x", GB_8BIT + ARG_16},
|
||||
{ "ld [bc], a", GB_8BIT },
|
||||
{ "inc bc", GB_8BIT },
|
||||
{ "inc b", GB_8BIT },
|
||||
{ "dec b", GB_8BIT },
|
||||
{ "ld b, 0x%02x", GB_8BIT + ARG_8 },
|
||||
{ "rlca", GB_8BIT },
|
||||
{ "ld [0x%04x], sp", GB_8BIT + ARG_16}, //word or byte?
|
||||
{ "add hl, bc", GB_8BIT },
|
||||
{ "ld a, [bc]", GB_8BIT },
|
||||
{ "dec bc", GB_8BIT },
|
||||
{ "inc c", GB_8BIT },
|
||||
{ "dec c", GB_8BIT },
|
||||
{ "ld c, 0x%02x", GB_8BIT + ARG_8 },
|
||||
{ "rrca", GB_8BIT },
|
||||
{ "stop", GB_8BIT }, //0x10
|
||||
{ "ld de, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "ld [de], a" ,GB_8BIT },
|
||||
{ "inc de", GB_8BIT },
|
||||
{ "inc d", GB_8BIT },
|
||||
{ "dec d", GB_8BIT },
|
||||
{ "ld d, 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "rla", GB_8BIT },
|
||||
{ "jr 0x%02x", GB_8BIT+ARG_8 }, //signed
|
||||
{ "add hl, de" ,GB_8BIT },
|
||||
{ "ld a, [de]" ,GB_8BIT },
|
||||
{ "dec de", GB_8BIT },
|
||||
{ "inc e", GB_8BIT },
|
||||
{ "dec e", GB_8BIT },
|
||||
{ "ld e, 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "rra", GB_8BIT },
|
||||
|
||||
{"stop" ,GB_8BIT}, //0x10
|
||||
{"ld de, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"ld [de], a" ,GB_8BIT},
|
||||
{"inc de" ,GB_8BIT},
|
||||
{"inc d" ,GB_8BIT},
|
||||
{"dec d" ,GB_8BIT},
|
||||
{"ld d, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rla" ,GB_8BIT},
|
||||
{"jr 0x%02x" ,GB_8BIT+ARG_8}, //signed
|
||||
{"add hl, de" ,GB_8BIT},
|
||||
{"ld a, [de]" ,GB_8BIT},
|
||||
{"dec de" ,GB_8BIT},
|
||||
{"inc e" ,GB_8BIT},
|
||||
{"dec e" ,GB_8BIT},
|
||||
{"ld e, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rra" ,GB_8BIT},
|
||||
{ "jr nZ, 0x%02x" ,GB_8BIT+ARG_8 }, //0x20 //signed
|
||||
{ "ld hl, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "ldi [hl], a" ,GB_8BIT },
|
||||
{ "inc hl", GB_8BIT },
|
||||
{ "inc h", GB_8BIT },
|
||||
{ "dec h", GB_8BIT },
|
||||
{ "ld h, 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "daa", GB_8BIT },
|
||||
{ "jr Z, 0x%02x" ,GB_8BIT+ARG_8 }, //signed
|
||||
{ "add hl, hl" ,GB_8BIT },
|
||||
{ "ldi a, [hl]" ,GB_8BIT },
|
||||
{ "dec hl", GB_8BIT },
|
||||
{ "inc l", GB_8BIT },
|
||||
{ "dec l", GB_8BIT },
|
||||
{ "ld l, 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "cpl", GB_8BIT },
|
||||
|
||||
{"jr nZ, 0x%02x" ,GB_8BIT+ARG_8}, //0x20 //signed
|
||||
{"ld hl, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"ldi [hl], a" ,GB_8BIT},
|
||||
{"inc hl" ,GB_8BIT},
|
||||
{"inc h" ,GB_8BIT},
|
||||
{"dec h" ,GB_8BIT},
|
||||
{"ld h, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"daa" ,GB_8BIT},
|
||||
{"jr Z, 0x%02x" ,GB_8BIT+ARG_8}, //signed
|
||||
{"add hl, hl" ,GB_8BIT},
|
||||
{"ldi a, [hl]" ,GB_8BIT},
|
||||
{"dec hl" ,GB_8BIT},
|
||||
{"inc l" ,GB_8BIT},
|
||||
{"dec l" ,GB_8BIT},
|
||||
{"ld l, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"cpl" ,GB_8BIT},
|
||||
{ "jr nC, 0x%02x" ,GB_8BIT+ARG_8 }, //0x30 //signed
|
||||
{ "ld sp, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "ldd [hl], a" ,GB_8BIT },
|
||||
{ "inc sp", GB_8BIT },
|
||||
{ "inc [hl]", GB_8BIT },
|
||||
{ "dec [hl]", GB_8BIT },
|
||||
{ "ld [hl], 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "scf", GB_8BIT },
|
||||
{ "jr C, 0x%02x" ,GB_8BIT+ARG_8 }, //signed
|
||||
{ "add hl, sp" ,GB_8BIT },
|
||||
{ "ldd a, [hl]" ,GB_8BIT },
|
||||
{ "dec sp", GB_8BIT },
|
||||
{ "inc a", GB_8BIT },
|
||||
{ "dec a", GB_8BIT },
|
||||
{ "ld a, 0x%02x" ,GB_8BIT+ARG_8 },
|
||||
{ "ccf", GB_8BIT },
|
||||
|
||||
{"jr nC, 0x%02x" ,GB_8BIT+ARG_8}, //0x30 //signed
|
||||
{"ld sp, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"ldd [hl], a" ,GB_8BIT},
|
||||
{"inc sp" ,GB_8BIT},
|
||||
{"inc [hl]" ,GB_8BIT},
|
||||
{"dec [hl]" ,GB_8BIT},
|
||||
{"ld [hl], 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"scf" ,GB_8BIT},
|
||||
{"jr C, 0x%02x" ,GB_8BIT+ARG_8}, //signed
|
||||
{"add hl, sp" ,GB_8BIT},
|
||||
{"ldd a, [hl]" ,GB_8BIT},
|
||||
{"dec sp" ,GB_8BIT},
|
||||
{"inc a" ,GB_8BIT},
|
||||
{"dec a" ,GB_8BIT},
|
||||
{"ld a, 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"ccf" ,GB_8BIT},
|
||||
{ "ld b, b" ,GB_8BIT }, //0x40
|
||||
{ "ld b, c" ,GB_8BIT },
|
||||
{ "ld b, d" ,GB_8BIT },
|
||||
{ "ld b, e" ,GB_8BIT },
|
||||
{ "ld b, h" ,GB_8BIT },
|
||||
{ "ld b, l" ,GB_8BIT },
|
||||
{ "ld b, [hl]" ,GB_8BIT },
|
||||
{ "ld b, a" ,GB_8BIT },
|
||||
{ "ld c, b" ,GB_8BIT },
|
||||
{ "ld c, c" ,GB_8BIT },
|
||||
{ "ld c, d" ,GB_8BIT },
|
||||
{ "ld c, e" ,GB_8BIT },
|
||||
{ "ld c, h" ,GB_8BIT },
|
||||
{ "ld c, l" ,GB_8BIT },
|
||||
{ "ld c, [hl]" ,GB_8BIT },
|
||||
{ "ld c, a" ,GB_8BIT },
|
||||
|
||||
{"ld b, b" ,GB_8BIT}, //0x40
|
||||
{"ld b, c" ,GB_8BIT},
|
||||
{"ld b, d" ,GB_8BIT},
|
||||
{"ld b, e" ,GB_8BIT},
|
||||
{"ld b, h" ,GB_8BIT},
|
||||
{"ld b, l" ,GB_8BIT},
|
||||
{"ld b, [hl]" ,GB_8BIT},
|
||||
{"ld b, a" ,GB_8BIT},
|
||||
{"ld c, b" ,GB_8BIT},
|
||||
{"ld c, c" ,GB_8BIT},
|
||||
{"ld c, d" ,GB_8BIT},
|
||||
{"ld c, e" ,GB_8BIT},
|
||||
{"ld c, h" ,GB_8BIT},
|
||||
{"ld c, l" ,GB_8BIT},
|
||||
{"ld c, [hl]" ,GB_8BIT},
|
||||
{"ld c, a" ,GB_8BIT},
|
||||
{ "ld d, b" ,GB_8BIT }, //0x50
|
||||
{ "ld d, c" ,GB_8BIT },
|
||||
{ "ld d, d" ,GB_8BIT },
|
||||
{ "ld d, e" ,GB_8BIT },
|
||||
{ "ld d, h" ,GB_8BIT },
|
||||
{ "ld d, l" ,GB_8BIT },
|
||||
{ "ld d, [hl]" ,GB_8BIT },
|
||||
{ "ld d, a" ,GB_8BIT },
|
||||
{ "ld e, b" ,GB_8BIT },
|
||||
{ "ld e, c" ,GB_8BIT },
|
||||
{ "ld e, d" ,GB_8BIT },
|
||||
{ "ld e, e" ,GB_8BIT },
|
||||
{ "ld e, h" ,GB_8BIT },
|
||||
{ "ld e, l" ,GB_8BIT },
|
||||
{ "ld e, [hl]" ,GB_8BIT },
|
||||
{ "ld e, a" ,GB_8BIT },
|
||||
|
||||
{"ld d, b" ,GB_8BIT}, //0x50
|
||||
{"ld d, c" ,GB_8BIT},
|
||||
{"ld d, d" ,GB_8BIT},
|
||||
{"ld d, e" ,GB_8BIT},
|
||||
{"ld d, h" ,GB_8BIT},
|
||||
{"ld d, l" ,GB_8BIT},
|
||||
{"ld d, [hl]" ,GB_8BIT},
|
||||
{"ld d, a" ,GB_8BIT},
|
||||
{"ld e, b" ,GB_8BIT},
|
||||
{"ld e, c" ,GB_8BIT},
|
||||
{"ld e, d" ,GB_8BIT},
|
||||
{"ld e, e" ,GB_8BIT},
|
||||
{"ld e, h" ,GB_8BIT},
|
||||
{"ld e, l" ,GB_8BIT},
|
||||
{"ld e, [hl]" ,GB_8BIT},
|
||||
{"ld e, a" ,GB_8BIT},
|
||||
{ "ld h, b" ,GB_8BIT }, //0x60
|
||||
{ "ld h, c" ,GB_8BIT },
|
||||
{ "ld h, d" ,GB_8BIT },
|
||||
{ "ld h, e" ,GB_8BIT },
|
||||
{ "ld h, h" ,GB_8BIT },
|
||||
{ "ld h, l" ,GB_8BIT },
|
||||
{ "ld h, [hl]" ,GB_8BIT },
|
||||
{ "ld h, a" ,GB_8BIT },
|
||||
{ "ld l, b" ,GB_8BIT },
|
||||
{ "ld l, c" ,GB_8BIT },
|
||||
{ "ld l, d" ,GB_8BIT },
|
||||
{ "ld l, e" ,GB_8BIT },
|
||||
{ "ld l, h" ,GB_8BIT },
|
||||
{ "ld l, l" ,GB_8BIT },
|
||||
{ "ld l, [hl]" ,GB_8BIT },
|
||||
{ "ld l, a" ,GB_8BIT },
|
||||
|
||||
{"ld h, b" ,GB_8BIT}, //0x60
|
||||
{"ld h, c" ,GB_8BIT},
|
||||
{"ld h, d" ,GB_8BIT},
|
||||
{"ld h, e" ,GB_8BIT},
|
||||
{"ld h, h" ,GB_8BIT},
|
||||
{"ld h, l" ,GB_8BIT},
|
||||
{"ld h, [hl]" ,GB_8BIT},
|
||||
{"ld h, a" ,GB_8BIT},
|
||||
{"ld l, b" ,GB_8BIT},
|
||||
{"ld l, c" ,GB_8BIT},
|
||||
{"ld l, d" ,GB_8BIT},
|
||||
{"ld l, e" ,GB_8BIT},
|
||||
{"ld l, h" ,GB_8BIT},
|
||||
{"ld l, l" ,GB_8BIT},
|
||||
{"ld l, [hl]" ,GB_8BIT},
|
||||
{"ld l, a" ,GB_8BIT},
|
||||
{ "ld [hl], b" ,GB_8BIT },//0X70
|
||||
{ "ld [hl], c" ,GB_8BIT },
|
||||
{ "ld [hl], d" ,GB_8BIT },
|
||||
{ "ld [hl], e" ,GB_8BIT },
|
||||
{ "ld [hl], h" ,GB_8BIT },
|
||||
{ "ld [hl], l" ,GB_8BIT },
|
||||
{ "halt", GB_8BIT },
|
||||
{ "ld [hl], a" ,GB_8BIT },
|
||||
{ "ld a, b" ,GB_8BIT },
|
||||
{ "ld a, c" ,GB_8BIT },
|
||||
{ "ld a, d" ,GB_8BIT },
|
||||
{ "ld a, e" ,GB_8BIT },
|
||||
{ "ld a, h" ,GB_8BIT },
|
||||
{ "ld a, l" ,GB_8BIT },
|
||||
{ "ld a, [hl]" ,GB_8BIT },
|
||||
{ "ld a, a" ,GB_8BIT },
|
||||
|
||||
{"ld [hl], b" ,GB_8BIT}, //0X70
|
||||
{"ld [hl], c" ,GB_8BIT},
|
||||
{"ld [hl], d" ,GB_8BIT},
|
||||
{"ld [hl], e" ,GB_8BIT},
|
||||
{"ld [hl], h" ,GB_8BIT},
|
||||
{"ld [hl], l" ,GB_8BIT},
|
||||
{"halt" ,GB_8BIT},
|
||||
{"ld [hl], a" ,GB_8BIT},
|
||||
{"ld a, b" ,GB_8BIT},
|
||||
{"ld a, c" ,GB_8BIT},
|
||||
{"ld a, d" ,GB_8BIT},
|
||||
{"ld a, e" ,GB_8BIT},
|
||||
{"ld a, h" ,GB_8BIT},
|
||||
{"ld a, l" ,GB_8BIT},
|
||||
{"ld a, [hl]" ,GB_8BIT},
|
||||
{"ld a, a" ,GB_8BIT},
|
||||
{ "add b", GB_8BIT }, //0x80
|
||||
{ "add c", GB_8BIT },
|
||||
{ "add d", GB_8BIT },
|
||||
{ "add e", GB_8BIT },
|
||||
{ "add h", GB_8BIT },
|
||||
{ "add l", GB_8BIT },
|
||||
{ "add [hl]", GB_8BIT },
|
||||
{ "add a", GB_8BIT },
|
||||
{ "adc b", GB_8BIT },
|
||||
{ "adc c", GB_8BIT },
|
||||
{ "adc d", GB_8BIT },
|
||||
{ "adc e", GB_8BIT },
|
||||
{ "adc h", GB_8BIT },
|
||||
{ "adc l", GB_8BIT },
|
||||
{ "adc [hl]", GB_8BIT },
|
||||
{ "adc a", GB_8BIT },
|
||||
|
||||
{"add b" ,GB_8BIT}, //0x80
|
||||
{"add c" ,GB_8BIT},
|
||||
{"add d" ,GB_8BIT},
|
||||
{"add e" ,GB_8BIT},
|
||||
{"add h" ,GB_8BIT},
|
||||
{"add l" ,GB_8BIT},
|
||||
{"add [hl]" ,GB_8BIT},
|
||||
{"add a" ,GB_8BIT},
|
||||
{"adc b" ,GB_8BIT},
|
||||
{"adc c" ,GB_8BIT},
|
||||
{"adc d" ,GB_8BIT},
|
||||
{"adc e" ,GB_8BIT},
|
||||
{"adc h" ,GB_8BIT},
|
||||
{"adc l" ,GB_8BIT},
|
||||
{"adc [hl]" ,GB_8BIT},
|
||||
{"adc a" ,GB_8BIT},
|
||||
{ "sub b", GB_8BIT }, //0x90
|
||||
{ "sub c", GB_8BIT },
|
||||
{ "sub d", GB_8BIT },
|
||||
{ "sub e", GB_8BIT },
|
||||
{ "sub h", GB_8BIT },
|
||||
{ "sub l", GB_8BIT },
|
||||
{ "sub [hl]", GB_8BIT },
|
||||
{ "sub a", GB_8BIT },
|
||||
{ "sbc b", GB_8BIT },
|
||||
{ "sbc c", GB_8BIT },
|
||||
{ "sbc d", GB_8BIT },
|
||||
{ "sbc e", GB_8BIT },
|
||||
{ "sbc h", GB_8BIT },
|
||||
{ "sbc l", GB_8BIT },
|
||||
{ "sbc [hl]", GB_8BIT },
|
||||
{ "sbc a", GB_8BIT },
|
||||
|
||||
{"sub b" ,GB_8BIT}, //0x90
|
||||
{"sub c" ,GB_8BIT},
|
||||
{"sub d" ,GB_8BIT},
|
||||
{"sub e" ,GB_8BIT},
|
||||
{"sub h" ,GB_8BIT},
|
||||
{"sub l" ,GB_8BIT},
|
||||
{"sub [hl]" ,GB_8BIT},
|
||||
{"sub a" ,GB_8BIT},
|
||||
{"sbc b" ,GB_8BIT},
|
||||
{"sbc c" ,GB_8BIT},
|
||||
{"sbc d" ,GB_8BIT},
|
||||
{"sbc e" ,GB_8BIT},
|
||||
{"sbc h" ,GB_8BIT},
|
||||
{"sbc l" ,GB_8BIT},
|
||||
{"sbc [hl]" ,GB_8BIT},
|
||||
{"sbc a" ,GB_8BIT},
|
||||
{ "and b", GB_8BIT }, //0xa0
|
||||
{ "and c", GB_8BIT },
|
||||
{ "and d", GB_8BIT },
|
||||
{ "and e", GB_8BIT },
|
||||
{ "and h", GB_8BIT },
|
||||
{ "and l", GB_8BIT },
|
||||
{ "and [hl]", GB_8BIT },
|
||||
{ "and a", GB_8BIT },
|
||||
{ "xor b", GB_8BIT },
|
||||
{ "xor c", GB_8BIT },
|
||||
{ "xor d", GB_8BIT },
|
||||
{ "xor e", GB_8BIT },
|
||||
{ "xor h", GB_8BIT },
|
||||
{ "xor l", GB_8BIT },
|
||||
{ "xor [hl]", GB_8BIT },
|
||||
{ "xor a", GB_8BIT },
|
||||
|
||||
{"and b" ,GB_8BIT}, //0xa0
|
||||
{"and c" ,GB_8BIT},
|
||||
{"and d" ,GB_8BIT},
|
||||
{"and e" ,GB_8BIT},
|
||||
{"and h" ,GB_8BIT},
|
||||
{"and l" ,GB_8BIT},
|
||||
{"and [hl]" ,GB_8BIT},
|
||||
{"and a" ,GB_8BIT},
|
||||
{"xor b" ,GB_8BIT},
|
||||
{"xor c" ,GB_8BIT},
|
||||
{"xor d" ,GB_8BIT},
|
||||
{"xor e" ,GB_8BIT},
|
||||
{"xor h" ,GB_8BIT},
|
||||
{"xor l" ,GB_8BIT},
|
||||
{"xor [hl]" ,GB_8BIT},
|
||||
{"xor a" ,GB_8BIT},
|
||||
{ "or b", GB_8BIT }, //0xb0
|
||||
{ "or c", GB_8BIT },
|
||||
{ "or d", GB_8BIT },
|
||||
{ "or e", GB_8BIT },
|
||||
{ "or h", GB_8BIT },
|
||||
{ "or l", GB_8BIT },
|
||||
{ "or [hl]", GB_8BIT },
|
||||
{ "or a", GB_8BIT },
|
||||
{ "cp b", GB_8BIT },
|
||||
{ "cp c", GB_8BIT },
|
||||
{ "cp d", GB_8BIT },
|
||||
{ "cp e", GB_8BIT },
|
||||
{ "cp h", GB_8BIT },
|
||||
{ "cp l", GB_8BIT },
|
||||
{ "cp [hl]", GB_8BIT },
|
||||
{ "cp a", GB_8BIT },
|
||||
|
||||
{"or b" ,GB_8BIT}, //0xb0
|
||||
{"or c" ,GB_8BIT},
|
||||
{"or d" ,GB_8BIT},
|
||||
{"or e" ,GB_8BIT},
|
||||
{"or h" ,GB_8BIT},
|
||||
{"or l" ,GB_8BIT},
|
||||
{"or [hl]" ,GB_8BIT},
|
||||
{"or a" ,GB_8BIT},
|
||||
{"cp b" ,GB_8BIT},
|
||||
{"cp c" ,GB_8BIT},
|
||||
{"cp d" ,GB_8BIT},
|
||||
{"cp e" ,GB_8BIT},
|
||||
{"cp h" ,GB_8BIT},
|
||||
{"cp l" ,GB_8BIT},
|
||||
{"cp [hl]" ,GB_8BIT},
|
||||
{"cp a" ,GB_8BIT},
|
||||
{ "ret nZ", GB_8BIT }, //0xc0
|
||||
{ "pop bc", GB_8BIT },
|
||||
{ "jp nZ, 0x%04x", GB_8BIT+ARG_16},
|
||||
{ "jp 0x%04x", GB_8BIT+ARG_16},
|
||||
{ "call nZ, 0x%04x", GB_8BIT+ARG_16},
|
||||
{ "push bc", GB_8BIT },
|
||||
{ "add 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 0", GB_8BIT },
|
||||
{ "ret Z", GB_8BIT },
|
||||
{ "ret", GB_8BIT },
|
||||
{ "jp Z, 0x%04x", GB_8BIT+ARG_16},
|
||||
{ "", GB_16BIT },
|
||||
{ "call Z, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "call 0x%04x", GB_8BIT+ARG_16},
|
||||
{ "adc 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 8", GB_8BIT },
|
||||
|
||||
{"ret nZ" ,GB_8BIT}, //0xc0
|
||||
{"pop bc" ,GB_8BIT},
|
||||
{"jp nZ, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"jp 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"call nZ, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"push bc" ,GB_8BIT},
|
||||
{"add 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 0" ,GB_8BIT},
|
||||
{"ret Z" ,GB_8BIT},
|
||||
{"ret" ,GB_8BIT},
|
||||
{"jp Z, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"" ,GB_16BIT},
|
||||
{"call Z, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"call 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"adc 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 8" ,GB_8BIT},
|
||||
{ "ret nC", GB_8BIT }, //0xd0
|
||||
{ "pop de", GB_8BIT },
|
||||
{ "jp nC, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "call nC, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "push de", GB_8BIT },
|
||||
{ "sub 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 16", GB_8BIT },
|
||||
{ "ret C", GB_8BIT },
|
||||
{ "reti", GB_8BIT },
|
||||
{ "jp C, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "call C, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "sbc 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 24", GB_8BIT },
|
||||
|
||||
{"ret nC" ,GB_8BIT}, //0xd0
|
||||
{"pop de" ,GB_8BIT},
|
||||
{"jp nC, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"call nC, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"push de" ,GB_8BIT},
|
||||
{"sub 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 16" ,GB_8BIT},
|
||||
{"ret C" ,GB_8BIT},
|
||||
{"reti" ,GB_8BIT},
|
||||
{"jp C, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"call C, 0x%04x" ,GB_8BIT+ARG_16},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"sbc 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 24" ,GB_8BIT},
|
||||
{ "ld [%s], a" ,GB_8BIT+ARG_8+GB_IO }, //0xe0
|
||||
{ "pop hl", GB_8BIT },
|
||||
{ "ld [0xff00 + c], a" ,GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "push hl", GB_8BIT },
|
||||
{ "and 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 32", GB_8BIT },
|
||||
{ "add sp, 0x%02x" ,GB_8BIT+ARG_8 }, //signed
|
||||
{ "jp hl", GB_8BIT },
|
||||
{ "ld [0x%04x], a" ,GB_8BIT+ARG_16}, //signed
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "xor 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 40", GB_8BIT },
|
||||
|
||||
{"ld [%s], a" ,GB_8BIT+ARG_8+GB_IO}, //0xe0
|
||||
{"pop hl" ,GB_8BIT},
|
||||
{"ld [0xff00 + c], a" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"push hl" ,GB_8BIT},
|
||||
{"and 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 32" ,GB_8BIT},
|
||||
{"add sp, 0x%02x" ,GB_8BIT+ARG_8}, //signed
|
||||
{"jp hl" ,GB_8BIT},
|
||||
{"ld [0x%04x], a" ,GB_8BIT+ARG_16}, //signed
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"xor 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 40" ,GB_8BIT},
|
||||
|
||||
{"ld a, [%s]" ,GB_8BIT+ARG_8+GB_IO}, //0xf0
|
||||
{"pop af" ,GB_8BIT},
|
||||
{"ld a, [0xff00 + c]" ,GB_8BIT},
|
||||
{"di" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"push af" ,GB_8BIT},
|
||||
{"or 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 48" ,GB_8BIT},
|
||||
{"ld hl, sp + 0x%02x" ,GB_8BIT+ARG_8}, //signed
|
||||
{"ld sp, hl" ,GB_8BIT},
|
||||
{"ld a, [0x%04x]" ,GB_8BIT+ARG_16},
|
||||
{"ei" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"invalid" ,GB_8BIT},
|
||||
{"cp 0x%02x" ,GB_8BIT+ARG_8},
|
||||
{"rst 56" ,GB_8BIT},
|
||||
{ "ld a, [%s]" ,GB_8BIT+ARG_8+GB_IO }, //0xf0
|
||||
{ "pop af", GB_8BIT },
|
||||
{ "ld a, [0xff00 + c]" ,GB_8BIT },
|
||||
{ "di", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "push af", GB_8BIT },
|
||||
{ "or 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 48", GB_8BIT },
|
||||
{ "ld hl, sp + 0x%02x" ,GB_8BIT+ARG_8 }, //signed
|
||||
{ "ld sp, hl", GB_8BIT },
|
||||
{ "ld a, [0x%04x]", GB_8BIT+ARG_16},
|
||||
{ "ei", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "invalid", GB_8BIT },
|
||||
{ "cp 0x%02x", GB_8BIT+ARG_8 },
|
||||
{ "rst 56", GB_8BIT },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -111,339 +111,339 @@ static const unsigned char i4004_lengthtable[] =
|
|||
static const struct i4004_kv i4004_wordlist[] =
|
||||
{
|
||||
#line 146 "i4004.gperf"
|
||||
{"ldm 0xe","de"},
|
||||
{ "ldm 0xe","de" },
|
||||
#line 93 "i4004.gperf"
|
||||
{"ld r9","a9"},
|
||||
{ "ld r9","a9" },
|
||||
#line 141 "i4004.gperf"
|
||||
{"ldm 0x9","d9"},
|
||||
{ "ldm 0x9","d9" },
|
||||
#line 29 "i4004.gperf"
|
||||
{"jin r8r9","39"},
|
||||
{ "jin r8r9","39" },
|
||||
#line 142 "i4004.gperf"
|
||||
{"ldm 0xa","da"},
|
||||
{ "ldm 0xa","da" },
|
||||
#line 90 "i4004.gperf"
|
||||
{"ld r6","a6"},
|
||||
{ "ld r6","a6" },
|
||||
#line 61 "i4004.gperf"
|
||||
{"add r9","89"},
|
||||
{ "add r9","89" },
|
||||
#line 138 "i4004.gperf"
|
||||
{"ldm 0x6","d6"},
|
||||
{ "ldm 0x6","d6" },
|
||||
#line 144 "i4004.gperf"
|
||||
{"ldm 0xc","dc"},
|
||||
{ "ldm 0xc","dc" },
|
||||
#line 168 "i4004.gperf"
|
||||
{"cma","f4"},
|
||||
{ "cma","f4" },
|
||||
#line 58 "i4004.gperf"
|
||||
{"add r6","86"},
|
||||
{ "add r6","86" },
|
||||
#line 143 "i4004.gperf"
|
||||
{"ldm 0xb","db"},
|
||||
{ "ldm 0xb","db" },
|
||||
#line 167 "i4004.gperf"
|
||||
{"cmc","f3"},
|
||||
{ "cmc","f3" },
|
||||
#line 166 "i4004.gperf"
|
||||
{"iac","f2"},
|
||||
{ "iac","f2" },
|
||||
#line 130 "i4004.gperf"
|
||||
{"bbl 0xe","ce"},
|
||||
{ "bbl 0xe","ce" },
|
||||
#line 176 "i4004.gperf"
|
||||
{"kbp","fc"},
|
||||
{ "kbp","fc" },
|
||||
#line 125 "i4004.gperf"
|
||||
{"bbl 0x9","c9"},
|
||||
{ "bbl 0x9","c9" },
|
||||
#line 126 "i4004.gperf"
|
||||
{"bbl 0xa","ca"},
|
||||
{ "bbl 0xa","ca" },
|
||||
#line 174 "i4004.gperf"
|
||||
{"stc","fa"},
|
||||
{ "stc","fa" },
|
||||
#line 122 "i4004.gperf"
|
||||
{"bbl 0x6","c6"},
|
||||
{ "bbl 0x6","c6" },
|
||||
#line 128 "i4004.gperf"
|
||||
{"bbl 0xc","cc"},
|
||||
{ "bbl 0xc","cc" },
|
||||
#line 11 "i4004.gperf"
|
||||
{"nop","00"},
|
||||
{ "nop","00" },
|
||||
#line 127 "i4004.gperf"
|
||||
{"bbl 0xb","cb"},
|
||||
{ "bbl 0xb","cb" },
|
||||
#line 87 "i4004.gperf"
|
||||
{"ld r3","a3"},
|
||||
{ "ld r3","a3" },
|
||||
#line 97 "i4004.gperf"
|
||||
{"ld r13","ad"},
|
||||
{ "ld r13","ad" },
|
||||
#line 135 "i4004.gperf"
|
||||
{"ldm 0x3","d3"},
|
||||
{ "ldm 0x3","d3" },
|
||||
#line 23 "i4004.gperf"
|
||||
{"jin r2r3","33"},
|
||||
{ "jin r2r3","33" },
|
||||
#line 33 "i4004.gperf"
|
||||
{"jin r12r13","3d"},
|
||||
{ "jin r12r13","3d" },
|
||||
#line 55 "i4004.gperf"
|
||||
{"add r3","83"},
|
||||
{ "add r3","83" },
|
||||
#line 65 "i4004.gperf"
|
||||
{"add r13","8d"},
|
||||
{ "add r13","8d" },
|
||||
#line 85 "i4004.gperf"
|
||||
{"ld r1","a1"},
|
||||
{ "ld r1","a1" },
|
||||
#line 95 "i4004.gperf"
|
||||
{"ld r11","ab"},
|
||||
{ "ld r11","ab" },
|
||||
#line 133 "i4004.gperf"
|
||||
{"ldm 0x1","d1"},
|
||||
{ "ldm 0x1","d1" },
|
||||
#line 21 "i4004.gperf"
|
||||
{"jin r0r1","31"},
|
||||
{ "jin r0r1","31" },
|
||||
#line 18 "i4004.gperf"
|
||||
{"src r6","2d"},
|
||||
{ "src r6","2d" },
|
||||
#line 31 "i4004.gperf"
|
||||
{"jin r10r11","3b"},
|
||||
{ "jin r10r11","3b" },
|
||||
#line 53 "i4004.gperf"
|
||||
{"add r1","81"},
|
||||
{ "add r1","81" },
|
||||
#line 63 "i4004.gperf"
|
||||
{"add r11","8b"},
|
||||
{ "add r11","8b" },
|
||||
#line 119 "i4004.gperf"
|
||||
{"bbl 0x3","c3"},
|
||||
{ "bbl 0x3","c3" },
|
||||
#line 169 "i4004.gperf"
|
||||
{"ral","f5"},
|
||||
{ "ral","f5" },
|
||||
#line 145 "i4004.gperf"
|
||||
{"ldm 0xd","dd"},
|
||||
{ "ldm 0xd","dd" },
|
||||
#line 149 "i4004.gperf"
|
||||
{"wmp","e1"},
|
||||
{ "wmp","e1" },
|
||||
#line 109 "i4004.gperf"
|
||||
{"xch r9","b9"},
|
||||
{ "xch r9","b9" },
|
||||
#line 117 "i4004.gperf"
|
||||
{"bbl 0x1","c1"},
|
||||
{ "bbl 0x1","c1" },
|
||||
#line 106 "i4004.gperf"
|
||||
{"xch r6","b6"},
|
||||
{ "xch r6","b6" },
|
||||
#line 89 "i4004.gperf"
|
||||
{"ld r5","a5"},
|
||||
{ "ld r5","a5" },
|
||||
#line 99 "i4004.gperf"
|
||||
{"ld r15","af"},
|
||||
{ "ld r15","af" },
|
||||
#line 137 "i4004.gperf"
|
||||
{"ldm 0x5","d5"},
|
||||
{ "ldm 0x5","d5" },
|
||||
#line 25 "i4004.gperf"
|
||||
{"jin r4r5","35"},
|
||||
{ "jin r4r5","35" },
|
||||
#line 35 "i4004.gperf"
|
||||
{"jin r14r15","3f"},
|
||||
{ "jin r14r15","3f" },
|
||||
#line 57 "i4004.gperf"
|
||||
{"add r5","85"},
|
||||
{ "add r5","85" },
|
||||
#line 67 "i4004.gperf"
|
||||
{"add r15","8f"},
|
||||
{ "add r15","8f" },
|
||||
#line 175 "i4004.gperf"
|
||||
{"daa","fb"},
|
||||
{ "daa","fb" },
|
||||
#line 15 "i4004.gperf"
|
||||
{"src r3","27"},
|
||||
{ "src r3","27" },
|
||||
#line 172 "i4004.gperf"
|
||||
{"dac","f8"},
|
||||
{ "dac","f8" },
|
||||
#line 92 "i4004.gperf"
|
||||
{"ld r8","a8"},
|
||||
{ "ld r8","a8" },
|
||||
#line 140 "i4004.gperf"
|
||||
{"ldm 0x8","d8"},
|
||||
{ "ldm 0x8","d8" },
|
||||
#line 129 "i4004.gperf"
|
||||
{"bbl 0xd","cd"},
|
||||
{ "bbl 0xd","cd" },
|
||||
#line 163 "i4004.gperf"
|
||||
{"rd3","ef"},
|
||||
{ "rd3","ef" },
|
||||
#line 60 "i4004.gperf"
|
||||
{"add r8","88"},
|
||||
{ "add r8","88" },
|
||||
#line 13 "i4004.gperf"
|
||||
{"src r1","23"},
|
||||
{ "src r1","23" },
|
||||
#line 171 "i4004.gperf"
|
||||
{"tcc","f7"},
|
||||
{ "tcc","f7" },
|
||||
#line 121 "i4004.gperf"
|
||||
{"bbl 0x5","c5"},
|
||||
{ "bbl 0x5","c5" },
|
||||
#line 161 "i4004.gperf"
|
||||
{"rd1","ed"},
|
||||
{ "rd1","ed" },
|
||||
#line 158 "i4004.gperf"
|
||||
{"rdr","ea"},
|
||||
{ "rdr","ea" },
|
||||
#line 103 "i4004.gperf"
|
||||
{"xch r3","b3"},
|
||||
{ "xch r3","b3" },
|
||||
#line 113 "i4004.gperf"
|
||||
{"xch r13","bd"},
|
||||
{ "xch r13","bd" },
|
||||
#line 173 "i4004.gperf"
|
||||
{"tcs","f9"},
|
||||
{ "tcs","f9" },
|
||||
#line 124 "i4004.gperf"
|
||||
{"bbl 0x8","c8"},
|
||||
{ "bbl 0x8","c8" },
|
||||
#line 155 "i4004.gperf"
|
||||
{"wr3","e7"},
|
||||
{ "wr3","e7" },
|
||||
#line 77 "i4004.gperf"
|
||||
{"sub r9","99"},
|
||||
{ "sub r9","99" },
|
||||
#line 101 "i4004.gperf"
|
||||
{"xch r1","b1"},
|
||||
{ "xch r1","b1" },
|
||||
#line 111 "i4004.gperf"
|
||||
{"xch r11","bb"},
|
||||
{ "xch r11","bb" },
|
||||
#line 170 "i4004.gperf"
|
||||
{"rar","f6"},
|
||||
{ "rar","f6" },
|
||||
#line 74 "i4004.gperf"
|
||||
{"sub r6","96"},
|
||||
{ "sub r6","96" },
|
||||
#line 17 "i4004.gperf"
|
||||
{"src r5","2b"},
|
||||
{ "src r5","2b" },
|
||||
#line 153 "i4004.gperf"
|
||||
{"wr1","e5"},
|
||||
{ "wr1","e5" },
|
||||
#line 86 "i4004.gperf"
|
||||
{"ld r2","a2"},
|
||||
{ "ld r2","a2" },
|
||||
#line 96 "i4004.gperf"
|
||||
{"ld r12","ac"},
|
||||
{ "ld r12","ac" },
|
||||
#line 134 "i4004.gperf"
|
||||
{"ldm 0x2","d2"},
|
||||
{ "ldm 0x2","d2" },
|
||||
#line 150 "i4004.gperf"
|
||||
{"wrr","e2"},
|
||||
{ "wrr","e2" },
|
||||
#line 54 "i4004.gperf"
|
||||
{"add r2","82"},
|
||||
{ "add r2","82" },
|
||||
#line 64 "i4004.gperf"
|
||||
{"add r12","8c"},
|
||||
{ "add r12","8c" },
|
||||
#line 177 "i4004.gperf"
|
||||
{"dcl","fd"},
|
||||
{ "dcl","fd" },
|
||||
#line 84 "i4004.gperf"
|
||||
{"ld r0","a0"},
|
||||
{ "ld r0","a0" },
|
||||
#line 94 "i4004.gperf"
|
||||
{"ld r10","aa"},
|
||||
{ "ld r10","aa" },
|
||||
#line 132 "i4004.gperf"
|
||||
{"ldm 0x0","d0"},
|
||||
{ "ldm 0x0","d0" },
|
||||
#line 52 "i4004.gperf"
|
||||
{"add r0","80"},
|
||||
{ "add r0","80" },
|
||||
#line 62 "i4004.gperf"
|
||||
{"add r10","8a"},
|
||||
{ "add r10","8a" },
|
||||
#line 159 "i4004.gperf"
|
||||
{"adm","eb"},
|
||||
{ "adm","eb" },
|
||||
#line 105 "i4004.gperf"
|
||||
{"xch r5","b5"},
|
||||
{ "xch r5","b5" },
|
||||
#line 115 "i4004.gperf"
|
||||
{"xch r15","bf"},
|
||||
{ "xch r15","bf" },
|
||||
#line 118 "i4004.gperf"
|
||||
{"bbl 0x2","c2"},
|
||||
{ "bbl 0x2","c2" },
|
||||
#line 71 "i4004.gperf"
|
||||
{"sub r3","93"},
|
||||
{ "sub r3","93" },
|
||||
#line 81 "i4004.gperf"
|
||||
{"sub r13","9d"},
|
||||
{ "sub r13","9d" },
|
||||
#line 165 "i4004.gperf"
|
||||
{"clc","f1"},
|
||||
{ "clc","f1" },
|
||||
#line 108 "i4004.gperf"
|
||||
{"xch r8","b8"},
|
||||
{ "xch r8","b8" },
|
||||
#line 116 "i4004.gperf"
|
||||
{"bbl 0x0","c0"},
|
||||
{ "bbl 0x0","c0" },
|
||||
#line 164 "i4004.gperf"
|
||||
{"clb","f0"},
|
||||
{ "clb","f0" },
|
||||
#line 69 "i4004.gperf"
|
||||
{"sub r1","91"},
|
||||
{ "sub r1","91" },
|
||||
#line 79 "i4004.gperf"
|
||||
{"sub r11","9b"},
|
||||
{ "sub r11","9b" },
|
||||
#line 156 "i4004.gperf"
|
||||
{"sbm","e8"},
|
||||
{ "sbm","e8" },
|
||||
#line 14 "i4004.gperf"
|
||||
{"src r2","25"},
|
||||
{ "src r2","25" },
|
||||
#line 91 "i4004.gperf"
|
||||
{"ld r7","a7"},
|
||||
{ "ld r7","a7" },
|
||||
#line 139 "i4004.gperf"
|
||||
{"ldm 0x7","d7"},
|
||||
{ "ldm 0x7","d7" },
|
||||
#line 27 "i4004.gperf"
|
||||
{"jin r6r7","37"},
|
||||
{ "jin r6r7","37" },
|
||||
#line 162 "i4004.gperf"
|
||||
{"rd2","ee"},
|
||||
{ "rd2","ee" },
|
||||
#line 59 "i4004.gperf"
|
||||
{"add r7","87"},
|
||||
{ "add r7","87" },
|
||||
#line 12 "i4004.gperf"
|
||||
{"src r0","21"},
|
||||
{ "src r0","21" },
|
||||
#line 160 "i4004.gperf"
|
||||
{"rd0","ec"},
|
||||
{ "rd0","ec" },
|
||||
#line 73 "i4004.gperf"
|
||||
{"sub r5","95"},
|
||||
{ "sub r5","95" },
|
||||
#line 83 "i4004.gperf"
|
||||
{"sub r15","9f"},
|
||||
{ "sub r15","9f" },
|
||||
#line 157 "i4004.gperf"
|
||||
{"rdm","e9"},
|
||||
{ "rdm","e9" },
|
||||
#line 102 "i4004.gperf"
|
||||
{"xch r2","b2"},
|
||||
{ "xch r2","b2" },
|
||||
#line 112 "i4004.gperf"
|
||||
{"xch r12","bc"},
|
||||
{ "xch r12","bc" },
|
||||
#line 151 "i4004.gperf"
|
||||
{"wpm","e3"},
|
||||
{ "wpm","e3" },
|
||||
#line 123 "i4004.gperf"
|
||||
{"bbl 0x7","c7"},
|
||||
{ "bbl 0x7","c7" },
|
||||
#line 154 "i4004.gperf"
|
||||
{"wr2","e6"},
|
||||
{ "wr2","e6" },
|
||||
#line 76 "i4004.gperf"
|
||||
{"sub r8","98"},
|
||||
{ "sub r8","98" },
|
||||
#line 100 "i4004.gperf"
|
||||
{"xch r0","b0"},
|
||||
{ "xch r0","b0" },
|
||||
#line 110 "i4004.gperf"
|
||||
{"xch r10","ba"},
|
||||
{ "xch r10","ba" },
|
||||
#line 88 "i4004.gperf"
|
||||
{"ld r4","a4"},
|
||||
{ "ld r4","a4" },
|
||||
#line 98 "i4004.gperf"
|
||||
{"ld r14","ae"},
|
||||
{ "ld r14","ae" },
|
||||
#line 136 "i4004.gperf"
|
||||
{"ldm 0x4","d4"},
|
||||
{ "ldm 0x4","d4" },
|
||||
#line 152 "i4004.gperf"
|
||||
{"wr0","e4"},
|
||||
{ "wr0","e4" },
|
||||
#line 56 "i4004.gperf"
|
||||
{"add r4","84"},
|
||||
{ "add r4","84" },
|
||||
#line 66 "i4004.gperf"
|
||||
{"add r14","8e"},
|
||||
{ "add r14","8e" },
|
||||
#line 148 "i4004.gperf"
|
||||
{"wrm","e0"},
|
||||
{ "wrm","e0" },
|
||||
#line 45 "i4004.gperf"
|
||||
{"inc r9","69"},
|
||||
{ "inc r9","69" },
|
||||
#line 19 "i4004.gperf"
|
||||
{"src r7","2f"},
|
||||
{ "src r7","2f" },
|
||||
#line 147 "i4004.gperf"
|
||||
{"ldm 0xf","df"},
|
||||
{ "ldm 0xf","df" },
|
||||
#line 42 "i4004.gperf"
|
||||
{"inc r6","66"},
|
||||
{ "inc r6","66" },
|
||||
#line 28 "i4004.gperf"
|
||||
{"fin r8r9","38"},
|
||||
{ "fin r8r9","38" },
|
||||
#line 120 "i4004.gperf"
|
||||
{"bbl 0x4","c4"},
|
||||
{ "bbl 0x4","c4" },
|
||||
#line 70 "i4004.gperf"
|
||||
{"sub r2","92"},
|
||||
{ "sub r2","92" },
|
||||
#line 80 "i4004.gperf"
|
||||
{"sub r12","9c"},
|
||||
{ "sub r12","9c" },
|
||||
#line 107 "i4004.gperf"
|
||||
{"xch r7","b7"},
|
||||
{ "xch r7","b7" },
|
||||
#line 131 "i4004.gperf"
|
||||
{"bbl 0xf","cf"},
|
||||
{ "bbl 0xf","cf" },
|
||||
#line 68 "i4004.gperf"
|
||||
{"sub r0","90"},
|
||||
{ "sub r0","90" },
|
||||
#line 78 "i4004.gperf"
|
||||
{"sub r10","9a"},
|
||||
{ "sub r10","9a" },
|
||||
#line 16 "i4004.gperf"
|
||||
{"src r4","29"},
|
||||
{ "src r4","29" },
|
||||
#line 39 "i4004.gperf"
|
||||
{"inc r3","63"},
|
||||
{ "inc r3","63" },
|
||||
#line 49 "i4004.gperf"
|
||||
{"inc r13","6d"},
|
||||
{ "inc r13","6d" },
|
||||
#line 22 "i4004.gperf"
|
||||
{"fin r2r3","32"},
|
||||
{ "fin r2r3","32" },
|
||||
#line 32 "i4004.gperf"
|
||||
{"fin r12r13","3c"},
|
||||
{ "fin r12r13","3c" },
|
||||
#line 37 "i4004.gperf"
|
||||
{"inc r1","61"},
|
||||
{ "inc r1","61" },
|
||||
#line 47 "i4004.gperf"
|
||||
{"inc r11","6b"},
|
||||
{ "inc r11","6b" },
|
||||
#line 20 "i4004.gperf"
|
||||
{"fin r0r1","30"},
|
||||
{ "fin r0r1","30" },
|
||||
#line 30 "i4004.gperf"
|
||||
{"fin r10r11","3a"},
|
||||
{ "fin r10r11","3a" },
|
||||
#line 104 "i4004.gperf"
|
||||
{"xch r4","b4"},
|
||||
{ "xch r4","b4" },
|
||||
#line 114 "i4004.gperf"
|
||||
{"xch r14","be"},
|
||||
{ "xch r14","be" },
|
||||
#line 75 "i4004.gperf"
|
||||
{"sub r7","97"},
|
||||
{ "sub r7","97" },
|
||||
#line 41 "i4004.gperf"
|
||||
{"inc r5","65"},
|
||||
{ "inc r5","65" },
|
||||
#line 51 "i4004.gperf"
|
||||
{"inc r15","6f"},
|
||||
{ "inc r15","6f" },
|
||||
#line 24 "i4004.gperf"
|
||||
{"fin r4r5","34"},
|
||||
{ "fin r4r5","34" },
|
||||
#line 34 "i4004.gperf"
|
||||
{"fin r14r15","3e"},
|
||||
{ "fin r14r15","3e" },
|
||||
#line 44 "i4004.gperf"
|
||||
{"inc r8","68"},
|
||||
{ "inc r8","68" },
|
||||
#line 72 "i4004.gperf"
|
||||
{"sub r4","94"},
|
||||
{ "sub r4","94" },
|
||||
#line 82 "i4004.gperf"
|
||||
{"sub r14","9e"},
|
||||
{ "sub r14","9e" },
|
||||
#line 38 "i4004.gperf"
|
||||
{"inc r2","62"},
|
||||
{ "inc r2","62" },
|
||||
#line 48 "i4004.gperf"
|
||||
{"inc r12","6c"},
|
||||
{ "inc r12","6c" },
|
||||
#line 36 "i4004.gperf"
|
||||
{"inc r0","60"},
|
||||
{ "inc r0","60" },
|
||||
#line 46 "i4004.gperf"
|
||||
{"inc r10","6a"},
|
||||
{ "inc r10","6a" },
|
||||
#line 43 "i4004.gperf"
|
||||
{"inc r7","67"},
|
||||
{ "inc r7","67" },
|
||||
#line 26 "i4004.gperf"
|
||||
{"fin r6r7","36"},
|
||||
{ "fin r6r7","36" },
|
||||
#line 40 "i4004.gperf"
|
||||
{"inc r4","64"},
|
||||
{ "inc r4","64" },
|
||||
#line 50 "i4004.gperf"
|
||||
{"inc r14","6e"}
|
||||
{ "inc r14","6e" }
|
||||
};
|
||||
|
||||
static const short i4004_lookup[] =
|
||||
|
|
|
|||
|
|
@ -17,27 +17,27 @@ typedef struct r_asm_lm32_csr_t {
|
|||
#define RAsmLm32CsrNumber 21
|
||||
|
||||
static const RAsmLm32Csr RAsmLm32Csrs[RAsmLm32CsrNumber] = {
|
||||
{0x00, "IE"},
|
||||
{0x01, "IM"},
|
||||
{0x02, "IP"},
|
||||
{0x03, "ICC"},
|
||||
{0x04, "DCC"},
|
||||
{0x05, "CC"},
|
||||
{0x06, "CFG"},
|
||||
{0x07, "EBA"},
|
||||
{0x08, "DC"},
|
||||
{0x09, "DEBA"},
|
||||
{0x0a, "CFG2"},
|
||||
{0x0e, "JTX"},
|
||||
{0x0f, "JRX"},
|
||||
{0x10, "BP0"},
|
||||
{0x11, "BP1"},
|
||||
{0x12, "BP2"},
|
||||
{0x13, "BP3"},
|
||||
{0x18, "WP0"},
|
||||
{0x19, "WP1"},
|
||||
{0x1a, "WP2"},
|
||||
{0x1b, "WP3"},
|
||||
{0x00, "IE" },
|
||||
{0x01, "IM" },
|
||||
{0x02, "IP" },
|
||||
{0x03, "ICC" },
|
||||
{0x04, "DCC" },
|
||||
{0x05, "CC" },
|
||||
{0x06, "CFG" },
|
||||
{0x07, "EBA" },
|
||||
{0x08, "DC" },
|
||||
{0x09, "DEBA" },
|
||||
{0x0a, "CFG2" },
|
||||
{0x0e, "JTX" },
|
||||
{0x0f, "JRX" },
|
||||
{0x10, "BP0" },
|
||||
{0x11, "BP1" },
|
||||
{0x12, "BP2" },
|
||||
{0x13, "BP3" },
|
||||
{0x18, "WP0" },
|
||||
{0x19, "WP1" },
|
||||
{0x1a, "WP2" },
|
||||
{0x1b, "WP3" },
|
||||
};
|
||||
|
||||
typedef struct r_asm_lm32_reg_t {
|
||||
|
|
@ -48,45 +48,45 @@ typedef struct r_asm_lm32_reg_t {
|
|||
#define RAsmLm32RegNumber 39
|
||||
|
||||
static const RAsmLm32Reg RAsmLm32Regs[RAsmLm32RegNumber] = {
|
||||
{0x00, "r0"},
|
||||
{0x00, "zero"},
|
||||
{0x01, "r1"},
|
||||
{0x02, "r2"},
|
||||
{0x03, "r3"},
|
||||
{0x04, "r4"},
|
||||
{0x05, "r5"},
|
||||
{0x06, "r6"},
|
||||
{0x07, "r7"},
|
||||
{0x08, "r8"},
|
||||
{0x09, "r9"},
|
||||
{0x0a, "r10"},
|
||||
{0x0b, "r11"},
|
||||
{0x0c, "r12"},
|
||||
{0x0d, "r13"},
|
||||
{0x0e, "r14"},
|
||||
{0x0f, "r15"},
|
||||
{0x10, "r16"},
|
||||
{0x11, "r17"},
|
||||
{0x12, "r18"},
|
||||
{0x13, "r19"},
|
||||
{0x14, "r20"},
|
||||
{0x15, "r21"},
|
||||
{0x16, "r22"},
|
||||
{0x17, "r23"},
|
||||
{0x18, "r24"},
|
||||
{0x19, "r25"},
|
||||
{0x1a, "gp"},
|
||||
{0x1a, "r26"},
|
||||
{0x1b, "fp"},
|
||||
{0x1b, "r27"},
|
||||
{0x1c, "sp"},
|
||||
{0x1c, "r28"},
|
||||
{0x1d, "ra"},
|
||||
{0x1d, "r29"},
|
||||
{0x1e, "ea"},
|
||||
{0x1e, "r30"},
|
||||
{0x1f, "ba"},
|
||||
{0x1f, "r31"},
|
||||
{0x00, "r0" },
|
||||
{0x00, "zero" },
|
||||
{0x01, "r1" },
|
||||
{0x02, "r2" },
|
||||
{0x03, "r3" },
|
||||
{0x04, "r4" },
|
||||
{0x05, "r5" },
|
||||
{0x06, "r6" },
|
||||
{0x07, "r7" },
|
||||
{0x08, "r8" },
|
||||
{0x09, "r9" },
|
||||
{0x0a, "r10" },
|
||||
{0x0b, "r11" },
|
||||
{0x0c, "r12" },
|
||||
{0x0d, "r13" },
|
||||
{0x0e, "r14" },
|
||||
{0x0f, "r15" },
|
||||
{0x10, "r16" },
|
||||
{0x11, "r17" },
|
||||
{0x12, "r18" },
|
||||
{0x13, "r19" },
|
||||
{0x14, "r20" },
|
||||
{0x15, "r21" },
|
||||
{0x16, "r22" },
|
||||
{0x17, "r23" },
|
||||
{0x18, "r24" },
|
||||
{0x19, "r25" },
|
||||
{0x1a, "gp" },
|
||||
{0x1a, "r26" },
|
||||
{0x1b, "fp" },
|
||||
{0x1b, "r27" },
|
||||
{0x1c, "sp" },
|
||||
{0x1c, "r28" },
|
||||
{0x1d, "ra" },
|
||||
{0x1d, "r29" },
|
||||
{0x1e, "ea" },
|
||||
{0x1e, "r30" },
|
||||
{0x1f, "ba" },
|
||||
{0x1f, "r31" },
|
||||
};
|
||||
|
||||
typedef enum r_asm_lm32_instr_type_t {
|
||||
|
|
@ -179,70 +179,70 @@ typedef struct r_asm_lm32_opcode {
|
|||
#define RAsmLm32OpcodeNumber 0x40
|
||||
|
||||
static const RAsmLm32Opcode RAsmLm32OpcodeList[RAsmLm32OpcodeNumber] = {
|
||||
{reg_imm5, "srui"}, //0x00
|
||||
{reg_imm16_zeroextend, "nori"}, //0x01
|
||||
{reg_imm16_signextend, "muli"}, //0x02
|
||||
{reg_imm16_signextend, "sh"}, //0x03
|
||||
{reg_imm16_signextend, "lb"}, //0x04
|
||||
{reg_imm5, "sri"}, //0x05
|
||||
{reg_imm16_zeroextend, "xori"}, //0x06
|
||||
{reg_imm16_signextend, "lh"}, //0x07
|
||||
{reg_imm16_zeroextend, "andi"}, //0x08
|
||||
{reg_imm16_zeroextend, "xnori"}, //0x09
|
||||
{reg_imm16_signextend, "lw"}, //0x0a
|
||||
{reg_imm16_signextend, "lhu"}, //0x0b
|
||||
{reg_imm16_signextend, "sb"}, //0x0c
|
||||
{reg_imm16_signextend, "addi"}, //0x0d
|
||||
{reg_imm16_zeroextend, "ori"}, //0x0e
|
||||
{reg_imm5, "sli"}, //0x0f
|
||||
{reg_imm16_signextend, "lbu"}, //0x10
|
||||
{reg_imm16_shift2_signextend, "be"}, //0x11
|
||||
{reg_imm16_shift2_signextend, "bg"}, //0x12
|
||||
{reg_imm16_shift2_signextend, "bge"}, //0x13
|
||||
{reg_imm16_shift2_signextend, "bgeu"}, //0x14
|
||||
{reg_imm16_shift2_signextend, "bgu"}, //0x15
|
||||
{reg_imm16_signextend, "sw"}, //0x16
|
||||
{reg_imm16_shift2_signextend, "bne"}, //0x17
|
||||
{reg_imm16_zeroextend, "andhi"}, //0x18
|
||||
{reg_imm16_signextend, "cmpei"}, //0x19
|
||||
{reg_imm16_signextend, "cmpgi"}, //0x1a
|
||||
{reg_imm16_signextend, "cmpgei"}, //0x1b
|
||||
{reg_imm16_zeroextend, "cmpgeui"}, //0x1c
|
||||
{reg_imm16_zeroextend, "cmpgui"}, //0x1d
|
||||
{reg_imm16_zeroextend, "orhi"}, //0x1e
|
||||
{reg_imm16_signextend, "cmpnei"}, //0x1f
|
||||
{three_regs, "sru"}, //0x20
|
||||
{three_regs, "nor"}, //0x21
|
||||
{three_regs, "mul"}, //0x22
|
||||
{three_regs, "divu"}, //0x23
|
||||
{csr_reg, "rcsr"}, //0x24
|
||||
{three_regs, "sr"}, //0x25
|
||||
{three_regs, "xor"}, //0x26
|
||||
{three_regs, "div"}, //0x27
|
||||
{three_regs, "and"}, //0x28
|
||||
{three_regs, "xnor"}, //0x29
|
||||
{reserved, "reserved"}, //0x2a
|
||||
{raise_instr, "raise"}, //0x2b (break, scall)
|
||||
{two_regs, "sextb"}, //0x2c
|
||||
{three_regs, "add"}, //0x2d
|
||||
{three_regs, "or"}, //0x2e
|
||||
{three_regs, "sl"}, //0x2f
|
||||
{one_reg, "b"}, //0x30
|
||||
{three_regs, "modu"}, //0x31
|
||||
{three_regs, "sub"}, //0x32
|
||||
{reserved, "reserved"}, //0x33
|
||||
{reg_csr, "wcsr"}, //0x34
|
||||
{three_regs, "mod"}, //0x35
|
||||
{one_reg, "call"}, //0x36
|
||||
{two_regs, "sexth"}, //0x37
|
||||
{imm26, "bi"}, //0x38
|
||||
{three_regs, "cmpe"}, //0x39
|
||||
{three_regs, "cmpg"}, //0x3a
|
||||
{three_regs, "cmpge"}, //0x3b
|
||||
{three_regs, "cmpgeu"}, //0x3c
|
||||
{three_regs, "cmpgu"}, //0x3d
|
||||
{imm26, "calli"}, //0x3e
|
||||
{three_regs, "cmpne"}, //0x3f
|
||||
{reg_imm5, "srui" }, //0x00
|
||||
{reg_imm16_zeroextend, "nori" }, //0x01
|
||||
{reg_imm16_signextend, "muli" }, //0x02
|
||||
{reg_imm16_signextend, "sh" }, //0x03
|
||||
{reg_imm16_signextend, "lb" }, //0x04
|
||||
{reg_imm5, "sri" }, //0x05
|
||||
{reg_imm16_zeroextend, "xori" }, //0x06
|
||||
{reg_imm16_signextend, "lh" }, //0x07
|
||||
{reg_imm16_zeroextend, "andi" }, //0x08
|
||||
{reg_imm16_zeroextend, "xnori" }, //0x09
|
||||
{reg_imm16_signextend, "lw" }, //0x0a
|
||||
{reg_imm16_signextend, "lhu" }, //0x0b
|
||||
{reg_imm16_signextend, "sb" }, //0x0c
|
||||
{reg_imm16_signextend, "addi" }, //0x0d
|
||||
{reg_imm16_zeroextend, "ori" }, //0x0e
|
||||
{reg_imm5, "sli" }, //0x0f
|
||||
{reg_imm16_signextend, "lbu" }, //0x10
|
||||
{reg_imm16_shift2_signextend, "be" }, //0x11
|
||||
{reg_imm16_shift2_signextend, "bg" }, //0x12
|
||||
{reg_imm16_shift2_signextend, "bge" }, //0x13
|
||||
{reg_imm16_shift2_signextend, "bgeu" }, //0x14
|
||||
{reg_imm16_shift2_signextend, "bgu" }, //0x15
|
||||
{reg_imm16_signextend, "sw" }, //0x16
|
||||
{reg_imm16_shift2_signextend, "bne" }, //0x17
|
||||
{reg_imm16_zeroextend, "andhi" }, //0x18
|
||||
{reg_imm16_signextend, "cmpei" }, //0x19
|
||||
{reg_imm16_signextend, "cmpgi" }, //0x1a
|
||||
{reg_imm16_signextend, "cmpgei" }, //0x1b
|
||||
{reg_imm16_zeroextend, "cmpgeui" }, //0x1c
|
||||
{reg_imm16_zeroextend, "cmpgui" }, //0x1d
|
||||
{reg_imm16_zeroextend, "orhi" }, //0x1e
|
||||
{reg_imm16_signextend, "cmpnei" }, //0x1f
|
||||
{three_regs, "sru" }, //0x20
|
||||
{three_regs, "nor" }, //0x21
|
||||
{three_regs, "mul" }, //0x22
|
||||
{three_regs, "divu" }, //0x23
|
||||
{csr_reg, "rcsr" }, //0x24
|
||||
{three_regs, "sr" }, //0x25
|
||||
{three_regs, "xor" }, //0x26
|
||||
{three_regs, "div" }, //0x27
|
||||
{three_regs, "and" }, //0x28
|
||||
{three_regs, "xnor" }, //0x29
|
||||
{reserved, "reserved" }, //0x2a
|
||||
{raise_instr, "raise" }, //0x2b (break, scall)
|
||||
{two_regs, "sextb" }, //0x2c
|
||||
{three_regs, "add" }, //0x2d
|
||||
{three_regs, "or" }, //0x2e
|
||||
{three_regs, "sl" }, //0x2f
|
||||
{one_reg, "b" }, //0x30
|
||||
{three_regs, "modu" }, //0x31
|
||||
{three_regs, "sub" }, //0x32
|
||||
{reserved, "reserved" }, //0x33
|
||||
{reg_csr, "wcsr" }, //0x34
|
||||
{three_regs, "mod" }, //0x35
|
||||
{one_reg, "call" }, //0x36
|
||||
{two_regs, "sexth" }, //0x37
|
||||
{imm26, "bi" }, //0x38
|
||||
{three_regs, "cmpe" }, //0x39
|
||||
{three_regs, "cmpg" }, //0x3a
|
||||
{three_regs, "cmpge" }, //0x3b
|
||||
{three_regs, "cmpgeu" }, //0x3c
|
||||
{three_regs, "cmpgu" }, //0x3d
|
||||
{imm26, "calli" }, //0x3e
|
||||
{three_regs, "cmpne" }, //0x3f
|
||||
};
|
||||
|
||||
typedef struct r_asm_lm32_instruction {
|
||||
|
|
|
|||
|
|
@ -26,263 +26,263 @@ typedef struct mcs96_op_t {
|
|||
|
||||
|
||||
static const Mcs96Op mcs96_op[] = {
|
||||
{"skip", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"shr", MCS96_3B},
|
||||
{"shl", MCS96_3B},
|
||||
{"shra", MCS96_3B}, //0x0a
|
||||
{"invalid", MCS96_1B},
|
||||
{"shrl", MCS96_3B},
|
||||
{"shll", MCS96_3B},
|
||||
{"shral", MCS96_3B},
|
||||
{"norml", MCS96_3B},
|
||||
{"invalid", MCS96_1B}, //0x10
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"shrb", MCS96_3B},
|
||||
{"shlb", MCS96_3B},
|
||||
{"shrab", MCS96_3B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"sjmp", MCS96_2B}, //0x20
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"sjmp", MCS96_2B},
|
||||
{"scall", MCS96_2B}, //0x28
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"scall", MCS96_2B},
|
||||
{"jbc", MCS96_3B}, //0x30
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbc", MCS96_3B},
|
||||
{"jbs", MCS96_3B}, //0x38
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"jbs", MCS96_3B},
|
||||
{"and", MCS96_4B|MCS96_3OP}, //0x40
|
||||
{"and", MCS96_5B|MCS96_3OP},
|
||||
{"and", MCS96_4B|MCS96_3OP},
|
||||
{"and", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{"add", MCS96_4B|MCS96_3OP},
|
||||
{"add", MCS96_5B|MCS96_3OP},
|
||||
{"add", MCS96_4B|MCS96_3OP},
|
||||
{"add", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{"sub", MCS96_4B|MCS96_3OP},
|
||||
{"sub", MCS96_5B|MCS96_3OP},
|
||||
{"sub", MCS96_4B|MCS96_3OP},
|
||||
{"sub", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{"mulu", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{"mulu", MCS96_5B|MCS96_3OP|MCS96_FE},
|
||||
{"mulu", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{"mulu", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x4f
|
||||
{"andb", MCS96_4B|MCS96_3OP|MCS96_REG_8},
|
||||
{"andb", MCS96_4B|MCS96_3OP},
|
||||
{"andb", MCS96_4B|MCS96_3OP},
|
||||
{"andb", MCS96_5B_OR_6B|MCS96_3OP}, //datasheet says that this is always 5 byte
|
||||
{ "skip", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "shr", MCS96_3B},
|
||||
{ "shl", MCS96_3B},
|
||||
{ "shra", MCS96_3B}, //0x0a
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "shrl", MCS96_3B},
|
||||
{ "shll", MCS96_3B},
|
||||
{ "shral", MCS96_3B},
|
||||
{ "norml", MCS96_3B},
|
||||
{ "invalid", MCS96_1B}, //0x10
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "shrb", MCS96_3B},
|
||||
{ "shlb", MCS96_3B},
|
||||
{ "shrab", MCS96_3B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "sjmp", MCS96_2B}, //0x20
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "sjmp", MCS96_2B},
|
||||
{ "scall", MCS96_2B}, //0x28
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "scall", MCS96_2B},
|
||||
{ "jbc", MCS96_3B}, //0x30
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbc", MCS96_3B},
|
||||
{ "jbs", MCS96_3B}, //0x38
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "jbs", MCS96_3B},
|
||||
{ "and", MCS96_4B|MCS96_3OP}, //0x40
|
||||
{ "and", MCS96_5B|MCS96_3OP},
|
||||
{ "and", MCS96_4B|MCS96_3OP},
|
||||
{ "and", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{ "add", MCS96_4B|MCS96_3OP},
|
||||
{ "add", MCS96_5B|MCS96_3OP},
|
||||
{ "add", MCS96_4B|MCS96_3OP},
|
||||
{ "add", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{ "sub", MCS96_4B|MCS96_3OP},
|
||||
{ "sub", MCS96_5B|MCS96_3OP},
|
||||
{ "sub", MCS96_4B|MCS96_3OP},
|
||||
{ "sub", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{ "mulu", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulu", MCS96_5B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulu", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulu", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x4f
|
||||
{ "andb", MCS96_4B|MCS96_3OP|MCS96_REG_8},
|
||||
{ "andb", MCS96_4B|MCS96_3OP},
|
||||
{ "andb", MCS96_4B|MCS96_3OP},
|
||||
{ "andb", MCS96_5B_OR_6B|MCS96_3OP}, //datasheet says that this is always 5 byte
|
||||
//that datasheet already has proven to have typos
|
||||
{"addb", MCS96_4B|MCS96_3OP},
|
||||
{"addb", MCS96_4B|MCS96_3OP},
|
||||
{"addb", MCS96_4B|MCS96_3OP},
|
||||
{"addb", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{"subb", MCS96_4B|MCS96_3OP},
|
||||
{"subb", MCS96_4B|MCS96_3OP},
|
||||
{"subb", MCS96_4B|MCS96_3OP},
|
||||
{"subb", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{"mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{"mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{"mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{"mulub", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x5f
|
||||
{"and", MCS96_3B|MCS96_2OP},
|
||||
{"and", MCS96_4B|MCS96_2OP},
|
||||
{"and", MCS96_3B|MCS96_2OP},
|
||||
{"and", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"add", MCS96_3B|MCS96_2OP},
|
||||
{"add", MCS96_4B|MCS96_2OP},
|
||||
{"add", MCS96_3B|MCS96_2OP},
|
||||
{"add", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"sub", MCS96_3B|MCS96_2OP},
|
||||
{"sub", MCS96_4B|MCS96_2OP},
|
||||
{"sub", MCS96_3B|MCS96_2OP},
|
||||
{"sub", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"mulu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"mulu", MCS96_4B|MCS96_2OP|MCS96_FE},
|
||||
{"mulu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"mulu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x6f
|
||||
{"andb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"andb", MCS96_3B|MCS96_2OP},
|
||||
{"andb", MCS96_3B|MCS96_2OP},
|
||||
{"andb", MCS96_4B_OR_5B|MCS96_2OP}, //again i don't trust the data-sheet here
|
||||
{"addb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"addb", MCS96_3B|MCS96_2OP},
|
||||
{"addb", MCS96_3B|MCS96_2OP},
|
||||
{"addb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"subb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"subb", MCS96_3B|MCS96_2OP},
|
||||
{"subb", MCS96_3B|MCS96_2OP},
|
||||
{"subb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"mulub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8},
|
||||
{"mulub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"mulub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"mulub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x7f
|
||||
{"or", MCS96_3B|MCS96_2OP},
|
||||
{"or", MCS96_4B|MCS96_2OP},
|
||||
{"or", MCS96_3B|MCS96_2OP},
|
||||
{"or", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"xor", MCS96_3B|MCS96_2OP},
|
||||
{"xor", MCS96_4B|MCS96_2OP},
|
||||
{"xor", MCS96_3B|MCS96_2OP},
|
||||
{"xor", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"cmp", MCS96_3B|MCS96_2OP},
|
||||
{"cmp", MCS96_4B|MCS96_2OP},
|
||||
{"cmp", MCS96_3B|MCS96_2OP},
|
||||
{"cmp", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"divu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"divu", MCS96_4B|MCS96_2OP|MCS96_FE},
|
||||
{"divu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"divu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x8f
|
||||
{"orb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"orb", MCS96_3B|MCS96_2OP},
|
||||
{"orb", MCS96_3B|MCS96_2OP},
|
||||
{"orb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"xorb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"xorb", MCS96_3B|MCS96_2OP},
|
||||
{"xorb", MCS96_3B|MCS96_2OP},
|
||||
{"xorb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"cmpb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"cmpb", MCS96_3B|MCS96_2OP},
|
||||
{"cmpb", MCS96_3B|MCS96_2OP},
|
||||
{"cmpb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"divub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8},
|
||||
{"divub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"divub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{"divub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x9f
|
||||
{"ld", MCS96_3B|MCS96_2OP},
|
||||
{"ld", MCS96_4B|MCS96_2OP},
|
||||
{"ld", MCS96_3B|MCS96_2OP},
|
||||
{"ld", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"addc", MCS96_3B|MCS96_2OP},
|
||||
{"addc", MCS96_4B|MCS96_2OP},
|
||||
{"addc", MCS96_3B|MCS96_2OP},
|
||||
{"addc", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"subc", MCS96_3B|MCS96_2OP},
|
||||
{"subc", MCS96_4B|MCS96_2OP},
|
||||
{"subc", MCS96_3B|MCS96_2OP},
|
||||
{"subc", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"lbsze", MCS96_3B|MCS96_2OP},
|
||||
{"lbsze", MCS96_3B|MCS96_2OP},
|
||||
{"lbsze", MCS96_3B|MCS96_2OP},
|
||||
{"lbsze", MCS96_4B_OR_5B|MCS96_2OP}, //0xaf
|
||||
{"ldb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"ldb", MCS96_3B|MCS96_2OP},
|
||||
{"ldb", MCS96_3B|MCS96_2OP},
|
||||
{"ldb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"addcb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"addcb", MCS96_3B|MCS96_2OP},
|
||||
{"addcb", MCS96_3B|MCS96_2OP},
|
||||
{"addcb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"subcb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"subcb", MCS96_3B|MCS96_2OP},
|
||||
{"subcb", MCS96_3B|MCS96_2OP},
|
||||
{"subcb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"ldbse", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{"ldbse", MCS96_3B|MCS96_2OP},
|
||||
{"ldbse", MCS96_3B|MCS96_2OP},
|
||||
{"ldbse", MCS96_4B_OR_5B|MCS96_2OP}, //0xbf
|
||||
{"st", MCS96_3B|MCS96_2OP},
|
||||
{"invalid", MCS96_1B},
|
||||
{"st", MCS96_3B|MCS96_2OP},
|
||||
{"st", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"stb", MCS96_3B|MCS96_2OP},
|
||||
{"invalid", MCS96_1B},
|
||||
{"stb", MCS96_3B|MCS96_2OP},
|
||||
{"stb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{"push", MCS96_2B},
|
||||
{"push", MCS96_3B},
|
||||
{"push", MCS96_2B},
|
||||
{"push", MCS96_3B_OR_4B},
|
||||
{"pop", MCS96_2B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"pop", MCS96_2B},
|
||||
{"pop", MCS96_3B_OR_4B}, //0xcf
|
||||
{"jnst", MCS96_2B},
|
||||
{"jnh", MCS96_2B},
|
||||
{"jgt", MCS96_2B},
|
||||
{"jnc", MCS96_2B},
|
||||
{"jnvt", MCS96_2B},
|
||||
{"jnv", MCS96_2B},
|
||||
{"jge", MCS96_2B},
|
||||
{"jne", MCS96_2B},
|
||||
{"jst", MCS96_2B},
|
||||
{"jh", MCS96_2B},
|
||||
{"jle", MCS96_2B},
|
||||
{"jc", MCS96_2B},
|
||||
{"jvt", MCS96_2B},
|
||||
{"jv", MCS96_2B},
|
||||
{"jlt", MCS96_2B},
|
||||
{"je", MCS96_2B}, //0xdf
|
||||
{"djnz", MCS96_3B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"br", MCS96_2B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"ljmp", MCS96_3B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"lcall", MCS96_3B}, //0xef
|
||||
{"ret", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"pushf", MCS96_1B},
|
||||
{"popf", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"trap", MCS96_1B},
|
||||
{"clrc", MCS96_1B},
|
||||
{"setc", MCS96_1B},
|
||||
{"di", MCS96_1B},
|
||||
{"ei", MCS96_1B},
|
||||
{"clrvt", MCS96_1B},
|
||||
{"nop", MCS96_1B},
|
||||
{"invalid", MCS96_1B},
|
||||
{"rst", MCS96_1B}
|
||||
{ "addb", MCS96_4B|MCS96_3OP},
|
||||
{ "addb", MCS96_4B|MCS96_3OP},
|
||||
{ "addb", MCS96_4B|MCS96_3OP},
|
||||
{ "addb", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{ "subb", MCS96_4B|MCS96_3OP},
|
||||
{ "subb", MCS96_4B|MCS96_3OP},
|
||||
{ "subb", MCS96_4B|MCS96_3OP},
|
||||
{ "subb", MCS96_5B_OR_6B|MCS96_3OP},
|
||||
{ "mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulub", MCS96_4B|MCS96_3OP|MCS96_FE},
|
||||
{ "mulub", MCS96_5B_OR_6B|MCS96_3OP|MCS96_FE}, //0x5f
|
||||
{ "and", MCS96_3B|MCS96_2OP},
|
||||
{ "and", MCS96_4B|MCS96_2OP},
|
||||
{ "and", MCS96_3B|MCS96_2OP},
|
||||
{ "and", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "add", MCS96_3B|MCS96_2OP},
|
||||
{ "add", MCS96_4B|MCS96_2OP},
|
||||
{ "add", MCS96_3B|MCS96_2OP},
|
||||
{ "add", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "sub", MCS96_3B|MCS96_2OP},
|
||||
{ "sub", MCS96_4B|MCS96_2OP},
|
||||
{ "sub", MCS96_3B|MCS96_2OP},
|
||||
{ "sub", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "mulu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "mulu", MCS96_4B|MCS96_2OP|MCS96_FE},
|
||||
{ "mulu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "mulu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x6f
|
||||
{ "andb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "andb", MCS96_3B|MCS96_2OP},
|
||||
{ "andb", MCS96_3B|MCS96_2OP},
|
||||
{ "andb", MCS96_4B_OR_5B|MCS96_2OP}, //again i don't trust the data-sheet here
|
||||
{ "addb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "addb", MCS96_3B|MCS96_2OP},
|
||||
{ "addb", MCS96_3B|MCS96_2OP},
|
||||
{ "addb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "subb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "subb", MCS96_3B|MCS96_2OP},
|
||||
{ "subb", MCS96_3B|MCS96_2OP},
|
||||
{ "subb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "mulub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8},
|
||||
{ "mulub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "mulub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "mulub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x7f
|
||||
{ "or", MCS96_3B|MCS96_2OP},
|
||||
{ "or", MCS96_4B|MCS96_2OP},
|
||||
{ "or", MCS96_3B|MCS96_2OP},
|
||||
{ "or", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "xor", MCS96_3B|MCS96_2OP},
|
||||
{ "xor", MCS96_4B|MCS96_2OP},
|
||||
{ "xor", MCS96_3B|MCS96_2OP},
|
||||
{ "xor", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "cmp", MCS96_3B|MCS96_2OP},
|
||||
{ "cmp", MCS96_4B|MCS96_2OP},
|
||||
{ "cmp", MCS96_3B|MCS96_2OP},
|
||||
{ "cmp", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "divu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "divu", MCS96_4B|MCS96_2OP|MCS96_FE},
|
||||
{ "divu", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "divu", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x8f
|
||||
{ "orb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "orb", MCS96_3B|MCS96_2OP},
|
||||
{ "orb", MCS96_3B|MCS96_2OP},
|
||||
{ "orb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "xorb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "xorb", MCS96_3B|MCS96_2OP},
|
||||
{ "xorb", MCS96_3B|MCS96_2OP},
|
||||
{ "xorb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "cmpb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "cmpb", MCS96_3B|MCS96_2OP},
|
||||
{ "cmpb", MCS96_3B|MCS96_2OP},
|
||||
{ "cmpb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "divub", MCS96_3B|MCS96_2OP|MCS96_FE|MCS96_REG_8},
|
||||
{ "divub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "divub", MCS96_3B|MCS96_2OP|MCS96_FE},
|
||||
{ "divub", MCS96_4B_OR_5B|MCS96_2OP|MCS96_FE}, //0x9f
|
||||
{ "ld", MCS96_3B|MCS96_2OP},
|
||||
{ "ld", MCS96_4B|MCS96_2OP},
|
||||
{ "ld", MCS96_3B|MCS96_2OP},
|
||||
{ "ld", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "addc", MCS96_3B|MCS96_2OP},
|
||||
{ "addc", MCS96_4B|MCS96_2OP},
|
||||
{ "addc", MCS96_3B|MCS96_2OP},
|
||||
{ "addc", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "subc", MCS96_3B|MCS96_2OP},
|
||||
{ "subc", MCS96_4B|MCS96_2OP},
|
||||
{ "subc", MCS96_3B|MCS96_2OP},
|
||||
{ "subc", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "lbsze", MCS96_3B|MCS96_2OP},
|
||||
{ "lbsze", MCS96_3B|MCS96_2OP},
|
||||
{ "lbsze", MCS96_3B|MCS96_2OP},
|
||||
{ "lbsze", MCS96_4B_OR_5B|MCS96_2OP}, //0xaf
|
||||
{ "ldb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "ldb", MCS96_3B|MCS96_2OP},
|
||||
{ "ldb", MCS96_3B|MCS96_2OP},
|
||||
{ "ldb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "addcb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "addcb", MCS96_3B|MCS96_2OP},
|
||||
{ "addcb", MCS96_3B|MCS96_2OP},
|
||||
{ "addcb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "subcb", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "subcb", MCS96_3B|MCS96_2OP},
|
||||
{ "subcb", MCS96_3B|MCS96_2OP},
|
||||
{ "subcb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "ldbse", MCS96_3B|MCS96_2OP|MCS96_REG_8},
|
||||
{ "ldbse", MCS96_3B|MCS96_2OP},
|
||||
{ "ldbse", MCS96_3B|MCS96_2OP},
|
||||
{ "ldbse", MCS96_4B_OR_5B|MCS96_2OP}, //0xbf
|
||||
{ "st", MCS96_3B|MCS96_2OP},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "st", MCS96_3B|MCS96_2OP},
|
||||
{ "st", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "stb", MCS96_3B|MCS96_2OP},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "stb", MCS96_3B|MCS96_2OP},
|
||||
{ "stb", MCS96_4B_OR_5B|MCS96_2OP},
|
||||
{ "push", MCS96_2B},
|
||||
{ "push", MCS96_3B},
|
||||
{ "push", MCS96_2B},
|
||||
{ "push", MCS96_3B_OR_4B},
|
||||
{ "pop", MCS96_2B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "pop", MCS96_2B},
|
||||
{ "pop", MCS96_3B_OR_4B}, //0xcf
|
||||
{ "jnst", MCS96_2B},
|
||||
{ "jnh", MCS96_2B},
|
||||
{ "jgt", MCS96_2B},
|
||||
{ "jnc", MCS96_2B},
|
||||
{ "jnvt", MCS96_2B},
|
||||
{ "jnv", MCS96_2B},
|
||||
{ "jge", MCS96_2B},
|
||||
{ "jne", MCS96_2B},
|
||||
{ "jst", MCS96_2B},
|
||||
{ "jh", MCS96_2B},
|
||||
{ "jle", MCS96_2B},
|
||||
{ "jc", MCS96_2B},
|
||||
{ "jvt", MCS96_2B},
|
||||
{ "jv", MCS96_2B},
|
||||
{ "jlt", MCS96_2B},
|
||||
{ "je", MCS96_2B}, //0xdf
|
||||
{ "djnz", MCS96_3B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "br", MCS96_2B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "ljmp", MCS96_3B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "lcall", MCS96_3B}, //0xef
|
||||
{ "ret", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "pushf", MCS96_1B},
|
||||
{ "popf", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "trap", MCS96_1B},
|
||||
{ "clrc", MCS96_1B},
|
||||
{ "setc", MCS96_1B},
|
||||
{ "di", MCS96_1B},
|
||||
{ "ei", MCS96_1B},
|
||||
{ "clrvt", MCS96_1B},
|
||||
{ "nop", MCS96_1B},
|
||||
{ "invalid", MCS96_1B},
|
||||
{ "rst", MCS96_1B}
|
||||
};
|
||||
|
||||
static const char * const mcs96_fe_op[] = { "mul", "mulb", "mul", "mulb", "div", "divb", "invalid", "invalid" };
|
||||
|
|
|
|||
|
|
@ -30,262 +30,262 @@ static int snes_op_get_size(int M_flag, int X_flag, snes_op_t* op) {
|
|||
}
|
||||
|
||||
static snes_op_t snes_op[]={
|
||||
{"brk 0x%02x", SNES_OP_16BIT},
|
||||
{"ora (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"cop 0x%02x", SNES_OP_16BIT},
|
||||
{"ora 0x%02x,s", SNES_OP_16BIT},
|
||||
{"tsb 0x%02x", SNES_OP_16BIT},
|
||||
{"ora 0x%02x", SNES_OP_16BIT},
|
||||
{"asl 0x%02x", SNES_OP_16BIT},
|
||||
{"ora [0x%02x]", SNES_OP_16BIT},
|
||||
{"php", SNES_OP_8BIT},
|
||||
{"ora", SNES_OP_IMM_M},
|
||||
{"asl a", SNES_OP_8BIT},
|
||||
{"phd", SNES_OP_8BIT},
|
||||
{"tsb 0x%04x", SNES_OP_24BIT},
|
||||
{"ora 0x%04x", SNES_OP_24BIT},
|
||||
{"asl 0x%04x", SNES_OP_24BIT},
|
||||
{"ora 0x%06x", SNES_OP_32BIT},
|
||||
{"bpl 0x%06x", SNES_OP_16BIT},
|
||||
{"ora (0x%02x),y", SNES_OP_16BIT},
|
||||
{"ora (0x%02x)", SNES_OP_16BIT},
|
||||
{"ora (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"trb 0x%02x", SNES_OP_16BIT},
|
||||
{"ora 0x%02x,x", SNES_OP_16BIT},
|
||||
{"asl 0x%02x,x", SNES_OP_16BIT},
|
||||
{"ora [0x%02x],y", SNES_OP_16BIT},
|
||||
{"clc", SNES_OP_8BIT},
|
||||
{"ora 0x%04x,y", SNES_OP_24BIT},
|
||||
{"inc a", SNES_OP_8BIT},
|
||||
{"tas", SNES_OP_8BIT},
|
||||
{"trb 0x%04x", SNES_OP_24BIT},
|
||||
{"ora 0x%04x,x", SNES_OP_24BIT},
|
||||
{"asl 0x%04x,x", SNES_OP_24BIT},
|
||||
{"ora 0x%06x,x", SNES_OP_32BIT},
|
||||
{"jsr 0x%04x", SNES_OP_24BIT},
|
||||
{"and (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"jsr 0x%06x", SNES_OP_32BIT},
|
||||
{"and 0x%02x,s", SNES_OP_16BIT},
|
||||
{"bit 0x%02x", SNES_OP_16BIT},
|
||||
{"and 0x%02x", SNES_OP_16BIT},
|
||||
{"rol 0x%02x", SNES_OP_16BIT},
|
||||
{"and [0x%02x]", SNES_OP_16BIT},
|
||||
{"plp", SNES_OP_8BIT},
|
||||
{"and", SNES_OP_IMM_M},
|
||||
{"rol a", SNES_OP_8BIT},
|
||||
{"pld", SNES_OP_8BIT},
|
||||
{"bit 0x%04x", SNES_OP_24BIT},
|
||||
{"and 0x%04x", SNES_OP_24BIT},
|
||||
{"rol 0x%04x", SNES_OP_24BIT},
|
||||
{"and 0x%06x", SNES_OP_32BIT},
|
||||
{"bmi 0x%06x", SNES_OP_16BIT},
|
||||
{"and (0x%02x),y", SNES_OP_16BIT},
|
||||
{"and (0x%02x)", SNES_OP_16BIT},
|
||||
{"and (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"bit 0x%02x,x", SNES_OP_16BIT},
|
||||
{"and 0x%02x,x", SNES_OP_16BIT},
|
||||
{"rol 0x%02x,x", SNES_OP_16BIT},
|
||||
{"and [0x%02x],y", SNES_OP_16BIT},
|
||||
{"sec", SNES_OP_8BIT},
|
||||
{"and 0x%04x,y", SNES_OP_24BIT},
|
||||
{"dec a", SNES_OP_8BIT},
|
||||
{"tsa", SNES_OP_8BIT},
|
||||
{"bit 0x%04x,x", SNES_OP_24BIT},
|
||||
{"and 0x%04x,x", SNES_OP_24BIT},
|
||||
{"rol 0x%04x,x", SNES_OP_24BIT},
|
||||
{"and 0x%06x,x", SNES_OP_32BIT},
|
||||
{"rti", SNES_OP_8BIT},
|
||||
{"eor (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"wdm 0x%02X", SNES_OP_16BIT},
|
||||
{"eor 0x%02x,s", SNES_OP_16BIT},
|
||||
{"mvp 0x%02x,0x%02x", SNES_OP_24BIT},
|
||||
{"eor 0x%02x", SNES_OP_16BIT},
|
||||
{"lsr 0x%02x", SNES_OP_16BIT},
|
||||
{"eor [0x%02x]", SNES_OP_16BIT},
|
||||
{"pha", SNES_OP_8BIT},
|
||||
{"eor", SNES_OP_IMM_M},
|
||||
{"lsr a", SNES_OP_8BIT},
|
||||
{"phk", SNES_OP_8BIT},
|
||||
{"jmp 0x%04x", SNES_OP_24BIT},
|
||||
{"eor 0x%04x", SNES_OP_24BIT},
|
||||
{"lsr 0x%04x", SNES_OP_24BIT},
|
||||
{"eor 0x%06x", SNES_OP_32BIT},
|
||||
{"bvc 0x%06x", SNES_OP_16BIT},
|
||||
{"eor (0x%02x),y", SNES_OP_16BIT},
|
||||
{"eor (0x%02x)", SNES_OP_16BIT},
|
||||
{"eor (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"mvn 0x%02x,0x%02x", SNES_OP_16BIT},
|
||||
{"eor 0x%02x,x", SNES_OP_16BIT},
|
||||
{"lsr 0x%02x,x", SNES_OP_16BIT},
|
||||
{"eor [0x%02x],y", SNES_OP_16BIT},
|
||||
{"cli", SNES_OP_8BIT},
|
||||
{"eor 0x%04x,y", SNES_OP_24BIT},
|
||||
{"phy", SNES_OP_8BIT},
|
||||
{"tad", SNES_OP_8BIT},
|
||||
{"jmp 0x%06x", SNES_OP_32BIT},
|
||||
{"eor 0x%04x,x", SNES_OP_24BIT},
|
||||
{"lsr 0x%04x,x", SNES_OP_24BIT},
|
||||
{"eor 0x%06x,x", SNES_OP_32BIT},
|
||||
{"rts", SNES_OP_8BIT},
|
||||
{"adc (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"per 0x%04x", SNES_OP_24BIT},
|
||||
{"adc 0x%02x,s", SNES_OP_16BIT},
|
||||
{"stz 0x%02x", SNES_OP_16BIT},
|
||||
{"adc 0x%02x", SNES_OP_16BIT},
|
||||
{"ror 0x%02x", SNES_OP_16BIT},
|
||||
{"adc [0x%02x]", SNES_OP_16BIT},
|
||||
{"pla", SNES_OP_8BIT},
|
||||
{"adc", SNES_OP_IMM_M},
|
||||
{"ror a", SNES_OP_8BIT},
|
||||
{"rtl", SNES_OP_8BIT},
|
||||
{"jmp (0x%04x)", SNES_OP_24BIT},
|
||||
{"adc 0x%04x", SNES_OP_24BIT},
|
||||
{"ror 0x%04x", SNES_OP_24BIT},
|
||||
{"adc 0x%06x", SNES_OP_32BIT},
|
||||
{"bvs 0x%06x", SNES_OP_16BIT},
|
||||
{"adc (0x%02x),y", SNES_OP_16BIT},
|
||||
{"adc (0x%02x)", SNES_OP_16BIT},
|
||||
{"adc (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"stz 0x%02x,x", SNES_OP_16BIT},
|
||||
{"adc 0x%02x,x", SNES_OP_16BIT},
|
||||
{"ror 0x%02x,x", SNES_OP_16BIT},
|
||||
{"adc [0x%02x],y", SNES_OP_16BIT},
|
||||
{"sei", SNES_OP_8BIT},
|
||||
{"adc 0x%04x,y", SNES_OP_24BIT},
|
||||
{"ply", SNES_OP_8BIT},
|
||||
{"tda", SNES_OP_8BIT},
|
||||
{"jmp (0x%04x,x)", SNES_OP_24BIT},
|
||||
{"adc 0x%04x,x", SNES_OP_24BIT},
|
||||
{"ror 0x%04x,x", SNES_OP_24BIT},
|
||||
{"adc 0x%06x,x", SNES_OP_32BIT},
|
||||
{"bra 0x%06x", SNES_OP_16BIT},
|
||||
{"sta (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"brl 0x%06x", SNES_OP_24BIT},
|
||||
{"sta 0x%02x,s", SNES_OP_16BIT},
|
||||
{"sty 0x%02x", SNES_OP_16BIT},
|
||||
{"sta 0x%02x", SNES_OP_16BIT},
|
||||
{"stx 0x%02x", SNES_OP_16BIT},
|
||||
{"sta [0x%02x]", SNES_OP_16BIT},
|
||||
{"dey", SNES_OP_8BIT},
|
||||
{"bit", SNES_OP_IMM_M},
|
||||
{"txa", SNES_OP_8BIT},
|
||||
{"phb", SNES_OP_8BIT},
|
||||
{"sty 0x%04x", SNES_OP_24BIT},
|
||||
{"sta 0x%04x", SNES_OP_24BIT},
|
||||
{"stx 0x%04x", SNES_OP_24BIT},
|
||||
{"sta 0x%06x", SNES_OP_32BIT},
|
||||
{"bcc 0x%06x", SNES_OP_16BIT},
|
||||
{"sta (0x%02x),y", SNES_OP_16BIT},
|
||||
{"sta (0x%02x)", SNES_OP_16BIT},
|
||||
{"sta (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"sty 0x%02x,x", SNES_OP_16BIT},
|
||||
{"sta 0x%02x,x", SNES_OP_16BIT},
|
||||
{"stx 0x%02x,y", SNES_OP_16BIT},
|
||||
{"sta [0x%02x],y", SNES_OP_16BIT},
|
||||
{"tya", SNES_OP_8BIT},
|
||||
{"sta 0x%04x,y", SNES_OP_24BIT},
|
||||
{"txs", SNES_OP_8BIT},
|
||||
{"txy", SNES_OP_8BIT},
|
||||
{"stz 0x%04x", SNES_OP_24BIT},
|
||||
{"sta 0x%04x,x", SNES_OP_24BIT},
|
||||
{"stz 0x%04x,x", SNES_OP_24BIT},
|
||||
{"sta 0x%06x,x", SNES_OP_32BIT},
|
||||
{"ldy", SNES_OP_IMM_X},
|
||||
{"lda (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"ldx", SNES_OP_IMM_X},
|
||||
{"lda 0x%02x,s", SNES_OP_16BIT},
|
||||
{"ldy 0x%02x", SNES_OP_16BIT},
|
||||
{"lda 0x%02x", SNES_OP_16BIT},
|
||||
{"ldx 0x%02x", SNES_OP_16BIT},
|
||||
{"lda [0x%02x]", SNES_OP_16BIT},
|
||||
{"tay", SNES_OP_8BIT},
|
||||
{"lda", SNES_OP_IMM_M},
|
||||
{"tax", SNES_OP_8BIT},
|
||||
{"plb", SNES_OP_8BIT},
|
||||
{"ldy 0x%04x", SNES_OP_24BIT},
|
||||
{"lda 0x%04x", SNES_OP_24BIT},
|
||||
{"ldx 0x%04x", SNES_OP_24BIT},
|
||||
{"lda 0x%06x", SNES_OP_32BIT},
|
||||
{"bcs 0x%06x", SNES_OP_16BIT},
|
||||
{"lda (0x%02x),y", SNES_OP_16BIT},
|
||||
{"lda (0x%02x)", SNES_OP_16BIT},
|
||||
{"lda (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"ldy 0x%02x,x", SNES_OP_16BIT},
|
||||
{"lda 0x%02x,x", SNES_OP_16BIT},
|
||||
{"ldx 0x%02x,y", SNES_OP_16BIT},
|
||||
{"lda [0x%02x],y", SNES_OP_16BIT},
|
||||
{"clv", SNES_OP_8BIT},
|
||||
{"lda 0x%04x,y", SNES_OP_24BIT},
|
||||
{"tsx", SNES_OP_8BIT},
|
||||
{"tyx", SNES_OP_8BIT},
|
||||
{"ldy 0x%04x,x", SNES_OP_24BIT},
|
||||
{"lda 0x%04x,x", SNES_OP_24BIT},
|
||||
{"ldx 0x%04x,y", SNES_OP_24BIT},
|
||||
{"lda 0x%06x,x", SNES_OP_32BIT},
|
||||
{"cpy", SNES_OP_IMM_X},
|
||||
{"cmp (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"rep #0x%02x", SNES_OP_16BIT},
|
||||
{"cmp 0x%02x,s", SNES_OP_16BIT},
|
||||
{"cpy 0x%02x", SNES_OP_16BIT},
|
||||
{"cmp 0x%02x", SNES_OP_16BIT},
|
||||
{"dec 0x%02x", SNES_OP_16BIT},
|
||||
{"cmp [0x%02x]", SNES_OP_16BIT},
|
||||
{"iny", SNES_OP_8BIT},
|
||||
{"cmp", SNES_OP_IMM_M},
|
||||
{"dex", SNES_OP_8BIT},
|
||||
{"wai", SNES_OP_8BIT},
|
||||
{"cpy 0x%04x", SNES_OP_24BIT},
|
||||
{"cmp 0x%04x", SNES_OP_24BIT},
|
||||
{"dec 0x%04x", SNES_OP_24BIT},
|
||||
{"cmp 0x%06x", SNES_OP_32BIT},
|
||||
{"bne 0x%06x", SNES_OP_16BIT},
|
||||
{"cmp (0x%02x),y", SNES_OP_16BIT},
|
||||
{"cmp (0x%02x)", SNES_OP_16BIT},
|
||||
{"cmp (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"pei (0x%02x)", SNES_OP_16BIT},
|
||||
{"cmp 0x%02x,x", SNES_OP_16BIT},
|
||||
{"dec 0x%02x,x", SNES_OP_16BIT},
|
||||
{"cmp [0x%02x],y", SNES_OP_16BIT},
|
||||
{"cld", SNES_OP_8BIT},
|
||||
{"cmp 0x%04x,y", SNES_OP_24BIT},
|
||||
{"phx", SNES_OP_8BIT},
|
||||
{"stp", SNES_OP_8BIT},
|
||||
{"jmp [0x%04x]", SNES_OP_24BIT},
|
||||
{"cmp 0x%04x,x", SNES_OP_24BIT},
|
||||
{"dec 0x%04x,x", SNES_OP_24BIT},
|
||||
{"cmp 0x%06x,x", SNES_OP_32BIT},
|
||||
{"cpx", SNES_OP_IMM_X},
|
||||
{"sbc (0x%02x,x)", SNES_OP_16BIT},
|
||||
{"sep #0x%02x", SNES_OP_16BIT},
|
||||
{"sbc 0x%02x,s", SNES_OP_16BIT},
|
||||
{"cpx 0x%02x", SNES_OP_16BIT},
|
||||
{"sbc 0x%02x", SNES_OP_16BIT},
|
||||
{"inc 0x%02x", SNES_OP_16BIT},
|
||||
{"sbc [0x%02x]", SNES_OP_16BIT},
|
||||
{"inx", SNES_OP_8BIT},
|
||||
{"sbc", SNES_OP_IMM_M},
|
||||
{"nop", SNES_OP_8BIT},
|
||||
{"swa", SNES_OP_8BIT},
|
||||
{"cpx 0x%04x", SNES_OP_24BIT},
|
||||
{"sbc 0x%04x", SNES_OP_24BIT},
|
||||
{"inc 0x%04x", SNES_OP_24BIT},
|
||||
{"sbc 0x%06x", SNES_OP_32BIT},
|
||||
{"beq 0x%06x", SNES_OP_16BIT},
|
||||
{"sbc (0x%02x),y", SNES_OP_16BIT},
|
||||
{"sbc (0x%02x)", SNES_OP_16BIT},
|
||||
{"sbc (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{"pea 0x%04x", SNES_OP_24BIT},
|
||||
{"sbc 0x%02x,x", SNES_OP_16BIT},
|
||||
{"inc 0x%02x,x", SNES_OP_16BIT},
|
||||
{"sbc [0x%02x],y", SNES_OP_16BIT},
|
||||
{"sed", SNES_OP_8BIT},
|
||||
{"sbc 0x%04x,y", SNES_OP_24BIT},
|
||||
{"plx", SNES_OP_8BIT},
|
||||
{"xce", SNES_OP_8BIT},
|
||||
{"jsr (0x%04x,x)", SNES_OP_24BIT},
|
||||
{"sbc 0x%04x,x", SNES_OP_24BIT},
|
||||
{"inc 0x%04x,x", SNES_OP_24BIT},
|
||||
{"sbc 0x%06x,x", SNES_OP_32BIT}
|
||||
{ "brk 0x%02x", SNES_OP_16BIT},
|
||||
{ "ora (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "cop 0x%02x", SNES_OP_16BIT},
|
||||
{ "ora 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "tsb 0x%02x", SNES_OP_16BIT},
|
||||
{ "ora 0x%02x", SNES_OP_16BIT},
|
||||
{ "asl 0x%02x", SNES_OP_16BIT},
|
||||
{ "ora [0x%02x]", SNES_OP_16BIT},
|
||||
{ "php", SNES_OP_8BIT},
|
||||
{ "ora", SNES_OP_IMM_M},
|
||||
{ "asl a", SNES_OP_8BIT},
|
||||
{ "phd", SNES_OP_8BIT},
|
||||
{ "tsb 0x%04x", SNES_OP_24BIT},
|
||||
{ "ora 0x%04x", SNES_OP_24BIT},
|
||||
{ "asl 0x%04x", SNES_OP_24BIT},
|
||||
{ "ora 0x%06x", SNES_OP_32BIT},
|
||||
{ "bpl 0x%06x", SNES_OP_16BIT},
|
||||
{ "ora (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "ora (0x%02x)", SNES_OP_16BIT},
|
||||
{ "ora (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "trb 0x%02x", SNES_OP_16BIT},
|
||||
{ "ora 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "asl 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "ora [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "clc", SNES_OP_8BIT},
|
||||
{ "ora 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "inc a", SNES_OP_8BIT},
|
||||
{ "tas", SNES_OP_8BIT},
|
||||
{ "trb 0x%04x", SNES_OP_24BIT},
|
||||
{ "ora 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "asl 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "ora 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "jsr 0x%04x", SNES_OP_24BIT},
|
||||
{ "and (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "jsr 0x%06x", SNES_OP_32BIT},
|
||||
{ "and 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "bit 0x%02x", SNES_OP_16BIT},
|
||||
{ "and 0x%02x", SNES_OP_16BIT},
|
||||
{ "rol 0x%02x", SNES_OP_16BIT},
|
||||
{ "and [0x%02x]", SNES_OP_16BIT},
|
||||
{ "plp", SNES_OP_8BIT},
|
||||
{ "and", SNES_OP_IMM_M},
|
||||
{ "rol a", SNES_OP_8BIT},
|
||||
{ "pld", SNES_OP_8BIT},
|
||||
{ "bit 0x%04x", SNES_OP_24BIT},
|
||||
{ "and 0x%04x", SNES_OP_24BIT},
|
||||
{ "rol 0x%04x", SNES_OP_24BIT},
|
||||
{ "and 0x%06x", SNES_OP_32BIT},
|
||||
{ "bmi 0x%06x", SNES_OP_16BIT},
|
||||
{ "and (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "and (0x%02x)", SNES_OP_16BIT},
|
||||
{ "and (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "bit 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "and 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "rol 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "and [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "sec", SNES_OP_8BIT},
|
||||
{ "and 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "dec a", SNES_OP_8BIT},
|
||||
{ "tsa", SNES_OP_8BIT},
|
||||
{ "bit 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "and 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "rol 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "and 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "rti", SNES_OP_8BIT},
|
||||
{ "eor (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "wdm 0x%02X", SNES_OP_16BIT},
|
||||
{ "eor 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "mvp 0x%02x,0x%02x", SNES_OP_24BIT},
|
||||
{ "eor 0x%02x", SNES_OP_16BIT},
|
||||
{ "lsr 0x%02x", SNES_OP_16BIT},
|
||||
{ "eor [0x%02x]", SNES_OP_16BIT},
|
||||
{ "pha", SNES_OP_8BIT},
|
||||
{ "eor", SNES_OP_IMM_M},
|
||||
{ "lsr a", SNES_OP_8BIT},
|
||||
{ "phk", SNES_OP_8BIT},
|
||||
{ "jmp 0x%04x", SNES_OP_24BIT},
|
||||
{ "eor 0x%04x", SNES_OP_24BIT},
|
||||
{ "lsr 0x%04x", SNES_OP_24BIT},
|
||||
{ "eor 0x%06x", SNES_OP_32BIT},
|
||||
{ "bvc 0x%06x", SNES_OP_16BIT},
|
||||
{ "eor (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "eor (0x%02x)", SNES_OP_16BIT},
|
||||
{ "eor (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "mvn 0x%02x,0x%02x", SNES_OP_16BIT},
|
||||
{ "eor 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "lsr 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "eor [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "cli", SNES_OP_8BIT},
|
||||
{ "eor 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "phy", SNES_OP_8BIT},
|
||||
{ "tad", SNES_OP_8BIT},
|
||||
{ "jmp 0x%06x", SNES_OP_32BIT},
|
||||
{ "eor 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "lsr 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "eor 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "rts", SNES_OP_8BIT},
|
||||
{ "adc (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "per 0x%04x", SNES_OP_24BIT},
|
||||
{ "adc 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "stz 0x%02x", SNES_OP_16BIT},
|
||||
{ "adc 0x%02x", SNES_OP_16BIT},
|
||||
{ "ror 0x%02x", SNES_OP_16BIT},
|
||||
{ "adc [0x%02x]", SNES_OP_16BIT},
|
||||
{ "pla", SNES_OP_8BIT},
|
||||
{ "adc", SNES_OP_IMM_M},
|
||||
{ "ror a", SNES_OP_8BIT},
|
||||
{ "rtl", SNES_OP_8BIT},
|
||||
{ "jmp (0x%04x)", SNES_OP_24BIT},
|
||||
{ "adc 0x%04x", SNES_OP_24BIT},
|
||||
{ "ror 0x%04x", SNES_OP_24BIT},
|
||||
{ "adc 0x%06x", SNES_OP_32BIT},
|
||||
{ "bvs 0x%06x", SNES_OP_16BIT},
|
||||
{ "adc (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "adc (0x%02x)", SNES_OP_16BIT},
|
||||
{ "adc (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "stz 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "adc 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "ror 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "adc [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "sei", SNES_OP_8BIT},
|
||||
{ "adc 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "ply", SNES_OP_8BIT},
|
||||
{ "tda", SNES_OP_8BIT},
|
||||
{ "jmp (0x%04x,x)", SNES_OP_24BIT},
|
||||
{ "adc 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "ror 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "adc 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "bra 0x%06x", SNES_OP_16BIT},
|
||||
{ "sta (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "brl 0x%06x", SNES_OP_24BIT},
|
||||
{ "sta 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "sty 0x%02x", SNES_OP_16BIT},
|
||||
{ "sta 0x%02x", SNES_OP_16BIT},
|
||||
{ "stx 0x%02x", SNES_OP_16BIT},
|
||||
{ "sta [0x%02x]", SNES_OP_16BIT},
|
||||
{ "dey", SNES_OP_8BIT},
|
||||
{ "bit", SNES_OP_IMM_M},
|
||||
{ "txa", SNES_OP_8BIT},
|
||||
{ "phb", SNES_OP_8BIT},
|
||||
{ "sty 0x%04x", SNES_OP_24BIT},
|
||||
{ "sta 0x%04x", SNES_OP_24BIT},
|
||||
{ "stx 0x%04x", SNES_OP_24BIT},
|
||||
{ "sta 0x%06x", SNES_OP_32BIT},
|
||||
{ "bcc 0x%06x", SNES_OP_16BIT},
|
||||
{ "sta (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "sta (0x%02x)", SNES_OP_16BIT},
|
||||
{ "sta (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "sty 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "sta 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "stx 0x%02x,y", SNES_OP_16BIT},
|
||||
{ "sta [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "tya", SNES_OP_8BIT},
|
||||
{ "sta 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "txs", SNES_OP_8BIT},
|
||||
{ "txy", SNES_OP_8BIT},
|
||||
{ "stz 0x%04x", SNES_OP_24BIT},
|
||||
{ "sta 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "stz 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "sta 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "ldy", SNES_OP_IMM_X},
|
||||
{ "lda (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "ldx", SNES_OP_IMM_X},
|
||||
{ "lda 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "ldy 0x%02x", SNES_OP_16BIT},
|
||||
{ "lda 0x%02x", SNES_OP_16BIT},
|
||||
{ "ldx 0x%02x", SNES_OP_16BIT},
|
||||
{ "lda [0x%02x]", SNES_OP_16BIT},
|
||||
{ "tay", SNES_OP_8BIT},
|
||||
{ "lda", SNES_OP_IMM_M},
|
||||
{ "tax", SNES_OP_8BIT},
|
||||
{ "plb", SNES_OP_8BIT},
|
||||
{ "ldy 0x%04x", SNES_OP_24BIT},
|
||||
{ "lda 0x%04x", SNES_OP_24BIT},
|
||||
{ "ldx 0x%04x", SNES_OP_24BIT},
|
||||
{ "lda 0x%06x", SNES_OP_32BIT},
|
||||
{ "bcs 0x%06x", SNES_OP_16BIT},
|
||||
{ "lda (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "lda (0x%02x)", SNES_OP_16BIT},
|
||||
{ "lda (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "ldy 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "lda 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "ldx 0x%02x,y", SNES_OP_16BIT},
|
||||
{ "lda [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "clv", SNES_OP_8BIT},
|
||||
{ "lda 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "tsx", SNES_OP_8BIT},
|
||||
{ "tyx", SNES_OP_8BIT},
|
||||
{ "ldy 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "lda 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "ldx 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "lda 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "cpy", SNES_OP_IMM_X},
|
||||
{ "cmp (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "rep #0x%02x", SNES_OP_16BIT},
|
||||
{ "cmp 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "cpy 0x%02x", SNES_OP_16BIT},
|
||||
{ "cmp 0x%02x", SNES_OP_16BIT},
|
||||
{ "dec 0x%02x", SNES_OP_16BIT},
|
||||
{ "cmp [0x%02x]", SNES_OP_16BIT},
|
||||
{ "iny", SNES_OP_8BIT},
|
||||
{ "cmp", SNES_OP_IMM_M},
|
||||
{ "dex", SNES_OP_8BIT},
|
||||
{ "wai", SNES_OP_8BIT},
|
||||
{ "cpy 0x%04x", SNES_OP_24BIT},
|
||||
{ "cmp 0x%04x", SNES_OP_24BIT},
|
||||
{ "dec 0x%04x", SNES_OP_24BIT},
|
||||
{ "cmp 0x%06x", SNES_OP_32BIT},
|
||||
{ "bne 0x%06x", SNES_OP_16BIT},
|
||||
{ "cmp (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "cmp (0x%02x)", SNES_OP_16BIT},
|
||||
{ "cmp (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "pei (0x%02x)", SNES_OP_16BIT},
|
||||
{ "cmp 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "dec 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "cmp [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "cld", SNES_OP_8BIT},
|
||||
{ "cmp 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "phx", SNES_OP_8BIT},
|
||||
{ "stp", SNES_OP_8BIT},
|
||||
{ "jmp [0x%04x]", SNES_OP_24BIT},
|
||||
{ "cmp 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "dec 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "cmp 0x%06x,x", SNES_OP_32BIT},
|
||||
{ "cpx", SNES_OP_IMM_X},
|
||||
{ "sbc (0x%02x,x)", SNES_OP_16BIT},
|
||||
{ "sep #0x%02x", SNES_OP_16BIT},
|
||||
{ "sbc 0x%02x,s", SNES_OP_16BIT},
|
||||
{ "cpx 0x%02x", SNES_OP_16BIT},
|
||||
{ "sbc 0x%02x", SNES_OP_16BIT},
|
||||
{ "inc 0x%02x", SNES_OP_16BIT},
|
||||
{ "sbc [0x%02x]", SNES_OP_16BIT},
|
||||
{ "inx", SNES_OP_8BIT},
|
||||
{ "sbc", SNES_OP_IMM_M},
|
||||
{ "nop", SNES_OP_8BIT},
|
||||
{ "swa", SNES_OP_8BIT},
|
||||
{ "cpx 0x%04x", SNES_OP_24BIT},
|
||||
{ "sbc 0x%04x", SNES_OP_24BIT},
|
||||
{ "inc 0x%04x", SNES_OP_24BIT},
|
||||
{ "sbc 0x%06x", SNES_OP_32BIT},
|
||||
{ "beq 0x%06x", SNES_OP_16BIT},
|
||||
{ "sbc (0x%02x),y", SNES_OP_16BIT},
|
||||
{ "sbc (0x%02x)", SNES_OP_16BIT},
|
||||
{ "sbc (0x%02x,s),y", SNES_OP_16BIT},
|
||||
{ "pea 0x%04x", SNES_OP_24BIT},
|
||||
{ "sbc 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "inc 0x%02x,x", SNES_OP_16BIT},
|
||||
{ "sbc [0x%02x],y", SNES_OP_16BIT},
|
||||
{ "sed", SNES_OP_8BIT},
|
||||
{ "sbc 0x%04x,y", SNES_OP_24BIT},
|
||||
{ "plx", SNES_OP_8BIT},
|
||||
{ "xce", SNES_OP_8BIT},
|
||||
{ "jsr (0x%04x,x)", SNES_OP_24BIT},
|
||||
{ "sbc 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "inc 0x%04x,x", SNES_OP_24BIT},
|
||||
{ "sbc 0x%06x,x", SNES_OP_32BIT}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -709,14 +709,14 @@ const struct v850_operand v850_operands[] = {
|
|||
|
||||
const struct v850_opcode v850_opcodes[] = {
|
||||
/* Standard instructions. */
|
||||
{ "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+="},
|
||||
{ "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+=" },
|
||||
{ "add", OP (0x12), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+=" },
|
||||
{ "addi", OP (0x30), OP_MASK, IF6, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+,#2,=" },
|
||||
{ "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, V850_CPU_E2_UP },
|
||||
{ "and", OP (0x0a), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,0,o,:=,$s,s,:=,$z,z,:=" },
|
||||
{ "andi", OP (0x36), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,0,o,:=,$s,s,:=,$z,z,:=" },
|
||||
/* Signed integer. */
|
||||
{ "bge", BOP (0xe), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,!,?{,#0,PC,:=,}"},
|
||||
{ "bge", BOP (0xe), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,!,?{,#0,PC,:=,}" },
|
||||
{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
|
||||
{ "ble", BOP (0x7), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
|
||||
{ "blt", BOP (0x6), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "s,o,^,?{,#0,PC,:=,}" },
|
||||
|
|
@ -827,7 +827,7 @@ const struct v850_opcode v850_opcodes[] = {
|
|||
{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_POP, "DISPOSE,#1" },
|
||||
|
||||
{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_DIV, "#2,#1,/,#2,=,#2,#1,%,#3,=" },
|
||||
{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0 , R_ANAL_OP_TYPE_DIV, ""},
|
||||
{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0 , R_ANAL_OP_TYPE_DIV, "" },
|
||||
{ "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_DIV, "" },
|
||||
{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, V850_CPU_NON0 | V850_CPU_OPTION_EXTENSION, R_ANAL_OP_TYPE_DIV, "" },
|
||||
{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_DIV, "" },
|
||||
|
|
@ -852,9 +852,9 @@ const struct v850_opcode v850_opcodes[] = {
|
|||
{ "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, V850_CPU_E3V5_UP },
|
||||
{ "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, V850_CPU_E3V5_UP },
|
||||
|
||||
{ "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="}, // TODO: Incorrect? PC+4, PC+6 not impl here?
|
||||
{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="},
|
||||
{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,#0,PC,="},
|
||||
{ "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,=" }, // TODO: Incorrect? PC+4, PC+6 not impl here?
|
||||
{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,=" },
|
||||
{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,#0,PC,=" },
|
||||
/* Gas local alias (not defined in spec). */
|
||||
{ "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_RCALL},
|
||||
/* Gas local alias of jarl imm22 (not defined in spec). */
|
||||
|
|
@ -1016,7 +1016,7 @@ const struct v850_opcode v850_opcodes[] = {
|
|||
{ "sld.w", one (0x0500), one (0x0781), {D8_6U, EP, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD },
|
||||
|
||||
{ "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, V850_CPU_E3V5_UP },
|
||||
{ "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[1],ep,=[1]"},
|
||||
{ "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[1],ep,=[1]" },
|
||||
{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[2],ep,=[2]" },
|
||||
{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6U, EP}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,[4],ep,=[4]" },
|
||||
{ "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION },
|
||||
|
|
@ -1043,7 +1043,7 @@ const struct v850_opcode v850_opcodes[] = {
|
|||
{ "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "sub", OP (0x0d), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#0,#1,-,="},
|
||||
{ "sub", OP (0x0d), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#0,#1,-,=" },
|
||||
{ "subr", OP (0x0c), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SUB, "#1,#0,-,=" },
|
||||
{ "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_RJMP },
|
||||
{ "sxb", one (0x00a0), one (0xffe0), {R1}, 0, V850_CPU_NON0 },
|
||||
|
|
@ -1058,7 +1058,7 @@ const struct v850_opcode v850_opcodes[] = {
|
|||
{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP },
|
||||
{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0, R_ANAL_OP_TYPE_CMP },
|
||||
{ "xor", OP (0x09), OP_MASK, IF1, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#1,=" },
|
||||
{ "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#2,="},
|
||||
{ "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#2,=" },
|
||||
{ "zxb", one (0x0080), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV },
|
||||
{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV },
|
||||
|
||||
|
|
|
|||
|
|
@ -43,340 +43,340 @@ struct vot /* vax opcode text */
|
|||
static const struct vot
|
||||
votstrs[] =
|
||||
{
|
||||
{ "halt", {"", 0x00 } },
|
||||
{ "nop", {"", 0x01 } },
|
||||
{ "rei", {"", 0x02 } },
|
||||
{ "bpt", {"", 0x03 } },
|
||||
{ "ret", {"", 0x04 } },
|
||||
{ "rsb", {"", 0x05 } },
|
||||
{ "ldpctx", {"", 0x06 } },
|
||||
{ "svpctx", {"", 0x07 } },
|
||||
{ "cvtps", {"rwabrwab", 0x08 } },
|
||||
{ "cvtsp", {"rwabrwab", 0x09 } },
|
||||
{ "index", {"rlrlrlrlrlwl", 0x0a } },
|
||||
{ "crc", {"abrlrwab", 0x0b } },
|
||||
{ "prober", {"rbrwab", 0x0c } },
|
||||
{ "probew", {"rbrwab", 0x0d } },
|
||||
{ "insque", {"abab", 0x0e } },
|
||||
{ "remque", {"abwl", 0x0f } },
|
||||
{ "bsbb", {"bb", 0x10 } },
|
||||
{ "brb", {"bb", 0x11 } },
|
||||
{ "bneq", {"bb", 0x12 } },
|
||||
{ "bnequ", {"bb", 0x12 } },
|
||||
{ "beql", {"bb", 0x13 } },
|
||||
{ "beqlu", {"bb", 0x13 } },
|
||||
{ "bgtr", {"bb", 0x14 } },
|
||||
{ "bleq", {"bb", 0x15 } },
|
||||
{ "jsb", {"ab", 0x16 } },
|
||||
{ "jmp", {"ab", 0x17 } },
|
||||
{ "bgeq", {"bb", 0x18 } },
|
||||
{ "blss", {"bb", 0x19 } },
|
||||
{ "bgtru", {"bb", 0x1a } },
|
||||
{ "blequ", {"bb", 0x1b } },
|
||||
{ "bvc", {"bb", 0x1c } },
|
||||
{ "bvs", {"bb", 0x1d } },
|
||||
{ "bcc", {"bb", 0x1e } },
|
||||
{ "bgequ", {"bb", 0x1e } },
|
||||
{ "blssu", {"bb", 0x1f } },
|
||||
{ "bcs", {"bb", 0x1f } },
|
||||
{ "addp4", {"rwabrwab", 0x20 } },
|
||||
{ "addp6", {"rwabrwabrwab", 0x21 } },
|
||||
{ "subp4", {"rwabrwab", 0x22 } },
|
||||
{ "subp6", {"rwabrwabrwab", 0x23 } },
|
||||
{ "cvtpt", {"rwababrwab", 0x24 } },
|
||||
{ "mulp", {"rwabrwabrwab", 0x25 } },
|
||||
{ "cvttp", {"rwababrwab", 0x26 } },
|
||||
{ "divp", {"rwabrwabrwab", 0x27 } },
|
||||
{ "movc3", {"rwabab", 0x28 } },
|
||||
{ "cmpc3", {"rwabab", 0x29 } },
|
||||
{ "scanc", {"rwababrb", 0x2a } },
|
||||
{ "spanc", {"rwababrb", 0x2b } },
|
||||
{ "movc5", {"rwabrbrwab", 0x2c } },
|
||||
{ "cmpc5", {"rwabrbrwab", 0x2d } },
|
||||
{ "movtc", {"rwabrbabrwab", 0x2e } },
|
||||
{ "movtuc", {"rwabrbabrwab", 0x2f } },
|
||||
{ "bsbw", {"bw", 0x30 } },
|
||||
{ "brw", {"bw", 0x31 } },
|
||||
{ "cvtwl", {"rwwl", 0x32 } },
|
||||
{ "cvtwb", {"rwwb", 0x33 } },
|
||||
{ "movp", {"rwabab", 0x34 } },
|
||||
{ "cmpp3", {"rwabab", 0x35 } },
|
||||
{ "cvtpl", {"rwabwl", 0x36 } },
|
||||
{ "cmpp4", {"rwabrwab", 0x37 } },
|
||||
{ "editpc", {"rwababab", 0x38 } },
|
||||
{ "matchc", {"rwabrwab", 0x39 } },
|
||||
{ "locc", {"rbrwab", 0x3a } },
|
||||
{ "skpc", {"rbrwab", 0x3b } },
|
||||
{ "movzwl", {"rwwl", 0x3c } },
|
||||
{ "acbw", {"rwrwmwbw", 0x3d } },
|
||||
{ "movaw", {"awwl", 0x3e } },
|
||||
{ "pushaw", {"aw", 0x3f } },
|
||||
{ "addf2", {"rfmf", 0x40 } },
|
||||
{ "addf3", {"rfrfwf", 0x41 } },
|
||||
{ "subf2", {"rfmf", 0x42 } },
|
||||
{ "subf3", {"rfrfwf", 0x43 } },
|
||||
{ "mulf2", {"rfmf", 0x44 } },
|
||||
{ "mulf3", {"rfrfwf", 0x45 } },
|
||||
{ "divf2", {"rfmf", 0x46 } },
|
||||
{ "divf3", {"rfrfwf", 0x47 } },
|
||||
{ "cvtfb", {"rfwb", 0x48 } },
|
||||
{ "cvtfw", {"rfww", 0x49 } },
|
||||
{ "cvtfl", {"rfwl", 0x4a } },
|
||||
{ "cvtrfl", {"rfwl", 0x4b } },
|
||||
{ "cvtbf", {"rbwf", 0x4c } },
|
||||
{ "cvtwf", {"rwwf", 0x4d } },
|
||||
{ "cvtlf", {"rlwf", 0x4e } },
|
||||
{ "acbf", {"rfrfmfbw", 0x4f } },
|
||||
{ "movf", {"rfwf", 0x50 } },
|
||||
{ "cmpf", {"rfrf", 0x51 } },
|
||||
{ "mnegf", {"rfwf", 0x52 } },
|
||||
{ "tstf", {"rf", 0x53 } },
|
||||
{ "emodf", {"rfrbrfwlwf", 0x54 } },
|
||||
{ "polyf", {"rfrwab", 0x55 } },
|
||||
{ "cvtfd", {"rfwd", 0x56 } },
|
||||
{ "halt", { "", 0x00 } },
|
||||
{ "nop", { "", 0x01 } },
|
||||
{ "rei", { "", 0x02 } },
|
||||
{ "bpt", { "", 0x03 } },
|
||||
{ "ret", { "", 0x04 } },
|
||||
{ "rsb", { "", 0x05 } },
|
||||
{ "ldpctx", { "", 0x06 } },
|
||||
{ "svpctx", { "", 0x07 } },
|
||||
{ "cvtps", { "rwabrwab", 0x08 } },
|
||||
{ "cvtsp", { "rwabrwab", 0x09 } },
|
||||
{ "index", { "rlrlrlrlrlwl", 0x0a } },
|
||||
{ "crc", { "abrlrwab", 0x0b } },
|
||||
{ "prober", { "rbrwab", 0x0c } },
|
||||
{ "probew", { "rbrwab", 0x0d } },
|
||||
{ "insque", { "abab", 0x0e } },
|
||||
{ "remque", { "abwl", 0x0f } },
|
||||
{ "bsbb", { "bb", 0x10 } },
|
||||
{ "brb", { "bb", 0x11 } },
|
||||
{ "bneq", { "bb", 0x12 } },
|
||||
{ "bnequ", { "bb", 0x12 } },
|
||||
{ "beql", { "bb", 0x13 } },
|
||||
{ "beqlu", { "bb", 0x13 } },
|
||||
{ "bgtr", { "bb", 0x14 } },
|
||||
{ "bleq", { "bb", 0x15 } },
|
||||
{ "jsb", { "ab", 0x16 } },
|
||||
{ "jmp", { "ab", 0x17 } },
|
||||
{ "bgeq", { "bb", 0x18 } },
|
||||
{ "blss", { "bb", 0x19 } },
|
||||
{ "bgtru", { "bb", 0x1a } },
|
||||
{ "blequ", { "bb", 0x1b } },
|
||||
{ "bvc", { "bb", 0x1c } },
|
||||
{ "bvs", { "bb", 0x1d } },
|
||||
{ "bcc", { "bb", 0x1e } },
|
||||
{ "bgequ", { "bb", 0x1e } },
|
||||
{ "blssu", { "bb", 0x1f } },
|
||||
{ "bcs", { "bb", 0x1f } },
|
||||
{ "addp4", { "rwabrwab", 0x20 } },
|
||||
{ "addp6", { "rwabrwabrwab", 0x21 } },
|
||||
{ "subp4", { "rwabrwab", 0x22 } },
|
||||
{ "subp6", { "rwabrwabrwab", 0x23 } },
|
||||
{ "cvtpt", { "rwababrwab", 0x24 } },
|
||||
{ "mulp", { "rwabrwabrwab", 0x25 } },
|
||||
{ "cvttp", { "rwababrwab", 0x26 } },
|
||||
{ "divp", { "rwabrwabrwab", 0x27 } },
|
||||
{ "movc3", { "rwabab", 0x28 } },
|
||||
{ "cmpc3", { "rwabab", 0x29 } },
|
||||
{ "scanc", { "rwababrb", 0x2a } },
|
||||
{ "spanc", { "rwababrb", 0x2b } },
|
||||
{ "movc5", { "rwabrbrwab", 0x2c } },
|
||||
{ "cmpc5", { "rwabrbrwab", 0x2d } },
|
||||
{ "movtc", { "rwabrbabrwab", 0x2e } },
|
||||
{ "movtuc", { "rwabrbabrwab", 0x2f } },
|
||||
{ "bsbw", { "bw", 0x30 } },
|
||||
{ "brw", { "bw", 0x31 } },
|
||||
{ "cvtwl", { "rwwl", 0x32 } },
|
||||
{ "cvtwb", { "rwwb", 0x33 } },
|
||||
{ "movp", { "rwabab", 0x34 } },
|
||||
{ "cmpp3", { "rwabab", 0x35 } },
|
||||
{ "cvtpl", { "rwabwl", 0x36 } },
|
||||
{ "cmpp4", { "rwabrwab", 0x37 } },
|
||||
{ "editpc", { "rwababab", 0x38 } },
|
||||
{ "matchc", { "rwabrwab", 0x39 } },
|
||||
{ "locc", { "rbrwab", 0x3a } },
|
||||
{ "skpc", { "rbrwab", 0x3b } },
|
||||
{ "movzwl", { "rwwl", 0x3c } },
|
||||
{ "acbw", { "rwrwmwbw", 0x3d } },
|
||||
{ "movaw", { "awwl", 0x3e } },
|
||||
{ "pushaw", { "aw", 0x3f } },
|
||||
{ "addf2", { "rfmf", 0x40 } },
|
||||
{ "addf3", { "rfrfwf", 0x41 } },
|
||||
{ "subf2", { "rfmf", 0x42 } },
|
||||
{ "subf3", { "rfrfwf", 0x43 } },
|
||||
{ "mulf2", { "rfmf", 0x44 } },
|
||||
{ "mulf3", { "rfrfwf", 0x45 } },
|
||||
{ "divf2", { "rfmf", 0x46 } },
|
||||
{ "divf3", { "rfrfwf", 0x47 } },
|
||||
{ "cvtfb", { "rfwb", 0x48 } },
|
||||
{ "cvtfw", { "rfww", 0x49 } },
|
||||
{ "cvtfl", { "rfwl", 0x4a } },
|
||||
{ "cvtrfl", { "rfwl", 0x4b } },
|
||||
{ "cvtbf", { "rbwf", 0x4c } },
|
||||
{ "cvtwf", { "rwwf", 0x4d } },
|
||||
{ "cvtlf", { "rlwf", 0x4e } },
|
||||
{ "acbf", { "rfrfmfbw", 0x4f } },
|
||||
{ "movf", { "rfwf", 0x50 } },
|
||||
{ "cmpf", { "rfrf", 0x51 } },
|
||||
{ "mnegf", { "rfwf", 0x52 } },
|
||||
{ "tstf", { "rf", 0x53 } },
|
||||
{ "emodf", { "rfrbrfwlwf", 0x54 } },
|
||||
{ "polyf", { "rfrwab", 0x55 } },
|
||||
{ "cvtfd", { "rfwd", 0x56 } },
|
||||
/* opcode 57 is not defined yet */
|
||||
{ "adawi", {"rwmw", 0x58 } },
|
||||
{ "adawi", { "rwmw", 0x58 } },
|
||||
/* opcode 59 is not defined yet */
|
||||
/* opcode 5a is not defined yet */
|
||||
/* opcode 5b is not defined yet */
|
||||
{ "insqhi", {"abaq", 0x5c } },
|
||||
{ "insqti", {"abaq", 0x5d } },
|
||||
{ "remqhi", {"aqwl", 0x5e } },
|
||||
{ "remqti", {"aqwl", 0x5f } },
|
||||
{ "addd2", {"rdmd", 0x60 } },
|
||||
{ "addd3", {"rdrdwd", 0x61 } },
|
||||
{ "subd2", {"rdmd", 0x62 } },
|
||||
{ "subd3", {"rdrdwd", 0x63 } },
|
||||
{ "muld2", {"rdmd", 0x64 } },
|
||||
{ "muld3", {"rdrdwd", 0x65 } },
|
||||
{ "divd2", {"rdmd", 0x66 } },
|
||||
{ "divd3", {"rdrdwd", 0x67 } },
|
||||
{ "cvtdb", {"rdwb", 0x68 } },
|
||||
{ "cvtdw", {"rdww", 0x69 } },
|
||||
{ "cvtdl", {"rdwl", 0x6a } },
|
||||
{ "cvtrdl", {"rdwl", 0x6b } },
|
||||
{ "cvtbd", {"rbwd", 0x6c } },
|
||||
{ "cvtwd", {"rwwd", 0x6d } },
|
||||
{ "cvtld", {"rlwd", 0x6e } },
|
||||
{ "acbd", {"rdrdmdbw", 0x6f } },
|
||||
{ "movd", {"rdwd", 0x70 } },
|
||||
{ "cmpd", {"rdrd", 0x71 } },
|
||||
{ "mnegd", {"rdwd", 0x72 } },
|
||||
{ "tstd", {"rd", 0x73 } },
|
||||
{ "emodd", {"rdrbrdwlwd", 0x74 } },
|
||||
{ "polyd", {"rdrwab", 0x75 } },
|
||||
{ "cvtdf", {"rdwf", 0x76 } },
|
||||
{ "insqhi", { "abaq", 0x5c } },
|
||||
{ "insqti", { "abaq", 0x5d } },
|
||||
{ "remqhi", { "aqwl", 0x5e } },
|
||||
{ "remqti", { "aqwl", 0x5f } },
|
||||
{ "addd2", { "rdmd", 0x60 } },
|
||||
{ "addd3", { "rdrdwd", 0x61 } },
|
||||
{ "subd2", { "rdmd", 0x62 } },
|
||||
{ "subd3", { "rdrdwd", 0x63 } },
|
||||
{ "muld2", { "rdmd", 0x64 } },
|
||||
{ "muld3", { "rdrdwd", 0x65 } },
|
||||
{ "divd2", { "rdmd", 0x66 } },
|
||||
{ "divd3", { "rdrdwd", 0x67 } },
|
||||
{ "cvtdb", { "rdwb", 0x68 } },
|
||||
{ "cvtdw", { "rdww", 0x69 } },
|
||||
{ "cvtdl", { "rdwl", 0x6a } },
|
||||
{ "cvtrdl", { "rdwl", 0x6b } },
|
||||
{ "cvtbd", { "rbwd", 0x6c } },
|
||||
{ "cvtwd", { "rwwd", 0x6d } },
|
||||
{ "cvtld", { "rlwd", 0x6e } },
|
||||
{ "acbd", { "rdrdmdbw", 0x6f } },
|
||||
{ "movd", { "rdwd", 0x70 } },
|
||||
{ "cmpd", { "rdrd", 0x71 } },
|
||||
{ "mnegd", { "rdwd", 0x72 } },
|
||||
{ "tstd", { "rd", 0x73 } },
|
||||
{ "emodd", { "rdrbrdwlwd", 0x74 } },
|
||||
{ "polyd", { "rdrwab", 0x75 } },
|
||||
{ "cvtdf", { "rdwf", 0x76 } },
|
||||
/* opcode 77 is not defined yet */
|
||||
{ "ashl", {"rbrlwl", 0x78 } },
|
||||
{ "ashq", {"rbrqwq", 0x79 } },
|
||||
{ "emul", {"rlrlrlwq", 0x7a } },
|
||||
{ "ediv", {"rlrqwlwl", 0x7b } },
|
||||
{ "clrd", {"wd", 0x7c } },
|
||||
{ "clrg", {"wg", 0x7c } },
|
||||
{ "clrq", {"wd", 0x7c } },
|
||||
{ "movq", {"rqwq", 0x7d } },
|
||||
{ "movaq", {"aqwl", 0x7e } },
|
||||
{ "movad", {"adwl", 0x7e } },
|
||||
{ "pushaq", {"aq", 0x7f } },
|
||||
{ "pushad", {"ad", 0x7f } },
|
||||
{ "addb2", {"rbmb", 0x80 } },
|
||||
{ "addb3", {"rbrbwb", 0x81 } },
|
||||
{ "subb2", {"rbmb", 0x82 } },
|
||||
{ "subb3", {"rbrbwb", 0x83 } },
|
||||
{ "mulb2", {"rbmb", 0x84 } },
|
||||
{ "mulb3", {"rbrbwb", 0x85 } },
|
||||
{ "divb2", {"rbmb", 0x86 } },
|
||||
{ "divb3", {"rbrbwb", 0x87 } },
|
||||
{ "bisb2", {"rbmb", 0x88 } },
|
||||
{ "bisb3", {"rbrbwb", 0x89 } },
|
||||
{ "bicb2", {"rbmb", 0x8a } },
|
||||
{ "bicb3", {"rbrbwb", 0x8b } },
|
||||
{ "xorb2", {"rbmb", 0x8c } },
|
||||
{ "xorb3", {"rbrbwb", 0x8d } },
|
||||
{ "mnegb", {"rbwb", 0x8e } },
|
||||
{ "caseb", {"rbrbrb", 0x8f } },
|
||||
{ "movb", {"rbwb", 0x90 } },
|
||||
{ "cmpb", {"rbrb", 0x91 } },
|
||||
{ "mcomb", {"rbwb", 0x92 } },
|
||||
{ "bitb", {"rbrb", 0x93 } },
|
||||
{ "clrb", {"wb", 0x94 } },
|
||||
{ "tstb", {"rb", 0x95 } },
|
||||
{ "incb", {"mb", 0x96 } },
|
||||
{ "decb", {"mb", 0x97 } },
|
||||
{ "cvtbl", {"rbwl", 0x98 } },
|
||||
{ "cvtbw", {"rbww", 0x99 } },
|
||||
{ "movzbl", {"rbwl", 0x9a } },
|
||||
{ "movzbw", {"rbww", 0x9b } },
|
||||
{ "rotl", {"rbrlwl", 0x9c } },
|
||||
{ "acbb", {"rbrbmbbw", 0x9d } },
|
||||
{ "movab", {"abwl", 0x9e } },
|
||||
{ "pushab", {"ab", 0x9f } },
|
||||
{ "addw2", {"rwmw", 0xa0 } },
|
||||
{ "addw3", {"rwrwww", 0xa1 } },
|
||||
{ "subw2", {"rwmw", 0xa2 } },
|
||||
{ "subw3", {"rwrwww", 0xa3 } },
|
||||
{ "mulw2", {"rwmw", 0xa4 } },
|
||||
{ "mulw3", {"rwrwww", 0xa5 } },
|
||||
{ "divw2", {"rwmw", 0xa6 } },
|
||||
{ "divw3", {"rwrwww", 0xa7 } },
|
||||
{ "bisw2", {"rwmw", 0xa8 } },
|
||||
{ "bisw3", {"rwrwww", 0xa9 } },
|
||||
{ "bicw2", {"rwmw", 0xaa } },
|
||||
{ "bicw3", {"rwrwww", 0xab } },
|
||||
{ "xorw2", {"rwmw", 0xac } },
|
||||
{ "xorw3", {"rwrwww", 0xad } },
|
||||
{ "mnegw", {"rwww", 0xae } },
|
||||
{ "casew", {"rwrwrw", 0xaf } },
|
||||
{ "movw", {"rwww", 0xb0 } },
|
||||
{ "cmpw", {"rwrw", 0xb1 } },
|
||||
{ "mcomw", {"rwww", 0xb2 } },
|
||||
{ "bitw", {"rwrw", 0xb3 } },
|
||||
{ "clrw", {"ww", 0xb4 } },
|
||||
{ "tstw", {"rw", 0xb5 } },
|
||||
{ "incw", {"mw", 0xb6 } },
|
||||
{ "decw", {"mw", 0xb7 } },
|
||||
{ "bispsw", {"rw", 0xb8 } },
|
||||
{ "bicpsw", {"rw", 0xb9 } },
|
||||
{ "popr", {"rw", 0xba } },
|
||||
{ "pushr", {"rw", 0xbb } },
|
||||
{ "chmk", {"rw", 0xbc } },
|
||||
{ "chme", {"rw", 0xbd } },
|
||||
{ "chms", {"rw", 0xbe } },
|
||||
{ "chmu", {"rw", 0xbf } },
|
||||
{ "addl2", {"rlml", 0xc0 } },
|
||||
{ "addl3", {"rlrlwl", 0xc1 } },
|
||||
{ "subl2", {"rlml", 0xc2 } },
|
||||
{ "subl3", {"rlrlwl", 0xc3 } },
|
||||
{ "mull2", {"rlml", 0xc4 } },
|
||||
{ "mull3", {"rlrlwl", 0xc5 } },
|
||||
{ "divl2", {"rlml", 0xc6 } },
|
||||
{ "divl3", {"rlrlwl", 0xc7 } },
|
||||
{ "bisl2", {"rlml", 0xc8 } },
|
||||
{ "bisl3", {"rlrlwl", 0xc9 } },
|
||||
{ "bicl2", {"rlml", 0xca } },
|
||||
{ "bicl3", {"rlrlwl", 0xcb } },
|
||||
{ "xorl2", {"rlml", 0xcc } },
|
||||
{ "xorl3", {"rlrlwl", 0xcd } },
|
||||
{ "mnegl", {"rlwl", 0xce } },
|
||||
{ "casel", {"rlrlrl", 0xcf } },
|
||||
{ "movl", {"rlwl", 0xd0 } },
|
||||
{ "cmpl", {"rlrl", 0xd1 } },
|
||||
{ "mcoml", {"rlwl", 0xd2 } },
|
||||
{ "bitl", {"rlrl", 0xd3 } },
|
||||
{ "clrf", {"wf", 0xd4 } },
|
||||
{ "clrl", {"wl", 0xd4 } },
|
||||
{ "tstl", {"rl", 0xd5 } },
|
||||
{ "incl", {"ml", 0xd6 } },
|
||||
{ "decl", {"ml", 0xd7 } },
|
||||
{ "adwc", {"rlml", 0xd8 } },
|
||||
{ "sbwc", {"rlml", 0xd9 } },
|
||||
{ "mtpr", {"rlrl", 0xda } },
|
||||
{ "mfpr", {"rlwl", 0xdb } },
|
||||
{ "movpsl", {"wl", 0xdc } },
|
||||
{ "pushl", {"rl", 0xdd } },
|
||||
{ "moval", {"alwl", 0xde } },
|
||||
{ "movaf", {"afwl", 0xde } },
|
||||
{ "pushal", {"al", 0xdf } },
|
||||
{ "pushaf", {"af", 0xdf } },
|
||||
{ "bbs", {"rlvbbb", 0xe0 } },
|
||||
{ "bbc", {"rlvbbb", 0xe1 } },
|
||||
{ "bbss", {"rlvbbb", 0xe2 } },
|
||||
{ "bbcs", {"rlvbbb", 0xe3 } },
|
||||
{ "bbsc", {"rlvbbb", 0xe4 } },
|
||||
{ "bbcc", {"rlvbbb", 0xe5 } },
|
||||
{ "bbssi", {"rlvbbb", 0xe6 } },
|
||||
{ "bbcci", {"rlvbbb", 0xe7 } },
|
||||
{ "blbs", {"rlbb", 0xe8 } },
|
||||
{ "blbc", {"rlbb", 0xe9 } },
|
||||
{ "ffs", {"rlrbvbwl", 0xea } },
|
||||
{ "ffc", {"rlrbvbwl", 0xeb } },
|
||||
{ "cmpv", {"rlrbvbrl", 0xec } },
|
||||
{ "cmpzv", {"rlrbvbrl", 0xed } },
|
||||
{ "extv", {"rlrbvbwl", 0xee } },
|
||||
{ "extzv", {"rlrbvbwl", 0xef } },
|
||||
{ "insv", {"rlrlrbvb", 0xf0 } },
|
||||
{ "acbl", {"rlrlmlbw", 0xf1 } },
|
||||
{ "aoblss", {"rlmlbb", 0xf2 } },
|
||||
{ "aobleq", {"rlmlbb", 0xf3 } },
|
||||
{ "sobgeq", {"mlbb", 0xf4 } },
|
||||
{ "sobgtr", {"mlbb", 0xf5 } },
|
||||
{ "cvtlb", {"rlwb", 0xf6 } },
|
||||
{ "cvtlw", {"rlww", 0xf7 } },
|
||||
{ "ashp", {"rbrwabrbrwab", 0xf8 } },
|
||||
{ "cvtlp", {"rlrwab", 0xf9 } },
|
||||
{ "callg", {"abab", 0xfa } },
|
||||
{ "calls", {"rlab", 0xfb } },
|
||||
{ "xfc", {"", 0xfc } },
|
||||
{ "ashl", { "rbrlwl", 0x78 } },
|
||||
{ "ashq", { "rbrqwq", 0x79 } },
|
||||
{ "emul", { "rlrlrlwq", 0x7a } },
|
||||
{ "ediv", { "rlrqwlwl", 0x7b } },
|
||||
{ "clrd", { "wd", 0x7c } },
|
||||
{ "clrg", { "wg", 0x7c } },
|
||||
{ "clrq", { "wd", 0x7c } },
|
||||
{ "movq", { "rqwq", 0x7d } },
|
||||
{ "movaq", { "aqwl", 0x7e } },
|
||||
{ "movad", { "adwl", 0x7e } },
|
||||
{ "pushaq", { "aq", 0x7f } },
|
||||
{ "pushad", { "ad", 0x7f } },
|
||||
{ "addb2", { "rbmb", 0x80 } },
|
||||
{ "addb3", { "rbrbwb", 0x81 } },
|
||||
{ "subb2", { "rbmb", 0x82 } },
|
||||
{ "subb3", { "rbrbwb", 0x83 } },
|
||||
{ "mulb2", { "rbmb", 0x84 } },
|
||||
{ "mulb3", { "rbrbwb", 0x85 } },
|
||||
{ "divb2", { "rbmb", 0x86 } },
|
||||
{ "divb3", { "rbrbwb", 0x87 } },
|
||||
{ "bisb2", { "rbmb", 0x88 } },
|
||||
{ "bisb3", { "rbrbwb", 0x89 } },
|
||||
{ "bicb2", { "rbmb", 0x8a } },
|
||||
{ "bicb3", { "rbrbwb", 0x8b } },
|
||||
{ "xorb2", { "rbmb", 0x8c } },
|
||||
{ "xorb3", { "rbrbwb", 0x8d } },
|
||||
{ "mnegb", { "rbwb", 0x8e } },
|
||||
{ "caseb", { "rbrbrb", 0x8f } },
|
||||
{ "movb", { "rbwb", 0x90 } },
|
||||
{ "cmpb", { "rbrb", 0x91 } },
|
||||
{ "mcomb", { "rbwb", 0x92 } },
|
||||
{ "bitb", { "rbrb", 0x93 } },
|
||||
{ "clrb", { "wb", 0x94 } },
|
||||
{ "tstb", { "rb", 0x95 } },
|
||||
{ "incb", { "mb", 0x96 } },
|
||||
{ "decb", { "mb", 0x97 } },
|
||||
{ "cvtbl", { "rbwl", 0x98 } },
|
||||
{ "cvtbw", { "rbww", 0x99 } },
|
||||
{ "movzbl", { "rbwl", 0x9a } },
|
||||
{ "movzbw", { "rbww", 0x9b } },
|
||||
{ "rotl", { "rbrlwl", 0x9c } },
|
||||
{ "acbb", { "rbrbmbbw", 0x9d } },
|
||||
{ "movab", { "abwl", 0x9e } },
|
||||
{ "pushab", { "ab", 0x9f } },
|
||||
{ "addw2", { "rwmw", 0xa0 } },
|
||||
{ "addw3", { "rwrwww", 0xa1 } },
|
||||
{ "subw2", { "rwmw", 0xa2 } },
|
||||
{ "subw3", { "rwrwww", 0xa3 } },
|
||||
{ "mulw2", { "rwmw", 0xa4 } },
|
||||
{ "mulw3", { "rwrwww", 0xa5 } },
|
||||
{ "divw2", { "rwmw", 0xa6 } },
|
||||
{ "divw3", { "rwrwww", 0xa7 } },
|
||||
{ "bisw2", { "rwmw", 0xa8 } },
|
||||
{ "bisw3", { "rwrwww", 0xa9 } },
|
||||
{ "bicw2", { "rwmw", 0xaa } },
|
||||
{ "bicw3", { "rwrwww", 0xab } },
|
||||
{ "xorw2", { "rwmw", 0xac } },
|
||||
{ "xorw3", { "rwrwww", 0xad } },
|
||||
{ "mnegw", { "rwww", 0xae } },
|
||||
{ "casew", { "rwrwrw", 0xaf } },
|
||||
{ "movw", { "rwww", 0xb0 } },
|
||||
{ "cmpw", { "rwrw", 0xb1 } },
|
||||
{ "mcomw", { "rwww", 0xb2 } },
|
||||
{ "bitw", { "rwrw", 0xb3 } },
|
||||
{ "clrw", { "ww", 0xb4 } },
|
||||
{ "tstw", { "rw", 0xb5 } },
|
||||
{ "incw", { "mw", 0xb6 } },
|
||||
{ "decw", { "mw", 0xb7 } },
|
||||
{ "bispsw", { "rw", 0xb8 } },
|
||||
{ "bicpsw", { "rw", 0xb9 } },
|
||||
{ "popr", { "rw", 0xba } },
|
||||
{ "pushr", { "rw", 0xbb } },
|
||||
{ "chmk", { "rw", 0xbc } },
|
||||
{ "chme", { "rw", 0xbd } },
|
||||
{ "chms", { "rw", 0xbe } },
|
||||
{ "chmu", { "rw", 0xbf } },
|
||||
{ "addl2", { "rlml", 0xc0 } },
|
||||
{ "addl3", { "rlrlwl", 0xc1 } },
|
||||
{ "subl2", { "rlml", 0xc2 } },
|
||||
{ "subl3", { "rlrlwl", 0xc3 } },
|
||||
{ "mull2", { "rlml", 0xc4 } },
|
||||
{ "mull3", { "rlrlwl", 0xc5 } },
|
||||
{ "divl2", { "rlml", 0xc6 } },
|
||||
{ "divl3", { "rlrlwl", 0xc7 } },
|
||||
{ "bisl2", { "rlml", 0xc8 } },
|
||||
{ "bisl3", { "rlrlwl", 0xc9 } },
|
||||
{ "bicl2", { "rlml", 0xca } },
|
||||
{ "bicl3", { "rlrlwl", 0xcb } },
|
||||
{ "xorl2", { "rlml", 0xcc } },
|
||||
{ "xorl3", { "rlrlwl", 0xcd } },
|
||||
{ "mnegl", { "rlwl", 0xce } },
|
||||
{ "casel", { "rlrlrl", 0xcf } },
|
||||
{ "movl", { "rlwl", 0xd0 } },
|
||||
{ "cmpl", { "rlrl", 0xd1 } },
|
||||
{ "mcoml", { "rlwl", 0xd2 } },
|
||||
{ "bitl", { "rlrl", 0xd3 } },
|
||||
{ "clrf", { "wf", 0xd4 } },
|
||||
{ "clrl", { "wl", 0xd4 } },
|
||||
{ "tstl", { "rl", 0xd5 } },
|
||||
{ "incl", { "ml", 0xd6 } },
|
||||
{ "decl", { "ml", 0xd7 } },
|
||||
{ "adwc", { "rlml", 0xd8 } },
|
||||
{ "sbwc", { "rlml", 0xd9 } },
|
||||
{ "mtpr", { "rlrl", 0xda } },
|
||||
{ "mfpr", { "rlwl", 0xdb } },
|
||||
{ "movpsl", { "wl", 0xdc } },
|
||||
{ "pushl", { "rl", 0xdd } },
|
||||
{ "moval", { "alwl", 0xde } },
|
||||
{ "movaf", { "afwl", 0xde } },
|
||||
{ "pushal", { "al", 0xdf } },
|
||||
{ "pushaf", { "af", 0xdf } },
|
||||
{ "bbs", { "rlvbbb", 0xe0 } },
|
||||
{ "bbc", { "rlvbbb", 0xe1 } },
|
||||
{ "bbss", { "rlvbbb", 0xe2 } },
|
||||
{ "bbcs", { "rlvbbb", 0xe3 } },
|
||||
{ "bbsc", { "rlvbbb", 0xe4 } },
|
||||
{ "bbcc", { "rlvbbb", 0xe5 } },
|
||||
{ "bbssi", { "rlvbbb", 0xe6 } },
|
||||
{ "bbcci", { "rlvbbb", 0xe7 } },
|
||||
{ "blbs", { "rlbb", 0xe8 } },
|
||||
{ "blbc", { "rlbb", 0xe9 } },
|
||||
{ "ffs", { "rlrbvbwl", 0xea } },
|
||||
{ "ffc", { "rlrbvbwl", 0xeb } },
|
||||
{ "cmpv", { "rlrbvbrl", 0xec } },
|
||||
{ "cmpzv", { "rlrbvbrl", 0xed } },
|
||||
{ "extv", { "rlrbvbwl", 0xee } },
|
||||
{ "extzv", { "rlrbvbwl", 0xef } },
|
||||
{ "insv", { "rlrlrbvb", 0xf0 } },
|
||||
{ "acbl", { "rlrlmlbw", 0xf1 } },
|
||||
{ "aoblss", { "rlmlbb", 0xf2 } },
|
||||
{ "aobleq", { "rlmlbb", 0xf3 } },
|
||||
{ "sobgeq", { "mlbb", 0xf4 } },
|
||||
{ "sobgtr", { "mlbb", 0xf5 } },
|
||||
{ "cvtlb", { "rlwb", 0xf6 } },
|
||||
{ "cvtlw", { "rlww", 0xf7 } },
|
||||
{ "ashp", { "rbrwabrbrwab", 0xf8 } },
|
||||
{ "cvtlp", { "rlrwab", 0xf9 } },
|
||||
{ "callg", { "abab", 0xfa } },
|
||||
{ "calls", { "rlab", 0xfb } },
|
||||
{ "xfc", { "", 0xfc } },
|
||||
/* undefined opcodes here */
|
||||
{ "cvtdh", {"rdwh", 0x32fd } },
|
||||
{ "cvtgf", {"rgwh", 0x33fd } },
|
||||
{ "addg2", {"rgmg", 0x40fd } },
|
||||
{ "addg3", {"rgrgwg", 0x41fd } },
|
||||
{ "subg2", {"rgmg", 0x42fd } },
|
||||
{ "subg3", {"rgrgwg", 0x43fd } },
|
||||
{ "mulg2", {"rgmg", 0x44fd } },
|
||||
{ "mulg3", {"rgrgwg", 0x45fd } },
|
||||
{ "divg2", {"rgmg", 0x46fd } },
|
||||
{ "divg3", {"rgrgwg", 0x47fd } },
|
||||
{ "cvtgb", {"rgwb", 0x48fd } },
|
||||
{ "cvtgw", {"rgww", 0x49fd } },
|
||||
{ "cvtgl", {"rgwl", 0x4afd } },
|
||||
{ "cvtrgl", {"rgwl", 0x4bfd } },
|
||||
{ "cvtbg", {"rbwg", 0x4cfd } },
|
||||
{ "cvtwg", {"rwwg", 0x4dfd } },
|
||||
{ "cvtlg", {"rlwg", 0x4efd } },
|
||||
{ "acbg", {"rgrgmgbw", 0x4ffd } },
|
||||
{ "movg", {"rgwg", 0x50fd } },
|
||||
{ "cmpg", {"rgrg", 0x51fd } },
|
||||
{ "mnegg", {"rgwg", 0x52fd } },
|
||||
{ "tstg", {"rg", 0x53fd } },
|
||||
{ "emodg", {"rgrwrgwlwg", 0x54fd } },
|
||||
{ "polyg", {"rgrwab", 0x55fd } },
|
||||
{ "cvtgh", {"rgwh", 0x56fd } },
|
||||
{ "cvtdh", { "rdwh", 0x32fd } },
|
||||
{ "cvtgf", { "rgwh", 0x33fd } },
|
||||
{ "addg2", { "rgmg", 0x40fd } },
|
||||
{ "addg3", { "rgrgwg", 0x41fd } },
|
||||
{ "subg2", { "rgmg", 0x42fd } },
|
||||
{ "subg3", { "rgrgwg", 0x43fd } },
|
||||
{ "mulg2", { "rgmg", 0x44fd } },
|
||||
{ "mulg3", { "rgrgwg", 0x45fd } },
|
||||
{ "divg2", { "rgmg", 0x46fd } },
|
||||
{ "divg3", { "rgrgwg", 0x47fd } },
|
||||
{ "cvtgb", { "rgwb", 0x48fd } },
|
||||
{ "cvtgw", { "rgww", 0x49fd } },
|
||||
{ "cvtgl", { "rgwl", 0x4afd } },
|
||||
{ "cvtrgl", { "rgwl", 0x4bfd } },
|
||||
{ "cvtbg", { "rbwg", 0x4cfd } },
|
||||
{ "cvtwg", { "rwwg", 0x4dfd } },
|
||||
{ "cvtlg", { "rlwg", 0x4efd } },
|
||||
{ "acbg", { "rgrgmgbw", 0x4ffd } },
|
||||
{ "movg", { "rgwg", 0x50fd } },
|
||||
{ "cmpg", { "rgrg", 0x51fd } },
|
||||
{ "mnegg", { "rgwg", 0x52fd } },
|
||||
{ "tstg", { "rg", 0x53fd } },
|
||||
{ "emodg", { "rgrwrgwlwg", 0x54fd } },
|
||||
{ "polyg", { "rgrwab", 0x55fd } },
|
||||
{ "cvtgh", { "rgwh", 0x56fd } },
|
||||
/* undefined opcodes here */
|
||||
{ "addh2", {"rhmh", 0x60fd } },
|
||||
{ "addh3", {"rhrhwh", 0x61fd } },
|
||||
{ "subh2", {"rhmh", 0x62fd } },
|
||||
{ "subh3", {"rhrhwh", 0x63fd } },
|
||||
{ "mulh2", {"rhmh", 0x64fd } },
|
||||
{ "mulh3", {"rhrhwh", 0x65fd } },
|
||||
{ "divh2", {"rhmh", 0x66fd } },
|
||||
{ "divh3", {"rhrhwh", 0x67fd } },
|
||||
{ "cvthb", {"rhwb", 0x68fd } },
|
||||
{ "cvthw", {"rhww", 0x69fd } },
|
||||
{ "cvthl", {"rhwl", 0x6afd } },
|
||||
{ "cvtrhl", {"rhwl", 0x6bfd } },
|
||||
{ "cvtbh", {"rbwh", 0x6cfd } },
|
||||
{ "cvtwh", {"rwwh", 0x6dfd } },
|
||||
{ "cvtlh", {"rlwh", 0x6efd } },
|
||||
{ "acbh", {"rhrhmhbw", 0x6ffd } },
|
||||
{ "movh", {"rhwh", 0x70fd } },
|
||||
{ "cmph", {"rhrh", 0x71fd } },
|
||||
{ "mnegh", {"rhwh", 0x72fd } },
|
||||
{ "tsth", {"rh", 0x73fd } },
|
||||
{ "emodh", {"rhrwrhwlwh", 0x74fd } },
|
||||
{ "polyh", {"rhrwab", 0x75fd } },
|
||||
{ "cvthg", {"rhwg", 0x76fd } },
|
||||
{ "addh2", { "rhmh", 0x60fd } },
|
||||
{ "addh3", { "rhrhwh", 0x61fd } },
|
||||
{ "subh2", { "rhmh", 0x62fd } },
|
||||
{ "subh3", { "rhrhwh", 0x63fd } },
|
||||
{ "mulh2", { "rhmh", 0x64fd } },
|
||||
{ "mulh3", { "rhrhwh", 0x65fd } },
|
||||
{ "divh2", { "rhmh", 0x66fd } },
|
||||
{ "divh3", { "rhrhwh", 0x67fd } },
|
||||
{ "cvthb", { "rhwb", 0x68fd } },
|
||||
{ "cvthw", { "rhww", 0x69fd } },
|
||||
{ "cvthl", { "rhwl", 0x6afd } },
|
||||
{ "cvtrhl", { "rhwl", 0x6bfd } },
|
||||
{ "cvtbh", { "rbwh", 0x6cfd } },
|
||||
{ "cvtwh", { "rwwh", 0x6dfd } },
|
||||
{ "cvtlh", { "rlwh", 0x6efd } },
|
||||
{ "acbh", { "rhrhmhbw", 0x6ffd } },
|
||||
{ "movh", { "rhwh", 0x70fd } },
|
||||
{ "cmph", { "rhrh", 0x71fd } },
|
||||
{ "mnegh", { "rhwh", 0x72fd } },
|
||||
{ "tsth", { "rh", 0x73fd } },
|
||||
{ "emodh", { "rhrwrhwlwh", 0x74fd } },
|
||||
{ "polyh", { "rhrwab", 0x75fd } },
|
||||
{ "cvthg", { "rhwg", 0x76fd } },
|
||||
/* undefined opcodes here */
|
||||
{ "clrh", {"wh", 0x7cfd } },
|
||||
{ "clro", {"wo", 0x7cfd } },
|
||||
{ "movo", {"rowo", 0x7dfd } },
|
||||
{ "movah", {"ahwl", 0x7efd } },
|
||||
{ "movao", {"aowl", 0x7efd } },
|
||||
{ "pushah", {"ah", 0x7ffd } },
|
||||
{ "pushao", {"ao", 0x7ffd } },
|
||||
{ "clrh", { "wh", 0x7cfd } },
|
||||
{ "clro", { "wo", 0x7cfd } },
|
||||
{ "movo", { "rowo", 0x7dfd } },
|
||||
{ "movah", { "ahwl", 0x7efd } },
|
||||
{ "movao", { "aowl", 0x7efd } },
|
||||
{ "pushah", { "ah", 0x7ffd } },
|
||||
{ "pushao", { "ao", 0x7ffd } },
|
||||
/* undefined opcodes here */
|
||||
{ "cvtfh", {"rfwh", 0x98fd } },
|
||||
{ "cvtfg", {"rfwg", 0x99fd } },
|
||||
{ "cvtfh", { "rfwh", 0x98fd } },
|
||||
{ "cvtfg", { "rfwg", 0x99fd } },
|
||||
/* undefined opcodes here */
|
||||
{ "cvthf", {"rhwf", 0xf6fd } },
|
||||
{ "cvthd", {"rhwd", 0xf7fd } },
|
||||
{ "cvthf", { "rhwf", 0xf6fd } },
|
||||
{ "cvthd", { "rhwd", 0xf7fd } },
|
||||
/* undefined opcodes here */
|
||||
{ "bugl", {"rl", 0xfdff } },
|
||||
{ "bugw", {"rw", 0xfeff } },
|
||||
{ "bugl", { "rl", 0xfdff } },
|
||||
{ "bugw", { "rw", 0xfeff } },
|
||||
/* undefined opcodes here */
|
||||
|
||||
{ "", {"", 0} } /* empty is end sentinel */
|
||||
{ "", { "", 0} } /* empty is end sentinel */
|
||||
|
||||
}; /* votstrs */
|
||||
|
||||
|
|
|
|||
|
|
@ -71,8 +71,8 @@ static WasmOpDef opcodes[256] = {
|
|||
[WASM_OP_I32GES] = { "i32.ge_s", 1, 1 },
|
||||
[WASM_OP_I32GEU] = { "i32.ge_u", 1, 1 },
|
||||
[WASM_OP_I64EQZ] = { "i64.eqz", 1, 1 },
|
||||
[WASM_OP_I64EQ] = {" i64.eq", 1, 1 },
|
||||
[WASM_OP_I64NE] = {" i64.ne", 1, 1 },
|
||||
[WASM_OP_I64EQ] = { " i64.eq", 1, 1 },
|
||||
[WASM_OP_I64NE] = { " i64.ne", 1, 1 },
|
||||
[WASM_OP_I64LTS] = { "i64.lt_s", 1, 1 },
|
||||
[WASM_OP_I64LTU] = { "i64.lt_u", 1, 1 },
|
||||
[WASM_OP_I64GTS] = { "i64.gt_s", 1, 1 },
|
||||
|
|
@ -142,7 +142,7 @@ static WasmOpDef opcodes[256] = {
|
|||
[WASM_OP_F32DIV] = { "f32.div", 1, 1 },
|
||||
[WASM_OP_F32MIN] = { "f32.min", 1, 1 },
|
||||
[WASM_OP_F32MAX] = { "f32.max", 1, 1 },
|
||||
[WASM_OP_F32COPYSIGN] = {" f32.copysign", 1, 1 },
|
||||
[WASM_OP_F32COPYSIGN] = { " f32.copysign", 1, 1 },
|
||||
[WASM_OP_F64ABS] = { "f64.abs", 1, 1 },
|
||||
[WASM_OP_F64NEG] = { "f64.neg", 1, 1 },
|
||||
[WASM_OP_F64CEIL] = { "f64.ceil", 1, 1 },
|
||||
|
|
|
|||
|
|
@ -841,505 +841,505 @@ static const char *fdcb[]={
|
|||
|
||||
|
||||
static const z80_opcode dd[] = { //dd
|
||||
{"add ix, bc", Z80_OP16 ,NULL},
|
||||
{"add ix, de", Z80_OP16 ,NULL},
|
||||
{"ld ix, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"ld [0x%04x], ix", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"inc ix", Z80_OP16 ,NULL},
|
||||
{"inc ixh", Z80_OP16 ,NULL},
|
||||
{"dec ixh", Z80_OP16 ,NULL},
|
||||
{"ld ixh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"add ix, ix", Z80_OP16 ,NULL},
|
||||
{"ld ix, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"dec ix", Z80_OP16 ,NULL},
|
||||
{"inc ixl", Z80_OP16 ,NULL},
|
||||
{"dec ixl", Z80_OP16 ,NULL},
|
||||
{"ld ixl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"inc [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"dec [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL},
|
||||
{"add ix, sp", Z80_OP16 ,NULL},
|
||||
{"ld b, ixh", Z80_OP16 ,NULL},
|
||||
{"ld b, ixl", Z80_OP16 ,NULL},
|
||||
{"ld b, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld c, ixh", Z80_OP16 ,NULL},
|
||||
{"ld c, ixl", Z80_OP16 ,NULL},
|
||||
{"ld c, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld d, ixh", Z80_OP16 ,NULL},
|
||||
{"ld d, ixl", Z80_OP16 ,NULL},
|
||||
{"ld d, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld e, ixh", Z80_OP16 ,NULL},
|
||||
{"ld e, ixl", Z80_OP16 ,NULL},
|
||||
{"ld e, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld ixh, b", Z80_OP16 ,NULL},
|
||||
{"ld ixh, c", Z80_OP16 ,NULL},
|
||||
{"ld ixh, d", Z80_OP16 ,NULL},
|
||||
{"ld ixh, e", Z80_OP16 ,NULL},
|
||||
{"ld ixh, ixh", Z80_OP16 ,NULL},
|
||||
{"ld ixh, ixl", Z80_OP16 ,NULL},
|
||||
{"ld h, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld ixh, a", Z80_OP16 ,NULL},
|
||||
{"ld ixl, b", Z80_OP16 ,NULL},
|
||||
{"ld ixl, c", Z80_OP16 ,NULL},
|
||||
{"ld ixl, d", Z80_OP16 ,NULL},
|
||||
{"ld ixl, e", Z80_OP16 ,NULL},
|
||||
{"ld ixl, ixh", Z80_OP16 ,NULL},
|
||||
{"ld ixl, ixl", Z80_OP16 ,NULL},
|
||||
{"ld l, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld ixl, a", Z80_OP16 ,NULL},
|
||||
{"ld [ix+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [ix+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld a, ixh", Z80_OP16 ,NULL},
|
||||
{"ld a, ixl", Z80_OP16 ,NULL},
|
||||
{"ld a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"add a, ixh", Z80_OP16 ,NULL},
|
||||
{"add a, ixl", Z80_OP16 ,NULL},
|
||||
{"add a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"adc a, ixh", Z80_OP16 ,NULL},
|
||||
{"adc a, ixl", Z80_OP16 ,NULL},
|
||||
{"adc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"sub a, ixh", Z80_OP16 ,NULL},
|
||||
{"sub a, ixl", Z80_OP16 ,NULL},
|
||||
{"sub [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"sbc a, ixh", Z80_OP16 ,NULL},
|
||||
{"sbc a, ixl", Z80_OP16 ,NULL},
|
||||
{"sbc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"and ixh", Z80_OP16 ,NULL},
|
||||
{"and ixl", Z80_OP16 ,NULL},
|
||||
{"and [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"xor ixh", Z80_OP16 ,NULL},
|
||||
{"xor ixl", Z80_OP16 ,NULL},
|
||||
{"xor [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"or ixh", Z80_OP16 ,NULL},
|
||||
{"or ixl", Z80_OP16 ,NULL},
|
||||
{"or [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"cp ixh", Z80_OP16 ,NULL},
|
||||
{"cp ixl", Z80_OP16 ,NULL},
|
||||
{"cp [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"", Z80_OP24^Z80_ARG8 ,ddcb},
|
||||
{"pop ix", Z80_OP16 ,NULL},
|
||||
{"ex [sp], ix", Z80_OP16 ,NULL},
|
||||
{"push ix", Z80_OP16 ,NULL},
|
||||
{"jp [ix]", Z80_OP16 ,NULL},
|
||||
{"ld sp, ix", Z80_OP16 ,NULL},
|
||||
{"invalid", Z80_OP16 ,NULL}
|
||||
{ "add ix, bc", Z80_OP16 ,NULL},
|
||||
{ "add ix, de", Z80_OP16 ,NULL},
|
||||
{ "ld ix, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "ld [0x%04x], ix", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "inc ix", Z80_OP16 ,NULL},
|
||||
{ "inc ixh", Z80_OP16 ,NULL},
|
||||
{ "dec ixh", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "add ix, ix", Z80_OP16 ,NULL},
|
||||
{ "ld ix, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "dec ix", Z80_OP16 ,NULL},
|
||||
{ "inc ixl", Z80_OP16 ,NULL},
|
||||
{ "dec ixl", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "inc [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "dec [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL},
|
||||
{ "add ix, sp", Z80_OP16 ,NULL},
|
||||
{ "ld b, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld b, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld b, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld c, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld c, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld c, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld d, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld d, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld d, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld e, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld e, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld e, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld ixh, b", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, c", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, d", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, e", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld ixh, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld h, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld ixh, a", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, b", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, c", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, d", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, e", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld ixl, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld l, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld ixl, a", Z80_OP16 ,NULL},
|
||||
{ "ld [ix+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [ix+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld a, ixh", Z80_OP16 ,NULL},
|
||||
{ "ld a, ixl", Z80_OP16 ,NULL},
|
||||
{ "ld a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "add a, ixh", Z80_OP16 ,NULL},
|
||||
{ "add a, ixl", Z80_OP16 ,NULL},
|
||||
{ "add a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "adc a, ixh", Z80_OP16 ,NULL},
|
||||
{ "adc a, ixl", Z80_OP16 ,NULL},
|
||||
{ "adc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "sub a, ixh", Z80_OP16 ,NULL},
|
||||
{ "sub a, ixl", Z80_OP16 ,NULL},
|
||||
{ "sub [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "sbc a, ixh", Z80_OP16 ,NULL},
|
||||
{ "sbc a, ixl", Z80_OP16 ,NULL},
|
||||
{ "sbc a, [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "and ixh", Z80_OP16 ,NULL},
|
||||
{ "and ixl", Z80_OP16 ,NULL},
|
||||
{ "and [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "xor ixh", Z80_OP16 ,NULL},
|
||||
{ "xor ixl", Z80_OP16 ,NULL},
|
||||
{ "xor [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "or ixh", Z80_OP16 ,NULL},
|
||||
{ "or ixl", Z80_OP16 ,NULL},
|
||||
{ "or [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "cp ixh", Z80_OP16 ,NULL},
|
||||
{ "cp ixl", Z80_OP16 ,NULL},
|
||||
{ "cp [ix+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "", Z80_OP24^Z80_ARG8 ,ddcb},
|
||||
{ "pop ix", Z80_OP16 ,NULL},
|
||||
{ "ex [sp], ix", Z80_OP16 ,NULL},
|
||||
{ "push ix", Z80_OP16 ,NULL},
|
||||
{ "jp [ix]", Z80_OP16 ,NULL},
|
||||
{ "ld sp, ix", Z80_OP16 ,NULL},
|
||||
{ "invalid", Z80_OP16 ,NULL}
|
||||
};
|
||||
|
||||
static const z80_opcode ed[]={ //ed
|
||||
{"in b, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], b", Z80_OP16 ,NULL},
|
||||
{"sbc hl, bc", Z80_OP16 ,NULL},
|
||||
{"ld [0x%04x], bc", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"neg", Z80_OP16 ,NULL},
|
||||
{"retn", Z80_OP16 ,NULL},
|
||||
{"im 0", Z80_OP16 ,NULL},
|
||||
{"ld i, a", Z80_OP16 ,NULL},
|
||||
{"in c, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], c", Z80_OP16 ,NULL},
|
||||
{"adc hl, bc", Z80_OP16 ,NULL},
|
||||
{"ld bc, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"reti", Z80_OP16 ,NULL},
|
||||
{"ld r, a", Z80_OP16 ,NULL},
|
||||
{"in d, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], d", Z80_OP16 ,NULL},
|
||||
{"sbc hl, de", Z80_OP16 ,NULL},
|
||||
{"ld [0x%04x], de", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"im 1", Z80_OP16 ,NULL},
|
||||
{"ld a, i", Z80_OP16 ,NULL},
|
||||
{"in e, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], e", Z80_OP16 ,NULL},
|
||||
{"adc hl, de", Z80_OP16 ,NULL},
|
||||
{"ld de, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"im 2", Z80_OP16 ,NULL},
|
||||
{"ld a, r", Z80_OP16 ,NULL},
|
||||
{"in h, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], h", Z80_OP16 ,NULL},
|
||||
{"sbc hl, hl", Z80_OP16 ,NULL},
|
||||
{"rrd", Z80_OP16 ,NULL},
|
||||
{"in l, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], l", Z80_OP16 ,NULL},
|
||||
{"adc hl, hl", Z80_OP16 ,NULL},
|
||||
{"rld", Z80_OP16 ,NULL},
|
||||
{"in [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], 0", Z80_OP16 ,NULL},
|
||||
{"sbc hl, sp", Z80_OP16 ,NULL},
|
||||
{"ld [0x%04x], sp", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"in a, [c]", Z80_OP16 ,NULL},
|
||||
{"out [c], a", Z80_OP16 ,NULL},
|
||||
{"adc hl, sp", Z80_OP16 ,NULL},
|
||||
{"ld sp, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"ldi", Z80_OP16 ,NULL},
|
||||
{"cpi", Z80_OP16 ,NULL},
|
||||
{"ini", Z80_OP16 ,NULL},
|
||||
{"outi", Z80_OP16 ,NULL},
|
||||
{"ldd", Z80_OP16 ,NULL},
|
||||
{"cpd", Z80_OP16 ,NULL},
|
||||
{"ind", Z80_OP16 ,NULL},
|
||||
{"outd", Z80_OP16 ,NULL},
|
||||
{"ldir", Z80_OP16 ,NULL},
|
||||
{"cpir", Z80_OP16 ,NULL},
|
||||
{"inir", Z80_OP16 ,NULL},
|
||||
{"otir", Z80_OP16 ,NULL},
|
||||
{"lddr", Z80_OP16 ,NULL},
|
||||
{"cpdr", Z80_OP16 ,NULL},
|
||||
{"indr", Z80_OP16 ,NULL},
|
||||
{"otdr", Z80_OP16 ,NULL},
|
||||
{"invalid", Z80_OP16 ,NULL},
|
||||
{"invalid", Z80_OP16 ,NULL}
|
||||
{ "in b, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], b", Z80_OP16 ,NULL},
|
||||
{ "sbc hl, bc", Z80_OP16 ,NULL},
|
||||
{ "ld [0x%04x], bc", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "neg", Z80_OP16 ,NULL},
|
||||
{ "retn", Z80_OP16 ,NULL},
|
||||
{ "im 0", Z80_OP16 ,NULL},
|
||||
{ "ld i, a", Z80_OP16 ,NULL},
|
||||
{ "in c, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], c", Z80_OP16 ,NULL},
|
||||
{ "adc hl, bc", Z80_OP16 ,NULL},
|
||||
{ "ld bc, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "reti", Z80_OP16 ,NULL},
|
||||
{ "ld r, a", Z80_OP16 ,NULL},
|
||||
{ "in d, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], d", Z80_OP16 ,NULL},
|
||||
{ "sbc hl, de", Z80_OP16 ,NULL},
|
||||
{ "ld [0x%04x], de", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "im 1", Z80_OP16 ,NULL},
|
||||
{ "ld a, i", Z80_OP16 ,NULL},
|
||||
{ "in e, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], e", Z80_OP16 ,NULL},
|
||||
{ "adc hl, de", Z80_OP16 ,NULL},
|
||||
{ "ld de, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "im 2", Z80_OP16 ,NULL},
|
||||
{ "ld a, r", Z80_OP16 ,NULL},
|
||||
{ "in h, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], h", Z80_OP16 ,NULL},
|
||||
{ "sbc hl, hl", Z80_OP16 ,NULL},
|
||||
{ "rrd", Z80_OP16 ,NULL},
|
||||
{ "in l, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], l", Z80_OP16 ,NULL},
|
||||
{ "adc hl, hl", Z80_OP16 ,NULL},
|
||||
{ "rld", Z80_OP16 ,NULL},
|
||||
{ "in [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], 0", Z80_OP16 ,NULL},
|
||||
{ "sbc hl, sp", Z80_OP16 ,NULL},
|
||||
{ "ld [0x%04x], sp", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "in a, [c]", Z80_OP16 ,NULL},
|
||||
{ "out [c], a", Z80_OP16 ,NULL},
|
||||
{ "adc hl, sp", Z80_OP16 ,NULL},
|
||||
{ "ld sp, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "ldi", Z80_OP16 ,NULL},
|
||||
{ "cpi", Z80_OP16 ,NULL},
|
||||
{ "ini", Z80_OP16 ,NULL},
|
||||
{ "outi", Z80_OP16 ,NULL},
|
||||
{ "ldd", Z80_OP16 ,NULL},
|
||||
{ "cpd", Z80_OP16 ,NULL},
|
||||
{ "ind", Z80_OP16 ,NULL},
|
||||
{ "outd", Z80_OP16 ,NULL},
|
||||
{ "ldir", Z80_OP16 ,NULL},
|
||||
{ "cpir", Z80_OP16 ,NULL},
|
||||
{ "inir", Z80_OP16 ,NULL},
|
||||
{ "otir", Z80_OP16 ,NULL},
|
||||
{ "lddr", Z80_OP16 ,NULL},
|
||||
{ "cpdr", Z80_OP16 ,NULL},
|
||||
{ "indr", Z80_OP16 ,NULL},
|
||||
{ "otdr", Z80_OP16 ,NULL},
|
||||
{ "invalid", Z80_OP16 ,NULL},
|
||||
{ "invalid", Z80_OP16 ,NULL}
|
||||
};
|
||||
|
||||
static const z80_opcode fd[]={ //fd
|
||||
{"add iy, bc", Z80_OP16 ,NULL},
|
||||
{"add iy, de", Z80_OP16 ,NULL},
|
||||
{"ld iy, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"ld [0x%04x], iy", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"inc iy", Z80_OP16 ,NULL},
|
||||
{"inc iyh", Z80_OP16 ,NULL},
|
||||
{"dec iyh", Z80_OP16 ,NULL},
|
||||
{"ld iyh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"add iy, iy", Z80_OP16 ,NULL},
|
||||
{"ld iy, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{"dec iy", Z80_OP16 ,NULL},
|
||||
{"inc iyl", Z80_OP16 ,NULL},
|
||||
{"dec iyl", Z80_OP16 ,NULL},
|
||||
{"ld iyl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"inc [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"dec [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL},
|
||||
{"add iy, sp", Z80_OP16 ,NULL},
|
||||
{"ld b, iyh", Z80_OP16 ,NULL},
|
||||
{"ld b, iyl", Z80_OP16 ,NULL},
|
||||
{"ld b, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld c, iyh", Z80_OP16 ,NULL},
|
||||
{"ld c, iyl", Z80_OP16 ,NULL},
|
||||
{"ld c, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld d, iyh", Z80_OP16 ,NULL},
|
||||
{"ld d, iyl", Z80_OP16 ,NULL},
|
||||
{"ld d, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld e, iyh", Z80_OP16 ,NULL},
|
||||
{"ld e, iyl", Z80_OP16 ,NULL},
|
||||
{"ld e, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld iyh, b", Z80_OP16 ,NULL},
|
||||
{"ld iyh, c", Z80_OP16 ,NULL},
|
||||
{"ld iyh, d", Z80_OP16 ,NULL},
|
||||
{"ld iyh, e", Z80_OP16 ,NULL},
|
||||
{"ld iyh, iyh", Z80_OP16 ,NULL},
|
||||
{"ld iyh, iyl", Z80_OP16 ,NULL},
|
||||
{"ld h, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld iyh, a", Z80_OP16 ,NULL},
|
||||
{"ld iyl, b", Z80_OP16 ,NULL},
|
||||
{"ld iyl, c", Z80_OP16 ,NULL},
|
||||
{"ld iyl, d", Z80_OP16 ,NULL},
|
||||
{"ld iyl, e", Z80_OP16 ,NULL},
|
||||
{"ld iyl, iyh", Z80_OP16 ,NULL},
|
||||
{"ld iyl, iyl", Z80_OP16 ,NULL},
|
||||
{"ld l, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld iyl, a", Z80_OP16 ,NULL},
|
||||
{"ld [iy+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld [iy+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"ld a, iyh", Z80_OP16 ,NULL},
|
||||
{"ld a, iyl", Z80_OP16 ,NULL},
|
||||
{"ld a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"add a, iyh", Z80_OP16 ,NULL},
|
||||
{"add a, iyl", Z80_OP16 ,NULL},
|
||||
{"add a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"adc a, iyh", Z80_OP16 ,NULL},
|
||||
{"adc a, iyl", Z80_OP16 ,NULL},
|
||||
{"adc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"sub iyh", Z80_OP16 ,NULL},
|
||||
{"sub iyl", Z80_OP16 ,NULL},
|
||||
{"sub [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"sbc a, iyh", Z80_OP16 ,NULL},
|
||||
{"sbc a, iyl", Z80_OP16 ,NULL},
|
||||
{"sbc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"and iyh", Z80_OP16 ,NULL},
|
||||
{"and iyl", Z80_OP16 ,NULL},
|
||||
{"and [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"xor iyh", Z80_OP16 ,NULL},
|
||||
{"xor iyl", Z80_OP16 ,NULL},
|
||||
{"xor [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"or iyh", Z80_OP16 ,NULL},
|
||||
{"or iyl", Z80_OP16 ,NULL},
|
||||
{"or [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"cp iyh", Z80_OP16 ,NULL},
|
||||
{"cp iyl", Z80_OP16 ,NULL},
|
||||
{"cp [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{"", Z80_OP24^Z80_ARG8 ,fdcb},
|
||||
{"pop iy", Z80_OP16 ,NULL},
|
||||
{"ex [sp], iy", Z80_OP16 ,NULL},
|
||||
{"push iy", Z80_OP16 ,NULL},
|
||||
{"jp [iy]", Z80_OP16 ,NULL},
|
||||
{"ld sp, iy", Z80_OP16 ,NULL},
|
||||
{"invalid", Z80_OP16 ,NULL}
|
||||
{ "add iy, bc", Z80_OP16 ,NULL},
|
||||
{ "add iy, de", Z80_OP16 ,NULL},
|
||||
{ "ld iy, 0x%04x", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "ld [0x%04x], iy", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "inc iy", Z80_OP16 ,NULL},
|
||||
{ "inc iyh", Z80_OP16 ,NULL},
|
||||
{ "dec iyh", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "add iy, iy", Z80_OP16 ,NULL},
|
||||
{ "ld iy, [0x%04x]", Z80_OP16^Z80_ARG16 ,NULL},
|
||||
{ "dec iy", Z80_OP16 ,NULL},
|
||||
{ "inc iyl", Z80_OP16 ,NULL},
|
||||
{ "dec iyl", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, 0x%02x", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "inc [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "dec [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], 0x%02x",Z80_OP16^Z80_ARG8^Z80_ARG16 ,NULL},
|
||||
{ "add iy, sp", Z80_OP16 ,NULL},
|
||||
{ "ld b, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld b, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld b, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld c, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld c, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld c, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld d, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld d, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld d, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld e, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld e, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld e, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld iyh, b", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, c", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, d", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, e", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld iyh, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld h, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld iyh, a", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, b", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, c", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, d", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, e", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld iyl, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld l, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld iyl, a", Z80_OP16 ,NULL},
|
||||
{ "ld [iy+0x%02x], b", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], c", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], d", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], e", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], h", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], l", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld [iy+0x%02x], a", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "ld a, iyh", Z80_OP16 ,NULL},
|
||||
{ "ld a, iyl", Z80_OP16 ,NULL},
|
||||
{ "ld a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "add a, iyh", Z80_OP16 ,NULL},
|
||||
{ "add a, iyl", Z80_OP16 ,NULL},
|
||||
{ "add a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "adc a, iyh", Z80_OP16 ,NULL},
|
||||
{ "adc a, iyl", Z80_OP16 ,NULL},
|
||||
{ "adc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "sub iyh", Z80_OP16 ,NULL},
|
||||
{ "sub iyl", Z80_OP16 ,NULL},
|
||||
{ "sub [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "sbc a, iyh", Z80_OP16 ,NULL},
|
||||
{ "sbc a, iyl", Z80_OP16 ,NULL},
|
||||
{ "sbc a, [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "and iyh", Z80_OP16 ,NULL},
|
||||
{ "and iyl", Z80_OP16 ,NULL},
|
||||
{ "and [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "xor iyh", Z80_OP16 ,NULL},
|
||||
{ "xor iyl", Z80_OP16 ,NULL},
|
||||
{ "xor [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "or iyh", Z80_OP16 ,NULL},
|
||||
{ "or iyl", Z80_OP16 ,NULL},
|
||||
{ "or [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "cp iyh", Z80_OP16 ,NULL},
|
||||
{ "cp iyl", Z80_OP16 ,NULL},
|
||||
{ "cp [iy+0x%02x]", Z80_OP16^Z80_ARG8 ,NULL},
|
||||
{ "", Z80_OP24^Z80_ARG8 ,fdcb},
|
||||
{ "pop iy", Z80_OP16 ,NULL},
|
||||
{ "ex [sp], iy", Z80_OP16 ,NULL},
|
||||
{ "push iy", Z80_OP16 ,NULL},
|
||||
{ "jp [iy]", Z80_OP16 ,NULL},
|
||||
{ "ld sp, iy", Z80_OP16 ,NULL},
|
||||
{ "invalid", Z80_OP16 ,NULL}
|
||||
};
|
||||
|
||||
static const z80_opcode z80_op[] = {
|
||||
{"nop", Z80_OP8 ,NULL},
|
||||
{"ld bc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ld [bc], a", Z80_OP8 ,NULL},
|
||||
{"inc bc", Z80_OP8 ,NULL},
|
||||
{"inc b", Z80_OP8 ,NULL},
|
||||
{"dec b", Z80_OP8 ,NULL},
|
||||
{"ld b, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rlca", Z80_OP8 ,NULL},
|
||||
{"ex af, af'", Z80_OP8 ,NULL},
|
||||
{"add hl, bc", Z80_OP8 ,NULL},
|
||||
{"ld a, [bc]", Z80_OP8 ,NULL},
|
||||
{"dec bc", Z80_OP8 ,NULL},
|
||||
{"inc c", Z80_OP8 ,NULL},
|
||||
{"dec c", Z80_OP8 ,NULL},
|
||||
{"ld c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rrca", Z80_OP8 ,NULL},
|
||||
{"djnz 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"ld de, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ld [de], a", Z80_OP8 ,NULL},
|
||||
{"inc de", Z80_OP8 ,NULL},
|
||||
{"inc d", Z80_OP8 ,NULL},
|
||||
{"dec d", Z80_OP8 ,NULL},
|
||||
{"ld d, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rla", Z80_OP8 ,NULL},
|
||||
{"jr 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"add hl, de", Z80_OP8 ,NULL},
|
||||
{"ld a, [de]", Z80_OP8 ,NULL},
|
||||
{"dec de", Z80_OP8 ,NULL},
|
||||
{"inc e", Z80_OP8 ,NULL},
|
||||
{"dec e", Z80_OP8 ,NULL},
|
||||
{"ld e, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rra", Z80_OP8 ,NULL},
|
||||
{"jr nz, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"ld hl, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ld [0x%04x], hl", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"inc hl", Z80_OP8 ,NULL},
|
||||
{"inc h", Z80_OP8 ,NULL},
|
||||
{"dec h", Z80_OP8 ,NULL},
|
||||
{"ld h, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"daa", Z80_OP8 ,NULL},
|
||||
{"jr z, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"add hl, hl", Z80_OP8 ,NULL},
|
||||
{"ld hl, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"dec hl", Z80_OP8 ,NULL},
|
||||
{"inc l", Z80_OP8 ,NULL},
|
||||
{"dec l", Z80_OP8 ,NULL},
|
||||
{"ld l, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"cpl", Z80_OP8 ,NULL},
|
||||
{"jr nc, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"ld sp, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ld [0x%04x], a", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"inc sp", Z80_OP8 ,NULL},
|
||||
{"inc [hl]", Z80_OP8 ,NULL},
|
||||
{"dec [hl]", Z80_OP8 ,NULL},
|
||||
{"ld [hl], 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"scf", Z80_OP8 ,NULL},
|
||||
{"jr c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"add hl, sp", Z80_OP8 ,NULL},
|
||||
{"ld a, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"dec sp", Z80_OP8 ,NULL},
|
||||
{"inc a", Z80_OP8 ,NULL},
|
||||
{"dec a", Z80_OP8 ,NULL},
|
||||
{"ld a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"ccf", Z80_OP8 ,NULL},
|
||||
{"ld b, b", Z80_OP8 ,NULL},
|
||||
{"ld b, c", Z80_OP8 ,NULL},
|
||||
{"ld b, d", Z80_OP8 ,NULL},
|
||||
{"ld b, e", Z80_OP8 ,NULL},
|
||||
{"ld b, h", Z80_OP8 ,NULL},
|
||||
{"ld b, l", Z80_OP8 ,NULL},
|
||||
{"ld b, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld b, a", Z80_OP8 ,NULL},
|
||||
{"ld c, b", Z80_OP8 ,NULL},
|
||||
{"ld c, c", Z80_OP8 ,NULL},
|
||||
{"ld c, d", Z80_OP8 ,NULL},
|
||||
{"ld c, e", Z80_OP8 ,NULL},
|
||||
{"ld c, h", Z80_OP8 ,NULL},
|
||||
{"ld c, l", Z80_OP8 ,NULL},
|
||||
{"ld c, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld c, a", Z80_OP8 ,NULL},
|
||||
{"ld d, b", Z80_OP8 ,NULL},
|
||||
{"ld d, c", Z80_OP8 ,NULL},
|
||||
{"ld d, d", Z80_OP8 ,NULL},
|
||||
{"ld d, e", Z80_OP8 ,NULL},
|
||||
{"ld d, h", Z80_OP8 ,NULL},
|
||||
{"ld d, l", Z80_OP8 ,NULL},
|
||||
{"ld d, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld d, a", Z80_OP8 ,NULL},
|
||||
{"ld e, b", Z80_OP8 ,NULL},
|
||||
{"ld e, c", Z80_OP8 ,NULL},
|
||||
{"ld e, d", Z80_OP8 ,NULL},
|
||||
{"ld e, e", Z80_OP8 ,NULL},
|
||||
{"ld e, h", Z80_OP8 ,NULL},
|
||||
{"ld e, l", Z80_OP8 ,NULL},
|
||||
{"ld e, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld e, a", Z80_OP8 ,NULL},
|
||||
{"ld h, b", Z80_OP8 ,NULL},
|
||||
{"ld h, c", Z80_OP8 ,NULL},
|
||||
{"ld h, d", Z80_OP8 ,NULL},
|
||||
{"ld h, e", Z80_OP8 ,NULL},
|
||||
{"ld h, h", Z80_OP8 ,NULL},
|
||||
{"ld h, l", Z80_OP8 ,NULL},
|
||||
{"ld h, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld h, a", Z80_OP8 ,NULL},
|
||||
{"ld l, b", Z80_OP8 ,NULL},
|
||||
{"ld l, c", Z80_OP8 ,NULL},
|
||||
{"ld l, d", Z80_OP8 ,NULL},
|
||||
{"ld l, e", Z80_OP8 ,NULL},
|
||||
{"ld l, h", Z80_OP8 ,NULL},
|
||||
{"ld l, l", Z80_OP8 ,NULL},
|
||||
{"ld l, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld l, a", Z80_OP8 ,NULL},
|
||||
{"ld [hl], b", Z80_OP8 ,NULL},
|
||||
{"ld [hl], c", Z80_OP8 ,NULL},
|
||||
{"ld [hl], d", Z80_OP8 ,NULL},
|
||||
{"ld [hl], e", Z80_OP8 ,NULL},
|
||||
{"ld [hl], h", Z80_OP8 ,NULL},
|
||||
{"ld [hl], l", Z80_OP8 ,NULL},
|
||||
{"halt", Z80_OP8 ,NULL},
|
||||
{"ld [hl], a", Z80_OP8 ,NULL},
|
||||
{"ld a, b", Z80_OP8 ,NULL},
|
||||
{"ld a, c", Z80_OP8 ,NULL},
|
||||
{"ld a, d", Z80_OP8 ,NULL},
|
||||
{"ld a, e", Z80_OP8 ,NULL},
|
||||
{"ld a, h", Z80_OP8 ,NULL},
|
||||
{"ld a, l", Z80_OP8 ,NULL},
|
||||
{"ld a, [hl]", Z80_OP8 ,NULL},
|
||||
{"ld a, a", Z80_OP8 ,NULL},
|
||||
{"add a, b", Z80_OP8 ,NULL},
|
||||
{"add a, c", Z80_OP8 ,NULL},
|
||||
{"add a, d", Z80_OP8 ,NULL},
|
||||
{"add a, e", Z80_OP8 ,NULL},
|
||||
{"add a, h", Z80_OP8 ,NULL},
|
||||
{"add a, l", Z80_OP8 ,NULL},
|
||||
{"add a, [hl]", Z80_OP8 ,NULL},
|
||||
{"add a, a", Z80_OP8 ,NULL},
|
||||
{"adc a, b", Z80_OP8 ,NULL},
|
||||
{"adc a, c", Z80_OP8 ,NULL},
|
||||
{"adc a, d", Z80_OP8 ,NULL},
|
||||
{"adc a, e", Z80_OP8 ,NULL},
|
||||
{"adc a, h", Z80_OP8 ,NULL},
|
||||
{"adc a, l", Z80_OP8 ,NULL},
|
||||
{"adc a, [hl]", Z80_OP8 ,NULL},
|
||||
{"adc a, a", Z80_OP8 ,NULL},
|
||||
{"sub b", Z80_OP8 ,NULL},
|
||||
{"sub c", Z80_OP8 ,NULL},
|
||||
{"sub d", Z80_OP8 ,NULL},
|
||||
{"sub e", Z80_OP8 ,NULL},
|
||||
{"sub h", Z80_OP8 ,NULL},
|
||||
{"sub l", Z80_OP8 ,NULL},
|
||||
{"sub [hl]", Z80_OP8 ,NULL},
|
||||
{"sub a", Z80_OP8 ,NULL},
|
||||
{"sbc a, b", Z80_OP8 ,NULL},
|
||||
{"sbc a, c", Z80_OP8 ,NULL},
|
||||
{"sbc a, d", Z80_OP8 ,NULL},
|
||||
{"sbc a, e", Z80_OP8 ,NULL},
|
||||
{"sbc a, h", Z80_OP8 ,NULL},
|
||||
{"sbc a, l", Z80_OP8 ,NULL},
|
||||
{"sbc a, [hl]", Z80_OP8 ,NULL},
|
||||
{"sbc a, a", Z80_OP8 ,NULL},
|
||||
{"and b", Z80_OP8 ,NULL},
|
||||
{"and c", Z80_OP8 ,NULL},
|
||||
{"and d", Z80_OP8 ,NULL},
|
||||
{"and e", Z80_OP8 ,NULL},
|
||||
{"and h", Z80_OP8 ,NULL},
|
||||
{"and l", Z80_OP8 ,NULL},
|
||||
{"and [hl]", Z80_OP8 ,NULL},
|
||||
{"and a", Z80_OP8 ,NULL},
|
||||
{"xor b", Z80_OP8 ,NULL},
|
||||
{"xor c", Z80_OP8 ,NULL},
|
||||
{"xor d", Z80_OP8 ,NULL},
|
||||
{"xor e", Z80_OP8 ,NULL},
|
||||
{"xor h", Z80_OP8 ,NULL},
|
||||
{"xor l", Z80_OP8 ,NULL},
|
||||
{"xor [hl]", Z80_OP8 ,NULL},
|
||||
{"xor a", Z80_OP8 ,NULL},
|
||||
{"or b", Z80_OP8 ,NULL},
|
||||
{"or c", Z80_OP8 ,NULL},
|
||||
{"or d", Z80_OP8 ,NULL},
|
||||
{"or e", Z80_OP8 ,NULL},
|
||||
{"or h", Z80_OP8 ,NULL},
|
||||
{"or l", Z80_OP8 ,NULL},
|
||||
{"or [hl]", Z80_OP8 ,NULL},
|
||||
{"or a", Z80_OP8 ,NULL},
|
||||
{"cp b", Z80_OP8 ,NULL},
|
||||
{"cp c", Z80_OP8 ,NULL},
|
||||
{"cp d", Z80_OP8 ,NULL},
|
||||
{"cp e", Z80_OP8 ,NULL},
|
||||
{"cp h", Z80_OP8 ,NULL},
|
||||
{"cp l", Z80_OP8 ,NULL},
|
||||
{"cp [hl]", Z80_OP8 ,NULL},
|
||||
{"cp a", Z80_OP8 ,NULL},
|
||||
{"ret nz", Z80_OP8 ,NULL},
|
||||
{"pop bc", Z80_OP8 ,NULL},
|
||||
{"jp nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"jp 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"call nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"push bc", Z80_OP8 ,NULL},
|
||||
{"add a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x00", Z80_OP8 ,NULL},
|
||||
{"ret z", Z80_OP8 ,NULL},
|
||||
{"ret", Z80_OP8 ,NULL},
|
||||
{"jp z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"", Z80_OP16 ,cb},
|
||||
{"call z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"call 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"adc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x08", Z80_OP8 ,NULL},
|
||||
{"ret nc", Z80_OP8 ,NULL},
|
||||
{"pop de", Z80_OP8 ,NULL},
|
||||
{"jp nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"out [0x%02x], a", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"call nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"push de", Z80_OP8 ,NULL},
|
||||
{"sub 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x10", Z80_OP8 ,NULL},
|
||||
{"ret c", Z80_OP8 ,NULL},
|
||||
{"exx", Z80_OP8 ,NULL},
|
||||
{"jp c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"in a, [0x%02x]", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"call c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"", Z80_OP_UNK^Z80_ENC0 ,dd},
|
||||
{"sbc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x18", Z80_OP8 ,NULL},
|
||||
{"ret po", Z80_OP8 ,NULL},
|
||||
{"pop hl", Z80_OP8 ,NULL},
|
||||
{"jp po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ex [sp], hl", Z80_OP8 ,NULL},
|
||||
{"call po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"push hl", Z80_OP8 ,NULL},
|
||||
{"and 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x20", Z80_OP8 ,NULL},
|
||||
{"ret pe", Z80_OP8 ,NULL},
|
||||
{"jp [hl]", Z80_OP8 ,NULL},
|
||||
{"jp pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ex de, hl", Z80_OP8 ,NULL},
|
||||
{"call pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"", Z80_OP_UNK^Z80_ENC1 ,ed},
|
||||
{"xor 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x28", Z80_OP8 ,NULL},
|
||||
{"ret p", Z80_OP8 ,NULL},
|
||||
{"pop af", Z80_OP8 ,NULL},
|
||||
{"jp p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"di", Z80_OP8 ,NULL},
|
||||
{"call p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"push af", Z80_OP8 ,NULL},
|
||||
{"or 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x30", Z80_OP8 ,NULL},
|
||||
{"ret m", Z80_OP8 ,NULL},
|
||||
{"ld sp, hl", Z80_OP8 ,NULL},
|
||||
{"jp m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"ei", Z80_OP8 ,NULL},
|
||||
{"call m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{"", Z80_OP_UNK^Z80_ENC0 ,fd},
|
||||
{"cp 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{"rst 0x38", Z80_OP8 ,NULL},
|
||||
{ "nop", Z80_OP8 ,NULL},
|
||||
{ "ld bc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ld [bc], a", Z80_OP8 ,NULL},
|
||||
{ "inc bc", Z80_OP8 ,NULL},
|
||||
{ "inc b", Z80_OP8 ,NULL},
|
||||
{ "dec b", Z80_OP8 ,NULL},
|
||||
{ "ld b, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rlca", Z80_OP8 ,NULL},
|
||||
{ "ex af, af'", Z80_OP8 ,NULL},
|
||||
{ "add hl, bc", Z80_OP8 ,NULL},
|
||||
{ "ld a, [bc]", Z80_OP8 ,NULL},
|
||||
{ "dec bc", Z80_OP8 ,NULL},
|
||||
{ "inc c", Z80_OP8 ,NULL},
|
||||
{ "dec c", Z80_OP8 ,NULL},
|
||||
{ "ld c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rrca", Z80_OP8 ,NULL},
|
||||
{ "djnz 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "ld de, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ld [de], a", Z80_OP8 ,NULL},
|
||||
{ "inc de", Z80_OP8 ,NULL},
|
||||
{ "inc d", Z80_OP8 ,NULL},
|
||||
{ "dec d", Z80_OP8 ,NULL},
|
||||
{ "ld d, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rla", Z80_OP8 ,NULL},
|
||||
{ "jr 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "add hl, de", Z80_OP8 ,NULL},
|
||||
{ "ld a, [de]", Z80_OP8 ,NULL},
|
||||
{ "dec de", Z80_OP8 ,NULL},
|
||||
{ "inc e", Z80_OP8 ,NULL},
|
||||
{ "dec e", Z80_OP8 ,NULL},
|
||||
{ "ld e, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rra", Z80_OP8 ,NULL},
|
||||
{ "jr nz, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "ld hl, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ld [0x%04x], hl", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "inc hl", Z80_OP8 ,NULL},
|
||||
{ "inc h", Z80_OP8 ,NULL},
|
||||
{ "dec h", Z80_OP8 ,NULL},
|
||||
{ "ld h, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "daa", Z80_OP8 ,NULL},
|
||||
{ "jr z, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "add hl, hl", Z80_OP8 ,NULL},
|
||||
{ "ld hl, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "dec hl", Z80_OP8 ,NULL},
|
||||
{ "inc l", Z80_OP8 ,NULL},
|
||||
{ "dec l", Z80_OP8 ,NULL},
|
||||
{ "ld l, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "cpl", Z80_OP8 ,NULL},
|
||||
{ "jr nc, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "ld sp, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ld [0x%04x], a", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "inc sp", Z80_OP8 ,NULL},
|
||||
{ "inc [hl]", Z80_OP8 ,NULL},
|
||||
{ "dec [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "scf", Z80_OP8 ,NULL},
|
||||
{ "jr c, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "add hl, sp", Z80_OP8 ,NULL},
|
||||
{ "ld a, [0x%04x]", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "dec sp", Z80_OP8 ,NULL},
|
||||
{ "inc a", Z80_OP8 ,NULL},
|
||||
{ "dec a", Z80_OP8 ,NULL},
|
||||
{ "ld a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "ccf", Z80_OP8 ,NULL},
|
||||
{ "ld b, b", Z80_OP8 ,NULL},
|
||||
{ "ld b, c", Z80_OP8 ,NULL},
|
||||
{ "ld b, d", Z80_OP8 ,NULL},
|
||||
{ "ld b, e", Z80_OP8 ,NULL},
|
||||
{ "ld b, h", Z80_OP8 ,NULL},
|
||||
{ "ld b, l", Z80_OP8 ,NULL},
|
||||
{ "ld b, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld b, a", Z80_OP8 ,NULL},
|
||||
{ "ld c, b", Z80_OP8 ,NULL},
|
||||
{ "ld c, c", Z80_OP8 ,NULL},
|
||||
{ "ld c, d", Z80_OP8 ,NULL},
|
||||
{ "ld c, e", Z80_OP8 ,NULL},
|
||||
{ "ld c, h", Z80_OP8 ,NULL},
|
||||
{ "ld c, l", Z80_OP8 ,NULL},
|
||||
{ "ld c, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld c, a", Z80_OP8 ,NULL},
|
||||
{ "ld d, b", Z80_OP8 ,NULL},
|
||||
{ "ld d, c", Z80_OP8 ,NULL},
|
||||
{ "ld d, d", Z80_OP8 ,NULL},
|
||||
{ "ld d, e", Z80_OP8 ,NULL},
|
||||
{ "ld d, h", Z80_OP8 ,NULL},
|
||||
{ "ld d, l", Z80_OP8 ,NULL},
|
||||
{ "ld d, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld d, a", Z80_OP8 ,NULL},
|
||||
{ "ld e, b", Z80_OP8 ,NULL},
|
||||
{ "ld e, c", Z80_OP8 ,NULL},
|
||||
{ "ld e, d", Z80_OP8 ,NULL},
|
||||
{ "ld e, e", Z80_OP8 ,NULL},
|
||||
{ "ld e, h", Z80_OP8 ,NULL},
|
||||
{ "ld e, l", Z80_OP8 ,NULL},
|
||||
{ "ld e, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld e, a", Z80_OP8 ,NULL},
|
||||
{ "ld h, b", Z80_OP8 ,NULL},
|
||||
{ "ld h, c", Z80_OP8 ,NULL},
|
||||
{ "ld h, d", Z80_OP8 ,NULL},
|
||||
{ "ld h, e", Z80_OP8 ,NULL},
|
||||
{ "ld h, h", Z80_OP8 ,NULL},
|
||||
{ "ld h, l", Z80_OP8 ,NULL},
|
||||
{ "ld h, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld h, a", Z80_OP8 ,NULL},
|
||||
{ "ld l, b", Z80_OP8 ,NULL},
|
||||
{ "ld l, c", Z80_OP8 ,NULL},
|
||||
{ "ld l, d", Z80_OP8 ,NULL},
|
||||
{ "ld l, e", Z80_OP8 ,NULL},
|
||||
{ "ld l, h", Z80_OP8 ,NULL},
|
||||
{ "ld l, l", Z80_OP8 ,NULL},
|
||||
{ "ld l, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld l, a", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], b", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], c", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], d", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], e", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], h", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], l", Z80_OP8 ,NULL},
|
||||
{ "halt", Z80_OP8 ,NULL},
|
||||
{ "ld [hl], a", Z80_OP8 ,NULL},
|
||||
{ "ld a, b", Z80_OP8 ,NULL},
|
||||
{ "ld a, c", Z80_OP8 ,NULL},
|
||||
{ "ld a, d", Z80_OP8 ,NULL},
|
||||
{ "ld a, e", Z80_OP8 ,NULL},
|
||||
{ "ld a, h", Z80_OP8 ,NULL},
|
||||
{ "ld a, l", Z80_OP8 ,NULL},
|
||||
{ "ld a, [hl]", Z80_OP8 ,NULL},
|
||||
{ "ld a, a", Z80_OP8 ,NULL},
|
||||
{ "add a, b", Z80_OP8 ,NULL},
|
||||
{ "add a, c", Z80_OP8 ,NULL},
|
||||
{ "add a, d", Z80_OP8 ,NULL},
|
||||
{ "add a, e", Z80_OP8 ,NULL},
|
||||
{ "add a, h", Z80_OP8 ,NULL},
|
||||
{ "add a, l", Z80_OP8 ,NULL},
|
||||
{ "add a, [hl]", Z80_OP8 ,NULL},
|
||||
{ "add a, a", Z80_OP8 ,NULL},
|
||||
{ "adc a, b", Z80_OP8 ,NULL},
|
||||
{ "adc a, c", Z80_OP8 ,NULL},
|
||||
{ "adc a, d", Z80_OP8 ,NULL},
|
||||
{ "adc a, e", Z80_OP8 ,NULL},
|
||||
{ "adc a, h", Z80_OP8 ,NULL},
|
||||
{ "adc a, l", Z80_OP8 ,NULL},
|
||||
{ "adc a, [hl]", Z80_OP8 ,NULL},
|
||||
{ "adc a, a", Z80_OP8 ,NULL},
|
||||
{ "sub b", Z80_OP8 ,NULL},
|
||||
{ "sub c", Z80_OP8 ,NULL},
|
||||
{ "sub d", Z80_OP8 ,NULL},
|
||||
{ "sub e", Z80_OP8 ,NULL},
|
||||
{ "sub h", Z80_OP8 ,NULL},
|
||||
{ "sub l", Z80_OP8 ,NULL},
|
||||
{ "sub [hl]", Z80_OP8 ,NULL},
|
||||
{ "sub a", Z80_OP8 ,NULL},
|
||||
{ "sbc a, b", Z80_OP8 ,NULL},
|
||||
{ "sbc a, c", Z80_OP8 ,NULL},
|
||||
{ "sbc a, d", Z80_OP8 ,NULL},
|
||||
{ "sbc a, e", Z80_OP8 ,NULL},
|
||||
{ "sbc a, h", Z80_OP8 ,NULL},
|
||||
{ "sbc a, l", Z80_OP8 ,NULL},
|
||||
{ "sbc a, [hl]", Z80_OP8 ,NULL},
|
||||
{ "sbc a, a", Z80_OP8 ,NULL},
|
||||
{ "and b", Z80_OP8 ,NULL},
|
||||
{ "and c", Z80_OP8 ,NULL},
|
||||
{ "and d", Z80_OP8 ,NULL},
|
||||
{ "and e", Z80_OP8 ,NULL},
|
||||
{ "and h", Z80_OP8 ,NULL},
|
||||
{ "and l", Z80_OP8 ,NULL},
|
||||
{ "and [hl]", Z80_OP8 ,NULL},
|
||||
{ "and a", Z80_OP8 ,NULL},
|
||||
{ "xor b", Z80_OP8 ,NULL},
|
||||
{ "xor c", Z80_OP8 ,NULL},
|
||||
{ "xor d", Z80_OP8 ,NULL},
|
||||
{ "xor e", Z80_OP8 ,NULL},
|
||||
{ "xor h", Z80_OP8 ,NULL},
|
||||
{ "xor l", Z80_OP8 ,NULL},
|
||||
{ "xor [hl]", Z80_OP8 ,NULL},
|
||||
{ "xor a", Z80_OP8 ,NULL},
|
||||
{ "or b", Z80_OP8 ,NULL},
|
||||
{ "or c", Z80_OP8 ,NULL},
|
||||
{ "or d", Z80_OP8 ,NULL},
|
||||
{ "or e", Z80_OP8 ,NULL},
|
||||
{ "or h", Z80_OP8 ,NULL},
|
||||
{ "or l", Z80_OP8 ,NULL},
|
||||
{ "or [hl]", Z80_OP8 ,NULL},
|
||||
{ "or a", Z80_OP8 ,NULL},
|
||||
{ "cp b", Z80_OP8 ,NULL},
|
||||
{ "cp c", Z80_OP8 ,NULL},
|
||||
{ "cp d", Z80_OP8 ,NULL},
|
||||
{ "cp e", Z80_OP8 ,NULL},
|
||||
{ "cp h", Z80_OP8 ,NULL},
|
||||
{ "cp l", Z80_OP8 ,NULL},
|
||||
{ "cp [hl]", Z80_OP8 ,NULL},
|
||||
{ "cp a", Z80_OP8 ,NULL},
|
||||
{ "ret nz", Z80_OP8 ,NULL},
|
||||
{ "pop bc", Z80_OP8 ,NULL},
|
||||
{ "jp nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "jp 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "call nz, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "push bc", Z80_OP8 ,NULL},
|
||||
{ "add a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x00", Z80_OP8 ,NULL},
|
||||
{ "ret z", Z80_OP8 ,NULL},
|
||||
{ "ret", Z80_OP8 ,NULL},
|
||||
{ "jp z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "", Z80_OP16 ,cb},
|
||||
{ "call z, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "call 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "adc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x08", Z80_OP8 ,NULL},
|
||||
{ "ret nc", Z80_OP8 ,NULL},
|
||||
{ "pop de", Z80_OP8 ,NULL},
|
||||
{ "jp nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "out [0x%02x], a", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "call nc, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "push de", Z80_OP8 ,NULL},
|
||||
{ "sub 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x10", Z80_OP8 ,NULL},
|
||||
{ "ret c", Z80_OP8 ,NULL},
|
||||
{ "exx", Z80_OP8 ,NULL},
|
||||
{ "jp c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "in a, [0x%02x]", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "call c, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "", Z80_OP_UNK^Z80_ENC0 ,dd},
|
||||
{ "sbc a, 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x18", Z80_OP8 ,NULL},
|
||||
{ "ret po", Z80_OP8 ,NULL},
|
||||
{ "pop hl", Z80_OP8 ,NULL},
|
||||
{ "jp po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ex [sp], hl", Z80_OP8 ,NULL},
|
||||
{ "call po, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "push hl", Z80_OP8 ,NULL},
|
||||
{ "and 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x20", Z80_OP8 ,NULL},
|
||||
{ "ret pe", Z80_OP8 ,NULL},
|
||||
{ "jp [hl]", Z80_OP8 ,NULL},
|
||||
{ "jp pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ex de, hl", Z80_OP8 ,NULL},
|
||||
{ "call pe, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "", Z80_OP_UNK^Z80_ENC1 ,ed},
|
||||
{ "xor 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x28", Z80_OP8 ,NULL},
|
||||
{ "ret p", Z80_OP8 ,NULL},
|
||||
{ "pop af", Z80_OP8 ,NULL},
|
||||
{ "jp p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "di", Z80_OP8 ,NULL},
|
||||
{ "call p, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "push af", Z80_OP8 ,NULL},
|
||||
{ "or 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x30", Z80_OP8 ,NULL},
|
||||
{ "ret m", Z80_OP8 ,NULL},
|
||||
{ "ld sp, hl", Z80_OP8 ,NULL},
|
||||
{ "jp m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "ei", Z80_OP8 ,NULL},
|
||||
{ "call m, 0x%04x", Z80_OP8^Z80_ARG16 ,NULL},
|
||||
{ "", Z80_OP_UNK^Z80_ENC0 ,fd},
|
||||
{ "cp 0x%02x", Z80_OP8^Z80_ARG8 ,NULL},
|
||||
{ "rst 0x38", Z80_OP8 ,NULL},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -686,16 +686,16 @@ struct op_family {
|
|||
int id;
|
||||
};
|
||||
static const struct op_family of[] = {
|
||||
{"cpu", R_ANAL_OP_FAMILY_CPU},
|
||||
{"fpu", R_ANAL_OP_FAMILY_FPU},
|
||||
{"mmx", R_ANAL_OP_FAMILY_MMX},
|
||||
{"sse", R_ANAL_OP_FAMILY_SSE},
|
||||
{"priv", R_ANAL_OP_FAMILY_PRIV},
|
||||
{"virt", R_ANAL_OP_FAMILY_VIRT},
|
||||
{"crpt", R_ANAL_OP_FAMILY_CRYPTO},
|
||||
{"io", R_ANAL_OP_FAMILY_IO},
|
||||
{"sec", R_ANAL_OP_FAMILY_SECURITY},
|
||||
{"thread", R_ANAL_OP_FAMILY_THREAD},
|
||||
{ "cpu", R_ANAL_OP_FAMILY_CPU},
|
||||
{ "fpu", R_ANAL_OP_FAMILY_FPU},
|
||||
{ "mmx", R_ANAL_OP_FAMILY_MMX},
|
||||
{ "sse", R_ANAL_OP_FAMILY_SSE},
|
||||
{ "priv", R_ANAL_OP_FAMILY_PRIV},
|
||||
{ "virt", R_ANAL_OP_FAMILY_VIRT},
|
||||
{ "crpt", R_ANAL_OP_FAMILY_CRYPTO},
|
||||
{ "io", R_ANAL_OP_FAMILY_IO},
|
||||
{ "sec", R_ANAL_OP_FAMILY_SECURITY},
|
||||
{ "thread", R_ANAL_OP_FAMILY_THREAD},
|
||||
};
|
||||
|
||||
R_API int r_anal_op_family_from_string(const char *f) {
|
||||
|
|
|
|||
|
|
@ -181,36 +181,36 @@ typedef struct {
|
|||
// custom reg read/write temporarily disabled - see r2 issue #9242
|
||||
static RI8051Reg registers[] = {
|
||||
// keep these sorted
|
||||
{"a", 0xE0, 0x00, 1, 0},
|
||||
{"b", 0xF0, 0x00, 1, 0},
|
||||
{"dph", 0x83, 0x00, 1, 0},
|
||||
{"dpl", 0x82, 0x00, 1, 0},
|
||||
{"dptr", 0x82, 0x00, 2, 0, 1},
|
||||
{"ie", 0xA8, 0x00, 1, 0},
|
||||
{"ip", 0xB8, 0x00, 1, 0},
|
||||
{"p0", 0x80, 0xFF, 1, 0},
|
||||
{"p1", 0x90, 0xFF, 1, 0},
|
||||
{"p2", 0xA0, 0xFF, 1, 0},
|
||||
{"p3", 0xB0, 0xFF, 1, 0},
|
||||
{"pcon", 0x87, 0x00, 1, 0},
|
||||
{"psw", 0xD0, 0x00, 1, 0},
|
||||
{"r0", 0x00, 0x00, 1, 1},
|
||||
{"r1", 0x01, 0x00, 1, 1},
|
||||
{"r2", 0x02, 0x00, 1, 1},
|
||||
{"r3", 0x03, 0x00, 1, 1},
|
||||
{"r4", 0x04, 0x00, 1, 1},
|
||||
{"r5", 0x05, 0x00, 1, 1},
|
||||
{"r6", 0x06, 0x00, 1, 1},
|
||||
{"r7", 0x07, 0x00, 1, 1},
|
||||
{"sbuf", 0x99, 0x00, 1, 0},
|
||||
{"scon", 0x98, 0x00, 1, 0},
|
||||
{"sp", 0x81, 0x07, 1, 0},
|
||||
{"tcon", 0x88, 0x00, 1, 0},
|
||||
{"th0", 0x8C, 0x00, 1, 0},
|
||||
{"th1", 0x8D, 0x00, 1, 0},
|
||||
{"tl0", 0x8A, 0x00, 1, 0},
|
||||
{"tl1", 0x8B, 0x00, 1, 0},
|
||||
{"tmod", 0x89, 0x00, 1, 0}
|
||||
{ "a", 0xE0, 0x00, 1, 0},
|
||||
{ "b", 0xF0, 0x00, 1, 0},
|
||||
{ "dph", 0x83, 0x00, 1, 0},
|
||||
{ "dpl", 0x82, 0x00, 1, 0},
|
||||
{ "dptr", 0x82, 0x00, 2, 0, 1},
|
||||
{ "ie", 0xA8, 0x00, 1, 0},
|
||||
{ "ip", 0xB8, 0x00, 1, 0},
|
||||
{ "p0", 0x80, 0xFF, 1, 0},
|
||||
{ "p1", 0x90, 0xFF, 1, 0},
|
||||
{ "p2", 0xA0, 0xFF, 1, 0},
|
||||
{ "p3", 0xB0, 0xFF, 1, 0},
|
||||
{ "pcon", 0x87, 0x00, 1, 0},
|
||||
{ "psw", 0xD0, 0x00, 1, 0},
|
||||
{ "r0", 0x00, 0x00, 1, 1},
|
||||
{ "r1", 0x01, 0x00, 1, 1},
|
||||
{ "r2", 0x02, 0x00, 1, 1},
|
||||
{ "r3", 0x03, 0x00, 1, 1},
|
||||
{ "r4", 0x04, 0x00, 1, 1},
|
||||
{ "r5", 0x05, 0x00, 1, 1},
|
||||
{ "r6", 0x06, 0x00, 1, 1},
|
||||
{ "r7", 0x07, 0x00, 1, 1},
|
||||
{ "sbuf", 0x99, 0x00, 1, 0},
|
||||
{ "scon", 0x98, 0x00, 1, 0},
|
||||
{ "sp", 0x81, 0x07, 1, 0},
|
||||
{ "tcon", 0x88, 0x00, 1, 0},
|
||||
{ "th0", 0x8C, 0x00, 1, 0},
|
||||
{ "th1", 0x8D, 0x00, 1, 0},
|
||||
{ "tl0", 0x8A, 0x00, 1, 0},
|
||||
{ "tl1", 0x8B, 0x00, 1, 0},
|
||||
{ "tmod", 0x89, 0x00, 1, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,9 @@
|
|||
/* radare - LGPL - Copyright 2012 - pancake<nopcode.org>
|
||||
2022 - condret
|
||||
|
||||
/* radare - LGPL - Copyright 2012 - pancake<nopcode.org> 2022 - condret
|
||||
this file was based on anal_i8080.c */
|
||||
|
||||
#include <string.h>
|
||||
#include <r_types.h>
|
||||
#include <r_util.h>
|
||||
#include <r_asm.h>
|
||||
#include <r_anal.h>
|
||||
#include <r_reg.h>
|
||||
#include "gb/gbdis.c"
|
||||
#include "gb/gbasm.c"
|
||||
#include "gb/gb_makros.h"
|
||||
|
|
@ -16,11 +11,11 @@
|
|||
#include "gb/gb_makros.h"
|
||||
#include "gb/gb.h"
|
||||
|
||||
static const char *regs_1[] = { "Z", "N", "H", "C"};
|
||||
static const char *regs_8[] = { "b", "c", "d", "e", "h", "l", "a", "a"}; //deprecate this and rename regs_x
|
||||
static const char *regs_x[] = { "b", "c", "d", "e", "h", "l", "hl", "a"};
|
||||
static const char *regs_16[] = { "bc", "de", "hl", "sp"};
|
||||
static const char *regs_16_alt[] = { "bc", "de", "hl", "af" };
|
||||
static const char * const regs_1[] = { "Z", "N", "H", "C" };
|
||||
static const char * const regs_8[] = { "b", "c", "d", "e", "h", "l", "a", "a" }; //deprecate this and rename regs_x
|
||||
static const char * const regs_x[] = { "b", "c", "d", "e", "h", "l", "hl", "a" };
|
||||
static const char * const regs_16[] = { "bc", "de", "hl", "sp" };
|
||||
static const char * const regs_16_alt[] = { "bc", "de", "hl", "af" };
|
||||
|
||||
static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr) {
|
||||
if (GB_IS_RAM_DST (data[1],data[2])) {
|
||||
|
|
@ -36,11 +31,11 @@ static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr) {
|
|||
return true;
|
||||
}
|
||||
|
||||
#if 0
|
||||
#if 0
|
||||
static inline int gb_anal_esil_banksw(RAnalOp *op) {
|
||||
ut64 base = op->dst->base;
|
||||
if (op->addr < 0x4000 && 0x1fff < base && base < 0x4000) {
|
||||
r_strbuf_set (&op->esil, "mbcrom=0,?a%0x20,mbcrom=a-1"); //if a is a multiple of 0x20 mbcrom is 0, else it gets its value from a
|
||||
r_strbuf_set (&op->esil, "mbcrom=0,?a%0x20,mbcrom=a-1"); //if a is a multiple of 0x20 mbcrom is 0, else it gets its value from a
|
||||
return true;
|
||||
}
|
||||
if (base < 0x6000 && 0x3fff < base) {
|
||||
|
|
@ -470,7 +465,7 @@ static void gb_anal_xoaasc_imm(RReg *reg, RAnalOp *op, const ut8 *data) {
|
|||
}
|
||||
}
|
||||
|
||||
//load with [hl] as memref
|
||||
//load with [hl] as memref
|
||||
static inline void gb_anal_load_hl(RReg *reg, RAnalOp *op, const ut8 data) {
|
||||
RAnalValue *dst, *src;
|
||||
dst = r_vector_push (op->dsts, NULL);
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ static ut64 disarm_8bit_offset(ut64 pc, ut32 offs) {
|
|||
return (off << 1) + pc + 4;
|
||||
}
|
||||
|
||||
static char *regs[]={"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","pc"};
|
||||
static char *regs[]={ "r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","pc" };
|
||||
|
||||
static RAnalValue *anal_fill_ai_rg(RAnal *anal, int idx) {
|
||||
RAnalValue *ret = r_anal_value_new ();
|
||||
|
|
|
|||
|
|
@ -347,7 +347,7 @@ static int cond_x862r2(int id) {
|
|||
|
||||
/* reg indices are based on Intel doc for 32-bit ModR/M byte */
|
||||
static const char *reg32_to_name(ut8 reg) {
|
||||
const char * const names[] = {"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
|
||||
const char * const names[] = { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi" };
|
||||
return reg < R_ARRAY_SIZE (names) ? names[reg] : "unk";
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -279,16 +279,16 @@ struct op_family {
|
|||
int id;
|
||||
};
|
||||
static const struct op_family of[] = {
|
||||
{"cpu", R_ARCH_OP_FAMILY_CPU},
|
||||
{"fpu", R_ARCH_OP_FAMILY_FPU},
|
||||
{"mmx", R_ARCH_OP_FAMILY_MMX},
|
||||
{"sse", R_ARCH_OP_FAMILY_SSE},
|
||||
{"priv", R_ARCH_OP_FAMILY_PRIV},
|
||||
{"virt", R_ARCH_OP_FAMILY_VIRT},
|
||||
{"crpt", R_ARCH_OP_FAMILY_CRYPTO},
|
||||
{"io", R_ARCH_OP_FAMILY_IO},
|
||||
{"sec", R_ARCH_OP_FAMILY_SECURITY},
|
||||
{"thread", R_ARCH_OP_FAMILY_THREAD},
|
||||
{ "cpu", R_ARCH_OP_FAMILY_CPU},
|
||||
{ "fpu", R_ARCH_OP_FAMILY_FPU},
|
||||
{ "mmx", R_ARCH_OP_FAMILY_MMX},
|
||||
{ "sse", R_ARCH_OP_FAMILY_SSE},
|
||||
{ "priv", R_ARCH_OP_FAMILY_PRIV},
|
||||
{ "virt", R_ARCH_OP_FAMILY_VIRT},
|
||||
{ "crpt", R_ARCH_OP_FAMILY_CRYPTO},
|
||||
{ "io", R_ARCH_OP_FAMILY_IO},
|
||||
{ "sec", R_ARCH_OP_FAMILY_SECURITY},
|
||||
{ "thread", R_ARCH_OP_FAMILY_THREAD},
|
||||
};
|
||||
|
||||
R_API int r_arch_op_family_from_string(const char *f) {
|
||||
|
|
|
|||
|
|
@ -24,200 +24,200 @@
|
|||
|
||||
const struct aarch64_operand aarch64_operands[] =
|
||||
{
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {0}, "the second reg of a pair"},
|
||||
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional extension"},
|
||||
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional shift"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"},
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"},
|
||||
{AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector element list"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a left shift amount for an AdvSIMD register"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a right shift amount for an AdvSIMD register"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit unsigned immediate with optional shift"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit floating-point constant"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {0}, "an immediate shift amount of 8, 16 or 32"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {0}, "0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {0}, "0.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {0}, "an immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a condition"},
|
||||
{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "one of the standard conditions, excluding AL and NV."},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a post-indexed address with immediate or register increment"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a system register"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a PSTATE field name"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address translation operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a data cache maintenance operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an instruction cache maintenance operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a TBL invalidation operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a barrier option name"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a prefetch operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the PSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {0}, "the second reg of a pair" },
|
||||
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional extension" },
|
||||
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an integer register with optional shift" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register" },
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register" },
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register" },
|
||||
{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register" },
|
||||
{AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element" },
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element" },
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element" },
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector register list" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a SIMD vector element list" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a left shift amount for an AdvSIMD register" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a right shift amount for an AdvSIMD register" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit unsigned immediate with optional shift" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an 8-bit floating-point constant" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {0}, "an immediate shift amount of 8, 16 or 32" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {0}, "0" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {0}, "0.0" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {0}, "an immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations" },
|
||||
{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a condition" },
|
||||
{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "one of the standard conditions, excluding AL and NV." },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address with base register (no offset)" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a post-indexed address with immediate or register increment" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a system register" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a PSTATE field name" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an address translation operation specifier" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a data cache maintenance operation specifier" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "an instruction cache maintenance operation specifier" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a TBL invalidation operation specifier" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a barrier option name" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the ISB option name SY or an optional 4-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "a prefetch operation specifier" },
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {0}, "the PSB option name CSYNC" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero" },
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register" },
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register" },
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers" },
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate" },
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY" },
|
||||
};
|
||||
|
||||
/* Indexed by an enum aarch64_op enumerator, the value is the offset of
|
||||
|
|
|
|||
|
|
@ -344,22 +344,22 @@ aarch64_get_operand_desc (enum aarch64_opnd type)
|
|||
/* Table of all conditional affixes. */
|
||||
const aarch64_cond aarch64_conds[16] =
|
||||
{
|
||||
{{"eq", "none"}, 0x0},
|
||||
{{"ne", "any"}, 0x1},
|
||||
{{"cs", "hs", "nlast"}, 0x2},
|
||||
{{"cc", "lo", "ul", "last"}, 0x3},
|
||||
{{"mi", "first"}, 0x4},
|
||||
{{"pl", "nfrst"}, 0x5},
|
||||
{{"vs"}, 0x6},
|
||||
{{"vc"}, 0x7},
|
||||
{{"hi", "pmore"}, 0x8},
|
||||
{{"ls", "plast"}, 0x9},
|
||||
{{"ge", "tcont"}, 0xa},
|
||||
{{"lt", "tstop"}, 0xb},
|
||||
{{"gt"}, 0xc},
|
||||
{{"le"}, 0xd},
|
||||
{{"al"}, 0xe},
|
||||
{{"nv"}, 0xf},
|
||||
{{ "eq", "none" }, 0x0},
|
||||
{{ "ne", "any" }, 0x1},
|
||||
{{ "cs", "hs", "nlast" }, 0x2},
|
||||
{{ "cc", "lo", "ul", "last" }, 0x3},
|
||||
{{ "mi", "first" }, 0x4},
|
||||
{{ "pl", "nfrst" }, 0x5},
|
||||
{{ "vs" }, 0x6},
|
||||
{{ "vc" }, 0x7},
|
||||
{{ "hi", "pmore" }, 0x8},
|
||||
{{ "ls", "plast" }, 0x9},
|
||||
{{ "ge", "tcont" }, 0xa},
|
||||
{{ "lt", "tstop" }, 0xb},
|
||||
{{ "gt" }, 0xc},
|
||||
{{ "le" }, 0xd},
|
||||
{{ "al" }, 0xe},
|
||||
{{ "nv" }, 0xf},
|
||||
};
|
||||
|
||||
const aarch64_cond *
|
||||
|
|
@ -382,22 +382,22 @@ get_inverted_cond (const aarch64_cond *cond)
|
|||
which enables table-driven encoding/decoding for the modifiers. */
|
||||
const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
|
||||
{
|
||||
{"none", 0x0},
|
||||
{"msl", 0x0},
|
||||
{"ror", 0x3},
|
||||
{"asr", 0x2},
|
||||
{"lsr", 0x1},
|
||||
{"lsl", 0x0},
|
||||
{"uxtb", 0x0},
|
||||
{"uxth", 0x1},
|
||||
{"uxtw", 0x2},
|
||||
{"uxtx", 0x3},
|
||||
{"sxtb", 0x4},
|
||||
{"sxth", 0x5},
|
||||
{"sxtw", 0x6},
|
||||
{"sxtx", 0x7},
|
||||
{"mul", 0x0},
|
||||
{"mul vl", 0x0},
|
||||
{ "none", 0x0},
|
||||
{ "msl", 0x0},
|
||||
{ "ror", 0x3},
|
||||
{ "asr", 0x2},
|
||||
{ "lsr", 0x1},
|
||||
{ "lsl", 0x0},
|
||||
{ "uxtb", 0x0},
|
||||
{ "uxth", 0x1},
|
||||
{ "uxtw", 0x2},
|
||||
{ "uxtx", 0x3},
|
||||
{ "sxtb", 0x4},
|
||||
{ "sxth", 0x5},
|
||||
{ "sxtw", 0x6},
|
||||
{ "sxtx", 0x7},
|
||||
{ "mul", 0x0},
|
||||
{ "mul vl", 0x0},
|
||||
{NULL, 0},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3070,7 +3070,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
|
||||
__FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
|
||||
__FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
|
||||
{"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL },
|
||||
{ "fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL },
|
||||
/* Floating-point conditional compare. */
|
||||
__FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
|
||||
FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),
|
||||
|
|
@ -3250,13 +3250,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
|
||||
CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
{"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
|
||||
{ "ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
|
||||
/* Load/store register pair (indexed). */
|
||||
CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
|
||||
CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
|
||||
CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
|
||||
{"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
|
||||
{ "ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
|
||||
/* Load register (literal). */
|
||||
CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
|
||||
CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
|
||||
|
|
@ -3480,8 +3480,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS),
|
||||
V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS),
|
||||
V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {{0}}, F_ALIAS),
|
||||
{"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {{0}}, F_ALIAS, 0, NULL},
|
||||
{"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {{0}}, F_ALIAS, 0, NULL},
|
||||
{ "esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {{0}}, F_ALIAS, 0, NULL},
|
||||
{ "psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {{0}}, F_ALIAS, 0, NULL},
|
||||
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {{0}}, F_OPD0_OPT | F_DEFAULT (0xF)),
|
||||
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {{0}}, F_HAS_ALIAS),
|
||||
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {{0}}, F_ALIAS),
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ static int strcmpnull(const char *a, const char *b) {
|
|||
return (a && b) ? strcmp (a, b) : -1;
|
||||
}
|
||||
|
||||
// static const char *const arm_shift[] = {"lsl", "lsr", "asr", "ror"};
|
||||
// static const char *const arm_shift[] = { "lsl", "lsr", "asr", "ror" };
|
||||
|
||||
static ArmOp ops[] = {
|
||||
{ "adc", 0xa000, TYPE_ARI },
|
||||
|
|
@ -136,18 +136,18 @@ static ArmOp ops[] = {
|
|||
{ "teq", 0x3001, TYPE_TST },
|
||||
{ "tst", 0x1001, TYPE_TST },
|
||||
|
||||
{"lsr", 0x3000a0e1, TYPE_SHFT},
|
||||
{"asr", 0x5000a0e1, TYPE_SHFT},
|
||||
{"lsl", 0x1000a0e1, TYPE_SHFT},
|
||||
{"ror", 0x7000a0e1, TYPE_SHFT},
|
||||
{ "lsr", 0x3000a0e1, TYPE_SHFT},
|
||||
{ "asr", 0x5000a0e1, TYPE_SHFT},
|
||||
{ "lsl", 0x1000a0e1, TYPE_SHFT},
|
||||
{ "ror", 0x7000a0e1, TYPE_SHFT},
|
||||
|
||||
{"rev16", 0xb00fbf06, TYPE_REV},
|
||||
{"revsh", 0xb00fff06, TYPE_REV},
|
||||
{"rev", 0x300fbf06, TYPE_REV},
|
||||
{"rbit", 0x300fff06, TYPE_REV},
|
||||
{ "rev16", 0xb00fbf06, TYPE_REV},
|
||||
{ "revsh", 0xb00fff06, TYPE_REV},
|
||||
{ "rev", 0x300fbf06, TYPE_REV},
|
||||
{ "rbit", 0x300fff06, TYPE_REV},
|
||||
|
||||
{"mrc", 0x100010ee, TYPE_COPROC},
|
||||
{"setend", 0x000001f1, TYPE_ENDIAN},
|
||||
{ "mrc", 0x100010ee, TYPE_COPROC},
|
||||
{ "setend", 0x000001f1, TYPE_ENDIAN},
|
||||
{ "clz", 0x000f6f01, TYPE_CLZ},
|
||||
{ "neg", 0x7000, TYPE_NEG },
|
||||
|
||||
|
|
|
|||
|
|
@ -87,9 +87,11 @@ typedef struct Opcode_t {
|
|||
|
||||
static int get_mem_option(char *token) {
|
||||
// values 4, 8, 12, are unused. XXX to adjust
|
||||
const char *options[] = {"sy", "st", "ld", "xxx", "ish", "ishst",
|
||||
"ishld", "xxx", "nsh", "nshst", "nshld",
|
||||
"xxx", "osh", "oshst", "oshld", NULL};
|
||||
const char *options[] = {
|
||||
"sy", "st", "ld", "xxx", "ish", "ishst",
|
||||
"ishld", "xxx", "nsh", "nshst", "nshld",
|
||||
"xxx", "osh", "oshst", "oshld", NULL
|
||||
};
|
||||
int i = 0;
|
||||
while (options[i]) {
|
||||
if (!r_str_casecmp (token, options[i])) {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -35,9 +35,9 @@ static int getnum(const char *s) {
|
|||
|
||||
// radare tolower instruction in rasm, so we use 'x' instead of 'X' etc.
|
||||
specialregs RegsTable[REGS_TABLE] = {
|
||||
{"-x", OPERAND_XP}, {"x", OPERAND_X}, {"x+", OPERAND_XP},
|
||||
{"-y", OPERAND_YP}, {"y", OPERAND_Y}, {"y+", OPERAND_YP},
|
||||
{"-z", OPERAND_ZP}, {"z", OPERAND_Z}, {"z+", OPERAND_ZP},
|
||||
{ "-x", OPERAND_XP}, { "x", OPERAND_X}, { "x+", OPERAND_XP},
|
||||
{ "-y", OPERAND_YP}, { "y", OPERAND_Y}, { "y+", OPERAND_YP},
|
||||
{ "-z", OPERAND_ZP}, { "z", OPERAND_Z}, { "z+", OPERAND_ZP},
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -44,150 +44,150 @@
|
|||
*/
|
||||
|
||||
instructionInfo instructionSet[AVR_TOTAL_INSTRUCTIONS] = {
|
||||
{"break", 0x9598, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"clc", 0x9488, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"clh", 0x94d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"cli", 0x94f8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"cln", 0x94a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"cls", 0x94c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"clt", 0x94e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"clv", 0x94b8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"clz", 0x9498, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"eicall", 0x9519, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"eijmp", 0x9419, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"elpm", 0x95d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"icall", 0x9509, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"ijmp", 0x9409, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"lpm", 0x95c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"nop", 0x0000, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"ret", 0x9508, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"reti", 0x9518, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sec", 0x9408, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"seh", 0x9458, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sei", 0x9478, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sen", 0x9428, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"ses", 0x9448, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"set", 0x9468, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sev", 0x9438, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sez", 0x9418, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"sleep", 0x9588, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"spm", 0x95e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"spm", 0x95f8, 1, {0x0000, 0x0000}, {OPERAND_ZP, OPERAND_NONE}},
|
||||
{"wdr", 0x95a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{"des", 0x940b, 1, {0x00f0, 0x0000}, {OPERAND_DES_ROUND, OPERAND_NONE}},
|
||||
{"asr", 0x9405, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"bclr", 0x9488, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}},
|
||||
{"brcc", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brcs", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"breq", 0xf001, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brge", 0xf404, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brhc", 0xf405, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brhs", 0xf005, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brid", 0xf407, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brie", 0xf007, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brlo", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brlt", 0xf004, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brmi", 0xf002, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brne", 0xf401, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brpl", 0xf402, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brsh", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brtc", 0xf406, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brts", 0xf006, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brvc", 0xf403, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"brvs", 0xf003, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{"bset", 0x9408, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}},
|
||||
{"call", 0x940e, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}},
|
||||
{"clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{"com", 0x9400, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"dec", 0x940a, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"inc", 0x9403, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"jmp", 0x940c, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}},
|
||||
{"lpm", 0x9004, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{"lpm", 0x9005, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{"lsl", 0x0c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{"lsr", 0x9406, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"neg", 0x9401, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"pop", 0x900f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"xch", 0x9204, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{"las", 0x9205, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{"lac", 0x9206, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{"lat", 0x9207, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{"push", 0x920f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"rcall", 0xd000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}},
|
||||
{"rjmp", 0xc000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}},
|
||||
{"rol", 0x1c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{"ror", 0x9407, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"ser", 0xef0f, 1, {0x00f0, 0x0000}, {OPERAND_REGISTER_STARTR16, OPERAND_NONE}},
|
||||
{"swap", 0x9402, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{"tst", 0x2000, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{ "break", 0x9598, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "clc", 0x9488, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "clh", 0x94d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "cli", 0x94f8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "cln", 0x94a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "cls", 0x94c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "clt", 0x94e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "clv", 0x94b8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "clz", 0x9498, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "eicall", 0x9519, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "eijmp", 0x9419, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "elpm", 0x95d8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "icall", 0x9509, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "ijmp", 0x9409, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "lpm", 0x95c8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "nop", 0x0000, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "ret", 0x9508, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "reti", 0x9518, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sec", 0x9408, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "seh", 0x9458, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sei", 0x9478, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sen", 0x9428, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "ses", 0x9448, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "set", 0x9468, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sev", 0x9438, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sez", 0x9418, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "sleep", 0x9588, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "spm", 0x95e8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "spm", 0x95f8, 1, {0x0000, 0x0000}, {OPERAND_ZP, OPERAND_NONE}},
|
||||
{ "wdr", 0x95a8, 0, {0x0000, 0x0000}, {OPERAND_NONE, OPERAND_NONE}},
|
||||
{ "des", 0x940b, 1, {0x00f0, 0x0000}, {OPERAND_DES_ROUND, OPERAND_NONE}},
|
||||
{ "asr", 0x9405, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "bclr", 0x9488, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}},
|
||||
{ "brcc", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brcs", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "breq", 0xf001, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brge", 0xf404, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brhc", 0xf405, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brhs", 0xf005, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brid", 0xf407, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brie", 0xf007, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brlo", 0xf000, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brlt", 0xf004, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brmi", 0xf002, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brne", 0xf401, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brpl", 0xf402, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brsh", 0xf400, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brtc", 0xf406, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brts", 0xf006, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brvc", 0xf403, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "brvs", 0xf003, 1, {0x03f8, 0x0000}, {OPERAND_BRANCH_ADDRESS, OPERAND_NONE}},
|
||||
{ "bset", 0x9408, 1, {0x0070, 0x0000}, {OPERAND_BIT, OPERAND_NONE}},
|
||||
{ "call", 0x940e, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}},
|
||||
{ "clr", 0x2400, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{ "com", 0x9400, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "dec", 0x940a, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "inc", 0x9403, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "jmp", 0x940c, 1, {0x01f1, 0x0000}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_NONE}},
|
||||
{ "lpm", 0x9004, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{ "lpm", 0x9005, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{ "lsl", 0x0c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{ "lsr", 0x9406, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "neg", 0x9401, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "pop", 0x900f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "xch", 0x9204, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{ "las", 0x9205, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{ "lac", 0x9206, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{ "lat", 0x9207, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{ "push", 0x920f, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "rcall", 0xd000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}},
|
||||
{ "rjmp", 0xc000, 1, {0x0fff, 0x0000}, {OPERAND_RELATIVE_ADDRESS, OPERAND_NONE}},
|
||||
{ "rol", 0x1c00, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
{ "ror", 0x9407, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "ser", 0xef0f, 1, {0x00f0, 0x0000}, {OPERAND_REGISTER_STARTR16, OPERAND_NONE}},
|
||||
{ "swap", 0x9402, 1, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_NONE}},
|
||||
{ "tst", 0x2000, 1, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER_GHOST}},
|
||||
|
||||
{"adc", 0x1c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"add", 0x0c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"adiw", 0x9600, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}},
|
||||
{"and", 0x2000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"andi", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"bld", 0xf800, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{"brbc", 0xf400, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}},
|
||||
{"brbs", 0xf000, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}},
|
||||
{"bst", 0xfa00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{"cbi", 0x9800, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{"cbr", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_COMPLEMENTED_DATA}},
|
||||
{"cp", 0x1400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"cpc", 0x0400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"cpi", 0x3000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"cpse", 0x1000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"elpm", 0x9006, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{"elpm", 0x9007, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{"eor", 0x2400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"fmul", 0x0308, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{"fmuls", 0x0380, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{"fmulsu", 0x0388, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{"in", 0xb000, 2, {0x01f0, 0x060f}, {OPERAND_REGISTER, OPERAND_DATA}},
|
||||
{"ld", 0x900c, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_X}},
|
||||
{"ld", 0x900d, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_XP}},
|
||||
{"ld", 0x900e, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MX}},
|
||||
{"ld", 0x8008, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Y}},
|
||||
{"ld", 0x9009, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_YP}},
|
||||
{"ld", 0x900a, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MY}},
|
||||
{"ld", 0x8000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{"ld", 0x9001, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{"ld", 0x9002, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MZ}},
|
||||
{"ldd", 0x8008, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_YPQ}},
|
||||
{"ldd", 0x8000, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_ZPQ}},
|
||||
{"ldi", 0xe000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"std", 0x8208, 2, {0x2c07, 0x01f0}, {OPERAND_YPQ, OPERAND_REGISTER}},
|
||||
{"std", 0x8200, 2, {0x2c07, 0x01f0}, {OPERAND_ZPQ, OPERAND_REGISTER}},
|
||||
{"lds", 0x9000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_LONG_ABSOLUTE_ADDRESS}},
|
||||
{"lds", 0xA000, 2, {0x00f0, 0x070f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"mov", 0x2c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"movw", 0x0100, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_EVEN_PAIR, OPERAND_REGISTER_EVEN_PAIR}},
|
||||
{"mul", 0x9c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"muls", 0x0200, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{"mulsu", 0x0300, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{"or", 0x2800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"ori", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"out", 0xb800, 2, {0x060f, 0x01f0}, {OPERAND_IO_REGISTER, OPERAND_REGISTER}},
|
||||
{"sbc", 0x0800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"sbci", 0x4000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"sbi", 0x9a00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{"sbic", 0x9900, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{"sbis", 0x9b00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{"sbiw", 0x9700, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}},
|
||||
{"sbr", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{"sbrc", 0xfc00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{"sbrs", 0xfe00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{"st", 0x920c, 2, {0x0000, 0x01f0}, {OPERAND_X, OPERAND_REGISTER}},
|
||||
{"st", 0x920d, 2, {0x0000, 0x01f0}, {OPERAND_XP, OPERAND_REGISTER}},
|
||||
{"st", 0x920e, 2, {0x0000, 0x01f0}, {OPERAND_MX, OPERAND_REGISTER}},
|
||||
{"st", 0x8208, 2, {0x0000, 0x01f0}, {OPERAND_Y, OPERAND_REGISTER}},
|
||||
{"st", 0x9209, 2, {0x0000, 0x01f0}, {OPERAND_YP, OPERAND_REGISTER}},
|
||||
{"st", 0x920a, 2, {0x0000, 0x01f0}, {OPERAND_MY, OPERAND_REGISTER}},
|
||||
{"st", 0x8200, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{"st", 0x9201, 2, {0x0000, 0x01f0}, {OPERAND_ZP, OPERAND_REGISTER}},
|
||||
{"st", 0x9202, 2, {0x0000, 0x01f0}, {OPERAND_MZ, OPERAND_REGISTER}},
|
||||
{"sts", 0x9200, 2, {0x0000, 0x01f0}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_REGISTER}},
|
||||
{"sts", 0xA800, 2, {0x00f0, 0x070f}, {OPERAND_DATA, OPERAND_REGISTER_STARTR16}}, // was {OPERAND_REGISTER_STARTR16, OPERAND_DATA}, bug?
|
||||
{"sub", 0x1800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{"subi", 0x5000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{".word", 0x0000, 1, {0xFFFF, 0x0000}, {OPERAND_WORD_DATA, OPERAND_NONE}},
|
||||
{ "adc", 0x1c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "add", 0x0c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "adiw", 0x9600, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}},
|
||||
{ "and", 0x2000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "andi", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "bld", 0xf800, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{ "brbc", 0xf400, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}},
|
||||
{ "brbs", 0xf000, 2, {0x0007, 0x03f8}, {OPERAND_BIT, OPERAND_BRANCH_ADDRESS}},
|
||||
{ "bst", 0xfa00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{ "cbi", 0x9800, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{ "cbr", 0x7000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_COMPLEMENTED_DATA}},
|
||||
{ "cp", 0x1400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "cpc", 0x0400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "cpi", 0x3000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "cpse", 0x1000, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "elpm", 0x9006, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{ "elpm", 0x9007, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{ "eor", 0x2400, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "fmul", 0x0308, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{ "fmuls", 0x0380, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{ "fmulsu", 0x0388, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{ "in", 0xb000, 2, {0x01f0, 0x060f}, {OPERAND_REGISTER, OPERAND_DATA}},
|
||||
{ "ld", 0x900c, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_X}},
|
||||
{ "ld", 0x900d, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_XP}},
|
||||
{ "ld", 0x900e, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MX}},
|
||||
{ "ld", 0x8008, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Y}},
|
||||
{ "ld", 0x9009, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_YP}},
|
||||
{ "ld", 0x900a, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MY}},
|
||||
{ "ld", 0x8000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_Z}},
|
||||
{ "ld", 0x9001, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_ZP}},
|
||||
{ "ld", 0x9002, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_MZ}},
|
||||
{ "ldd", 0x8008, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_YPQ}},
|
||||
{ "ldd", 0x8000, 2, {0x01f0, 0x2c07}, {OPERAND_REGISTER, OPERAND_ZPQ}},
|
||||
{ "ldi", 0xe000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "std", 0x8208, 2, {0x2c07, 0x01f0}, {OPERAND_YPQ, OPERAND_REGISTER}},
|
||||
{ "std", 0x8200, 2, {0x2c07, 0x01f0}, {OPERAND_ZPQ, OPERAND_REGISTER}},
|
||||
{ "lds", 0x9000, 2, {0x01f0, 0x0000}, {OPERAND_REGISTER, OPERAND_LONG_ABSOLUTE_ADDRESS}},
|
||||
{ "lds", 0xA000, 2, {0x00f0, 0x070f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "mov", 0x2c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "movw", 0x0100, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_EVEN_PAIR, OPERAND_REGISTER_EVEN_PAIR}},
|
||||
{ "mul", 0x9c00, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "muls", 0x0200, 2, {0x00f0, 0x000f}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{ "mulsu", 0x0300, 2, {0x0070, 0x0007}, {OPERAND_REGISTER_STARTR16, OPERAND_REGISTER_STARTR16}},
|
||||
{ "or", 0x2800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "ori", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "out", 0xb800, 2, {0x060f, 0x01f0}, {OPERAND_IO_REGISTER, OPERAND_REGISTER}},
|
||||
{ "sbc", 0x0800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "sbci", 0x4000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "sbi", 0x9a00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{ "sbic", 0x9900, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{ "sbis", 0x9b00, 2, {0x00f8, 0x0007}, {OPERAND_IO_REGISTER, OPERAND_BIT}},
|
||||
{ "sbiw", 0x9700, 2, {0x0030, 0x00cf}, {OPERAND_REGISTER_EVEN_PAIR_STARTR24, OPERAND_DATA}},
|
||||
{ "sbr", 0x6000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ "sbrc", 0xfc00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{ "sbrs", 0xfe00, 2, {0x01f0, 0x0007}, {OPERAND_REGISTER, OPERAND_BIT}},
|
||||
{ "st", 0x920c, 2, {0x0000, 0x01f0}, {OPERAND_X, OPERAND_REGISTER}},
|
||||
{ "st", 0x920d, 2, {0x0000, 0x01f0}, {OPERAND_XP, OPERAND_REGISTER}},
|
||||
{ "st", 0x920e, 2, {0x0000, 0x01f0}, {OPERAND_MX, OPERAND_REGISTER}},
|
||||
{ "st", 0x8208, 2, {0x0000, 0x01f0}, {OPERAND_Y, OPERAND_REGISTER}},
|
||||
{ "st", 0x9209, 2, {0x0000, 0x01f0}, {OPERAND_YP, OPERAND_REGISTER}},
|
||||
{ "st", 0x920a, 2, {0x0000, 0x01f0}, {OPERAND_MY, OPERAND_REGISTER}},
|
||||
{ "st", 0x8200, 2, {0x0000, 0x01f0}, {OPERAND_Z, OPERAND_REGISTER}},
|
||||
{ "st", 0x9201, 2, {0x0000, 0x01f0}, {OPERAND_ZP, OPERAND_REGISTER}},
|
||||
{ "st", 0x9202, 2, {0x0000, 0x01f0}, {OPERAND_MZ, OPERAND_REGISTER}},
|
||||
{ "sts", 0x9200, 2, {0x0000, 0x01f0}, {OPERAND_LONG_ABSOLUTE_ADDRESS, OPERAND_REGISTER}},
|
||||
{ "sts", 0xA800, 2, {0x00f0, 0x070f}, {OPERAND_DATA, OPERAND_REGISTER_STARTR16}}, // was {OPERAND_REGISTER_STARTR16, OPERAND_DATA}, bug?
|
||||
{ "sub", 0x1800, 2, {0x01f0, 0x020f}, {OPERAND_REGISTER, OPERAND_REGISTER}},
|
||||
{ "subi", 0x5000, 2, {0x00f0, 0x0f0f}, {OPERAND_REGISTER_STARTR16, OPERAND_DATA}},
|
||||
{ ".word", 0x0000, 1, {0xFFFF, 0x0000}, {OPERAND_WORD_DATA, OPERAND_NONE}},
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -112,11 +112,11 @@ static const char *const wide_add_cond_names[] =
|
|||
static const char *const logical_cond_names[] =
|
||||
{
|
||||
"", ",=", ",<", ",<=", 0, 0, 0, ",od",
|
||||
",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
|
||||
",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev" };
|
||||
static const char *const logical_cond_64_names[] =
|
||||
{
|
||||
",*", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od",
|
||||
",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"};
|
||||
",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev" };
|
||||
static const char *const unit_cond_names[] =
|
||||
{
|
||||
"", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc",
|
||||
|
|
@ -139,15 +139,15 @@ static const char *const bb_cond_64_names[] =
|
|||
{
|
||||
",*<", ",*>="
|
||||
};
|
||||
static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"};
|
||||
static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"};
|
||||
static const char *const index_compl_names[] = { "", ",m", ",s", ",sm" };
|
||||
static const char *const short_ldst_compl_names[] = { "", ",ma", "", ",mb" };
|
||||
static const char *const short_bytes_compl_names[] =
|
||||
{
|
||||
"", ",b,m", ",e", ",e,m"
|
||||
};
|
||||
static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
|
||||
static const char *const fcnv_fixed_names[] = {",w", ",dw", "", ",qw"};
|
||||
static const char *const fcnv_ufixed_names[] = {",uw", ",udw", "", ",uqw"};
|
||||
static const char *const float_format_names[] = { ",sgl", ",dbl", "", ",quad" };
|
||||
static const char *const fcnv_fixed_names[] = { ",w", ",dw", "", ",qw" };
|
||||
static const char *const fcnv_ufixed_names[] = { ",uw", ",udw", "", ",uqw" };
|
||||
static const char *const float_comp_names[] =
|
||||
{
|
||||
",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
|
||||
|
|
@ -155,10 +155,10 @@ static const char *const float_comp_names[] =
|
|||
",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
|
||||
",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
|
||||
};
|
||||
static const char *const signed_unsigned_names[] = {",u", ",s"};
|
||||
static const char *const mix_half_names[] = {",l", ",r"};
|
||||
static const char *const saturation_names[] = {",us", ",ss", 0, ""};
|
||||
static const char *const read_write_names[] = {",r", ",w"};
|
||||
static const char *const signed_unsigned_names[] = { ",u", ",s" };
|
||||
static const char *const mix_half_names[] = { ",l", ",r" };
|
||||
static const char *const saturation_names[] = { ",us", ",ss", 0, "" };
|
||||
static const char *const read_write_names[] = { ",r", ",w" };
|
||||
static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
|
||||
|
||||
/* For a bunch of different instructions form an index into a
|
||||
|
|
|
|||
|
|
@ -718,35 +718,35 @@ print_insn_arg (const char *d,
|
|||
struct regname { char * name; int value; };
|
||||
static const struct regname names[] =
|
||||
{
|
||||
{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
|
||||
{"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
|
||||
{"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
|
||||
{"%rgpiobar", 0x009}, {"%acr4",0x00c},
|
||||
{"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f},
|
||||
{"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
|
||||
{"%msp", 0x803}, {"%isp", 0x804},
|
||||
{"%pc", 0x80f},
|
||||
{ "%sfc", 0x000}, { "%dfc", 0x001}, { "%cacr", 0x002},
|
||||
{ "%tc", 0x003}, { "%itt0",0x004}, { "%itt1", 0x005},
|
||||
{ "%dtt0",0x006}, { "%dtt1",0x007}, { "%buscr",0x008},
|
||||
{ "%rgpiobar", 0x009}, { "%acr4",0x00c},
|
||||
{ "%acr5",0x00d}, { "%acr6",0x00e}, { "%acr7", 0x00f},
|
||||
{ "%usp", 0x800}, { "%vbr", 0x801}, { "%caar", 0x802},
|
||||
{ "%msp", 0x803}, { "%isp", 0x804},
|
||||
{ "%pc", 0x80f},
|
||||
/* Reg c04 is sometimes called flashbar or rambar.
|
||||
Reg c05 is also sometimes called rambar. */
|
||||
{"%rambar0", 0xc04}, {"%rambar1", 0xc05},
|
||||
{ "%rambar0", 0xc04}, { "%rambar1", 0xc05},
|
||||
|
||||
/* reg c0e is sometimes called mbar2 or secmbar.
|
||||
reg c0f is sometimes called mbar. */
|
||||
{"%mbar0", 0xc0e}, {"%mbar1", 0xc0f},
|
||||
{ "%mbar0", 0xc0e}, { "%mbar1", 0xc0f},
|
||||
|
||||
/* Should we be calling this psr like we do in case 'Y'? */
|
||||
{"%mmusr",0x805},
|
||||
{ "%mmusr",0x805},
|
||||
|
||||
{"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
|
||||
{ "%urp", 0x806}, { "%srp", 0x807}, { "%pcr", 0x808},
|
||||
|
||||
/* Fido added these. */
|
||||
{"%cac", 0xffe}, {"%mbo", 0xfff}
|
||||
{ "%cac", 0xffe}, { "%mbo", 0xfff}
|
||||
};
|
||||
/* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */
|
||||
static const struct regname names_v4e[] =
|
||||
{
|
||||
{"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005},
|
||||
{"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008},
|
||||
{ "%asid",0x003}, { "%acr0",0x004}, { "%acr1",0x005},
|
||||
{ "%acr2",0x006}, { "%acr3",0x007}, { "%mmubar",0x008},
|
||||
};
|
||||
unsigned int arch_mask;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -214,272 +214,272 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
|
|||
const struct mips_opcode mips16_opcodes[] =
|
||||
{
|
||||
/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
|
||||
{"nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */
|
||||
{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
|
||||
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
|
||||
{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
|
||||
{"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
|
||||
{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{"addu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{"addu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{"addu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"andi", "x,u", 0xf0006860, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
|
||||
{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
|
||||
{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
|
||||
{"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
|
||||
{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
{"cache", "T,9(x)", 0xf000d0a0, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
|
||||
{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
|
||||
{"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
|
||||
{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
|
||||
{"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
|
||||
{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"di", "", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{"di", ".", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{"di", "y", 0xf002670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
|
||||
{"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
|
||||
{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
|
||||
{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
|
||||
{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{"ehb", "", 0xf0c03010, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{"ei", "", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{"ei", ".", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{"ei", "y", 0xf003670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
|
||||
{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
|
||||
{"ext", "y,x,b,d", 0xf0203008, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"ins", "y,.,b,c", 0xf0003004, 0xf820ff1f, WR_1, 0, 0, E2, 0 },
|
||||
{"ins", "y,x,b,c", 0xf0203004, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
|
||||
{"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
|
||||
{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
|
||||
{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
|
||||
{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
|
||||
{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
|
||||
{ "nop", "", 0x6500, 0xffff, 0, SH|RD_16|AL, I1, 0, 0 }, /* move $0,$Z */
|
||||
{ "la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
|
||||
{ "abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{ "addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
|
||||
{ "addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{ "addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{ "addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{ "addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{ "addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{ "addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{ "addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
|
||||
{ "addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{ "addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
|
||||
{ "addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{ "addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
|
||||
{ "addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{ "addu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{ "addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{ "addu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{ "addu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "andi", "x,u", 0xf0006860, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{ "b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
|
||||
{ "beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
|
||||
{ "bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
|
||||
{ "break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{ "break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 },
|
||||
{ "bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
{ "btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
|
||||
{ "cache", "T,9(x)", 0xf000d0a0, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
|
||||
{ "cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{ "cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
|
||||
{ "daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{ "daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
|
||||
{ "daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{ "daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{ "daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{ "daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{ "daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
|
||||
{ "daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{ "daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
|
||||
{ "daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{ "daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{ "daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{ "daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{ "ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "di", "", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{ "di", ".", 0xf006670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{ "di", "y", 0xf002670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
|
||||
{ "div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
|
||||
{ "dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
|
||||
{ "dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
|
||||
{ "dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
|
||||
{ "dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
|
||||
{ "dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
|
||||
{ "dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 },
|
||||
{ "ehb", "", 0xf0c03010, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{ "ei", "", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{ "ei", ".", 0xf007670c, 0xffffffff, WR_C0, 0, 0, E2, 0 },
|
||||
{ "ei", "y", 0xf003670c, 0xffffff1f, WR_1|WR_C0, 0, 0, E2, 0 },
|
||||
{ "exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{ "exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{ "exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{ "exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 },
|
||||
{ "entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 },
|
||||
{ "entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 },
|
||||
{ "ext", "y,x,b,d", 0xf0203008, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "ins", "y,.,b,c", 0xf0003004, 0xf820ff1f, WR_1, 0, 0, E2, 0 },
|
||||
{ "ins", "y,x,b,c", 0xf0203004, 0xf820f81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{ "jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{ "jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{ "jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 },
|
||||
{ "jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
|
||||
{ "jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
|
||||
{ "jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
|
||||
{ "jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
|
||||
{ "j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 },
|
||||
{ "j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 },
|
||||
/* MIPS16e compact jumps. We keep them near the ordinary jumps
|
||||
so that we easily find them when converting a normal jump
|
||||
to a compact one. */
|
||||
{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 },
|
||||
{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 },
|
||||
{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 },
|
||||
{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 },
|
||||
{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{"lb", "x,V(G)", 0xf0009060, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{"lbu", "x,V(G)", 0xf00090a0, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
|
||||
{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
|
||||
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{"lh", "x,V(G)", 0xf0009040, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{"lhu", "x,V(G)", 0xf0009080, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"li", "x,U", 0x6800, 0xf800, WR_1, SH, 0, E2, 0 },
|
||||
{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
|
||||
{"li", "x,U", 0xf0006800, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{"ll", "x,9(r)", 0xf00090c0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lui", "x,u", 0xf0006820, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
|
||||
{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{"lw", "x,V(S)", 0xf0009000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{"lw", "x,V(G)", 0xf0009020, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lwl", "x,9(r)", 0xf00090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lwr", "x,9(r)", 0xf01090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
|
||||
{"mfc0", "y,N", 0xf0006700, 0xffffff00, WR_1|RD_C0, 0, 0, E2, 0 },
|
||||
{"mfc0", "y,N,O", 0xf0006700, 0xff1fff00, WR_1|RD_C0, 0, 0, E2, 0 },
|
||||
{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 },
|
||||
{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 },
|
||||
{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{"movn", "x,.,w", 0xf000300a, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{"movn", "x,r,w", 0xf020300a, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{"movtn", "x,.", 0xf000301a, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{"movtn", "x,r", 0xf020301a, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{"movtz", "x,.", 0xf0003016, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{"movtz", "x,r", 0xf0203016, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{"movz", "x,.,w", 0xf0003006, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{"movz", "x,r,w", 0xf0203006, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{"mtc0", "y,N", 0xf0016700, 0xffffff00, RD_1|WR_C0, 0, 0, E2, 0 },
|
||||
{"mtc0", "y,N,O", 0xf0016700, 0xff1fff00, RD_1|WR_C0, 0, 0, E2, 0 },
|
||||
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"ori", "x,u", 0xf0006840, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{"pause", "", 0xf1403018, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{"pref", "T,9(x)", 0xf000d080, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
|
||||
{"rdhwr", "y,Q", 0xf000300c, 0xffe0ff1f, WR_1, 0, 0, E2, 0 },
|
||||
{"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{"sb", "x,V(G)", 0xf000d060, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"sc", "x,9(r)", 0xf000d0c0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
|
||||
{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
|
||||
{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
|
||||
{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{"sh", "x,V(G)", 0xf000d040, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
|
||||
{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{"sll", "x,w,<", 0xf0003000, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
|
||||
{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{"srl", "x,w,<", 0xf0003002, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
|
||||
{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, SH|RD_SP, 0, E2, 0 },
|
||||
{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
|
||||
{"sw", "x,V(S)", 0xf000d000, 0xf800f8e0, RD_1, RD_SP, 0, E2, 0 },
|
||||
{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
|
||||
{"sw", "x,V(G)", 0xf000d020, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"swl", "x,9(r)", 0xf000d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"swr", "x,9(r)", 0xf010d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{"sync_acquire", "", 0xf4403014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{"sync_mb", "", 0xf4003014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{"sync_release", "", 0xf4803014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{"sync_rmb", "", 0xf4c03014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{"sync_wmb", "", 0xf1003014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{"sync", "", 0xf0003014, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{"sync", ">", 0xf0003014, 0xf83fffff, 0, 0, 0, E2, 0 },
|
||||
{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{"xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{ "jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 },
|
||||
{ "jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 },
|
||||
{ "jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 },
|
||||
{ "jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 },
|
||||
{ "lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "lb", "x,V(G)", 0xf0009060, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "lbu", "x,V(G)", 0xf00090a0, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
|
||||
{ "ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC|AL, I3, 0, 0 },
|
||||
{ "ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
|
||||
{ "ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
|
||||
{ "lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "lh", "x,V(G)", 0xf0009040, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "lhu", "x,V(G)", 0xf0009080, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "li", "x,U", 0x6800, 0xf800, WR_1, SH, 0, E2, 0 },
|
||||
{ "li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
|
||||
{ "li", "x,U", 0xf0006800, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{ "ll", "x,9(r)", 0xf00090c0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lui", "x,u", 0xf0006820, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{ "lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC|AL, I1, 0, 0 },
|
||||
{ "lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
|
||||
{ "lw", "x,V(S)", 0x9000, 0xf800, WR_1, SH|RD_SP, 0, E2, 0 },
|
||||
{ "lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
|
||||
{ "lw", "x,V(S)", 0xf0009000, 0xf800f8e0, WR_1, RD_SP, 0, E2, 0 },
|
||||
{ "lw", "x,V(G)", 0xf0009020, 0xf800f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lwl", "x,9(r)", 0xf00090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lwr", "x,9(r)", 0xf01090e0, 0xfe18f8e0, WR_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
|
||||
{ "mfc0", "y,N", 0xf0006700, 0xffffff00, WR_1|RD_C0, 0, 0, E2, 0 },
|
||||
{ "mfc0", "y,N,O", 0xf0006700, 0xff1fff00, WR_1|RD_C0, 0, 0, E2, 0 },
|
||||
{ "mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 },
|
||||
{ "mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 },
|
||||
{ "move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "movn", "x,.,w", 0xf000300a, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{ "movn", "x,r,w", 0xf020300a, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{ "movtn", "x,.", 0xf000301a, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{ "movtn", "x,r", 0xf020301a, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{ "movtz", "x,.", 0xf0003016, 0xfffff8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{ "movtz", "x,r", 0xf0203016, 0xfff8f8ff, WR_1|RD_2|RD_T, 0, 0, E2, 0 },
|
||||
{ "movz", "x,.,w", 0xf0003006, 0xfffff81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{ "movz", "x,r,w", 0xf0203006, 0xfff8f81f, WR_1|RD_2|RD_3, 0, 0, E2, 0 },
|
||||
{ "mtc0", "y,N", 0xf0016700, 0xffffff00, RD_1|WR_C0, 0, 0, E2, 0 },
|
||||
{ "mtc0", "y,N,O", 0xf0016700, 0xff1fff00, RD_1|WR_C0, 0, 0, E2, 0 },
|
||||
{ "mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "ori", "x,u", 0xf0006840, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
{ "pause", "", 0xf1403018, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{ "pref", "T,9(x)", 0xf000d080, 0xfe00f8e0, RD_3, 0, 0, E2, 0 },
|
||||
{ "rdhwr", "y,Q", 0xf000300c, 0xffe0ff1f, WR_1, 0, 0, E2, 0 },
|
||||
{ "rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
|
||||
{ "remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "sb", "x,V(G)", 0xf000d060, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "sc", "x,9(r)", 0xf000d0c0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
|
||||
{ "sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
|
||||
{ "sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
|
||||
{ "sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "sh", "x,V(G)", 0xf000d040, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
|
||||
{ "sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{ "sll", "x,w,<", 0xf0003000, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{ "slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
|
||||
{ "sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
|
||||
{ "srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{ "sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, SH, 0, E2, 0 },
|
||||
{ "srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
|
||||
{ "srl", "x,w,<", 0xf0003002, 0xf83ff81f, WR_1|RD_2, 0, 0, E2, 0 },
|
||||
{ "srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
|
||||
{ "subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{ "sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
|
||||
{ "sw", "x,V(S)", 0xd000, 0xf800, RD_1, SH|RD_SP, 0, E2, 0 },
|
||||
{ "sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
|
||||
{ "sw", "x,V(S)", 0xf000d000, 0xf800f8e0, RD_1, RD_SP, 0, E2, 0 },
|
||||
{ "sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
|
||||
{ "sw", "x,V(G)", 0xf000d020, 0xf800f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "swl", "x,9(r)", 0xf000d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "swr", "x,9(r)", 0xf010d0e0, 0xfe18f8e0, RD_1|RD_3, 0, 0, E2, 0 },
|
||||
{ "sync_acquire", "", 0xf4403014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{ "sync_mb", "", 0xf4003014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{ "sync_release", "", 0xf4803014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{ "sync_rmb", "", 0xf4c03014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{ "sync_wmb", "", 0xf1003014, 0xffffffff, 0, AL, 0, E2, 0 },
|
||||
{ "sync", "", 0xf0003014, 0xffffffff, 0, 0, 0, E2, 0 },
|
||||
{ "sync", ">", 0xf0003014, 0xf83fffff, 0, 0, 0, E2, 0 },
|
||||
{ "xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
|
||||
{ "xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
|
||||
/* MIPS16e additions; see above for compact jumps. */
|
||||
{"restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
|
||||
{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
|
||||
{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 },
|
||||
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
|
||||
{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
||||
{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
||||
{ "restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
|
||||
{ "save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
|
||||
{ "sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 },
|
||||
{ "sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },
|
||||
{ "seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{ "seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{ "sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
||||
{ "zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{ "zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
|
||||
{ "zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
|
||||
/* MIPS16e2 MT ASE instructions. */
|
||||
{"dmt", "", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"dmt", ".", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"dmt", "y", 0xf0226701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{"dvpe", "", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"dvpe", ".", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"dvpe", "y", 0xf0226700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{"emt", "", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"emt", ".", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"emt", "y", 0xf0236701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{"evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{"evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dmt", "", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dmt", ".", 0xf0266701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dmt", "y", 0xf0226701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dvpe", "", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dvpe", ".", 0xf0266700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "dvpe", "y", 0xf0226700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "emt", "", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "emt", ".", 0xf0276701, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "emt", "y", 0xf0236701, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 },
|
||||
{ "evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 },
|
||||
/* interAptiv MR2 instruction extensions. */
|
||||
{"copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
|
||||
{"ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
|
||||
{ "copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
|
||||
{ "ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 },
|
||||
/* Place asmacro at the bottom so that it catches any implementation
|
||||
specific macros that didn't match anything. */
|
||||
{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
|
||||
{ "asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
|
||||
/* Place EXTEND last so that it catches any prefix that didn't match
|
||||
anything. */
|
||||
{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },
|
||||
{ "extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },
|
||||
};
|
||||
|
||||
const int bfd_mips16_num_opcodes =
|
||||
|
|
|
|||
|
|
@ -28,136 +28,136 @@
|
|||
|
||||
const struct nios2_reg nios2_builtin_regs[] = {
|
||||
/* Standard register names. */
|
||||
{"zero", 0},
|
||||
{"at", 1}, /* assembler temporary */
|
||||
{"r2", 2},
|
||||
{"r3", 3},
|
||||
{"r4", 4},
|
||||
{"r5", 5},
|
||||
{"r6", 6},
|
||||
{"r7", 7},
|
||||
{"r8", 8},
|
||||
{"r9", 9},
|
||||
{"r10", 10},
|
||||
{"r11", 11},
|
||||
{"r12", 12},
|
||||
{"r13", 13},
|
||||
{"r14", 14},
|
||||
{"r15", 15},
|
||||
{"r16", 16},
|
||||
{"r17", 17},
|
||||
{"r18", 18},
|
||||
{"r19", 19},
|
||||
{"r20", 20},
|
||||
{"r21", 21},
|
||||
{"r22", 22},
|
||||
{"r23", 23},
|
||||
{"et", 24},
|
||||
{"bt", 25},
|
||||
{"gp", 26}, /* global pointer */
|
||||
{"sp", 27}, /* stack pointer */
|
||||
{"fp", 28}, /* frame pointer */
|
||||
{"ea", 29}, /* exception return address */
|
||||
{"ba", 30}, /* breakpoint return address */
|
||||
{"ra", 31}, /* return address */
|
||||
{ "zero", 0},
|
||||
{ "at", 1}, /* assembler temporary */
|
||||
{ "r2", 2},
|
||||
{ "r3", 3},
|
||||
{ "r4", 4},
|
||||
{ "r5", 5},
|
||||
{ "r6", 6},
|
||||
{ "r7", 7},
|
||||
{ "r8", 8},
|
||||
{ "r9", 9},
|
||||
{ "r10", 10},
|
||||
{ "r11", 11},
|
||||
{ "r12", 12},
|
||||
{ "r13", 13},
|
||||
{ "r14", 14},
|
||||
{ "r15", 15},
|
||||
{ "r16", 16},
|
||||
{ "r17", 17},
|
||||
{ "r18", 18},
|
||||
{ "r19", 19},
|
||||
{ "r20", 20},
|
||||
{ "r21", 21},
|
||||
{ "r22", 22},
|
||||
{ "r23", 23},
|
||||
{ "et", 24},
|
||||
{ "bt", 25},
|
||||
{ "gp", 26}, /* global pointer */
|
||||
{ "sp", 27}, /* stack pointer */
|
||||
{ "fp", 28}, /* frame pointer */
|
||||
{ "ea", 29}, /* exception return address */
|
||||
{ "ba", 30}, /* breakpoint return address */
|
||||
{ "ra", 31}, /* return address */
|
||||
|
||||
/* Alternative names for special registers. */
|
||||
{"r0", 0},
|
||||
{"r1", 1},
|
||||
{"r24", 24},
|
||||
{"r25", 25},
|
||||
{"r26", 26},
|
||||
{"r27", 27},
|
||||
{"r28", 28},
|
||||
{"r29", 29},
|
||||
{"r30", 30},
|
||||
{"sstatus", 30},
|
||||
{"r31", 31},
|
||||
{ "r0", 0},
|
||||
{ "r1", 1},
|
||||
{ "r24", 24},
|
||||
{ "r25", 25},
|
||||
{ "r26", 26},
|
||||
{ "r27", 27},
|
||||
{ "r28", 28},
|
||||
{ "r29", 29},
|
||||
{ "r30", 30},
|
||||
{ "sstatus", 30},
|
||||
{ "r31", 31},
|
||||
|
||||
/* Control register names. */
|
||||
{"status", 0},
|
||||
{"estatus", 1},
|
||||
{"bstatus", 2},
|
||||
{"ienable", 3},
|
||||
{"ipending", 4},
|
||||
{"cpuid", 5},
|
||||
{"ctl6", 6},
|
||||
{"exception", 7},
|
||||
{"pteaddr", 8},
|
||||
{"tlbacc", 9},
|
||||
{"tlbmisc", 10},
|
||||
{"eccinj", 11},
|
||||
{"badaddr", 12},
|
||||
{"config", 13},
|
||||
{"mpubase", 14},
|
||||
{"mpuacc", 15},
|
||||
{"ctl16", 16},
|
||||
{"ctl17", 17},
|
||||
{"ctl18", 18},
|
||||
{"ctl19", 19},
|
||||
{"ctl20", 20},
|
||||
{"ctl21", 21},
|
||||
{"ctl22", 22},
|
||||
{"ctl23", 23},
|
||||
{"ctl24", 24},
|
||||
{"ctl25", 25},
|
||||
{"ctl26", 26},
|
||||
{"ctl27", 27},
|
||||
{"ctl28", 28},
|
||||
{"ctl29", 29},
|
||||
{"ctl30", 30},
|
||||
{"ctl31", 31},
|
||||
{ "status", 0},
|
||||
{ "estatus", 1},
|
||||
{ "bstatus", 2},
|
||||
{ "ienable", 3},
|
||||
{ "ipending", 4},
|
||||
{ "cpuid", 5},
|
||||
{ "ctl6", 6},
|
||||
{ "exception", 7},
|
||||
{ "pteaddr", 8},
|
||||
{ "tlbacc", 9},
|
||||
{ "tlbmisc", 10},
|
||||
{ "eccinj", 11},
|
||||
{ "badaddr", 12},
|
||||
{ "config", 13},
|
||||
{ "mpubase", 14},
|
||||
{ "mpuacc", 15},
|
||||
{ "ctl16", 16},
|
||||
{ "ctl17", 17},
|
||||
{ "ctl18", 18},
|
||||
{ "ctl19", 19},
|
||||
{ "ctl20", 20},
|
||||
{ "ctl21", 21},
|
||||
{ "ctl22", 22},
|
||||
{ "ctl23", 23},
|
||||
{ "ctl24", 24},
|
||||
{ "ctl25", 25},
|
||||
{ "ctl26", 26},
|
||||
{ "ctl27", 27},
|
||||
{ "ctl28", 28},
|
||||
{ "ctl29", 29},
|
||||
{ "ctl30", 30},
|
||||
{ "ctl31", 31},
|
||||
|
||||
/* Alternative names for special control registers. */
|
||||
{"ctl0", 0},
|
||||
{"ctl1", 1},
|
||||
{"ctl2", 2},
|
||||
{"ctl3", 3},
|
||||
{"ctl4", 4},
|
||||
{"ctl5", 5},
|
||||
{"ctl7", 7},
|
||||
{"ctl8", 8},
|
||||
{"ctl9", 9},
|
||||
{"ctl10", 10},
|
||||
{"ctl11", 11},
|
||||
{"ctl12", 12},
|
||||
{"ctl13", 13},
|
||||
{"ctl14", 14},
|
||||
{"ctl15", 15},
|
||||
{ "ctl0", 0},
|
||||
{ "ctl1", 1},
|
||||
{ "ctl2", 2},
|
||||
{ "ctl3", 3},
|
||||
{ "ctl4", 4},
|
||||
{ "ctl5", 5},
|
||||
{ "ctl7", 7},
|
||||
{ "ctl8", 8},
|
||||
{ "ctl9", 9},
|
||||
{ "ctl10", 10},
|
||||
{ "ctl11", 11},
|
||||
{ "ctl12", 12},
|
||||
{ "ctl13", 13},
|
||||
{ "ctl14", 14},
|
||||
{ "ctl15", 15},
|
||||
|
||||
/* Coprocessor register names. */
|
||||
{"c0", 0},
|
||||
{"c1", 1},
|
||||
{"c2", 2},
|
||||
{"c3", 3},
|
||||
{"c4", 4},
|
||||
{"c5", 5},
|
||||
{"c6", 6},
|
||||
{"c7", 7},
|
||||
{"c8", 8},
|
||||
{"c9", 9},
|
||||
{"c10", 10},
|
||||
{"c11", 11},
|
||||
{"c12", 12},
|
||||
{"c13", 13},
|
||||
{"c14", 14},
|
||||
{"c15", 15},
|
||||
{"c16", 16},
|
||||
{"c17", 17},
|
||||
{"c18", 18},
|
||||
{"c19", 19},
|
||||
{"c20", 20},
|
||||
{"c21", 21},
|
||||
{"c22", 22},
|
||||
{"c23", 23},
|
||||
{"c24", 24},
|
||||
{"c25", 25},
|
||||
{"c26", 26},
|
||||
{"c27", 27},
|
||||
{"c28", 28},
|
||||
{"c29", 29},
|
||||
{"c30", 30},
|
||||
{"c31", 31},
|
||||
{ "c0", 0},
|
||||
{ "c1", 1},
|
||||
{ "c2", 2},
|
||||
{ "c3", 3},
|
||||
{ "c4", 4},
|
||||
{ "c5", 5},
|
||||
{ "c6", 6},
|
||||
{ "c7", 7},
|
||||
{ "c8", 8},
|
||||
{ "c9", 9},
|
||||
{ "c10", 10},
|
||||
{ "c11", 11},
|
||||
{ "c12", 12},
|
||||
{ "c13", 13},
|
||||
{ "c14", 14},
|
||||
{ "c15", 15},
|
||||
{ "c16", 16},
|
||||
{ "c17", 17},
|
||||
{ "c18", 18},
|
||||
{ "c19", 19},
|
||||
{ "c20", 20},
|
||||
{ "c21", 21},
|
||||
{ "c22", 22},
|
||||
{ "c23", 23},
|
||||
{ "c24", 24},
|
||||
{ "c25", 25},
|
||||
{ "c26", 26},
|
||||
{ "c27", 27},
|
||||
{ "c28", 28},
|
||||
{ "c29", 29},
|
||||
{ "c30", 30},
|
||||
{ "c31", 31},
|
||||
};
|
||||
|
||||
#define NIOS2_NUM_REGS \
|
||||
|
|
@ -176,230 +176,230 @@ const struct nios2_opcode nios2_builtin_opcodes[] =
|
|||
{
|
||||
/* { name, args, args_test, num_args,
|
||||
match, mask, pinfo, overflow_msg } */
|
||||
{"add", "d,s,t", "d,s,t,E", 3,
|
||||
{ "add", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_ADD, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"addi", "t,s,i", "t,s,i,E", 3,
|
||||
{ "addi", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_ADDI, signed_immed16_overflow},
|
||||
{"subi", "t,s,i", "t,s,i,E", 3,
|
||||
{ "subi", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_ADDI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
|
||||
{"and", "d,s,t", "d,s,t,E", 3,
|
||||
{ "and", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_AND, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"andhi", "t,s,u", "t,s,u,E", 3,
|
||||
{ "andhi", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_ANDHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"andi", "t,s,u", "t,s,u,E", 3,
|
||||
{ "andi", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_ANDI, OP_MASK_IOP, NIOS2_INSN_ANDI, unsigned_immed16_overflow},
|
||||
{"beq", "s,t,o", "s,t,o,E", 3,
|
||||
{ "beq", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BEQ, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"bge", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bge", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"bgeu", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bgeu", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"bgt", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bgt", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
|
||||
branch_target_overflow},
|
||||
{"bgtu", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bgtu", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
|
||||
branch_target_overflow},
|
||||
{"ble", "s,t,o", "s,t,o,E", 3,
|
||||
{ "ble", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BGE, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
|
||||
branch_target_overflow},
|
||||
{"bleu", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bleu", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BGEU, OP_MASK_IOP, NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH,
|
||||
branch_target_overflow},
|
||||
{"blt", "s,t,o", "s,t,o,E", 3,
|
||||
{ "blt", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BLT, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"bltu", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bltu", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BLTU, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"bne", "s,t,o", "s,t,o,E", 3,
|
||||
{ "bne", "s,t,o", "s,t,o,E", 3,
|
||||
OP_MATCH_BNE, OP_MASK_IOP, NIOS2_INSN_CBRANCH, branch_target_overflow},
|
||||
{"br", "o", "o,E", 1,
|
||||
{ "br", "o", "o,E", 1,
|
||||
OP_MATCH_BR, OP_MASK_IOP, NIOS2_INSN_UBRANCH, branch_target_overflow},
|
||||
{"break", "b", "b,E", 1,
|
||||
{ "break", "b", "b,E", 1,
|
||||
OP_MATCH_BREAK, OP_MASK_BREAK, 0, no_overflow},
|
||||
{"bret", "", "E", 0,
|
||||
{ "bret", "", "E", 0,
|
||||
OP_MATCH_BRET, OP_MASK, 0, no_overflow},
|
||||
{"flushd", "i(s)", "i(s)E", 2,
|
||||
{ "flushd", "i(s)", "i(s)E", 2,
|
||||
OP_MATCH_FLUSHD, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"flushda", "i(s)", "i(s)E", 2,
|
||||
{ "flushda", "i(s)", "i(s)E", 2,
|
||||
OP_MATCH_FLUSHDA, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"flushi", "s", "s,E", 1,
|
||||
{ "flushi", "s", "s,E", 1,
|
||||
OP_MATCH_FLUSHI, OP_MASK_FLUSHI, 0, no_overflow},
|
||||
{"flushp", "", "E", 0,
|
||||
{ "flushp", "", "E", 0,
|
||||
OP_MATCH_FLUSHP, OP_MASK, 0, no_overflow},
|
||||
{"initd", "i(s)", "i(s)E", 2,
|
||||
{ "initd", "i(s)", "i(s)E", 2,
|
||||
OP_MATCH_INITD, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"initda", "i(s)", "i(s)E", 2,
|
||||
{ "initda", "i(s)", "i(s)E", 2,
|
||||
OP_MATCH_INITDA, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"initi", "s", "s,E", 1,
|
||||
{ "initi", "s", "s,E", 1,
|
||||
OP_MATCH_INITI, OP_MASK_INITI, 0, no_overflow},
|
||||
{"call", "m", "m,E", 1,
|
||||
{ "call", "m", "m,E", 1,
|
||||
OP_MATCH_CALL, OP_MASK_IOP, NIOS2_INSN_CALL, call_target_overflow},
|
||||
{"callr", "s", "s,E", 1,
|
||||
{ "callr", "s", "s,E", 1,
|
||||
OP_MATCH_CALLR, OP_MASK_CALLR, 0, no_overflow},
|
||||
{"cmpeq", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpeq", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPEQ, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmpeqi", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmpeqi", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPEQI, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"cmpge", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpge", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmpgei", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmpgei", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPGEI, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"cmpgeu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpgeu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmpgeui", "t,s,u", "t,s,u,E", 3,
|
||||
{ "cmpgeui", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_CMPGEUI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"cmpgt", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpgt", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
|
||||
{"cmpgti", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmpgti", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPGEI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
|
||||
{"cmpgtu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpgtu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
|
||||
{"cmpgtui", "t,s,u", "t,s,u,E", 3,
|
||||
{ "cmpgtui", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_CMPGEUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow},
|
||||
{"cmple", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmple", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPGE, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
|
||||
{"cmplei", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmplei", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPLTI, OP_MASK_IOP, NIOS2_INSN_MACRO, signed_immed16_overflow},
|
||||
{"cmpleu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpleu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPGEU, OP_MASK_ROPX | OP_MASK_ROP, NIOS2_INSN_MACRO, no_overflow},
|
||||
{"cmpleui", "t,s,u", "t,s,u,E", 3,
|
||||
{ "cmpleui", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_CMPLTUI, OP_MASK_IOP, NIOS2_INSN_MACRO, unsigned_immed16_overflow},
|
||||
{"cmplt", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmplt", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPLT, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmplti", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmplti", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPLTI, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"cmpltu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpltu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPLTU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmpltui", "t,s,u", "t,s,u,E", 3,
|
||||
{ "cmpltui", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_CMPLTUI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"cmpne", "d,s,t", "d,s,t,E", 3,
|
||||
{ "cmpne", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_CMPNE, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"cmpnei", "t,s,i", "t,s,i,E", 3,
|
||||
{ "cmpnei", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_CMPNEI, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"div", "d,s,t", "d,s,t,E", 3,
|
||||
{ "div", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_DIV, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"divu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "divu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_DIVU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"jmp", "s", "s,E", 1,
|
||||
{ "jmp", "s", "s,E", 1,
|
||||
OP_MATCH_JMP, OP_MASK_JMP, 0, no_overflow},
|
||||
{"jmpi", "m", "m,E", 1,
|
||||
{ "jmpi", "m", "m,E", 1,
|
||||
OP_MATCH_JMPI, OP_MASK_IOP, 0, no_overflow},
|
||||
{"ldb", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldb", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDB, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldbio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldbio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDBIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldbu", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldbu", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDBU, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldbuio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldbuio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDBUIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldh", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldh", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDH, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldhio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldhio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDHIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldhu", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldhu", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDHU, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldhuio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldhuio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDHUIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldl", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldl", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDL, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldw", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldw", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDW, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"ldwio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "ldwio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_LDWIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"mov", "d,s", "d,s,E", 2,
|
||||
{ "mov", "d,s", "d,s,E", 2,
|
||||
OP_MATCH_ADD, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, NIOS2_INSN_MACRO_MOV,
|
||||
no_overflow},
|
||||
{"movhi", "t,u", "t,u,E", 2,
|
||||
{ "movhi", "t,u", "t,u,E", 2,
|
||||
OP_MATCH_ORHI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
|
||||
unsigned_immed16_overflow},
|
||||
{"movui", "t,u", "t,u,E", 2,
|
||||
{ "movui", "t,u", "t,u,E", 2,
|
||||
OP_MATCH_ORI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
|
||||
unsigned_immed16_overflow},
|
||||
{"movi", "t,i", "t,i,E", 2,
|
||||
{ "movi", "t,i", "t,i,E", 2,
|
||||
OP_MATCH_ADDI, OP_MASK_IRS|OP_MASK_IOP, NIOS2_INSN_MACRO_MOVI,
|
||||
signed_immed16_overflow},
|
||||
/* movia expands to two instructions so there is no mask or match */
|
||||
{"movia", "t,o", "t,o,E", 2,
|
||||
{ "movia", "t,o", "t,o,E", 2,
|
||||
OP_MATCH_ORHI, OP_MASK_IOP, NIOS2_INSN_MACRO_MOVIA, no_overflow},
|
||||
{"mul", "d,s,t", "d,s,t,E", 3,
|
||||
{ "mul", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_MUL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"muli", "t,s,i", "t,s,i,E", 3,
|
||||
{ "muli", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_MULI, OP_MASK_IOP, 0, signed_immed16_overflow},
|
||||
{"mulxss", "d,s,t", "d,s,t,E", 3,
|
||||
{ "mulxss", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_MULXSS, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"mulxsu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "mulxsu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_MULXSU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"mulxuu", "d,s,t", "d,s,t,E", 3,
|
||||
{ "mulxuu", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_MULXUU, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"nextpc", "d", "d,E", 1,
|
||||
{ "nextpc", "d", "d,E", 1,
|
||||
OP_MATCH_NEXTPC, OP_MASK_NEXTPC, 0, no_overflow},
|
||||
{"nop", "", "E", 0,
|
||||
{ "nop", "", "E", 0,
|
||||
OP_MATCH_ADD, OP_MASK, NIOS2_INSN_MACRO_MOV, no_overflow},
|
||||
{"nor", "d,s,t", "d,s,t,E", 3,
|
||||
{ "nor", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_NOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"or", "d,s,t", "d,s,t,E", 3,
|
||||
{ "or", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_OR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"orhi", "t,s,u", "t,s,u,E", 3,
|
||||
{ "orhi", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_ORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"ori", "t,s,u", "t,s,u,E", 3,
|
||||
{ "ori", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_ORI, OP_MASK_IOP, NIOS2_INSN_ORI, unsigned_immed16_overflow},
|
||||
{"rdctl", "d,c", "d,c,E", 2,
|
||||
{ "rdctl", "d,c", "d,c,E", 2,
|
||||
OP_MATCH_RDCTL, OP_MASK_RDCTL, 0, no_overflow},
|
||||
{"rdprs", "t,s,i", "t,s,i,E", 3,
|
||||
{ "rdprs", "t,s,i", "t,s,i,E", 3,
|
||||
OP_MATCH_RDPRS, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"ret", "", "E", 0,
|
||||
{ "ret", "", "E", 0,
|
||||
OP_MATCH_RET, OP_MASK, 0, no_overflow},
|
||||
{"rol", "d,s,t", "d,s,t,E", 3,
|
||||
{ "rol", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_ROL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"roli", "d,s,j", "d,s,j,E", 3,
|
||||
{ "roli", "d,s,j", "d,s,j,E", 3,
|
||||
OP_MATCH_ROLI, OP_MASK_ROLI, 0, unsigned_immed5_overflow},
|
||||
{"ror", "d,s,t", "d,s,t,E", 3,
|
||||
{ "ror", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_ROR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"sll", "d,s,t", "d,s,t,E", 3,
|
||||
{ "sll", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_SLL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"slli", "d,s,j", "d,s,j,E", 3,
|
||||
{ "slli", "d,s,j", "d,s,j,E", 3,
|
||||
OP_MATCH_SLLI, OP_MASK_SLLI, 0, unsigned_immed5_overflow},
|
||||
{"sra", "d,s,t", "d,s,t,E", 3,
|
||||
{ "sra", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_SRA, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"srai", "d,s,j", "d,s,j,E", 3,
|
||||
{ "srai", "d,s,j", "d,s,j,E", 3,
|
||||
OP_MATCH_SRAI, OP_MASK_SRAI, 0, unsigned_immed5_overflow},
|
||||
{"srl", "d,s,t", "d,s,t,E", 3,
|
||||
{ "srl", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_SRL, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"srli", "d,s,j", "d,s,j,E", 3,
|
||||
{ "srli", "d,s,j", "d,s,j,E", 3,
|
||||
OP_MATCH_SRLI, OP_MASK_SRLI, 0, unsigned_immed5_overflow},
|
||||
{"stb", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "stb", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STB, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"stbio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "stbio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STBIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"stc", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "stc", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STC, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"sth", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "sth", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STH, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"sthio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "sthio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STHIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"stw", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "stw", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STW, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"stwio", "t,i(s)", "t,i(s)E", 3,
|
||||
{ "stwio", "t,i(s)", "t,i(s)E", 3,
|
||||
OP_MATCH_STWIO, OP_MASK_IOP, 0, address_offset_overflow},
|
||||
{"sub", "d,s,t", "d,s,t,E", 3,
|
||||
{ "sub", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_SUB, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"sync", "", "E", 0,
|
||||
{ "sync", "", "E", 0,
|
||||
OP_MATCH_SYNC, OP_MASK_SYNC, 0, no_overflow},
|
||||
{"trap", "b", "b,E", 1,
|
||||
{ "trap", "b", "b,E", 1,
|
||||
OP_MATCH_TRAP, OP_MASK_TRAP, 0, no_overflow},
|
||||
{"eret", "", "E", 0,
|
||||
{ "eret", "", "E", 0,
|
||||
OP_MATCH_ERET, OP_MASK, 0, no_overflow},
|
||||
{"custom", "l,d,s,t", "l,d,s,t,E", 4,
|
||||
{ "custom", "l,d,s,t", "l,d,s,t,E", 4,
|
||||
OP_MATCH_CUSTOM, OP_MASK_ROP, 0, custom_opcode_overflow},
|
||||
{"wrctl", "c,s", "c,s,E", 2,
|
||||
{ "wrctl", "c,s", "c,s,E", 2,
|
||||
OP_MATCH_WRCTL, OP_MASK_WRCTL, 0, no_overflow},
|
||||
{"wrprs", "d,s", "d,s,E", 2,
|
||||
{ "wrprs", "d,s", "d,s,E", 2,
|
||||
OP_MATCH_WRPRS, OP_MASK_RRT|OP_MASK_ROPX|OP_MASK_ROP, 0, no_overflow},
|
||||
{"xor", "d,s,t", "d,s,t,E", 3,
|
||||
{ "xor", "d,s,t", "d,s,t,E", 3,
|
||||
OP_MATCH_XOR, OP_MASK_ROPX | OP_MASK_ROP, 0, no_overflow},
|
||||
{"xorhi", "t,s,u", "t,s,u,E", 3,
|
||||
{ "xorhi", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_XORHI, OP_MASK_IOP, 0, unsigned_immed16_overflow},
|
||||
{"xori", "t,s,u", "t,s,u,E", 3,
|
||||
{ "xori", "t,s,u", "t,s,u,E", 3,
|
||||
OP_MATCH_XORI, OP_MASK_IOP, NIOS2_INSN_XORI, unsigned_immed16_overflow}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,58 +3,58 @@
|
|||
#include "pic_midrange.h"
|
||||
|
||||
static const PicMidrangeOpInfo pic_midrange_op_info[PIC_MIDRANGE_OPCODE_INVALID] = {
|
||||
{"nop", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"return", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"retfie", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"option", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"sleep", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"clrwdt", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"tris", PIC_MIDRANGE_OP_ARGS_2F},
|
||||
{"movwf", PIC_MIDRANGE_OP_ARGS_7F},
|
||||
{"clr", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"subwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"decf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"iorwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"andwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"xorwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"addwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"movf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"comf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"incf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"decfsz", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"rrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"rlf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"swapf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"incfsz", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"bcf", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{"bsf", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{"btfsc", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{"btfss", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{"call", PIC_MIDRANGE_OP_ARGS_11K},
|
||||
{"goto", PIC_MIDRANGE_OP_ARGS_11K},
|
||||
{"movlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"retlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"iorlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"andlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"xorlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"sublw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"addlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{"reset", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"callw", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"brw", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{"moviw", PIC_MIDRANGE_OP_ARGS_1N_2M},
|
||||
{"movwi", PIC_MIDRANGE_OP_ARGS_1N_2M},
|
||||
{"movlb", PIC_MIDRANGE_OP_ARGS_4K},
|
||||
{"lslf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"lsrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"asrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"subwfb", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"addwfc", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{"addfsr", PIC_MIDRANGE_OP_ARGS_1N_6K},
|
||||
{"movlp", PIC_MIDRANGE_OP_ARGS_7F},
|
||||
{"bra", PIC_MIDRANGE_OP_ARGS_9K},
|
||||
{"moviw", PIC_MIDRANGE_OP_ARGS_1N_6K},
|
||||
{"movwi", PIC_MIDRANGE_OP_ARGS_1N_6K}
|
||||
{ "nop", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "return", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "retfie", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "option", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "sleep", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "clrwdt", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "tris", PIC_MIDRANGE_OP_ARGS_2F},
|
||||
{ "movwf", PIC_MIDRANGE_OP_ARGS_7F},
|
||||
{ "clr", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "subwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "decf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "iorwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "andwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "xorwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "addwf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "movf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "comf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "incf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "decfsz", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "rrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "rlf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "swapf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "incfsz", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "bcf", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{ "bsf", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{ "btfsc", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{ "btfss", PIC_MIDRANGE_OP_ARGS_3B_7F},
|
||||
{ "call", PIC_MIDRANGE_OP_ARGS_11K},
|
||||
{ "goto", PIC_MIDRANGE_OP_ARGS_11K},
|
||||
{ "movlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "retlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "iorlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "andlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "xorlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "sublw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "addlw", PIC_MIDRANGE_OP_ARGS_8K},
|
||||
{ "reset", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "callw", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "brw", PIC_MIDRANGE_OP_ARGS_NONE},
|
||||
{ "moviw", PIC_MIDRANGE_OP_ARGS_1N_2M},
|
||||
{ "movwi", PIC_MIDRANGE_OP_ARGS_1N_2M},
|
||||
{ "movlb", PIC_MIDRANGE_OP_ARGS_4K},
|
||||
{ "lslf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "lsrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "asrf", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "subwfb", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "addwfc", PIC_MIDRANGE_OP_ARGS_1D_7F},
|
||||
{ "addfsr", PIC_MIDRANGE_OP_ARGS_1N_6K},
|
||||
{ "movlp", PIC_MIDRANGE_OP_ARGS_7F},
|
||||
{ "bra", PIC_MIDRANGE_OP_ARGS_9K},
|
||||
{ "moviw", PIC_MIDRANGE_OP_ARGS_1N_6K},
|
||||
{ "movwi", PIC_MIDRANGE_OP_ARGS_1N_6K}
|
||||
};
|
||||
|
||||
static const char *PicMidrangeFsrOps[] = {
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#define S_T 11
|
||||
#define LFSR_T 12
|
||||
|
||||
static char *fsr[] = {"fsr0", "fsr1", "fsr2", "reserved"};
|
||||
static char *fsr[] = { "fsr0", "fsr1", "fsr2", "reserved" };
|
||||
|
||||
static struct {
|
||||
ut16 opmin;
|
||||
|
|
|
|||
|
|
@ -361,7 +361,7 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
if (operand->bitm == 7) {
|
||||
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
||||
} else {
|
||||
static const char *cbnames[4] = {"lt", "gt", "eq", "so"};
|
||||
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
||||
int cr;
|
||||
int cc;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,76 +21,76 @@ ps_operand_t ps_operands_array[] = {
|
|||
|
||||
|
||||
ps_opcode_t ps_opcodes_array[] = {
|
||||
{ psq_lx, "psq_lx", OPM (4, 6), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load Indexed"},
|
||||
{ psq_stx, "psq_stx", OPM (4, 7), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store Indexed"},
|
||||
{ psq_lux, "psq_lux", OPM (4, 38), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load with update Indexed"},
|
||||
{ psq_stux, "psq_stux", OPM (4, 39), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store with update Indexed"},
|
||||
{ psq_lx, "psq_lx", OPM (4, 6), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load Indexed" },
|
||||
{ psq_stx, "psq_stx", OPM (4, 7), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store Indexed" },
|
||||
{ psq_lux, "psq_lux", OPM (4, 38), OPM_MASK, { OP_FD, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Load with update Indexed" },
|
||||
{ psq_stux, "psq_stux", OPM (4, 39), OPM_MASK, { OP_FS, OP_RA, OP_RB, OP_WC, OP_IC}, "Paired Single Quantized Store with update Indexed" },
|
||||
|
||||
{ psq_l, "psq_l", OP (56), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load"},
|
||||
{ psq_lu, "psq_lu", OP (57), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load with Update"},
|
||||
{ psq_st, "psq_st", OP (60), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store"},
|
||||
{ psq_stu, "psq_stu", OP (61), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store with update"},
|
||||
{ psq_l, "psq_l", OP (56), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load" },
|
||||
{ psq_lu, "psq_lu", OP (57), OP_MASK, { OP_FD, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Load with Update" },
|
||||
{ psq_st, "psq_st", OP (60), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store" },
|
||||
{ psq_stu, "psq_stu", OP (61), OP_MASK, { OP_FS, OP_DRA, OP_WB, OP_IB}, "Paired Single Quantized Store with update" },
|
||||
|
||||
{ ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"},
|
||||
{ ps_div_dot, "ps_div.", OPSC (4, 18, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide"},
|
||||
{ ps_sub, "ps_sub", OPSC (4, 20, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"},
|
||||
{ ps_sub_dot, "ps_sub.", OPSC (4, 20, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract"},
|
||||
{ ps_add, "ps_add", OPSC (4, 21, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Add"},
|
||||
{ ps_add_dot, "ps_add.", OPSC (4, 21, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Add"},
|
||||
{ ps_sel, "ps_sel", OPSC (4, 23, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select"},
|
||||
{ ps_sel_dot, "ps_sel.", OPSC (4, 23, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select"},
|
||||
{ ps_res, "ps_res", OPSC (4, 24, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate"},
|
||||
{ ps_res_dot, "ps_res.", OPSC (4, 24, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate"},
|
||||
{ ps_mul, "ps_mul", OPSC (4, 25, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply"},
|
||||
{ ps_mul_dot, "ps_mul.", OPSC (4, 25, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply"},
|
||||
{ ps_rsqrte, "ps_rsqrte", OPSC (4, 26, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate"},
|
||||
{ ps_rsqrte_dot, "ps_rsqrte.", OPSC (4, 26, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate"},
|
||||
{ ps_msub, "ps_msub", OPSC (4, 28, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract"},
|
||||
{ ps_msub_dot, "ps_msub.", OPSC (4, 28, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract"},
|
||||
{ ps_madd, "ps_madd", OPSC (4, 29, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add"},
|
||||
{ ps_madd_dot, "ps_madd.", OPSC (4, 29, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add"},
|
||||
{ ps_nmsub, "ps_nmsub", OPSC (4, 30, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract"},
|
||||
{ ps_nmsub_dot, "ps_nmsub.", OPSC (4, 30, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract"},
|
||||
{ ps_nmadd, "ps_nmadd", OPSC (4, 31, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add"},
|
||||
{ ps_nmadd_dot, "ps_nmadd.", OPSC (4, 31, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add"},
|
||||
{ ps_div, "ps_div", OPSC (4, 18, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide" },
|
||||
{ ps_div_dot, "ps_div.", OPSC (4, 18, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Divide" },
|
||||
{ ps_sub, "ps_sub", OPSC (4, 20, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract" },
|
||||
{ ps_sub_dot, "ps_sub.", OPSC (4, 20, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Subtract" },
|
||||
{ ps_add, "ps_add", OPSC (4, 21, 0), OPS_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single Add" },
|
||||
{ ps_add_dot, "ps_add.", OPSC (4, 21, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single Add" },
|
||||
{ ps_sel, "ps_sel", OPSC (4, 23, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select" },
|
||||
{ ps_sel_dot, "ps_sel.", OPSC (4, 23, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Select" },
|
||||
{ ps_res, "ps_res", OPSC (4, 24, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate" },
|
||||
{ ps_res_dot, "ps_res.", OPSC (4, 24, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Estimate" },
|
||||
{ ps_mul, "ps_mul", OPSC (4, 25, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply" },
|
||||
{ ps_mul_dot, "ps_mul.", OPSC (4, 25, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply" },
|
||||
{ ps_rsqrte, "ps_rsqrte", OPSC (4, 26, 0), OPS_MASK, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate" },
|
||||
{ ps_rsqrte_dot, "ps_rsqrte.", OPSC (4, 26, 1), OPS_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Reciprocal Square Root Estimate" },
|
||||
{ ps_msub, "ps_msub", OPSC (4, 28, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract" },
|
||||
{ ps_msub_dot, "ps_msub.", OPSC (4, 28, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Subtract" },
|
||||
{ ps_madd, "ps_madd", OPSC (4, 29, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add" },
|
||||
{ ps_madd_dot, "ps_madd.", OPSC (4, 29, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add" },
|
||||
{ ps_nmsub, "ps_nmsub", OPSC (4, 30, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract" },
|
||||
{ ps_nmsub_dot, "ps_nmsub.", OPSC (4, 30, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Subtract" },
|
||||
{ ps_nmadd, "ps_nmadd", OPSC (4, 31, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add" },
|
||||
{ ps_nmadd_dot, "ps_nmadd.", OPSC (4, 31, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Negative Multiply-Add" },
|
||||
|
||||
{ ps_neg, "ps_neg", OPLC (4, 40, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negate"},
|
||||
{ ps_neg_dot, "ps_neg.", OPLC (4, 40, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negate"},
|
||||
{ ps_mr, "ps_mr", OPLC (4, 72, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Move Register"},
|
||||
{ ps_mr_dot, "ps_mr.", OPLC (4, 72, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Move Register"},
|
||||
{ ps_nabs, "ps_nabs", OPLC (4, 136, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value"},
|
||||
{ ps_nabs_dot, "ps_nabs.", OPLC (4, 136, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value"},
|
||||
{ ps_abs, "ps_abs", OPLC (4, 264, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Absolute Value"},
|
||||
{ ps_abs_dot, "ps_abs.", OPLC (4, 264, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Absolute Value"},
|
||||
{ ps_neg, "ps_neg", OPLC (4, 40, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negate" },
|
||||
{ ps_neg_dot, "ps_neg.", OPLC (4, 40, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negate" },
|
||||
{ ps_mr, "ps_mr", OPLC (4, 72, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Move Register" },
|
||||
{ ps_mr_dot, "ps_mr.", OPLC (4, 72, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Move Register" },
|
||||
{ ps_nabs, "ps_nabs", OPLC (4, 136, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value" },
|
||||
{ ps_nabs_dot, "ps_nabs.", OPLC (4, 136, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Negative Absolute Value" },
|
||||
{ ps_abs, "ps_abs", OPLC (4, 264, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Absolute Value" },
|
||||
{ ps_abs_dot, "ps_abs.", OPLC (4, 264, 1), OPL_MASK_DOT, { OP_FD, OP_FB}, "Paired Single Absolute Value" },
|
||||
|
||||
{ ps_sum0, "ps_sum0", OPSC (4, 10, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high"},
|
||||
{ ps_sum0_dot, "ps_sum0.", OPSC (4, 10, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high"},
|
||||
{ ps_sum1, "ps_sum1", OPSC (4, 11, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low"},
|
||||
{ ps_sum1_dot, "ps_sum1.", OPSC (4, 11, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low"},
|
||||
{ ps_muls0, "ps_muls0", OPSC (4, 12, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high"},
|
||||
{ ps_muls0_dot, "ps_muls0.", OPSC (4, 12, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high"},
|
||||
{ ps_muls1, "ps_muls1", OPSC (4, 13, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low"},
|
||||
{ ps_muls1_dot, "ps_muls1.", OPSC (4, 13, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low"},
|
||||
{ ps_madds0, "ps_madds0", OPSC (4, 14, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high"},
|
||||
{ ps_madds0_dot, "ps_madds0.", OPSC (4, 14, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high"},
|
||||
{ ps_madds1, "ps_madds1", OPSC (4, 15, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low"},
|
||||
{ ps_madds1_dot, "ps_madds1.", OPSC (4, 15, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low"},
|
||||
{ ps_sum0, "ps_sum0", OPSC (4, 10, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high" },
|
||||
{ ps_sum0_dot, "ps_sum0.", OPSC (4, 10, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM high" },
|
||||
{ ps_sum1, "ps_sum1", OPSC (4, 11, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low" },
|
||||
{ ps_sum1_dot, "ps_sum1.", OPSC (4, 11, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single vector SUM low" },
|
||||
{ ps_muls0, "ps_muls0", OPSC (4, 12, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high" },
|
||||
{ ps_muls0_dot, "ps_muls0.", OPSC (4, 12, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar high" },
|
||||
{ ps_muls1, "ps_muls1", OPSC (4, 13, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low" },
|
||||
{ ps_muls1_dot, "ps_muls1.", OPSC (4, 13, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC}, "Paired Single Multiply Scalar low" },
|
||||
{ ps_madds0, "ps_madds0", OPSC (4, 14, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high" },
|
||||
{ ps_madds0_dot, "ps_madds0.", OPSC (4, 14, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar high" },
|
||||
{ ps_madds1, "ps_madds1", OPSC (4, 15, 0), OPS_MASK, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low" },
|
||||
{ ps_madds1_dot, "ps_madds1.", OPSC (4, 15, 1), OPS_MASK_DOT, { OP_FD, OP_FA, OP_FC, OP_FB}, "Paired Single Multiply-Add Scalar low" },
|
||||
|
||||
{ ps_cmpu0, "ps_cmpu0", OPL (4, 0), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered High"},
|
||||
{ ps_cmpo0, "ps_cmpo0", OPL (4, 32), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered High"},
|
||||
{ ps_cmpu1, "ps_cmpu1", OPL (4, 64), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered Low"},
|
||||
{ ps_cmpo1, "ps_cmpo1", OPL (4, 96), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered Low"},
|
||||
{ ps_cmpu0, "ps_cmpu0", OPL (4, 0), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered High" },
|
||||
{ ps_cmpo0, "ps_cmpo0", OPL (4, 32), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered High" },
|
||||
{ ps_cmpu1, "ps_cmpu1", OPL (4, 64), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Unordered Low" },
|
||||
{ ps_cmpo1, "ps_cmpo1", OPL (4, 96), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare Ordered Low" },
|
||||
|
||||
{ ps_merge00, "ps_merge00", OPLC (4, 528, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high"},
|
||||
{ ps_merge00_dot, "ps_merge00.", OPLC (4, 528, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high"},
|
||||
{ ps_merge01, "ps_merge01", OPLC (4, 560, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct"},
|
||||
{ ps_merge01_dot, "ps_merge01.", OPLC (4, 560, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct"},
|
||||
{ ps_merge10, "ps_merge10", OPLC (4, 592, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped"},
|
||||
{ ps_merge10_dot, "ps_merge10.", OPLC (4, 592, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped"},
|
||||
{ ps_merge11, "ps_merge11", OPLC (4, 624, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low"},
|
||||
{ ps_merge11_dot, "ps_merge11.", OPLC (4, 624, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low"},
|
||||
{ ps_merge00, "ps_merge00", OPLC (4, 528, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high" },
|
||||
{ ps_merge00_dot, "ps_merge00.", OPLC (4, 528, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE high" },
|
||||
{ ps_merge01, "ps_merge01", OPLC (4, 560, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct" },
|
||||
{ ps_merge01_dot, "ps_merge01.", OPLC (4, 560, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE direct" },
|
||||
{ ps_merge10, "ps_merge10", OPLC (4, 592, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped" },
|
||||
{ ps_merge10_dot, "ps_merge10.", OPLC (4, 592, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE swapped" },
|
||||
{ ps_merge11, "ps_merge11", OPLC (4, 624, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low" },
|
||||
{ ps_merge11_dot, "ps_merge11.", OPLC (4, 624, 1), OPL_MASK_DOT, { OP_FD, OP_FA, OP_FB}, "Paired Single MERGE low" },
|
||||
|
||||
{ ps_dcbz_l, "dcbz_l", OPL (4, 1014), OPL_MASK, { OP_RA, OP_RB}, "Data Cache Block Set to Zero Locked"},
|
||||
{ ps_dcbz_l, "dcbz_l", OPL (4, 1014), OPL_MASK, { OP_RA, OP_RB}, "Data Cache Block Set to Zero Locked" },
|
||||
|
||||
};
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -112,461 +112,461 @@ typedef struct {
|
|||
|
||||
sh_opcode_info sh_table[] = {
|
||||
|
||||
/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}},
|
||||
/* 0111nnnni8*1.... add #<imm>,<REG_N> */{ "add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}},
|
||||
|
||||
/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}},
|
||||
/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{ "add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}},
|
||||
/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{ "addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}},
|
||||
|
||||
/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}},
|
||||
/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{ "addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}},
|
||||
|
||||
/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}},
|
||||
/* 11001001i8*1.... and #<imm>,R0 */{ "and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}},
|
||||
|
||||
/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}},
|
||||
/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{ "and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}},
|
||||
|
||||
/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}},
|
||||
/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{ "and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}},
|
||||
|
||||
/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}},
|
||||
/* 1010i12......... bra <bdisp12> */{ "bra",{A_BDISP12},{HEX_A,BRANCH_12}},
|
||||
|
||||
/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}},
|
||||
/* 1011i12......... bsr <bdisp12> */{ "bsr",{A_BDISP12},{HEX_B,BRANCH_12}},
|
||||
|
||||
/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}},
|
||||
/* 10001001i8p1.... bt <bdisp8> */{ "bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}},
|
||||
|
||||
/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}},
|
||||
/* 10001011i8p1.... bf <bdisp8> */{ "bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}},
|
||||
|
||||
/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
|
||||
/* 10001101i8p1.... bt.s <bdisp8> */{ "bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
|
||||
|
||||
/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
|
||||
/* 10001101i8p1.... bt/s <bdisp8> */{ "bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
|
||||
|
||||
/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
|
||||
/* 10001111i8p1.... bf.s <bdisp8> */{ "bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
|
||||
|
||||
/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
|
||||
/* 10001111i8p1.... bf/s <bdisp8> */{ "bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
|
||||
|
||||
/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}},
|
||||
/* 0000000000101000 clrmac */{ "clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}},
|
||||
|
||||
/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
|
||||
/* 0000000001001000 clrs */{ "clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
|
||||
|
||||
/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}},
|
||||
/* 0000000000001000 clrt */{ "clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}},
|
||||
|
||||
/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}},
|
||||
/* 10001000i8*1.... cmp/eq #<imm>,R0 */{ "cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}},
|
||||
|
||||
/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}},
|
||||
/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{ "cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}},
|
||||
|
||||
/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}},
|
||||
/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{ "cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}},
|
||||
|
||||
/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}},
|
||||
/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{ "cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}},
|
||||
/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{ "cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}},
|
||||
/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{ "cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}},
|
||||
|
||||
/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}},
|
||||
/* 0100nnnn00010101 cmp/pl <REG_N> */{ "cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}},
|
||||
|
||||
/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}},
|
||||
/* 0100nnnn00010001 cmp/pz <REG_N> */{ "cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}},
|
||||
|
||||
/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}},
|
||||
/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{ "cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}},
|
||||
/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{ "div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}},
|
||||
/* 0000000000011001 div0u */{ "div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}},
|
||||
|
||||
/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}},
|
||||
/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{ "div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}},
|
||||
|
||||
/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}},
|
||||
/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{ "exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}},
|
||||
|
||||
/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}},
|
||||
/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{ "exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}},
|
||||
|
||||
/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}},
|
||||
/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{ "extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}},
|
||||
/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{ "extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}},
|
||||
|
||||
/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}},
|
||||
/* 0100nnnn00101011 jmp @<REG_N> */{ "jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}},
|
||||
|
||||
/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
|
||||
/* 0100nnnn00001011 jsr @<REG_N> */{ "jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
|
||||
|
||||
/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
|
||||
/* 0100nnnn00001110 ldc <REG_N>,SR */{ "ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
|
||||
|
||||
/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
|
||||
/* 0100nnnn00011110 ldc <REG_N>,GBR */{ "ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
|
||||
|
||||
/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
|
||||
/* 0100nnnn00101110 ldc <REG_N>,VBR */{ "ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
|
||||
|
||||
/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
|
||||
/* 0100nnnn00111110 ldc <REG_N>,SSR */{ "ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
|
||||
|
||||
/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
|
||||
/* 0100nnnn01001110 ldc <REG_N>,SPC */{ "ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
|
||||
|
||||
/* 0100nnnn01111110 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
|
||||
/* 0100nnnn01111110 ldc <REG_N>,DBR */{ "ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
|
||||
|
||||
/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
|
||||
/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{ "ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
|
||||
|
||||
/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
|
||||
/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{ "ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
|
||||
|
||||
/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
|
||||
/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{ "ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
|
||||
|
||||
/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
|
||||
/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{ "ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
|
||||
|
||||
/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}},
|
||||
/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{ "ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}},
|
||||
|
||||
/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}},
|
||||
/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{ "ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}},
|
||||
|
||||
/* 0100nnnn01110111 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}},
|
||||
/* 0100nnnn01110111 ldc.l @<REG_N>+,DBR */{ "ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}},
|
||||
|
||||
/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}},
|
||||
/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{ "ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}},
|
||||
|
||||
/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
|
||||
/* 0100nnnn00001010 lds <REG_N>,MACH */{ "lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
|
||||
|
||||
/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}},
|
||||
/* 0100nnnn00011010 lds <REG_N>,MACL */{ "lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}},
|
||||
|
||||
/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}},
|
||||
/* 0100nnnn00101010 lds <REG_N>,PR */{ "lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}},
|
||||
|
||||
/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}},
|
||||
/* 0100nnnn01011010 lds <REG_N>,FPUL */{ "lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}},
|
||||
|
||||
/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}},
|
||||
/* 0100nnnn01101010 lds <REG_M>,FPSCR */{ "lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}},
|
||||
|
||||
/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
|
||||
/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{ "lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
|
||||
|
||||
/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}},
|
||||
/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{ "lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}},
|
||||
|
||||
/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}},
|
||||
/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{ "lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}},
|
||||
|
||||
/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}},
|
||||
/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{ "lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}},
|
||||
|
||||
/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}},
|
||||
/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{ "lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}},
|
||||
|
||||
/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}},
|
||||
/* 0000000000111000 ldtlb */{ "ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}},
|
||||
|
||||
/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}},
|
||||
/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{ "mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}},
|
||||
|
||||
/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}},
|
||||
/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{ "mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}},
|
||||
|
||||
/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}},
|
||||
/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{ "mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}},
|
||||
|
||||
/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
|
||||
/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{ "mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
|
||||
|
||||
/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}},
|
||||
/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{ "mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}},
|
||||
|
||||
/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}},
|
||||
/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{ "mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}},
|
||||
|
||||
/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}},
|
||||
/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{ "mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}},
|
||||
|
||||
/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}},
|
||||
/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{ "mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}},
|
||||
|
||||
/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}},
|
||||
/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{ "mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}},
|
||||
/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{ "mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}},
|
||||
|
||||
/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}},
|
||||
/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{ "mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}},
|
||||
|
||||
/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}},
|
||||
/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{ "mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}},
|
||||
|
||||
/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}},
|
||||
/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{ "mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}},
|
||||
|
||||
/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}},
|
||||
/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{ "mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}},
|
||||
|
||||
/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}},
|
||||
/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{ "mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}},
|
||||
/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{ "mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}},
|
||||
/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{ "mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}},
|
||||
|
||||
/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}},
|
||||
/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{ "mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}},
|
||||
|
||||
/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}},
|
||||
/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{ "mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}},
|
||||
|
||||
/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}},
|
||||
/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{ "mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}},
|
||||
|
||||
/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}},
|
||||
/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{ "mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}},
|
||||
|
||||
/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}},
|
||||
/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{ "mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}},
|
||||
/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{ "mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}},
|
||||
|
||||
/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}},
|
||||
/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{ "mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}},
|
||||
|
||||
/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}},
|
||||
/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{ "mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}},
|
||||
|
||||
/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}},
|
||||
/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{ "mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}},
|
||||
|
||||
/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}},
|
||||
/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{ "mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}},
|
||||
|
||||
/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}},
|
||||
/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{ "mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}},
|
||||
|
||||
/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}},
|
||||
/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{ "mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}},
|
||||
|
||||
/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}},
|
||||
/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{ "mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}},
|
||||
|
||||
/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}},
|
||||
/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{ "mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}},
|
||||
|
||||
/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}},
|
||||
/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{ "mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}},
|
||||
|
||||
/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}},
|
||||
/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{ "mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}},
|
||||
|
||||
/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}},
|
||||
/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{ "mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}},
|
||||
|
||||
/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}},
|
||||
/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{ "mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}},
|
||||
|
||||
/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}},
|
||||
/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}},
|
||||
/* 11000111i8p4.... mova @(<disp>,PC),R0*/{ "mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}},
|
||||
/* 0000nnnn11000011 movca.l R0,@<REG_N> */{ "movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}},
|
||||
|
||||
|
||||
/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}},
|
||||
/* 0000nnnn00101001 movt <REG_N> */{ "movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}},
|
||||
|
||||
/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}},
|
||||
/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{ "muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}},
|
||||
|
||||
/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
|
||||
/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{ "mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}},
|
||||
/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{ "mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}},
|
||||
|
||||
/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}},
|
||||
/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{ "neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}},
|
||||
/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{ "negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
|
||||
/* 0000000000001001 nop */{ "nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
|
||||
|
||||
/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}},
|
||||
/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}},
|
||||
/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{ "not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}},
|
||||
/* 0000nnnn10010011 ocbi @<REG_N> */{ "ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}},
|
||||
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}},
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{ "ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}},
|
||||
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}},
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{ "ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}},
|
||||
|
||||
|
||||
/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}},
|
||||
/* 11001011i8*1.... or #<imm>,R0 */{ "or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}},
|
||||
|
||||
/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}},
|
||||
/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{ "or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}},
|
||||
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{ "or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}},
|
||||
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}},
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{ "pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}},
|
||||
|
||||
/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}},
|
||||
/* 0100nnnn00100100 rotcl <REG_N> */{ "rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}},
|
||||
|
||||
/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}},
|
||||
/* 0100nnnn00100101 rotcr <REG_N> */{ "rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}},
|
||||
|
||||
/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
|
||||
/* 0100nnnn00000100 rotl <REG_N> */{ "rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
|
||||
|
||||
/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
|
||||
/* 0100nnnn00000101 rotr <REG_N> */{ "rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
|
||||
|
||||
/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
|
||||
/* 0000000000101011 rte */{ "rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
|
||||
|
||||
/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
|
||||
/* 0000000000001011 rts */{ "rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
|
||||
|
||||
/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}},
|
||||
/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}},
|
||||
/* 0000000001011000 sets */{ "sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}},
|
||||
/* 0000000000011000 sett */{ "sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}},
|
||||
|
||||
/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}},
|
||||
/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{ "shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}},
|
||||
/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{ "shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
|
||||
/* 0100nnnn00100000 shal <REG_N> */{ "shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
|
||||
|
||||
/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}},
|
||||
/* 0100nnnn00100001 shar <REG_N> */{ "shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}},
|
||||
|
||||
/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
|
||||
/* 0100nnnn00000000 shll <REG_N> */{ "shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
|
||||
|
||||
/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}},
|
||||
/* 0100nnnn00101000 shll16 <REG_N> */{ "shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}},
|
||||
|
||||
/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
|
||||
/* 0100nnnn00001000 shll2 <REG_N> */{ "shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
|
||||
|
||||
/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}},
|
||||
/* 0100nnnn00011000 shll8 <REG_N> */{ "shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}},
|
||||
|
||||
/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
|
||||
/* 0100nnnn00000001 shlr <REG_N> */{ "shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
|
||||
|
||||
/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}},
|
||||
/* 0100nnnn00101001 shlr16 <REG_N> */{ "shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}},
|
||||
|
||||
/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
|
||||
/* 0100nnnn00001001 shlr2 <REG_N> */{ "shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
|
||||
|
||||
/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}},
|
||||
/* 0100nnnn00011001 shlr8 <REG_N> */{ "shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}},
|
||||
|
||||
/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}},
|
||||
/* 0000000000011011 sleep */{ "sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}},
|
||||
|
||||
/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}},
|
||||
/* 0000nnnn00000010 stc SR,<REG_N> */{ "stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}},
|
||||
|
||||
/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}},
|
||||
/* 0000nnnn00010010 stc GBR,<REG_N> */{ "stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}},
|
||||
|
||||
/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}},
|
||||
/* 0000nnnn00100010 stc VBR,<REG_N> */{ "stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}},
|
||||
|
||||
/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}},
|
||||
/* 0000nnnn00110010 stc SSR,<REG_N> */{ "stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}},
|
||||
|
||||
/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
|
||||
/* 0000nnnn01000010 stc SPC,<REG_N> */{ "stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
|
||||
|
||||
/* 0000nnnn01100010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}},
|
||||
/* 0000nnnn01100010 stc SGR,<REG_N> */{ "stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}},
|
||||
|
||||
/* 0000nnnn01110010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}},
|
||||
/* 0000nnnn01110010 stc DBR,<REG_N> */{ "stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}},
|
||||
|
||||
/* 0000nnnn1xxx0012 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}},
|
||||
/* 0000nnnn1xxx0012 stc Rn_BANK,<REG_N> */{ "stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}},
|
||||
|
||||
/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
|
||||
/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{ "stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
|
||||
|
||||
/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}},
|
||||
/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{ "stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}},
|
||||
|
||||
/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}},
|
||||
/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{ "stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}},
|
||||
|
||||
/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}},
|
||||
/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{ "stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}},
|
||||
|
||||
/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}},
|
||||
/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{ "stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}},
|
||||
|
||||
/* 0100nnnn01100011 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}},
|
||||
/* 0100nnnn01100011 stc.l SGR,@-<REG_N> */{ "stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}},
|
||||
|
||||
/* 0100nnnn01110011 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}},
|
||||
/* 0100nnnn01110011 stc.l DBR,@-<REG_N> */{ "stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}},
|
||||
|
||||
/* 0100nnnn1xxx0012 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}},
|
||||
/* 0100nnnn1xxx0012 stc.l Rn_BANK,@-<REG_N> */{ "stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}},
|
||||
|
||||
/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}},
|
||||
/* 0000nnnn00001010 sts MACH,<REG_N> */{ "sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}},
|
||||
|
||||
/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}},
|
||||
/* 0000nnnn00011010 sts MACL,<REG_N> */{ "sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}},
|
||||
|
||||
/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}},
|
||||
/* 0000nnnn00101010 sts PR,<REG_N> */{ "sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}},
|
||||
|
||||
/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}},
|
||||
/* 0000nnnn01011010 sts FPUL,<REG_N> */{ "sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}},
|
||||
|
||||
/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}},
|
||||
/* 0000nnnn01101010 sts FPSCR,<REG_N> */{ "sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}},
|
||||
|
||||
/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
|
||||
/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{ "sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
|
||||
|
||||
/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}},
|
||||
/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{ "sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}},
|
||||
|
||||
/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}},
|
||||
/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{ "sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}},
|
||||
|
||||
/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}},
|
||||
/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{ "sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}},
|
||||
|
||||
/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}},
|
||||
/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{ "sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}},
|
||||
|
||||
/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}},
|
||||
/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{ "sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}},
|
||||
/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{ "subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}},
|
||||
/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{ "subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}},
|
||||
/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{ "swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}},
|
||||
/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{ "swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}},
|
||||
|
||||
/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}},
|
||||
/* 0100nnnn00011011 tas.b @<REG_N> */{ "tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}},
|
||||
|
||||
/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}},
|
||||
/* 11000011i8*1.... trapa #<imm> */{ "trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}},
|
||||
|
||||
/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}},
|
||||
/* 11001000i8*1.... tst #<imm>,R0 */{ "tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}},
|
||||
|
||||
/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}},
|
||||
/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{ "tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}},
|
||||
/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{ "tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}},
|
||||
|
||||
/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}},
|
||||
/* 11001010i8*1.... xor #<imm>,R0 */{ "xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}},
|
||||
|
||||
/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}},
|
||||
/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{ "xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}},
|
||||
/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{ "xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}},
|
||||
|
||||
/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}},
|
||||
/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{ "xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}},
|
||||
|
||||
/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
|
||||
/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{ "mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
|
||||
/* 0100nnnn00010000 dt <REG_N> */{ "dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
|
||||
|
||||
/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}},
|
||||
/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{ "dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}},
|
||||
|
||||
/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}},
|
||||
/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{ "dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}},
|
||||
|
||||
/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}},
|
||||
/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{ "mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}},
|
||||
|
||||
/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}},
|
||||
/* 0000nnnn00100011 braf <REG_N> */{ "braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}},
|
||||
|
||||
/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}},
|
||||
/* 0000nnnn00000011 bsrf <REG_N> */{ "bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}},
|
||||
|
||||
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}},
|
||||
/* 1111nnnn01011101 fabs <F_REG_N> */{ "fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}},
|
||||
|
||||
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
|
||||
/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
|
||||
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{ "fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
|
||||
/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{ "fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
|
||||
|
||||
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
|
||||
/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
|
||||
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{ "fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
|
||||
/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{ "fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
|
||||
|
||||
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
|
||||
/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
|
||||
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{ "fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
|
||||
/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{ "fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
|
||||
|
||||
/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}},
|
||||
/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{ "fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}},
|
||||
|
||||
/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}},
|
||||
/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{ "fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}},
|
||||
|
||||
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
|
||||
/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
|
||||
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{ "fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
|
||||
/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{ "fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
|
||||
|
||||
/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}},
|
||||
/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{ "fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}},
|
||||
|
||||
/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}},
|
||||
/* 1111nnnn10001101 fldi0 <F_REG_N> */{ "fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}},
|
||||
|
||||
/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}},
|
||||
/* 1111nnnn10011101 fldi1 <F_REG_N> */{ "fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}},
|
||||
|
||||
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}},
|
||||
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{ "flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}},
|
||||
|
||||
/* 1111nnnn00101101 float FPUL,<FD_REG_N>*/{"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}},
|
||||
/* 1111nnnn00101101 float FPUL,<FD_REG_N>*/{ "float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}},
|
||||
|
||||
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}},
|
||||
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{ "fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}},
|
||||
|
||||
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
|
||||
/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
|
||||
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{ "fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
|
||||
/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{ "fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
|
||||
|
||||
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{ "fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{ "fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{ "fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{ "fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{ "fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{ "fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
|
||||
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{ "fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{ "fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{ "fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{ "fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{ "fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{ "fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{ "fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 1111nnnnmmmm1010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
/* 1111nnnnmmmm1010 fmov.d <DX_REG_M>,@<REG_N>*/{ "fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 1111nnnnmmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
/* 1111nnnnmmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{ "fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
|
||||
/* 1111nnnnmmmm1011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
/* 1111nnnnmmmm1011 fmov.d <DX_REG_M>,@-<REG_N>*/{ "fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 1111nnnnmmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
/* 1111nnnnmmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{ "fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{ "fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{ "fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
|
||||
|
||||
/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{ "fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
|
||||
|
||||
/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{ "fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
|
||||
|
||||
/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{ "fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
|
||||
|
||||
/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{ "fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
|
||||
|
||||
/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{ "fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
|
||||
|
||||
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
|
||||
/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
|
||||
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{ "fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
|
||||
/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{ "fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
|
||||
|
||||
/* 1111nnnn01001101 fneg <FD_REG_N> */{"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}},
|
||||
/* 1111nnnn01001101 fneg <FD_REG_N> */{ "fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}},
|
||||
|
||||
/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}},
|
||||
/* 1111101111111101 frchg */{ "frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}},
|
||||
|
||||
/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}},
|
||||
/* 1111001111111101 fschg */{ "fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}},
|
||||
|
||||
/* 1111nnnn01101101 fsqrt <FD_REG_N> */{"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}},
|
||||
/* 1111nnnn01101101 fsqrt <FD_REG_N> */{ "fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}},
|
||||
|
||||
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}},
|
||||
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{ "fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}},
|
||||
|
||||
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
|
||||
/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
|
||||
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{ "fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
|
||||
/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{ "fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
|
||||
|
||||
/* 1111nnnn00111101 ftrc <FD_REG_N>,FPUL*/{"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}},
|
||||
/* 1111nnnn00111101 ftrc <FD_REG_N>,FPUL*/{ "ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}},
|
||||
|
||||
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}},
|
||||
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{ "ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}},
|
||||
|
||||
{ 0 }
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4225,365 +4225,365 @@ typedef struct lookup_t {
|
|||
} LookupTable;
|
||||
|
||||
LookupTable oplookup[] = {
|
||||
{"aaa", 0, NULL, 0x37, 1},
|
||||
{"aad", 0, NULL, 0xd50a, 2},
|
||||
{"aam", 0, opaam, 0},
|
||||
{"aas", 0, NULL, 0x3f, 1},
|
||||
{"adc", 0, &opadc, 0},
|
||||
{"add", 0, &opadd, 0},
|
||||
{"adx", 0, NULL, 0xd4, 1},
|
||||
{"amx", 0, NULL, 0xd5, 1},
|
||||
{"and", 0, &opand, 0},
|
||||
{"bsf", 0, &opbs, 0},
|
||||
{"bsr", 0, &opbs, 0},
|
||||
{"bswap", 0, &opbswap, 0},
|
||||
{"call", 0, &opcall, 0},
|
||||
{"cbw", 0, NULL, 0x6698, 2},
|
||||
{"cdq", 0, NULL, 0x99, 1},
|
||||
{"cdqe", 0, &opcdqe, 0},
|
||||
{"cwde", 0, &opcdqe, 0},
|
||||
{"clc", 0, NULL, 0xf8, 1},
|
||||
{"cld", 0, NULL, 0xfc, 1},
|
||||
{"clflush", 0, &opclflush, 0},
|
||||
{"clgi", 0, NULL, 0x0f01dd, 3},
|
||||
{"cli", 0, NULL, 0xfa, 1},
|
||||
{"clts", 0, NULL, 0x0f06, 2},
|
||||
{"cmc", 0, NULL, 0xf5, 1},
|
||||
{"cmovo", 0, &opcmov, 0},
|
||||
{"cmovno", 0, &opcmov, 0},
|
||||
{"cmovb", 0, &opcmov, 0},
|
||||
{"cmovc", 0, &opcmov, 0},
|
||||
{"cmovnae", 0, &opcmov, 0},
|
||||
{"cmovae", 0, &opcmov, 0},
|
||||
{"cmovnb", 0, &opcmov, 0},
|
||||
{"cmovnc", 0, &opcmov, 0},
|
||||
{"cmove", 0, &opcmov, 0},
|
||||
{"cmovz", 0, &opcmov, 0},
|
||||
{"cmovne", 0, &opcmov, 0},
|
||||
{"cmovnz", 0, &opcmov, 0},
|
||||
{"cmovbe", 0, &opcmov, 0},
|
||||
{"cmovna", 0, &opcmov, 0},
|
||||
{"cmova", 0, &opcmov, 0},
|
||||
{"cmovnbe", 0, &opcmov, 0},
|
||||
{"cmovne", 0, &opcmov, 0},
|
||||
{"cmovnz", 0, &opcmov, 0},
|
||||
{"cmovs", 0, &opcmov, 0},
|
||||
{"cmovns", 0, &opcmov, 0},
|
||||
{"cmovp", 0, &opcmov, 0},
|
||||
{"cmovpe", 0, &opcmov, 0},
|
||||
{"cmovnp", 0, &opcmov, 0},
|
||||
{"cmovpo", 0, &opcmov, 0},
|
||||
{"cmovl", 0, &opcmov, 0},
|
||||
{"cmovnge", 0, &opcmov, 0},
|
||||
{"cmovge", 0, &opcmov, 0},
|
||||
{"cmovnl", 0, &opcmov, 0},
|
||||
{"cmovle", 0, &opcmov, 0},
|
||||
{"cmovng", 0, &opcmov, 0},
|
||||
{"cmovg", 0, &opcmov, 0},
|
||||
{"cmovnle", 0, &opcmov, 0},
|
||||
{"cmp", 0, &opcmp, 0},
|
||||
{"cmpsb", 0, NULL, 0xa6, 1},
|
||||
{"cmpsd", 0, NULL, 0xa7, 1},
|
||||
{"cmpsw", 0, NULL, 0x66a7, 2},
|
||||
{"cpuid", 0, NULL, 0x0fa2, 2},
|
||||
{"cwd", 0, NULL, 0x6699, 2},
|
||||
{"cwde", 0, NULL, 0x98, 1},
|
||||
{"daa", 0, NULL, 0x27, 1},
|
||||
{"das", 0, NULL, 0x2f, 1},
|
||||
{"dec", 0, &opdec, 0},
|
||||
{"div", 0, &opdiv, 0},
|
||||
{"emms", 0, NULL, 0x0f77, 2},
|
||||
{"endbr32", 0, endbr32, 0},
|
||||
{"endbr64", 0, endbr64, 0},
|
||||
{"f2xm1", 0, NULL, 0xd9f0, 2},
|
||||
{"fabs", 0, NULL, 0xd9e1, 2},
|
||||
{"fadd", 0, &opfadd, 0},
|
||||
{"faddp", 0, &opfaddp, 0},
|
||||
{"fbld", 0, &opfbld, 0},
|
||||
{"fbstp", 0, &opfbstp, 0},
|
||||
{"fchs", 0, NULL, 0xd9e0, 2},
|
||||
{"fclex", 0, NULL, 0x9bdbe2, 3},
|
||||
{"fcmovb", 0, &opfcmov, 0},
|
||||
{"fcmove", 0, &opfcmov, 0},
|
||||
{"fcmovbe", 0, &opfcmov, 0},
|
||||
{"fcmovu", 0, &opfcmov, 0},
|
||||
{"fcmovnb", 0, &opfcmov, 0},
|
||||
{"fcmovne", 0, &opfcmov, 0},
|
||||
{"fcmovnbe", 0, &opfcmov, 0},
|
||||
{"fcmovnu", 0, &opfcmov, 0},
|
||||
{"fcos", 0, NULL, 0xd9ff, 2},
|
||||
{"fdecstp", 0, NULL, 0xd9f6, 2},
|
||||
{"fdiv", 0, &opfdiv, 0},
|
||||
{"fdivp", 0, &opfdivp, 0},
|
||||
{"fdivr", 0, &opfdivr, 0},
|
||||
{"fdivrp", 0, &opfdivrp, 0},
|
||||
{"femms", 0, NULL, 0x0f0e, 2},
|
||||
{"ffree", 0, &opffree, 0},
|
||||
{"fiadd", 0, &opfiadd, 0},
|
||||
{"ficom", 0, &opficom, 0},
|
||||
{"ficomp", 0, &opficomp, 0},
|
||||
{"fidiv", 0, &opfidiv, 0},
|
||||
{"fidivr", 0, &opfidivr, 0},
|
||||
{"fild", 0, &opfild, 0},
|
||||
{"fimul", 0, &opfimul, 0},
|
||||
{"fincstp", 0, NULL, 0xd9f7, 2},
|
||||
{"finit", 0, NULL, 0x9bdbe3, 3},
|
||||
{"fist", 0, &opfist, 0},
|
||||
{"fistp", 0, &opfistp, 0},
|
||||
{"fisttp", 0, &opfisttp, 0},
|
||||
{"fisub", 0, &opfisub, 0},
|
||||
{"fisubr", 0, &opfisubr, 0},
|
||||
{"fld1", 0, NULL, 0xd9e8, 2},
|
||||
{"fldcw", 0, &opfldcw, 0},
|
||||
{"fldenv", 0, &opfldenv, 0},
|
||||
{"fldl2t", 0, NULL, 0xd9e9, 2},
|
||||
{"fldl2e", 0, NULL, 0xd9ea, 2},
|
||||
{"fldlg2", 0, NULL, 0xd9ec, 2},
|
||||
{"fldln2", 0, NULL, 0xd9ed, 2},
|
||||
{"fldpi", 0, NULL, 0xd9eb, 2},
|
||||
{"fldz", 0, NULL, 0xd9ee, 2},
|
||||
{"fmul", 0, &opfmul, 0},
|
||||
{"fmulp", 0, &opfmulp, 0},
|
||||
{"fnclex", 0, NULL, 0xdbe2, 2},
|
||||
{"fninit", 0, NULL, 0xdbe3, 2},
|
||||
{"fnop", 0, NULL, 0xd9d0, 2},
|
||||
{"fnsave", 0, &opfnsave, 0},
|
||||
{"fnstcw", 0, &opfnstcw, 0},
|
||||
{"fnstenv", 0, &opfnstenv, 0},
|
||||
{"fnstsw", 0, &opfnstsw, 0},
|
||||
{"fpatan", 0, NULL, 0xd9f3, 2},
|
||||
{"fprem", 0, NULL, 0xd9f8, 2},
|
||||
{"fprem1", 0, NULL, 0xd9f5, 2},
|
||||
{"fptan", 0, NULL, 0xd9f2, 2},
|
||||
{"frndint", 0, NULL, 0xd9fc, 2},
|
||||
{"frstor", 0, &opfrstor, 0},
|
||||
{"fsave", 0, &opfsave, 0},
|
||||
{"fscale", 0, NULL, 0xd9fd, 2},
|
||||
{"fsin", 0, NULL, 0xd9fe, 2},
|
||||
{"fsincos", 0, NULL, 0xd9fb, 2},
|
||||
{"fsqrt", 0, NULL, 0xd9fa, 2},
|
||||
{"fstcw", 0, &opfstcw, 0},
|
||||
{"fstenv", 0, &opfstenv, 0},
|
||||
{"fstsw", 0, &opfstsw, 0},
|
||||
{"fsub", 0, &opfsub, 0},
|
||||
{"fsubp", 0, &opfsubp, 0},
|
||||
{"fsubr", 0, &opfsubr, 0},
|
||||
{"fsubrp", 0, &opfsubrp, 0},
|
||||
{"ftst", 0, NULL, 0xd9e4, 2},
|
||||
{"fucom", 0, &opfucom, 0},
|
||||
{"fucomp", 0, &opfucomp, 0},
|
||||
{"fucompp", 0, NULL, 0xdae9, 2},
|
||||
{"fwait", 0, NULL, 0x9b, 1},
|
||||
{"fxam", 0, NULL, 0xd9e5, 2},
|
||||
{"fxch", 0, &opfxch, 0},
|
||||
{"fxrstor", 0, &opfxrstor, 0},
|
||||
{"fxsave", 0, &opfxsave, 0},
|
||||
{"fxtract", 0, NULL, 0xd9f4, 2},
|
||||
{"fyl2x", 0, NULL, 0xd9f1, 2},
|
||||
{"fyl2xp1", 0, NULL, 0xd9f9, 2},
|
||||
{"getsec", 0, NULL, 0x0f37, 2},
|
||||
{"hlt", 0, NULL, 0xf4, 1},
|
||||
{"idiv", 0, &opidiv, 0},
|
||||
{"imul", 0, &opimul, 0},
|
||||
{"in", 0, &opin, 0},
|
||||
{"inc", 0, &opinc, 0},
|
||||
{"ins", 0, NULL, 0x6d, 1},
|
||||
{"insb", 0, NULL, 0x6c, 1},
|
||||
{"insd", 0, NULL, 0x6d, 1},
|
||||
{"insw", 0, NULL, 0x666d, 2},
|
||||
{"int", 0, &opint, 0},
|
||||
{"int1", 0, NULL, 0xf1, 1},
|
||||
{"int3", 0, NULL, 0xcc, 1},
|
||||
{"into", 0, NULL, 0xce, 1},
|
||||
{"invd", 0, NULL, 0x0f08, 2},
|
||||
{"iret", 0, NULL, 0x66cf, 2},
|
||||
{"iretd", 0, NULL, 0xcf, 1},
|
||||
{"ja", 0, &opjc, 0},
|
||||
{"jae", 0, &opjc, 0},
|
||||
{"jb", 0, &opjc, 0},
|
||||
{"jbe", 0, &opjc, 0},
|
||||
{"jc", 0, &opjc, 0},
|
||||
{"je", 0, &opjc, 0},
|
||||
{"jg", 0, &opjc, 0},
|
||||
{"jge", 0, &opjc, 0},
|
||||
{"jl", 0, &opjc, 0},
|
||||
{"jle", 0, &opjc, 0},
|
||||
{"jmp", 0, &opjc, 0},
|
||||
{"jna", 0, &opjc, 0},
|
||||
{"jnae", 0, &opjc, 0},
|
||||
{"jnb", 0, &opjc, 0},
|
||||
{"jnbe", 0, &opjc, 0},
|
||||
{"jnc", 0, &opjc, 0},
|
||||
{"jne", 0, &opjc, 0},
|
||||
{"jng", 0, &opjc, 0},
|
||||
{"jnge", 0, &opjc, 0},
|
||||
{"jnl", 0, &opjc, 0},
|
||||
{"jnle", 0, &opjc, 0},
|
||||
{"jno", 0, &opjc, 0},
|
||||
{"jnp", 0, &opjc, 0},
|
||||
{"jns", 0, &opjc, 0},
|
||||
{"jnz", 0, &opjc, 0},
|
||||
{"jo", 0, &opjc, 0},
|
||||
{"jp", 0, &opjc, 0},
|
||||
{"jpe", 0, &opjc, 0},
|
||||
{"jpo", 0, &opjc, 0},
|
||||
{"js", 0, &opjc, 0},
|
||||
{"jz", 0, &opjc, 0},
|
||||
{"jcxz", 0, &opjc, 0},
|
||||
{"jecxz", 0, &opjc, 0},
|
||||
{"jrcxz", 0, &opjc, 0},
|
||||
{"lahf", 0, NULL, 0x9f, 1},
|
||||
{"lea", 0, &oplea, 0},
|
||||
{"leave", 0, NULL, 0xc9, 1},
|
||||
{"les", 0, &oples, 0},
|
||||
{"lfence", 0, NULL, 0x0faee8, 3},
|
||||
{"lgdt", 0, &oplgdt, 0},
|
||||
{"lidt", 0, &oplidt, 0},
|
||||
{"lldt", 0, &oplldt, 0},
|
||||
{"lmsw", 0, &oplmsw, 0},
|
||||
{"lodsb", 0, NULL, 0xac, 1},
|
||||
{"lodsd", 0, NULL, 0xad, 1},
|
||||
{"lodsw", 0, NULL, 0x66ad, 2},
|
||||
{"loop", 0, &oploop, 0},
|
||||
{"mfence", 0, NULL, 0x0faef0, 3},
|
||||
{"monitor", 0, NULL, 0x0f01c8, 3},
|
||||
{"mov", 0, &opmov, 0},
|
||||
{"movsb", 0, NULL, 0xa4, 1},
|
||||
{"movsd", 0, NULL, 0xa5, 1},
|
||||
{"movsw", 0, NULL, 0x66a5, 2},
|
||||
{"movzx", 0, &opmovx, 0},
|
||||
{"movsx", 0, &opmovx, 0},
|
||||
{"movabs", 0, &opmovabs, 0},
|
||||
{"mul", 0, &opmul, 0},
|
||||
{"mwait", 0, NULL, 0x0f01c9, 3},
|
||||
{"neg", 0, &opneg, 0},
|
||||
{"nop", 0, NULL, 0x90, 1},
|
||||
{"not", 0, &opnot, 0},
|
||||
{"or", 0, &opor, 0},
|
||||
{"out", 0, &opout, 0},
|
||||
{"outsb", 0, NULL, 0x6e, 1},
|
||||
{"outs", 0, NULL, 0x6f, 1},
|
||||
{"outsd", 0, NULL, 0x6f, 1},
|
||||
{"outsw", 0, NULL, 0x666f, 2},
|
||||
{"pop", 0, &oppop, 0},
|
||||
{"popa", 1, NULL, 0x61, 1},
|
||||
{"popad", 1, NULL, 0x61, 1},
|
||||
{"popal", 1, NULL, 0x61, 1},
|
||||
{"popaw", 1, NULL, 0x6661, 2},
|
||||
{"popfd", 1, NULL, 0x9d, 1},
|
||||
{"prefetch", 0, NULL, 0x0f0d, 2},
|
||||
{"push", 0, &oppush, 0},
|
||||
{"pusha", 1, NULL, 0x60, 1},
|
||||
{"pushad", 1, NULL, 0x60, 1},
|
||||
{"pushal", 1, NULL, 0x60, 1},
|
||||
{"pushf", 0, NULL, 0x669c, 2},
|
||||
{"popf", 0, NULL, 0x669d, 2},
|
||||
{"pushfd", 0, NULL, 0x9c, 1},
|
||||
{"rcl", 0, &process_group_2, 0},
|
||||
{"rcr", 0, &process_group_2, 0},
|
||||
{"rep", 0, &oprep, 0},
|
||||
{"repe", 0, &oprep, 0},
|
||||
{"repne", 0, &oprep, 0},
|
||||
{"repz", 0, &oprep, 0},
|
||||
{"repnz", 0, &oprep, 0},
|
||||
{"rdmsr", 0, NULL, 0x0f32, 2},
|
||||
{"rdpmc", 0, NULL, 0x0f33, 2},
|
||||
{"rdtsc", 0, NULL, 0x0f31, 2},
|
||||
{"rdtscp", 0, NULL, 0x0f01f9, 3},
|
||||
{"ret", 0, &opret, 0},
|
||||
{"retf", 0, &opretf, 0},
|
||||
{"retw", 0, NULL, 0x66c3, 2},
|
||||
{"rol", 0, &process_group_2, 0},
|
||||
{"ror", 0, &process_group_2, 0},
|
||||
{"rsm", 0, NULL, 0x0faa, 2},
|
||||
{"sahf", 0, NULL, 0x9e, 1},
|
||||
{"sal", 0, &process_group_2, 0},
|
||||
{"salc", 0, NULL, 0xd6, 1},
|
||||
{"sar", 0, &process_group_2, 0},
|
||||
{"sbb", 0, &opsbb, 0},
|
||||
{"scasb", 0, NULL, 0xae, 1},
|
||||
{"scasd", 0, NULL, 0xaf, 1},
|
||||
{"scasw", 0, NULL, 0x66af, 2},
|
||||
{"seto", 0, &opset, 0},
|
||||
{"setno", 0, &opset, 0},
|
||||
{"setb", 0, &opset, 0},
|
||||
{"setnae", 0, &opset, 0},
|
||||
{"setc", 0, &opset, 0},
|
||||
{"setnb", 0, &opset, 0},
|
||||
{"setae", 0, &opset, 0},
|
||||
{"setnc", 0, &opset, 0},
|
||||
{"setz", 0, &opset, 0},
|
||||
{"sete", 0, &opset, 0},
|
||||
{"setnz", 0, &opset, 0},
|
||||
{"setne", 0, &opset, 0},
|
||||
{"setbe", 0, &opset, 0},
|
||||
{"setna", 0, &opset, 0},
|
||||
{"setnbe", 0, &opset, 0},
|
||||
{"seta", 0, &opset, 0},
|
||||
{"sets", 0, &opset, 0},
|
||||
{"setns", 0, &opset, 0},
|
||||
{"setp", 0, &opset, 0},
|
||||
{"setpe", 0, &opset, 0},
|
||||
{"setnp", 0, &opset, 0},
|
||||
{"setpo", 0, &opset, 0},
|
||||
{"setl", 0, &opset, 0},
|
||||
{"setnge", 0, &opset, 0},
|
||||
{"setnl", 0, &opset, 0},
|
||||
{"setge", 0, &opset, 0},
|
||||
{"setle", 0, &opset, 0},
|
||||
{"setng", 0, &opset, 0},
|
||||
{"setnle", 0, &opset, 0},
|
||||
{"setg", 0, &opset, 0},
|
||||
{"sfence", 0, NULL, 0x0faef8, 3},
|
||||
{"sgdt", 0, &opsgdt, 0},
|
||||
{"shl", 0, &process_group_2, 0},
|
||||
{"shr", 0, &process_group_2, 0},
|
||||
{"sidt", 0, &opsidt, 0},
|
||||
{"sldt", 0, &opsldt, 0},
|
||||
{"smsw", 0, &opsmsw, 0},
|
||||
{"stc", 0, NULL, 0xf9, 1},
|
||||
{"std", 0, NULL, 0xfd, 1},
|
||||
{"stgi", 0, NULL, 0x0f01dc, 3},
|
||||
{"sti", 0, NULL, 0xfb, 1},
|
||||
{"stmxcsr", 0, &opstmxcsr, 0},
|
||||
{"stosb", 0, &opstos, 0},
|
||||
{"stosd", 0, &opstos, 0},
|
||||
{"stosw", 0, &opstos, 0},
|
||||
{"str", 0, &opstr, 0},
|
||||
{"sub", 0, &opsub, 0},
|
||||
{"swapgs", 0, NULL, 0x0f1ff8, 3},
|
||||
{"syscall", 0, NULL, 0x0f05, 2},
|
||||
{"sysenter", 0, NULL, 0x0f34, 2},
|
||||
{"sysexit", 0, NULL, 0x0f35, 2},
|
||||
{"sysret", 0, NULL, 0x0f07, 2},
|
||||
{"ud2", 0, NULL, 0x0f0b, 2},
|
||||
{"verr", 0, &opverr, 0},
|
||||
{"verw", 0, &opverw, 0},
|
||||
{"vmcall", 0, NULL, 0x0f01c1, 3},
|
||||
{"vmclear", 0, &opvmclear, 0},
|
||||
{"vmlaunch", 0, NULL, 0x0f01c2, 3},
|
||||
{"vmload", 0, NULL, 0x0f01da, 3},
|
||||
{"vmmcall", 0, NULL, 0x0f01d9, 3},
|
||||
{"vmptrld", 0, &opvmptrld, 0},
|
||||
{"vmptrst", 0, &opvmptrst, 0},
|
||||
{"vmresume", 0, NULL, 0x0f01c3, 3},
|
||||
{"vmrun", 0, NULL, 0x0f01d8, 3},
|
||||
{"vmsave", 0, NULL, 0x0f01db, 3},
|
||||
{"vmxoff", 0, NULL, 0x0f01c4, 3},
|
||||
{"vmxon", 0, &opvmon, 0},
|
||||
{"vzeroall", 0, NULL, 0xc5fc77, 3},
|
||||
{"vzeroupper", 0, NULL, 0xc5f877, 3},
|
||||
{"wait", 0, NULL, 0x9b, 1},
|
||||
{"wbinvd", 0, NULL, 0x0f09, 2},
|
||||
{"wrmsr", 0, NULL, 0x0f30, 2},
|
||||
{"xadd", 0, &opxadd, 0},
|
||||
{"xchg", 0, &opxchg, 0},
|
||||
{"xgetbv", 0, NULL, 0x0f01d0, 3},
|
||||
{"xlatb", 0, NULL, 0xd7, 1},
|
||||
{"xor", 0, &opxor, 0},
|
||||
{"xsetbv", 0, NULL, 0x0f01d1, 3},
|
||||
{"test", 0, &optest, 0},
|
||||
{"null", 0, NULL, 0, 0}
|
||||
{ "aaa", 0, NULL, 0x37, 1},
|
||||
{ "aad", 0, NULL, 0xd50a, 2},
|
||||
{ "aam", 0, opaam, 0},
|
||||
{ "aas", 0, NULL, 0x3f, 1},
|
||||
{ "adc", 0, &opadc, 0},
|
||||
{ "add", 0, &opadd, 0},
|
||||
{ "adx", 0, NULL, 0xd4, 1},
|
||||
{ "amx", 0, NULL, 0xd5, 1},
|
||||
{ "and", 0, &opand, 0},
|
||||
{ "bsf", 0, &opbs, 0},
|
||||
{ "bsr", 0, &opbs, 0},
|
||||
{ "bswap", 0, &opbswap, 0},
|
||||
{ "call", 0, &opcall, 0},
|
||||
{ "cbw", 0, NULL, 0x6698, 2},
|
||||
{ "cdq", 0, NULL, 0x99, 1},
|
||||
{ "cdqe", 0, &opcdqe, 0},
|
||||
{ "cwde", 0, &opcdqe, 0},
|
||||
{ "clc", 0, NULL, 0xf8, 1},
|
||||
{ "cld", 0, NULL, 0xfc, 1},
|
||||
{ "clflush", 0, &opclflush, 0},
|
||||
{ "clgi", 0, NULL, 0x0f01dd, 3},
|
||||
{ "cli", 0, NULL, 0xfa, 1},
|
||||
{ "clts", 0, NULL, 0x0f06, 2},
|
||||
{ "cmc", 0, NULL, 0xf5, 1},
|
||||
{ "cmovo", 0, &opcmov, 0},
|
||||
{ "cmovno", 0, &opcmov, 0},
|
||||
{ "cmovb", 0, &opcmov, 0},
|
||||
{ "cmovc", 0, &opcmov, 0},
|
||||
{ "cmovnae", 0, &opcmov, 0},
|
||||
{ "cmovae", 0, &opcmov, 0},
|
||||
{ "cmovnb", 0, &opcmov, 0},
|
||||
{ "cmovnc", 0, &opcmov, 0},
|
||||
{ "cmove", 0, &opcmov, 0},
|
||||
{ "cmovz", 0, &opcmov, 0},
|
||||
{ "cmovne", 0, &opcmov, 0},
|
||||
{ "cmovnz", 0, &opcmov, 0},
|
||||
{ "cmovbe", 0, &opcmov, 0},
|
||||
{ "cmovna", 0, &opcmov, 0},
|
||||
{ "cmova", 0, &opcmov, 0},
|
||||
{ "cmovnbe", 0, &opcmov, 0},
|
||||
{ "cmovne", 0, &opcmov, 0},
|
||||
{ "cmovnz", 0, &opcmov, 0},
|
||||
{ "cmovs", 0, &opcmov, 0},
|
||||
{ "cmovns", 0, &opcmov, 0},
|
||||
{ "cmovp", 0, &opcmov, 0},
|
||||
{ "cmovpe", 0, &opcmov, 0},
|
||||
{ "cmovnp", 0, &opcmov, 0},
|
||||
{ "cmovpo", 0, &opcmov, 0},
|
||||
{ "cmovl", 0, &opcmov, 0},
|
||||
{ "cmovnge", 0, &opcmov, 0},
|
||||
{ "cmovge", 0, &opcmov, 0},
|
||||
{ "cmovnl", 0, &opcmov, 0},
|
||||
{ "cmovle", 0, &opcmov, 0},
|
||||
{ "cmovng", 0, &opcmov, 0},
|
||||
{ "cmovg", 0, &opcmov, 0},
|
||||
{ "cmovnle", 0, &opcmov, 0},
|
||||
{ "cmp", 0, &opcmp, 0},
|
||||
{ "cmpsb", 0, NULL, 0xa6, 1},
|
||||
{ "cmpsd", 0, NULL, 0xa7, 1},
|
||||
{ "cmpsw", 0, NULL, 0x66a7, 2},
|
||||
{ "cpuid", 0, NULL, 0x0fa2, 2},
|
||||
{ "cwd", 0, NULL, 0x6699, 2},
|
||||
{ "cwde", 0, NULL, 0x98, 1},
|
||||
{ "daa", 0, NULL, 0x27, 1},
|
||||
{ "das", 0, NULL, 0x2f, 1},
|
||||
{ "dec", 0, &opdec, 0},
|
||||
{ "div", 0, &opdiv, 0},
|
||||
{ "emms", 0, NULL, 0x0f77, 2},
|
||||
{ "endbr32", 0, endbr32, 0},
|
||||
{ "endbr64", 0, endbr64, 0},
|
||||
{ "f2xm1", 0, NULL, 0xd9f0, 2},
|
||||
{ "fabs", 0, NULL, 0xd9e1, 2},
|
||||
{ "fadd", 0, &opfadd, 0},
|
||||
{ "faddp", 0, &opfaddp, 0},
|
||||
{ "fbld", 0, &opfbld, 0},
|
||||
{ "fbstp", 0, &opfbstp, 0},
|
||||
{ "fchs", 0, NULL, 0xd9e0, 2},
|
||||
{ "fclex", 0, NULL, 0x9bdbe2, 3},
|
||||
{ "fcmovb", 0, &opfcmov, 0},
|
||||
{ "fcmove", 0, &opfcmov, 0},
|
||||
{ "fcmovbe", 0, &opfcmov, 0},
|
||||
{ "fcmovu", 0, &opfcmov, 0},
|
||||
{ "fcmovnb", 0, &opfcmov, 0},
|
||||
{ "fcmovne", 0, &opfcmov, 0},
|
||||
{ "fcmovnbe", 0, &opfcmov, 0},
|
||||
{ "fcmovnu", 0, &opfcmov, 0},
|
||||
{ "fcos", 0, NULL, 0xd9ff, 2},
|
||||
{ "fdecstp", 0, NULL, 0xd9f6, 2},
|
||||
{ "fdiv", 0, &opfdiv, 0},
|
||||
{ "fdivp", 0, &opfdivp, 0},
|
||||
{ "fdivr", 0, &opfdivr, 0},
|
||||
{ "fdivrp", 0, &opfdivrp, 0},
|
||||
{ "femms", 0, NULL, 0x0f0e, 2},
|
||||
{ "ffree", 0, &opffree, 0},
|
||||
{ "fiadd", 0, &opfiadd, 0},
|
||||
{ "ficom", 0, &opficom, 0},
|
||||
{ "ficomp", 0, &opficomp, 0},
|
||||
{ "fidiv", 0, &opfidiv, 0},
|
||||
{ "fidivr", 0, &opfidivr, 0},
|
||||
{ "fild", 0, &opfild, 0},
|
||||
{ "fimul", 0, &opfimul, 0},
|
||||
{ "fincstp", 0, NULL, 0xd9f7, 2},
|
||||
{ "finit", 0, NULL, 0x9bdbe3, 3},
|
||||
{ "fist", 0, &opfist, 0},
|
||||
{ "fistp", 0, &opfistp, 0},
|
||||
{ "fisttp", 0, &opfisttp, 0},
|
||||
{ "fisub", 0, &opfisub, 0},
|
||||
{ "fisubr", 0, &opfisubr, 0},
|
||||
{ "fld1", 0, NULL, 0xd9e8, 2},
|
||||
{ "fldcw", 0, &opfldcw, 0},
|
||||
{ "fldenv", 0, &opfldenv, 0},
|
||||
{ "fldl2t", 0, NULL, 0xd9e9, 2},
|
||||
{ "fldl2e", 0, NULL, 0xd9ea, 2},
|
||||
{ "fldlg2", 0, NULL, 0xd9ec, 2},
|
||||
{ "fldln2", 0, NULL, 0xd9ed, 2},
|
||||
{ "fldpi", 0, NULL, 0xd9eb, 2},
|
||||
{ "fldz", 0, NULL, 0xd9ee, 2},
|
||||
{ "fmul", 0, &opfmul, 0},
|
||||
{ "fmulp", 0, &opfmulp, 0},
|
||||
{ "fnclex", 0, NULL, 0xdbe2, 2},
|
||||
{ "fninit", 0, NULL, 0xdbe3, 2},
|
||||
{ "fnop", 0, NULL, 0xd9d0, 2},
|
||||
{ "fnsave", 0, &opfnsave, 0},
|
||||
{ "fnstcw", 0, &opfnstcw, 0},
|
||||
{ "fnstenv", 0, &opfnstenv, 0},
|
||||
{ "fnstsw", 0, &opfnstsw, 0},
|
||||
{ "fpatan", 0, NULL, 0xd9f3, 2},
|
||||
{ "fprem", 0, NULL, 0xd9f8, 2},
|
||||
{ "fprem1", 0, NULL, 0xd9f5, 2},
|
||||
{ "fptan", 0, NULL, 0xd9f2, 2},
|
||||
{ "frndint", 0, NULL, 0xd9fc, 2},
|
||||
{ "frstor", 0, &opfrstor, 0},
|
||||
{ "fsave", 0, &opfsave, 0},
|
||||
{ "fscale", 0, NULL, 0xd9fd, 2},
|
||||
{ "fsin", 0, NULL, 0xd9fe, 2},
|
||||
{ "fsincos", 0, NULL, 0xd9fb, 2},
|
||||
{ "fsqrt", 0, NULL, 0xd9fa, 2},
|
||||
{ "fstcw", 0, &opfstcw, 0},
|
||||
{ "fstenv", 0, &opfstenv, 0},
|
||||
{ "fstsw", 0, &opfstsw, 0},
|
||||
{ "fsub", 0, &opfsub, 0},
|
||||
{ "fsubp", 0, &opfsubp, 0},
|
||||
{ "fsubr", 0, &opfsubr, 0},
|
||||
{ "fsubrp", 0, &opfsubrp, 0},
|
||||
{ "ftst", 0, NULL, 0xd9e4, 2},
|
||||
{ "fucom", 0, &opfucom, 0},
|
||||
{ "fucomp", 0, &opfucomp, 0},
|
||||
{ "fucompp", 0, NULL, 0xdae9, 2},
|
||||
{ "fwait", 0, NULL, 0x9b, 1},
|
||||
{ "fxam", 0, NULL, 0xd9e5, 2},
|
||||
{ "fxch", 0, &opfxch, 0},
|
||||
{ "fxrstor", 0, &opfxrstor, 0},
|
||||
{ "fxsave", 0, &opfxsave, 0},
|
||||
{ "fxtract", 0, NULL, 0xd9f4, 2},
|
||||
{ "fyl2x", 0, NULL, 0xd9f1, 2},
|
||||
{ "fyl2xp1", 0, NULL, 0xd9f9, 2},
|
||||
{ "getsec", 0, NULL, 0x0f37, 2},
|
||||
{ "hlt", 0, NULL, 0xf4, 1},
|
||||
{ "idiv", 0, &opidiv, 0},
|
||||
{ "imul", 0, &opimul, 0},
|
||||
{ "in", 0, &opin, 0},
|
||||
{ "inc", 0, &opinc, 0},
|
||||
{ "ins", 0, NULL, 0x6d, 1},
|
||||
{ "insb", 0, NULL, 0x6c, 1},
|
||||
{ "insd", 0, NULL, 0x6d, 1},
|
||||
{ "insw", 0, NULL, 0x666d, 2},
|
||||
{ "int", 0, &opint, 0},
|
||||
{ "int1", 0, NULL, 0xf1, 1},
|
||||
{ "int3", 0, NULL, 0xcc, 1},
|
||||
{ "into", 0, NULL, 0xce, 1},
|
||||
{ "invd", 0, NULL, 0x0f08, 2},
|
||||
{ "iret", 0, NULL, 0x66cf, 2},
|
||||
{ "iretd", 0, NULL, 0xcf, 1},
|
||||
{ "ja", 0, &opjc, 0},
|
||||
{ "jae", 0, &opjc, 0},
|
||||
{ "jb", 0, &opjc, 0},
|
||||
{ "jbe", 0, &opjc, 0},
|
||||
{ "jc", 0, &opjc, 0},
|
||||
{ "je", 0, &opjc, 0},
|
||||
{ "jg", 0, &opjc, 0},
|
||||
{ "jge", 0, &opjc, 0},
|
||||
{ "jl", 0, &opjc, 0},
|
||||
{ "jle", 0, &opjc, 0},
|
||||
{ "jmp", 0, &opjc, 0},
|
||||
{ "jna", 0, &opjc, 0},
|
||||
{ "jnae", 0, &opjc, 0},
|
||||
{ "jnb", 0, &opjc, 0},
|
||||
{ "jnbe", 0, &opjc, 0},
|
||||
{ "jnc", 0, &opjc, 0},
|
||||
{ "jne", 0, &opjc, 0},
|
||||
{ "jng", 0, &opjc, 0},
|
||||
{ "jnge", 0, &opjc, 0},
|
||||
{ "jnl", 0, &opjc, 0},
|
||||
{ "jnle", 0, &opjc, 0},
|
||||
{ "jno", 0, &opjc, 0},
|
||||
{ "jnp", 0, &opjc, 0},
|
||||
{ "jns", 0, &opjc, 0},
|
||||
{ "jnz", 0, &opjc, 0},
|
||||
{ "jo", 0, &opjc, 0},
|
||||
{ "jp", 0, &opjc, 0},
|
||||
{ "jpe", 0, &opjc, 0},
|
||||
{ "jpo", 0, &opjc, 0},
|
||||
{ "js", 0, &opjc, 0},
|
||||
{ "jz", 0, &opjc, 0},
|
||||
{ "jcxz", 0, &opjc, 0},
|
||||
{ "jecxz", 0, &opjc, 0},
|
||||
{ "jrcxz", 0, &opjc, 0},
|
||||
{ "lahf", 0, NULL, 0x9f, 1},
|
||||
{ "lea", 0, &oplea, 0},
|
||||
{ "leave", 0, NULL, 0xc9, 1},
|
||||
{ "les", 0, &oples, 0},
|
||||
{ "lfence", 0, NULL, 0x0faee8, 3},
|
||||
{ "lgdt", 0, &oplgdt, 0},
|
||||
{ "lidt", 0, &oplidt, 0},
|
||||
{ "lldt", 0, &oplldt, 0},
|
||||
{ "lmsw", 0, &oplmsw, 0},
|
||||
{ "lodsb", 0, NULL, 0xac, 1},
|
||||
{ "lodsd", 0, NULL, 0xad, 1},
|
||||
{ "lodsw", 0, NULL, 0x66ad, 2},
|
||||
{ "loop", 0, &oploop, 0},
|
||||
{ "mfence", 0, NULL, 0x0faef0, 3},
|
||||
{ "monitor", 0, NULL, 0x0f01c8, 3},
|
||||
{ "mov", 0, &opmov, 0},
|
||||
{ "movsb", 0, NULL, 0xa4, 1},
|
||||
{ "movsd", 0, NULL, 0xa5, 1},
|
||||
{ "movsw", 0, NULL, 0x66a5, 2},
|
||||
{ "movzx", 0, &opmovx, 0},
|
||||
{ "movsx", 0, &opmovx, 0},
|
||||
{ "movabs", 0, &opmovabs, 0},
|
||||
{ "mul", 0, &opmul, 0},
|
||||
{ "mwait", 0, NULL, 0x0f01c9, 3},
|
||||
{ "neg", 0, &opneg, 0},
|
||||
{ "nop", 0, NULL, 0x90, 1},
|
||||
{ "not", 0, &opnot, 0},
|
||||
{ "or", 0, &opor, 0},
|
||||
{ "out", 0, &opout, 0},
|
||||
{ "outsb", 0, NULL, 0x6e, 1},
|
||||
{ "outs", 0, NULL, 0x6f, 1},
|
||||
{ "outsd", 0, NULL, 0x6f, 1},
|
||||
{ "outsw", 0, NULL, 0x666f, 2},
|
||||
{ "pop", 0, &oppop, 0},
|
||||
{ "popa", 1, NULL, 0x61, 1},
|
||||
{ "popad", 1, NULL, 0x61, 1},
|
||||
{ "popal", 1, NULL, 0x61, 1},
|
||||
{ "popaw", 1, NULL, 0x6661, 2},
|
||||
{ "popfd", 1, NULL, 0x9d, 1},
|
||||
{ "prefetch", 0, NULL, 0x0f0d, 2},
|
||||
{ "push", 0, &oppush, 0},
|
||||
{ "pusha", 1, NULL, 0x60, 1},
|
||||
{ "pushad", 1, NULL, 0x60, 1},
|
||||
{ "pushal", 1, NULL, 0x60, 1},
|
||||
{ "pushf", 0, NULL, 0x669c, 2},
|
||||
{ "popf", 0, NULL, 0x669d, 2},
|
||||
{ "pushfd", 0, NULL, 0x9c, 1},
|
||||
{ "rcl", 0, &process_group_2, 0},
|
||||
{ "rcr", 0, &process_group_2, 0},
|
||||
{ "rep", 0, &oprep, 0},
|
||||
{ "repe", 0, &oprep, 0},
|
||||
{ "repne", 0, &oprep, 0},
|
||||
{ "repz", 0, &oprep, 0},
|
||||
{ "repnz", 0, &oprep, 0},
|
||||
{ "rdmsr", 0, NULL, 0x0f32, 2},
|
||||
{ "rdpmc", 0, NULL, 0x0f33, 2},
|
||||
{ "rdtsc", 0, NULL, 0x0f31, 2},
|
||||
{ "rdtscp", 0, NULL, 0x0f01f9, 3},
|
||||
{ "ret", 0, &opret, 0},
|
||||
{ "retf", 0, &opretf, 0},
|
||||
{ "retw", 0, NULL, 0x66c3, 2},
|
||||
{ "rol", 0, &process_group_2, 0},
|
||||
{ "ror", 0, &process_group_2, 0},
|
||||
{ "rsm", 0, NULL, 0x0faa, 2},
|
||||
{ "sahf", 0, NULL, 0x9e, 1},
|
||||
{ "sal", 0, &process_group_2, 0},
|
||||
{ "salc", 0, NULL, 0xd6, 1},
|
||||
{ "sar", 0, &process_group_2, 0},
|
||||
{ "sbb", 0, &opsbb, 0},
|
||||
{ "scasb", 0, NULL, 0xae, 1},
|
||||
{ "scasd", 0, NULL, 0xaf, 1},
|
||||
{ "scasw", 0, NULL, 0x66af, 2},
|
||||
{ "seto", 0, &opset, 0},
|
||||
{ "setno", 0, &opset, 0},
|
||||
{ "setb", 0, &opset, 0},
|
||||
{ "setnae", 0, &opset, 0},
|
||||
{ "setc", 0, &opset, 0},
|
||||
{ "setnb", 0, &opset, 0},
|
||||
{ "setae", 0, &opset, 0},
|
||||
{ "setnc", 0, &opset, 0},
|
||||
{ "setz", 0, &opset, 0},
|
||||
{ "sete", 0, &opset, 0},
|
||||
{ "setnz", 0, &opset, 0},
|
||||
{ "setne", 0, &opset, 0},
|
||||
{ "setbe", 0, &opset, 0},
|
||||
{ "setna", 0, &opset, 0},
|
||||
{ "setnbe", 0, &opset, 0},
|
||||
{ "seta", 0, &opset, 0},
|
||||
{ "sets", 0, &opset, 0},
|
||||
{ "setns", 0, &opset, 0},
|
||||
{ "setp", 0, &opset, 0},
|
||||
{ "setpe", 0, &opset, 0},
|
||||
{ "setnp", 0, &opset, 0},
|
||||
{ "setpo", 0, &opset, 0},
|
||||
{ "setl", 0, &opset, 0},
|
||||
{ "setnge", 0, &opset, 0},
|
||||
{ "setnl", 0, &opset, 0},
|
||||
{ "setge", 0, &opset, 0},
|
||||
{ "setle", 0, &opset, 0},
|
||||
{ "setng", 0, &opset, 0},
|
||||
{ "setnle", 0, &opset, 0},
|
||||
{ "setg", 0, &opset, 0},
|
||||
{ "sfence", 0, NULL, 0x0faef8, 3},
|
||||
{ "sgdt", 0, &opsgdt, 0},
|
||||
{ "shl", 0, &process_group_2, 0},
|
||||
{ "shr", 0, &process_group_2, 0},
|
||||
{ "sidt", 0, &opsidt, 0},
|
||||
{ "sldt", 0, &opsldt, 0},
|
||||
{ "smsw", 0, &opsmsw, 0},
|
||||
{ "stc", 0, NULL, 0xf9, 1},
|
||||
{ "std", 0, NULL, 0xfd, 1},
|
||||
{ "stgi", 0, NULL, 0x0f01dc, 3},
|
||||
{ "sti", 0, NULL, 0xfb, 1},
|
||||
{ "stmxcsr", 0, &opstmxcsr, 0},
|
||||
{ "stosb", 0, &opstos, 0},
|
||||
{ "stosd", 0, &opstos, 0},
|
||||
{ "stosw", 0, &opstos, 0},
|
||||
{ "str", 0, &opstr, 0},
|
||||
{ "sub", 0, &opsub, 0},
|
||||
{ "swapgs", 0, NULL, 0x0f1ff8, 3},
|
||||
{ "syscall", 0, NULL, 0x0f05, 2},
|
||||
{ "sysenter", 0, NULL, 0x0f34, 2},
|
||||
{ "sysexit", 0, NULL, 0x0f35, 2},
|
||||
{ "sysret", 0, NULL, 0x0f07, 2},
|
||||
{ "ud2", 0, NULL, 0x0f0b, 2},
|
||||
{ "verr", 0, &opverr, 0},
|
||||
{ "verw", 0, &opverw, 0},
|
||||
{ "vmcall", 0, NULL, 0x0f01c1, 3},
|
||||
{ "vmclear", 0, &opvmclear, 0},
|
||||
{ "vmlaunch", 0, NULL, 0x0f01c2, 3},
|
||||
{ "vmload", 0, NULL, 0x0f01da, 3},
|
||||
{ "vmmcall", 0, NULL, 0x0f01d9, 3},
|
||||
{ "vmptrld", 0, &opvmptrld, 0},
|
||||
{ "vmptrst", 0, &opvmptrst, 0},
|
||||
{ "vmresume", 0, NULL, 0x0f01c3, 3},
|
||||
{ "vmrun", 0, NULL, 0x0f01d8, 3},
|
||||
{ "vmsave", 0, NULL, 0x0f01db, 3},
|
||||
{ "vmxoff", 0, NULL, 0x0f01c4, 3},
|
||||
{ "vmxon", 0, &opvmon, 0},
|
||||
{ "vzeroall", 0, NULL, 0xc5fc77, 3},
|
||||
{ "vzeroupper", 0, NULL, 0xc5f877, 3},
|
||||
{ "wait", 0, NULL, 0x9b, 1},
|
||||
{ "wbinvd", 0, NULL, 0x0f09, 2},
|
||||
{ "wrmsr", 0, NULL, 0x0f30, 2},
|
||||
{ "xadd", 0, &opxadd, 0},
|
||||
{ "xchg", 0, &opxchg, 0},
|
||||
{ "xgetbv", 0, NULL, 0x0f01d0, 3},
|
||||
{ "xlatb", 0, NULL, 0xd7, 1},
|
||||
{ "xor", 0, &opxor, 0},
|
||||
{ "xsetbv", 0, NULL, 0x0f01d1, 3},
|
||||
{ "test", 0, &optest, 0},
|
||||
{ "null", 0, NULL, 0, 0}
|
||||
};
|
||||
|
||||
static x86newTokenType getToken(const char *str, size_t *begin, size_t *end) {
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@ static void print_usage(void) {
|
|||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
static const struct option long_options[] = {
|
||||
{"pdb_file", required_argument, 0, 'f'},
|
||||
{"print_types", no_argument, 0, 't'},
|
||||
{"print_globals", required_argument, 0, 'g'},
|
||||
{"help", no_argument, 0, 'h'},
|
||||
{ "pdb_file", required_argument, 0, 'f'},
|
||||
{ "print_types", no_argument, 0, 't'},
|
||||
{ "print_globals", required_argument, 0, 'g'},
|
||||
{ "help", no_argument, 0, 'h'},
|
||||
{NULL, 0, 0, 0}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
/* radare - LGPL - Copyright 2019-2022 - mrmacete, pancake */
|
||||
|
||||
#include <r_util.h>
|
||||
#include <r_util/r_xml.h>
|
||||
#include <r_list.h>
|
||||
|
|
@ -346,7 +346,6 @@ static void r_cf_value_dict_add(RCFValueDict *dict, RCFKeyValue *key_value) {
|
|||
if (!dict || !dict->pairs) {
|
||||
return;
|
||||
}
|
||||
|
||||
r_list_push (dict->pairs, key_value);
|
||||
}
|
||||
|
||||
|
|
@ -368,28 +367,21 @@ static void r_cf_value_dict_print(RCFValueDict *dict) {
|
|||
|
||||
static RCFValueArray *r_cf_value_array_new(void) {
|
||||
RCFValueArray *array = R_NEW0 (RCFValueArray);
|
||||
if (!array) {
|
||||
return NULL;
|
||||
if (array) {
|
||||
array->type = R_CF_ARRAY;
|
||||
array->values = r_list_newf ((RListFree)&r_cf_value_free);
|
||||
}
|
||||
|
||||
array->type = R_CF_ARRAY;
|
||||
array->values = r_list_newf ((RListFree)&r_cf_value_free);
|
||||
|
||||
return array;
|
||||
}
|
||||
|
||||
static void r_cf_value_array_free(RCFValueArray *array) {
|
||||
if (!array) {
|
||||
return;
|
||||
if (array) {
|
||||
if (array->values) {
|
||||
r_list_free (array->values);
|
||||
array->values = NULL;
|
||||
}
|
||||
free (array);
|
||||
}
|
||||
|
||||
if (array->values) {
|
||||
r_list_free (array->values);
|
||||
array->values = NULL;
|
||||
}
|
||||
|
||||
array->type = R_CF_INVALID;
|
||||
R_FREE (array);
|
||||
}
|
||||
|
||||
static void r_cf_value_array_add(RCFValueArray *array, RCFValue *value) {
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@ static const struct {
|
|||
const int offset_mem;
|
||||
const int ram_size;
|
||||
} _machines[] = {
|
||||
{"C64", "Commodore 64", r_offsetof(struct vsf_c64mem, ram), 64 * 1024},
|
||||
{"C128", "Commodore 128", r_offsetof(struct vsf_c128mem, ram), 128 * 1024},
|
||||
{ "C64", "Commodore 64", r_offsetof(struct vsf_c64mem, ram), 64 * 1024},
|
||||
{ "C128", "Commodore 128", r_offsetof(struct vsf_c128mem, ram), 128 * 1024},
|
||||
};
|
||||
static const int MACHINES_MAX = sizeof (_machines) / sizeof (_machines[0]);
|
||||
|
||||
|
|
@ -343,133 +343,133 @@ static RList* symbols(RBinFile *bf) {
|
|||
const ut16 address;
|
||||
const char* symbol_name;
|
||||
} _symbols[] = {
|
||||
// {0xfffa, "NMI_VECTOR_LSB"},
|
||||
// {0xfffb, "NMI_VECTOR_MSB"},
|
||||
// {0xfffe, "IRQ_VECTOR_LSB"},
|
||||
// {0xffff, "IRQ_VECTOR_MSB"},
|
||||
// {0xfffa, "NMI_VECTOR_LSB" },
|
||||
// {0xfffb, "NMI_VECTOR_MSB" },
|
||||
// {0xfffe, "IRQ_VECTOR_LSB" },
|
||||
// {0xffff, "IRQ_VECTOR_MSB" },
|
||||
|
||||
// Defines taken from c64.inc from cc65
|
||||
// I/O: VIC
|
||||
{0xd000, "VIC_SPR0_X"},
|
||||
{0xd001, "VIC_SPR0_Y"},
|
||||
{0xd002, "VIC_SPR1_X"},
|
||||
{0xd003, "VIC_SPR1_Y"},
|
||||
{0xd004, "VIC_SPR2_X"},
|
||||
{0xd005, "VIC_SPR2_Y"},
|
||||
{0xd006, "VIC_SPR3_X"},
|
||||
{0xd007, "VIC_SPR3_Y"},
|
||||
{0xd008, "VIC_SPR4_X"},
|
||||
{0xd009, "VIC_SPR4_Y"},
|
||||
{0xd00a, "VIC_SPR5_X"},
|
||||
{0xd00b, "VIC_SPR5_Y"},
|
||||
{0xd00c, "VIC_SPR6_X"},
|
||||
{0xd00d, "VIC_SPR6_Y"},
|
||||
{0xd00e, "VIC_SPR7_X"},
|
||||
{0xd00f, "VIC_SPR7_Y"},
|
||||
{0xd010, "VIC_SPR_HI_X"},
|
||||
{0xd015, "VIC_SPR_ENA"},
|
||||
{0xd017, "VIC_SPR_EXP_Y"},
|
||||
{0xd01d, "VIC_SPR_EXP_X"},
|
||||
{0xd01c, "VIC_SPR_MCOLOR"},
|
||||
{0xd01b, "VIC_SPR_BG_PRIO"},
|
||||
{0xd000, "VIC_SPR0_X" },
|
||||
{0xd001, "VIC_SPR0_Y" },
|
||||
{0xd002, "VIC_SPR1_X" },
|
||||
{0xd003, "VIC_SPR1_Y" },
|
||||
{0xd004, "VIC_SPR2_X" },
|
||||
{0xd005, "VIC_SPR2_Y" },
|
||||
{0xd006, "VIC_SPR3_X" },
|
||||
{0xd007, "VIC_SPR3_Y" },
|
||||
{0xd008, "VIC_SPR4_X" },
|
||||
{0xd009, "VIC_SPR4_Y" },
|
||||
{0xd00a, "VIC_SPR5_X" },
|
||||
{0xd00b, "VIC_SPR5_Y" },
|
||||
{0xd00c, "VIC_SPR6_X" },
|
||||
{0xd00d, "VIC_SPR6_Y" },
|
||||
{0xd00e, "VIC_SPR7_X" },
|
||||
{0xd00f, "VIC_SPR7_Y" },
|
||||
{0xd010, "VIC_SPR_HI_X" },
|
||||
{0xd015, "VIC_SPR_ENA" },
|
||||
{0xd017, "VIC_SPR_EXP_Y" },
|
||||
{0xd01d, "VIC_SPR_EXP_X" },
|
||||
{0xd01c, "VIC_SPR_MCOLOR" },
|
||||
{0xd01b, "VIC_SPR_BG_PRIO" },
|
||||
|
||||
{0xd025, "VIC_SPR_MCOLOR0"},
|
||||
{0xd026, "VIC_SPR_MCOLOR1"},
|
||||
{0xd025, "VIC_SPR_MCOLOR0" },
|
||||
{0xd026, "VIC_SPR_MCOLOR1" },
|
||||
|
||||
{0xd027, "VIC_SPR0_COLOR"},
|
||||
{0xd028, "VIC_SPR1_COLOR"},
|
||||
{0xd029, "VIC_SPR2_COLOR"},
|
||||
{0xd02A, "VIC_SPR3_COLOR"},
|
||||
{0xd02B, "VIC_SPR4_COLOR"},
|
||||
{0xd02C, "VIC_SPR5_COLOR"},
|
||||
{0xd02D, "VIC_SPR6_COLOR"},
|
||||
{0xd02E, "VIC_SPR7_COLOR"},
|
||||
{0xd027, "VIC_SPR0_COLOR" },
|
||||
{0xd028, "VIC_SPR1_COLOR" },
|
||||
{0xd029, "VIC_SPR2_COLOR" },
|
||||
{0xd02A, "VIC_SPR3_COLOR" },
|
||||
{0xd02B, "VIC_SPR4_COLOR" },
|
||||
{0xd02C, "VIC_SPR5_COLOR" },
|
||||
{0xd02D, "VIC_SPR6_COLOR" },
|
||||
{0xd02E, "VIC_SPR7_COLOR" },
|
||||
|
||||
{0xd011, "VIC_CTRL1"},
|
||||
{0xd016, "VIC_CTRL2"},
|
||||
{0xd011, "VIC_CTRL1" },
|
||||
{0xd016, "VIC_CTRL2" },
|
||||
|
||||
{0xd012, "VIC_HLINE"},
|
||||
{0xd012, "VIC_HLINE" },
|
||||
|
||||
{0xd013, "VIC_LPEN_X"},
|
||||
{0xd014, "VIC_LPEN_Y"},
|
||||
{0xd013, "VIC_LPEN_X" },
|
||||
{0xd014, "VIC_LPEN_Y" },
|
||||
|
||||
{0xd018, "VIC_VIDEO_ADR"},
|
||||
{0xd018, "VIC_VIDEO_ADR" },
|
||||
|
||||
{0xd019, "VIC_IRR"},
|
||||
{0xd01a, "VIC_IMR"},
|
||||
{0xd019, "VIC_IRR" },
|
||||
{0xd01a, "VIC_IMR" },
|
||||
|
||||
{0xd020, "VIC_BORDERCOLOR"},
|
||||
{0xd021, "VIC_BG_COLOR0"},
|
||||
{0xd022, "VIC_BG_COLOR1"},
|
||||
{0xd023, "VIC_BG_COLOR2"},
|
||||
{0xd024, "VIC_BG_COLOR3"},
|
||||
{0xd020, "VIC_BORDERCOLOR" },
|
||||
{0xd021, "VIC_BG_COLOR0" },
|
||||
{0xd022, "VIC_BG_COLOR1" },
|
||||
{0xd023, "VIC_BG_COLOR2" },
|
||||
{0xd024, "VIC_BG_COLOR3" },
|
||||
|
||||
// 128 stuff
|
||||
{0xd02F, "VIC_KBD_128"},
|
||||
{0xd030, "VIC_CLK_128"},
|
||||
{0xd02F, "VIC_KBD_128" },
|
||||
{0xd030, "VIC_CLK_128" },
|
||||
|
||||
// I/O: SID
|
||||
{0xD400, "SID_S1Lo"},
|
||||
{0xD401, "SID_S1Hi"},
|
||||
{0xD402, "SID_PB1Lo"},
|
||||
{0xD403, "SID_PB1Hi"},
|
||||
{0xD404, "SID_Ctl1"},
|
||||
{0xD405, "SID_AD1"},
|
||||
{0xD406, "SID_SUR1"},
|
||||
{0xD400, "SID_S1Lo" },
|
||||
{0xD401, "SID_S1Hi" },
|
||||
{0xD402, "SID_PB1Lo" },
|
||||
{0xD403, "SID_PB1Hi" },
|
||||
{0xD404, "SID_Ctl1" },
|
||||
{0xD405, "SID_AD1" },
|
||||
{0xD406, "SID_SUR1" },
|
||||
|
||||
{0xD407, "SID_S2Lo"},
|
||||
{0xD408, "SID_S2Hi"},
|
||||
{0xD409, "SID_PB2Lo"},
|
||||
{0xD40A, "SID_PB2Hi"},
|
||||
{0xD40B, "SID_Ctl2"},
|
||||
{0xD40C, "SID_AD2"},
|
||||
{0xD40D, "SID_SUR2"},
|
||||
{0xD407, "SID_S2Lo" },
|
||||
{0xD408, "SID_S2Hi" },
|
||||
{0xD409, "SID_PB2Lo" },
|
||||
{0xD40A, "SID_PB2Hi" },
|
||||
{0xD40B, "SID_Ctl2" },
|
||||
{0xD40C, "SID_AD2" },
|
||||
{0xD40D, "SID_SUR2" },
|
||||
|
||||
{0xD40E, "SID_S3Lo"},
|
||||
{0xD40F, "SID_S3Hi"},
|
||||
{0xD410, "SID_PB3Lo"},
|
||||
{0xD411, "SID_PB3Hi"},
|
||||
{0xD412, "SID_Ctl3"},
|
||||
{0xD413, "SID_AD3"},
|
||||
{0xD414, "SID_SUR3"},
|
||||
{0xD40E, "SID_S3Lo" },
|
||||
{0xD40F, "SID_S3Hi" },
|
||||
{0xD410, "SID_PB3Lo" },
|
||||
{0xD411, "SID_PB3Hi" },
|
||||
{0xD412, "SID_Ctl3" },
|
||||
{0xD413, "SID_AD3" },
|
||||
{0xD414, "SID_SUR3" },
|
||||
|
||||
{0xD415, "SID_FltLo"},
|
||||
{0xD416, "SID_FltHi"},
|
||||
{0xD417, "SID_FltCtl"},
|
||||
{0xD418, "SID_Amp"},
|
||||
{0xD419, "SID_ADConv1"},
|
||||
{0xD41A, "SID_ADConv2"},
|
||||
{0xD41B, "SID_Noise"},
|
||||
{0xD41C, "SID_Read3"},
|
||||
{0xD415, "SID_FltLo" },
|
||||
{0xD416, "SID_FltHi" },
|
||||
{0xD417, "SID_FltCtl" },
|
||||
{0xD418, "SID_Amp" },
|
||||
{0xD419, "SID_ADConv1" },
|
||||
{0xD41A, "SID_ADConv2" },
|
||||
{0xD41B, "SID_Noise" },
|
||||
{0xD41C, "SID_Read3" },
|
||||
|
||||
// I/O: VDC (128 only)
|
||||
{0xd600, "VDC_INDEX"},
|
||||
{0xd601, "VDC_DATA"},
|
||||
{0xd600, "VDC_INDEX" },
|
||||
{0xd601, "VDC_DATA" },
|
||||
|
||||
// I/O: CIAs
|
||||
{0xDC00, "CIA1_PRA"},
|
||||
{0xDC01, "CIA1_PRB"},
|
||||
{0xDC02, "CIA1_DDRA"},
|
||||
{0xDC03, "CIA1_DDRB"},
|
||||
{0xDC08, "CIA1_TOD10"},
|
||||
{0xDC09, "CIA1_TODSEC"},
|
||||
{0xDC0A, "CIA1_TODMIN"},
|
||||
{0xDC0B, "CIA1_TODHR"},
|
||||
{0xDC0D, "CIA1_ICR"},
|
||||
{0xDC0E, "CIA1_CRA"},
|
||||
{0xDC0F, "CIA1_CRB"},
|
||||
{0xDC00, "CIA1_PRA" },
|
||||
{0xDC01, "CIA1_PRB" },
|
||||
{0xDC02, "CIA1_DDRA" },
|
||||
{0xDC03, "CIA1_DDRB" },
|
||||
{0xDC08, "CIA1_TOD10" },
|
||||
{0xDC09, "CIA1_TODSEC" },
|
||||
{0xDC0A, "CIA1_TODMIN" },
|
||||
{0xDC0B, "CIA1_TODHR" },
|
||||
{0xDC0D, "CIA1_ICR" },
|
||||
{0xDC0E, "CIA1_CRA" },
|
||||
{0xDC0F, "CIA1_CRB" },
|
||||
|
||||
{0xDD00, "CIA2_PRA"},
|
||||
{0xDD01, "CIA2_PRB"},
|
||||
{0xDD02, "CIA2_DDRA"},
|
||||
{0xDD03, "CIA2_DDRB"},
|
||||
{0xDD08, "CIA2_TOD10"},
|
||||
{0xDD09, "CIA2_TODSEC"},
|
||||
{0xDD0A, "CIA2_TODMIN"},
|
||||
{0xDD0B, "CIA2_TODHR"},
|
||||
{0xDD0D, "CIA2_ICR"},
|
||||
{0xDD0E, "CIA2_CRA"},
|
||||
{0xDD0F, "CIA2_CRB"},
|
||||
{0xDD00, "CIA2_PRA" },
|
||||
{0xDD01, "CIA2_PRB" },
|
||||
{0xDD02, "CIA2_DDRA" },
|
||||
{0xDD03, "CIA2_DDRB" },
|
||||
{0xDD08, "CIA2_TOD10" },
|
||||
{0xDD09, "CIA2_TODSEC" },
|
||||
{0xDD0A, "CIA2_TODMIN" },
|
||||
{0xDD0B, "CIA2_TODHR" },
|
||||
{0xDD0D, "CIA2_ICR" },
|
||||
{0xDD0E, "CIA2_CRA" },
|
||||
{0xDD0F, "CIA2_CRB" },
|
||||
};
|
||||
static const int SYMBOLS_MAX = sizeof (_symbols) / sizeof (_symbols[0]);
|
||||
struct r_bin_vsf_obj* vsf_obj = (struct r_bin_vsf_obj*) bf->o->bin_obj;
|
||||
|
|
|
|||
|
|
@ -543,8 +543,10 @@ R_API void r_core_anal_autoname_all_golang_fcns(RCore *core) {
|
|||
r_name_filter ((char *)func_name, 0);
|
||||
//r_cons_printf ("[x] Found symbol %s at 0x%x\n", func_name, func_addr);
|
||||
char *flagname = r_str_newf ("sym.go.%s", func_name);
|
||||
r_flag_set (core->flags, flagname, func_addr, 1);
|
||||
free (flagname);
|
||||
if (flagname) {
|
||||
r_flag_set (core->flags, flagname, func_addr, 1);
|
||||
free (flagname);
|
||||
}
|
||||
offset += 2 * ptr_size;
|
||||
num_syms++;
|
||||
}
|
||||
|
|
@ -599,12 +601,13 @@ static bool r_anal_try_get_fcn(RCore *core, RAnalRef *ref, int fcndepth, int ref
|
|||
if (map->perm & R_PERM_X) {
|
||||
ut8 buf[64];
|
||||
r_io_read_at (core->io, ref->addr, buf, sizeof (buf));
|
||||
bool looksLikeAFunction = r_anal_check_fcn (core->anal, buf, sizeof (buf), ref->addr, r_io_map_begin (map),
|
||||
r_io_map_end (map));
|
||||
bool looksLikeAFunction = r_anal_check_fcn (core->anal, buf, sizeof (buf), ref->addr, r_io_map_begin (map), r_io_map_end (map));
|
||||
if (looksLikeAFunction) {
|
||||
if (core->anal->limit) {
|
||||
if (ref->addr < core->anal->limit->from ||
|
||||
ref->addr > core->anal->limit->to) {
|
||||
if (ref->addr < core->anal->limit->from) {
|
||||
return 1;
|
||||
}
|
||||
if (ref->addr > core->anal->limit->to) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5912,55 +5912,55 @@ R_API void r_core_cmd_init(RCore *core) {
|
|||
const char *description;
|
||||
RCmdCb cb;
|
||||
} cmds[] = {
|
||||
{"!", "run system command", cmd_system },
|
||||
{"_", "print last output", cmd_last },
|
||||
{"#", "calculate hash", cmd_hash },
|
||||
{"$", "alias", cmd_alias },
|
||||
{"%", "short version of 'env' command", cmd_env },
|
||||
{"&", "tasks", cmd_tasks },
|
||||
{"(", "macro", cmd_macro },
|
||||
{"*", "pointer read/write", cmd_pointer },
|
||||
{"+", "relative seek forward", cmd_plus },
|
||||
{"-", "open cfg.editor and run script", cmd_stdin },
|
||||
{".", "interpret", cmd_interpret },
|
||||
{",", "create and manipulate tables", cmd_table },
|
||||
{"/", "search kw, pattern aes", cmd_search },
|
||||
{"=", "io pipe", cmd_rap },
|
||||
{"?", "help message", cmd_help },
|
||||
{":", "alias for =!", cmd_rap_run },
|
||||
{"0", "alias for s 0x", cmd_ox },
|
||||
{"a", "analysis", cmd_anal },
|
||||
{"b", "change block size", cmd_bsize },
|
||||
{"c", "compare memory", cmd_cmp },
|
||||
{"C", "code metadata", cmd_meta },
|
||||
{"d", "debugger operations", cmd_debug },
|
||||
{"e", "evaluate configuration variable", cmd_eval },
|
||||
{"f", "get/set flags", cmd_flag },
|
||||
{"g", "egg manipulation", cmd_egg },
|
||||
{"i", "get file info", cmd_info },
|
||||
{"k", "perform sdb query", cmd_kuery },
|
||||
{"l", "list files and directories", cmd_l },
|
||||
{"j", "join the contents of the two files", cmd_join },
|
||||
{"h", "show the top n number of line in file", cmd_head },
|
||||
{"L", "manage dynamically loaded plugins", cmd_plugins },
|
||||
{"m", "mount filesystem", cmd_mount },
|
||||
{"o", "open or map file", cmd_open },
|
||||
{"p", "print current block", cmd_print },
|
||||
{"P", "project", cmd_project },
|
||||
{"q", "exit program session", cmd_quit },
|
||||
{"Q", "alias for q!", cmd_Quit },
|
||||
{"r", "change file size", cmd_resize },
|
||||
{"s", "seek to an offset", cmd_seek },
|
||||
{"t", "type information (cparse)", cmd_type },
|
||||
{"T", "Text log utility", cmd_log },
|
||||
{"u", "uname/undo", cmd_undo },
|
||||
{"<", "pipe into RCons.readChar", cmd_pipein },
|
||||
{"V", "enter visual mode", cmd_visual },
|
||||
{"v", "enter visual panels", cmd_panels },
|
||||
{"w", "write bytes", cmd_write },
|
||||
{"x", "alias for px", cmd_hexdump },
|
||||
{"y", "yank bytes", cmd_yank },
|
||||
{"z", "zignatures", cmd_zign },
|
||||
{ "!", "run system command", cmd_system },
|
||||
{ "_", "print last output", cmd_last },
|
||||
{ "#", "calculate hash", cmd_hash },
|
||||
{ "$", "alias", cmd_alias },
|
||||
{ "%", "short version of 'env' command", cmd_env },
|
||||
{ "&", "tasks", cmd_tasks },
|
||||
{ "(", "macro", cmd_macro },
|
||||
{ "*", "pointer read/write", cmd_pointer },
|
||||
{ "+", "relative seek forward", cmd_plus },
|
||||
{ "-", "open cfg.editor and run script", cmd_stdin },
|
||||
{ ".", "interpret", cmd_interpret },
|
||||
{ ",", "create and manipulate tables", cmd_table },
|
||||
{ "/", "search kw, pattern aes", cmd_search },
|
||||
{ "=", "io pipe", cmd_rap },
|
||||
{ "?", "help message", cmd_help },
|
||||
{ ":", "alias for =!", cmd_rap_run },
|
||||
{ "0", "alias for s 0x", cmd_ox },
|
||||
{ "a", "analysis", cmd_anal },
|
||||
{ "b", "change block size", cmd_bsize },
|
||||
{ "c", "compare memory", cmd_cmp },
|
||||
{ "C", "code metadata", cmd_meta },
|
||||
{ "d", "debugger operations", cmd_debug },
|
||||
{ "e", "evaluate configuration variable", cmd_eval },
|
||||
{ "f", "get/set flags", cmd_flag },
|
||||
{ "g", "egg manipulation", cmd_egg },
|
||||
{ "i", "get file info", cmd_info },
|
||||
{ "k", "perform sdb query", cmd_kuery },
|
||||
{ "l", "list files and directories", cmd_l },
|
||||
{ "j", "join the contents of the two files", cmd_join },
|
||||
{ "h", "show the top n number of line in file", cmd_head },
|
||||
{ "L", "manage dynamically loaded plugins", cmd_plugins },
|
||||
{ "m", "mount filesystem", cmd_mount },
|
||||
{ "o", "open or map file", cmd_open },
|
||||
{ "p", "print current block", cmd_print },
|
||||
{ "P", "project", cmd_project },
|
||||
{ "q", "exit program session", cmd_quit },
|
||||
{ "Q", "alias for q!", cmd_Quit },
|
||||
{ "r", "change file size", cmd_resize },
|
||||
{ "s", "seek to an offset", cmd_seek },
|
||||
{ "t", "type information (cparse)", cmd_type },
|
||||
{ "T", "Text log utility", cmd_log },
|
||||
{ "u", "uname/undo", cmd_undo },
|
||||
{ "<", "pipe into RCons.readChar", cmd_pipein },
|
||||
{ "V", "enter visual mode", cmd_visual },
|
||||
{ "v", "enter visual panels", cmd_panels },
|
||||
{ "w", "write bytes", cmd_write },
|
||||
{ "x", "alias for px", cmd_hexdump },
|
||||
{ "y", "yank bytes", cmd_yank },
|
||||
{ "z", "zignatures", cmd_zign },
|
||||
};
|
||||
|
||||
core->rcmd = r_cmd_new ();
|
||||
|
|
|
|||
|
|
@ -4850,7 +4850,7 @@ static int cmd_debug_desc(RCore *core, const char *input) {
|
|||
}
|
||||
|
||||
/* Wait to move the first arg forward past the first 'd' until after argv creation.
|
||||
* "dd filename" results in {"", "filename"} instead of {"filename"}.
|
||||
* "dd filename" results in { "", "filename" } instead of { "filename" }.
|
||||
*
|
||||
* This mimics passing input+1 but allows a possible empty argv[0]
|
||||
* to preserve argument positions.
|
||||
|
|
|
|||
|
|
@ -433,24 +433,24 @@ static int cmd_hash(void *data, const char *input) {
|
|||
}
|
||||
|
||||
static RHashHashHandlers hash_handlers[] = {
|
||||
{"md4", handle_md4},
|
||||
{"md5", handle_md5},
|
||||
{"sha1", handle_sha1},
|
||||
{"sha256", handle_sha256},
|
||||
{"sha512", handle_sha512},
|
||||
{"adler32", handle_adler32},
|
||||
{"xor", handle_xor},
|
||||
{"xorpair", handle_xorpair},
|
||||
{"entropy", handle_entropy},
|
||||
{"parity", handle_parity},
|
||||
{"hamdist", handle_hamdist},
|
||||
{"pcprint", handle_pcprint},
|
||||
{"mod255", handle_mod255},
|
||||
{"xxhash", handle_xxhash},
|
||||
{"luhn", handle_luhn},
|
||||
{"ssdeep", handle_ssdeep},
|
||||
{ "md4", handle_md4},
|
||||
{ "md5", handle_md5},
|
||||
{ "sha1", handle_sha1},
|
||||
{ "sha256", handle_sha256},
|
||||
{ "sha512", handle_sha512},
|
||||
{ "adler32", handle_adler32},
|
||||
{ "xor", handle_xor},
|
||||
{ "xorpair", handle_xorpair},
|
||||
{ "entropy", handle_entropy},
|
||||
{ "parity", handle_parity},
|
||||
{ "hamdist", handle_hamdist},
|
||||
{ "pcprint", handle_pcprint},
|
||||
{ "mod255", handle_mod255},
|
||||
{ "xxhash", handle_xxhash},
|
||||
{ "luhn", handle_luhn},
|
||||
{ "ssdeep", handle_ssdeep},
|
||||
|
||||
{"crc8smbus", handle_crc8_smbus},
|
||||
{ "crc8smbus", handle_crc8_smbus},
|
||||
#if R_HAVE_CRC8_EXTRA
|
||||
{ /* CRC-8/CDMA2000 */ "crc8cdma2000", handle_crc8_cdma2000},
|
||||
{ /* CRC-8/DARC */ "crc8darc", handle_crc8_darc},
|
||||
|
|
@ -464,11 +464,11 @@ static RHashHashHandlers hash_handlers[] = {
|
|||
#endif /* #if R_HAVE_CRC8_EXTRA */
|
||||
|
||||
#if R_HAVE_CRC15_EXTRA
|
||||
{"crc15can", handle_crc15_can},
|
||||
{ "crc15can", handle_crc15_can},
|
||||
#endif /* #if R_HAVE_CRC15_EXTRA */
|
||||
|
||||
{"crc16", handle_crc16},
|
||||
{"crc16hdlc", handle_crc16_hdlc},
|
||||
{ "crc16", handle_crc16},
|
||||
{ "crc16hdlc", handle_crc16_hdlc},
|
||||
{ /* CRC-16/USB */ "crc16usb", handle_crc16_usb},
|
||||
{ /* CRC-16/CCITT-FALSE */ "crc16citt", handle_crc16_citt},
|
||||
#if R_HAVE_CRC16_EXTRA
|
||||
|
|
@ -495,12 +495,12 @@ static RHashHashHandlers hash_handlers[] = {
|
|||
#endif /* #if R_HAVE_CRC16_EXTRA */
|
||||
|
||||
#if R_HAVE_CRC24
|
||||
{"crc24", handle_crc24},
|
||||
{ "crc24", handle_crc24},
|
||||
#endif /* #if R_HAVE_CRC24 */
|
||||
|
||||
{"crc32", handle_crc32},
|
||||
{"crc32c", handle_crc32c},
|
||||
{"crc32ecma267", handle_crc32_ecma_267},
|
||||
{ "crc32", handle_crc32},
|
||||
{ "crc32c", handle_crc32c},
|
||||
{ "crc32ecma267", handle_crc32_ecma_267},
|
||||
#if R_HAVE_CRC32_EXTRA
|
||||
{ /* CRC-32/BZIP2 */ "crc32bzip2", handle_crc32_bzip2 },
|
||||
{ /* CRC-32D */ "crc32d", handle_crc32d },
|
||||
|
|
@ -521,9 +521,9 @@ static RHashHashHandlers hash_handlers[] = {
|
|||
{ /* CRC-64/XZ */ "crc64xz", handle_crc64_xz },
|
||||
{ /* CRC-64/ISO */ "crc64iso", handle_crc64_iso },
|
||||
#endif /* #if R_HAVE_CRC64_EXTRA */
|
||||
{"fletcher8", handle_fletcher8},
|
||||
{"fletcher16", handle_fletcher16},
|
||||
{"fletcher32", handle_fletcher32},
|
||||
{"fletcher64", handle_fletcher64},
|
||||
{ "fletcher8", handle_fletcher8},
|
||||
{ "fletcher16", handle_fletcher16},
|
||||
{ "fletcher32", handle_fletcher32},
|
||||
{ "fletcher64", handle_fletcher64},
|
||||
{NULL, NULL},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
#include <r_core.h>
|
||||
|
||||
static const char *help_msg_at[] = {
|
||||
static RCoreHelpMessage help_msg_at = {
|
||||
"Usage: [.][#]<cmd>[*] [`cmd`] [@ addr] [~grep] [|syscmd] [>[>]file]", "", "",
|
||||
"0", "", "alias for 's 0'",
|
||||
"0x", "addr", "alias for 's 0x..'",
|
||||
|
|
@ -58,7 +58,7 @@ static const char *help_msg_at[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static const char *help_msg_at_at[] = {
|
||||
static RCoreHelpMessage help_msg_at_at = {
|
||||
"@@", "", " # foreach iterator command:",
|
||||
"x", " @@ sym.*", "run 'x' over all flags matching 'sym.' in current flagspace",
|
||||
"x", " @@.file", "run 'x' over the offsets specified in the file (one offset per line)",
|
||||
|
|
@ -79,7 +79,7 @@ static const char *help_msg_at_at[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static const char *help_msg_at_at_at[] = {
|
||||
static RCoreHelpMessage help_msg_at_at_at = {
|
||||
"@@@", "", " # foreach offset+size iterator command:",
|
||||
"x", " @@@=", "[addr] [size] ([addr] [size] ...)",
|
||||
"x", " @@@C:cmd", "comments matching",
|
||||
|
|
@ -217,7 +217,7 @@ static const char *help_msg_root[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static const char *help_msg_question_i[] = {
|
||||
static RCoreHelpMessage help_msg_question_i = {
|
||||
"Usage: ?e[=bdgnpst] arg", "print/echo things", "",
|
||||
"?i", " ([prompt])", "inquery the user and save that text into the yank clipboard (y)",
|
||||
"?ie", " [msg]", "same as ?i, but prints the output, useful for oneliners",
|
||||
|
|
@ -229,7 +229,7 @@ static const char *help_msg_question_i[] = {
|
|||
"?ip", " ([path])", "interactive hud mode to find files in given path",
|
||||
NULL
|
||||
};
|
||||
static const char *help_msg_question_e[] = {
|
||||
static RCoreHelpMessage help_msg_question_e = {
|
||||
"Usage: ?e[=bdgnpst] arg", "print/echo things", "",
|
||||
"?e", "", "echo message with newline",
|
||||
"?e=", " 32", "progress bar at 32 percentage",
|
||||
|
|
@ -245,7 +245,7 @@ static const char *help_msg_question_e[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static const char *help_msg_question[] = {
|
||||
static RCoreHelpMessage help_msg_question = {
|
||||
"Usage: ?[?[?]] expression", "", "",
|
||||
"?!", " [cmd]", "run cmd if $? == 0",
|
||||
"?", " eip-0x804800", "show all representation result for this math expr",
|
||||
|
|
|
|||
|
|
@ -1747,7 +1747,7 @@ static void ds_show_functions_argvar(RDisasmState *ds, RAnalFunction *fcn, RAnal
|
|||
var->name, COLOR_ARG (ds, color_func_var_addr),
|
||||
constr? " { ":"",
|
||||
r_str_get (constr),
|
||||
constr? "} ":"",
|
||||
constr? " } ":"",
|
||||
base, sign, delta);
|
||||
if (ds->show_varsum == -1) {
|
||||
char *val = r_core_cmd_strf (ds->core, ".afvd %s", var->name);
|
||||
|
|
@ -3523,15 +3523,15 @@ static void ds_print_vliw(RDisasmState *ds, bool after) {
|
|||
if (c > 0) {
|
||||
ds->vliw_count--;
|
||||
if (c == 1) {
|
||||
r_cons_printf (" }");
|
||||
r_cons_printf ("}");
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (v > 0) {
|
||||
if (c > 0) {
|
||||
r_cons_printf ("}{ ");
|
||||
r_cons_printf ("}{");
|
||||
} else {
|
||||
r_cons_printf ("{ ");
|
||||
r_cons_printf ("{");
|
||||
}
|
||||
ds->vliw_count = v;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -370,8 +370,8 @@ static void GH(print_arena_stats)(RCore *core, GHT m_arena, MallocState *main_ar
|
|||
r_cons_newline ();
|
||||
}
|
||||
|
||||
PRINT_GA (" }\n");
|
||||
PRINT_GA (" binmap = {");
|
||||
PRINT_GA ("}\n");
|
||||
PRINT_GA (" binmap = { ");
|
||||
|
||||
for (i = 0; i < BINMAPSIZE; i++) {
|
||||
if (i) {
|
||||
|
|
|
|||
|
|
@ -237,7 +237,7 @@ static void GH(jemalloc_get_chunks)(RCore *core, const char *input) {
|
|||
r_io_read_at (core->io, (GHT)(size_t)node->ql_link.qre_next, (ut8 *)node, sizeof (extent_node_t));
|
||||
}
|
||||
}
|
||||
PRINT_GA ("}\n");
|
||||
PRINT_GA (" }\n");
|
||||
}
|
||||
}
|
||||
free (ar);
|
||||
|
|
@ -298,7 +298,7 @@ static void GH(jemalloc_print_narenas)(RCore *core, const char *input) {
|
|||
PRINTF_BA ("@ 0x%"PFMT64x"\n", at);
|
||||
}
|
||||
}
|
||||
PRINT_GA ("}\n");
|
||||
PRINT_GA (" }\n");
|
||||
break;
|
||||
case ' ':
|
||||
arena = r_num_math (core->num, input + 1);
|
||||
|
|
@ -339,7 +339,7 @@ static void GH(jemalloc_print_narenas)(RCore *core, const char *input) {
|
|||
PRINTF_BA (" chunks_hooks = 0x%"PFMT64x"\n", OO(chunk_hooks));
|
||||
PRINTF_BA (" bins = %d 0x%"PFMT64x"\n", JM_NBINS, OO(bins));
|
||||
PRINTF_BA (" runs_avail = %d 0x%"PFMT64x"\n", NPSIZES, OO(runs_avail));
|
||||
PRINT_GA ("}\n");
|
||||
PRINT_GA (" }\n");
|
||||
break;
|
||||
}
|
||||
free (ar);
|
||||
|
|
@ -419,7 +419,7 @@ static void GH(jemalloc_get_bins)(RCore *core, const char *input) {
|
|||
PRINT_YA (" }\n");
|
||||
}
|
||||
}
|
||||
PRINT_GA ("}\n");
|
||||
PRINT_GA (" }\n");
|
||||
break;
|
||||
}
|
||||
free (ar);
|
||||
|
|
|
|||
|
|
@ -1,11 +1,10 @@
|
|||
/* radare - Apache - Copyright 2014-2020 - dso, pancake */
|
||||
/* radare - Apache - Copyright 2014-2022 - dso, pancake */
|
||||
|
||||
#include <r_types.h>
|
||||
#include <r_lib.h>
|
||||
#include <r_cmd.h>
|
||||
#include <r_core.h>
|
||||
#include <r_cons.h>
|
||||
#include <string.h>
|
||||
#include <r_anal.h>
|
||||
|
||||
#include "../../../shlr/java/ops.h"
|
||||
|
|
@ -16,7 +15,6 @@
|
|||
#undef IFDBG
|
||||
#define IFDBG if (DO_THE_DBG)
|
||||
|
||||
|
||||
typedef struct found_idx_t {
|
||||
ut16 idx;
|
||||
ut64 addr;
|
||||
|
|
|
|||
|
|
@ -731,12 +731,12 @@ R_API void r_core_rtr_add(RCore *core, const char *_input) {
|
|||
const char *name;
|
||||
int protocol;
|
||||
} uris[7] = {
|
||||
{"tcp", RTR_PROTOCOL_TCP},
|
||||
{"udp", RTR_PROTOCOL_UDP},
|
||||
{"rap", RTR_PROTOCOL_RAP},
|
||||
{"r2p", RTR_PROTOCOL_RAP},
|
||||
{"http", RTR_PROTOCOL_HTTP},
|
||||
{"unix", RTR_PROTOCOL_UNIX},
|
||||
{ "tcp", RTR_PROTOCOL_TCP},
|
||||
{ "udp", RTR_PROTOCOL_UDP},
|
||||
{ "rap", RTR_PROTOCOL_RAP},
|
||||
{ "r2p", RTR_PROTOCOL_RAP},
|
||||
{ "http", RTR_PROTOCOL_HTTP},
|
||||
{ "unix", RTR_PROTOCOL_UNIX},
|
||||
{NULL, 0}
|
||||
};
|
||||
char *s = r_str_ndup (input, pikaboo - input);
|
||||
|
|
@ -1326,7 +1326,7 @@ beach:
|
|||
#else
|
||||
|
||||
R_API int r_core_rtr_cmds(RCore *core, const char *port) {
|
||||
unsigned char buf[4097];
|
||||
ut8 buf[4097];
|
||||
RSocket *ch = NULL;
|
||||
int i, ret;
|
||||
char *str;
|
||||
|
|
|
|||
|
|
@ -3853,7 +3853,7 @@ static void handleHints(RCore *core) {
|
|||
//TODO extend for more anal hints
|
||||
int i = 0;
|
||||
char ch[64] = {0};
|
||||
const char *lines[] = {"[dh]- Define anal hint:"
|
||||
const char *lines[] = { "[dh]- Define anal hint:"
|
||||
," b [16,32,64] set bits hint"
|
||||
, NULL};
|
||||
for (i = 0; lines[i]; i++) {
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@ static const struct {
|
|||
{ "hamdist", R_HASH_HAMDIST },
|
||||
{ "pcprint", R_HASH_PCPRINT },
|
||||
{ "mod255", R_HASH_MOD255 },
|
||||
// {"base64", R_HASH_BASE64},
|
||||
// {"base91", R_HASH_BASE91},
|
||||
// {"punycode", R_HASH_PUNYCODE},
|
||||
// { "base64", R_HASH_BASE64},
|
||||
// { "base91", R_HASH_BASE91},
|
||||
// { "punycode", R_HASH_PUNYCODE},
|
||||
{ "luhn", R_HASH_LUHN },
|
||||
{ "ssdeep", R_HASH_SSDEEP },
|
||||
|
||||
|
|
|
|||
|
|
@ -275,7 +275,7 @@ static void serialize_registers(Sdb *db, HtUP *registers) {
|
|||
ht_up_foreach (registers, serialize_register_cb, db);
|
||||
}
|
||||
|
||||
// 0x<addr>={"size":<size_t>, "a":[<RDebugChangeMem>]}},
|
||||
// 0x<addr>={ "size":<size_t>, "a":[<RDebugChangeMem>]}},
|
||||
static bool serialize_memory_cb(void *db, const ut64 k, const void *v) {
|
||||
RDebugChangeMem *mem;
|
||||
RVector *vmem = (RVector *)v;
|
||||
|
|
@ -311,8 +311,8 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) {
|
|||
|
||||
r_vector_foreach (checkpoints, chkpt) {
|
||||
// 0x<cnum>={
|
||||
// registers:{"<RRegisterType>":<RRegArena>, ...},
|
||||
// snaps:{"size":<size_t>, "a":[<RDebugSnap>]}
|
||||
// registers:{ "<RRegisterType>":<RRegArena>, ...},
|
||||
// snaps:{ "size":<size_t>, "a":[<RDebugSnap>]}
|
||||
// }
|
||||
PJ *j = pj_new ();
|
||||
if (!j) {
|
||||
|
|
@ -321,7 +321,7 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) {
|
|||
pj_o (j);
|
||||
|
||||
// Serialize RRegArena to "registers"
|
||||
// {"size":<int>, "bytes":"<base64>"}
|
||||
// { "size":<int>, "bytes":"<base64>" }
|
||||
pj_ka (j, "registers");
|
||||
for (i = 0; i < R_REG_TYPE_LAST; i++) {
|
||||
RRegArena *arena = chkpt->arena[i];
|
||||
|
|
@ -338,7 +338,7 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) {
|
|||
pj_end (j);
|
||||
|
||||
// Serialize RDebugSnap to "snaps"
|
||||
// {"name":<str>, "addr":<ut64>, "addr_end":<ut64>, "size":<ut64>,
|
||||
// { "name":<str>, "addr":<ut64>, "addr_end":<ut64>, "size":<ut64>,
|
||||
// "data":"<base64>", "perm":<int>, "user":<int>, "shared":<bool>}
|
||||
pj_ka (j, "snaps");
|
||||
r_list_foreach (chkpt->snaps, iter, snap) {
|
||||
|
|
@ -375,28 +375,28 @@ static void serialize_checkpoints(Sdb *db, RVector *checkpoints) {
|
|||
* maxcnum=<maxcnum>
|
||||
*
|
||||
* /registers
|
||||
* 0x<addr>={"size":<size_t>, "a":[<RDebugChangeReg>]}
|
||||
* 0x<addr>={ "size":<size_t>, "a":[<RDebugChangeReg>]}
|
||||
*
|
||||
* /memory
|
||||
* 0x<addr>={"size":<size_t>, "a":[<RDebugChangeMem>]}
|
||||
* 0x<addr>={ "size":<size_t>, "a":[<RDebugChangeMem>]}
|
||||
*
|
||||
* /checkpoints
|
||||
* 0x<cnum>={
|
||||
* registers:{"<RRegisterType>":<RRegArena>, ...},
|
||||
* snaps:{"size":<size_t>, "a":[<RDebugSnap>]}
|
||||
* registers:{ "<RRegisterType>":<RRegArena>, ...},
|
||||
* snaps:{ "size":<size_t>, "a":[<RDebugSnap>]}
|
||||
* }
|
||||
*
|
||||
* RDebugChangeReg JSON:
|
||||
* {"cnum":<int>, "data":<ut64>}
|
||||
* { "cnum":<int>, "data":<ut64>}
|
||||
*
|
||||
* RDebugChangeMem JSON:
|
||||
* {"cnum":<int>, "data":<ut8>}
|
||||
* { "cnum":<int>, "data":<ut8>}
|
||||
*
|
||||
* RRegArena JSON:
|
||||
* {"size":<int>, "bytes":"<base64>"}
|
||||
* { "size":<int>, "bytes":"<base64>" }
|
||||
*
|
||||
* RDebugSnap JSON:
|
||||
* {"name":<str>, "addr":<ut64>, "addr_end":<ut64>, "size":<ut64>,
|
||||
* { "name":<str>, "addr":<ut64>, "addr_end":<ut64>, "size":<ut64>,
|
||||
* "data":"<base64>", "perm":<int>, "user":<int>, "shared":<bool>}
|
||||
*
|
||||
* Notes:
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ struct cEnv_t {
|
|||
|
||||
static char* r_egg_cfile_getCompiler(void) {
|
||||
size_t i;
|
||||
const char *compilers[] = {"llvm-gcc", "clang", "gcc"};
|
||||
const char *compilers[] = { "llvm-gcc", "clang", "gcc" };
|
||||
char *output = r_sys_getenv ("CC");
|
||||
|
||||
if (output) {
|
||||
|
|
@ -223,7 +223,7 @@ static bool r_egg_cfile_parseCompiled(const char *file) {
|
|||
buffer = r_str_replace (buffer, "rodata", "text", false);
|
||||
buffer = r_str_replace (buffer, "get_pc_thunk.bx", "__getesp__", true);
|
||||
|
||||
const char *words[] = {".cstring", "size", "___main", "section", "__alloca", "zero", "cfi"};
|
||||
const char *words[] = { ".cstring", "size", "___main", "section", "__alloca", "zero", "cfi" };
|
||||
size_t i;
|
||||
for (i = 0; i < 7; i++) {
|
||||
r_str_stripLine (buffer, words[i]);
|
||||
|
|
@ -325,7 +325,7 @@ R_API char* r_egg_cfile_parser(const char *file, const char *arch, const char *o
|
|||
}
|
||||
|
||||
size_t i;
|
||||
const char *extArray[] = {"bin", "tmp", "s", "o"};
|
||||
const char *extArray[] = { "bin", "tmp", "s", "o" };
|
||||
for (i = 0; i < 4; i++) {
|
||||
free (fileExt);
|
||||
if (!(fileExt = r_str_newf ("%s.%s", file, extArray[i]))) {
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ static void emit_arg(REgg *egg, int xs, int num, const char *str) {
|
|||
if (d) {
|
||||
r_egg_printf (egg, " add "R_BP ", %d\n", d);
|
||||
}
|
||||
r_egg_printf (egg, " push {"R_BP "}\n");
|
||||
r_egg_printf (egg, " push { "R_BP " }\n");
|
||||
if (d) {
|
||||
r_egg_printf (egg, " sub "R_BP ", %d\n", d);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ static void emit_arg(REgg *egg, int xs, int num, const char *str) {
|
|||
if (d) {
|
||||
r_egg_printf (egg, " add "R_BP ", %d\n", d);
|
||||
}
|
||||
r_egg_printf (egg, " push {"R_BP "}\n");
|
||||
r_egg_printf (egg, " push { "R_BP " }\n");
|
||||
if (d) {
|
||||
r_egg_printf (egg, " sub "R_BP ", %d\n", d);
|
||||
}
|
||||
|
|
|
|||
16
libr/fs/fs.c
16
libr/fs/fs.c
|
|
@ -530,19 +530,19 @@ static int fs_parhook(void* disk, void* ptr, void* closure) {
|
|||
|
||||
static RFSPartitionType partitions[] = {
|
||||
/* LGPL code */
|
||||
{"dos", &fs_part_dos, fs_parhook},
|
||||
{ "dos", &fs_part_dos, fs_parhook},
|
||||
#if USE_GRUB
|
||||
/* WARNING GPL code */
|
||||
#if !__EMSCRIPTEN__
|
||||
// wtf for some reason is not available on emscripten
|
||||
{"msdos", &grub_msdos_partition_map, grub_parhook},
|
||||
{ "msdos", &grub_msdos_partition_map, grub_parhook},
|
||||
#endif
|
||||
{"apple", &grub_apple_partition_map, grub_parhook},
|
||||
{"sun", &grub_sun_partition_map, grub_parhook},
|
||||
{"sunpc", &grub_sun_pc_partition_map, grub_parhook},
|
||||
{"amiga", &grub_amiga_partition_map, grub_parhook},
|
||||
{"bsdlabel", &grub_bsdlabel_partition_map, grub_parhook},
|
||||
{"gpt", &grub_gpt_partition_map, grub_parhook},
|
||||
{ "apple", &grub_apple_partition_map, grub_parhook},
|
||||
{ "sun", &grub_sun_partition_map, grub_parhook},
|
||||
{ "sunpc", &grub_sun_pc_partition_map, grub_parhook},
|
||||
{ "amiga", &grub_amiga_partition_map, grub_parhook},
|
||||
{ "bsdlabel", &grub_bsdlabel_partition_map, grub_parhook},
|
||||
{ "gpt", &grub_gpt_partition_map, grub_parhook},
|
||||
#endif
|
||||
// XXX: In BURG all bsd partition map are in bsdlabel
|
||||
//{ "openbsdlabel", &grub_openbsd_partition_map },
|
||||
|
|
|
|||
|
|
@ -29,12 +29,12 @@ static RList *__cfg(RFSRoot *root, const char *path);
|
|||
static RList *__flags(RFSRoot *root, const char *path);
|
||||
|
||||
static Routes routes[] = {
|
||||
{"/cfg", &__cfg, &__cfg_cat, &__cfg_write },
|
||||
{"/flags", &__flags, &__flags_cat, NULL},
|
||||
{"/version", NULL, &__version, NULL},
|
||||
{"/seek", NULL, &__seek_cat, &__seek_write },
|
||||
{"/bsize", NULL, &__bsize_cat, &__bsize_write },
|
||||
{"/", &__root},
|
||||
{ "/cfg", &__cfg, &__cfg_cat, &__cfg_write },
|
||||
{ "/flags", &__flags, &__flags_cat, NULL},
|
||||
{ "/version", NULL, &__version, NULL},
|
||||
{ "/seek", NULL, &__seek_cat, &__seek_write },
|
||||
{ "/bsize", NULL, &__bsize_cat, &__bsize_write },
|
||||
{ "/", &__root},
|
||||
{NULL, NULL}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ typedef int witness_comp_t (const witness_t *, const witness_t *);
|
|||
#define WITNESS_RANK_PROF_NEXT_THR_UID WITNESS_RANK_LEAF
|
||||
#define WITNESS_RANK_PROF_THREAD_ACTIVE_INIT WITNESS_RANK_LEAF
|
||||
|
||||
#define WITNESS_INITIALIZER(rank) {"initializer", rank, NULL, {NULL, NULL}}
|
||||
#define WITNESS_INITIALIZER(rank) { "initializer", rank, NULL, {NULL, NULL}}
|
||||
|
||||
#endif /* JEMALLOC_H_TYPES */
|
||||
/******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -23,18 +23,18 @@ typedef struct r_io_zip_uri_const_t {
|
|||
} RIOZipConstURI;
|
||||
|
||||
static RIOZipConstURI ZIP_URIS[] = {
|
||||
{"zip://", 6},
|
||||
{"ipa://", 6},
|
||||
{"jar://", 6},
|
||||
{ "zip://", 6},
|
||||
{ "ipa://", 6},
|
||||
{ "jar://", 6},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
static RIOZipConstURI ZIP_ALL_URIS[] = {
|
||||
{"apk://", 6},
|
||||
{"zipall://", 9},
|
||||
{"apkall://", 9},
|
||||
{"ipaall://", 9},
|
||||
{"jarall://", 9},
|
||||
{ "apk://", 6},
|
||||
{ "zipall://", 9},
|
||||
{ "apkall://", 9},
|
||||
{ "ipaall://", 9},
|
||||
{ "jarall://", 9},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -120,55 +120,55 @@ static const struct names {
|
|||
} names[] = {
|
||||
/* These must be sorted by eye for optimal hit rate */
|
||||
/* Add to this list only after substantial meditation */
|
||||
{"msgid", L_PO},
|
||||
{"dnl", L_M4},
|
||||
{"import", L_JAVA},
|
||||
{"\"libhdr\"", L_BCPL},
|
||||
{"\"LIBHDR\"", L_BCPL},
|
||||
{"//", L_CC},
|
||||
{"template", L_CC},
|
||||
{"virtual", L_CC},
|
||||
{"class", L_CC},
|
||||
{"public:", L_CC},
|
||||
{"private:", L_CC},
|
||||
{"/*", L_C}, /* must precede "The", "the", etc. */
|
||||
{"#include", L_C},
|
||||
{"char", L_C},
|
||||
{"The", L_ENG},
|
||||
{"the", L_ENG},
|
||||
{"double", L_C},
|
||||
{"extern", L_C},
|
||||
{"float", L_C},
|
||||
{"struct", L_C},
|
||||
{"union", L_C},
|
||||
{"CFLAGS", L_MAKE},
|
||||
{"LDFLAGS", L_MAKE},
|
||||
{"all:", L_MAKE},
|
||||
{".PRECIOUS", L_MAKE},
|
||||
{".ascii", L_MACH},
|
||||
{".asciiz", L_MACH},
|
||||
{".byte", L_MACH},
|
||||
{".even", L_MACH},
|
||||
{".globl", L_MACH},
|
||||
{".text", L_MACH},
|
||||
{"clr", L_MACH},
|
||||
{"(input,", L_PAS},
|
||||
{"program", L_PAS},
|
||||
{"record", L_PAS},
|
||||
{"dcl", L_PLI},
|
||||
{"Received:", L_MAIL},
|
||||
{">From", L_MAIL},
|
||||
{"Return-Path:",L_MAIL},
|
||||
{"Cc:", L_MAIL},
|
||||
{"Newsgroups:", L_NEWS},
|
||||
{"Path:", L_NEWS},
|
||||
{"Organization:",L_NEWS},
|
||||
{"href=", L_HTML},
|
||||
{"HREF=", L_HTML},
|
||||
{"<body", L_HTML},
|
||||
{"<BODY", L_HTML},
|
||||
{"<html", L_HTML},
|
||||
{"<HTML", L_HTML},
|
||||
{"<!--", L_HTML},
|
||||
{ "msgid", L_PO},
|
||||
{ "dnl", L_M4},
|
||||
{ "import", L_JAVA},
|
||||
{ "\"libhdr\"", L_BCPL},
|
||||
{ "\"LIBHDR\"", L_BCPL},
|
||||
{ "//", L_CC},
|
||||
{ "template", L_CC},
|
||||
{ "virtual", L_CC},
|
||||
{ "class", L_CC},
|
||||
{ "public:", L_CC},
|
||||
{ "private:", L_CC},
|
||||
{ "/*", L_C}, /* must precede "The", "the", etc. */
|
||||
{ "#include", L_C},
|
||||
{ "char", L_C},
|
||||
{ "The", L_ENG},
|
||||
{ "the", L_ENG},
|
||||
{ "double", L_C},
|
||||
{ "extern", L_C},
|
||||
{ "float", L_C},
|
||||
{ "struct", L_C},
|
||||
{ "union", L_C},
|
||||
{ "CFLAGS", L_MAKE},
|
||||
{ "LDFLAGS", L_MAKE},
|
||||
{ "all:", L_MAKE},
|
||||
{ ".PRECIOUS", L_MAKE},
|
||||
{ ".ascii", L_MACH},
|
||||
{ ".asciiz", L_MACH},
|
||||
{ ".byte", L_MACH},
|
||||
{ ".even", L_MACH},
|
||||
{ ".globl", L_MACH},
|
||||
{ ".text", L_MACH},
|
||||
{ "clr", L_MACH},
|
||||
{ "(input,", L_PAS},
|
||||
{ "program", L_PAS},
|
||||
{ "record", L_PAS},
|
||||
{ "dcl", L_PLI},
|
||||
{ "Received:", L_MAIL},
|
||||
{ ">From", L_MAIL},
|
||||
{ "Return-Path:",L_MAIL},
|
||||
{ "Cc:", L_MAIL},
|
||||
{ "Newsgroups:", L_NEWS},
|
||||
{ "Path:", L_NEWS},
|
||||
{ "Organization:",L_NEWS},
|
||||
{ "href=", L_HTML},
|
||||
{ "HREF=", L_HTML},
|
||||
{ "<body", L_HTML},
|
||||
{ "<BODY", L_HTML},
|
||||
{ "<html", L_HTML},
|
||||
{ "<HTML", L_HTML},
|
||||
{ "<!--", L_HTML},
|
||||
};
|
||||
#define NNAMES (sizeof (names)/sizeof (struct names))
|
||||
|
|
|
|||
|
|
@ -23,52 +23,52 @@ static int replace(int argc, const char *argv[], char *newstr, ADDR_TYPE type) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{1, "lda", "a = 1"},
|
||||
{2, "lda", "a = (1+2)"},
|
||||
{1, "ldx", "x = 1"},
|
||||
{2, "ldx", "x = (1+2)"},
|
||||
{1, "ldy", "y = 1"},
|
||||
{2, "ldy", "y = (1+2)"},
|
||||
{1, "sta", "[1] = a"},
|
||||
{2, "sta", "[1+2 ] = a"},
|
||||
{1, "stx", "[1] = x"},
|
||||
{2, "stx", "[1+2] = x"},
|
||||
{1, "sty", "[1] = y"},
|
||||
{2, "sty", "[1+2] = y"},
|
||||
{1, "dec", "1--"},
|
||||
{2, "dec", "(1+2)--"},
|
||||
{0, "dcx", "x--"},
|
||||
{0, "dcy", "y--"},
|
||||
{1, "inc", "1++"},
|
||||
{2, "inc", "(1+2)++"},
|
||||
{0, "inx", "x++"},
|
||||
{0, "iny", "y++"},
|
||||
{1, "adc", "a += 1"},
|
||||
{2, "adc", "a += (1+2)"},
|
||||
{1, "sbc", "a -= 1"},
|
||||
{2, "sbc", "a -= (1+2)"},
|
||||
{0, "pha", "push a"},
|
||||
{1, "and", "a &= 1"},
|
||||
{2, "and", "a &= (1+2)"},
|
||||
{1, "eor", "a ^= 1"},
|
||||
{2, "eor", "a ^= (1+2)"},
|
||||
{1, "ora", "a |= 1"},
|
||||
{2, "ora", "a |= (1+2)"},
|
||||
{0, "tax", "x = a"},
|
||||
{0, "tay", "y = a"},
|
||||
{0, "txa", "a = x"},
|
||||
{0, "tya", "a = y"},
|
||||
{0, "tsx", "x = s"},
|
||||
{0, "txs", "s = x"},
|
||||
{0, "brk", "break"},
|
||||
{0, "clc", "clear_carry"},
|
||||
{0, "cld", "clear_decimal"},
|
||||
{0, "cli", "clear_interrupt"},
|
||||
{0, "clv", "clear_overflow"},
|
||||
{0, "sec", "set_carry"},
|
||||
{0, "sed", "set_decimal"},
|
||||
{0, "sei", "set_interrupt"},
|
||||
{1, "jsr", "1()"},
|
||||
{1, "lda", "a = 1" },
|
||||
{2, "lda", "a = (1+2)" },
|
||||
{1, "ldx", "x = 1" },
|
||||
{2, "ldx", "x = (1+2)" },
|
||||
{1, "ldy", "y = 1" },
|
||||
{2, "ldy", "y = (1+2)" },
|
||||
{1, "sta", "[1] = a" },
|
||||
{2, "sta", "[1+2 ] = a" },
|
||||
{1, "stx", "[1] = x" },
|
||||
{2, "stx", "[1+2] = x" },
|
||||
{1, "sty", "[1] = y" },
|
||||
{2, "sty", "[1+2] = y" },
|
||||
{1, "dec", "1--" },
|
||||
{2, "dec", "(1+2)--" },
|
||||
{0, "dcx", "x--" },
|
||||
{0, "dcy", "y--" },
|
||||
{1, "inc", "1++" },
|
||||
{2, "inc", "(1+2)++" },
|
||||
{0, "inx", "x++" },
|
||||
{0, "iny", "y++" },
|
||||
{1, "adc", "a += 1" },
|
||||
{2, "adc", "a += (1+2)" },
|
||||
{1, "sbc", "a -= 1" },
|
||||
{2, "sbc", "a -= (1+2)" },
|
||||
{0, "pha", "push a" },
|
||||
{1, "and", "a &= 1" },
|
||||
{2, "and", "a &= (1+2)" },
|
||||
{1, "eor", "a ^= 1" },
|
||||
{2, "eor", "a ^= (1+2)" },
|
||||
{1, "ora", "a |= 1" },
|
||||
{2, "ora", "a |= (1+2)" },
|
||||
{0, "tax", "x = a" },
|
||||
{0, "tay", "y = a" },
|
||||
{0, "txa", "a = x" },
|
||||
{0, "tya", "a = y" },
|
||||
{0, "tsx", "x = s" },
|
||||
{0, "txs", "s = x" },
|
||||
{0, "brk", "break" },
|
||||
{0, "clc", "clear_carry" },
|
||||
{0, "cld", "clear_decimal" },
|
||||
{0, "cli", "clear_interrupt" },
|
||||
{0, "clv", "clear_overflow" },
|
||||
{0, "sec", "set_carry" },
|
||||
{0, "sed", "set_decimal" },
|
||||
{0, "sei", "set_interrupt" },
|
||||
{1, "jsr", "1()" },
|
||||
{0, NULL}};
|
||||
if (!newstr) {
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{ "cmpl", "cmp 2, 1"},
|
||||
{ "testl", "test 2, 1"},
|
||||
{ "leal", "lea 2, 1"},
|
||||
{ "movl", "mov 2, 1"},
|
||||
{ "xorl", "xor 2, 1"},
|
||||
{ "andl", "and 2, 1"},
|
||||
{ "orl", "or 2, 1"},
|
||||
{ "addl", "add 2, 1"},
|
||||
{ "incl", "inc 1"},
|
||||
{ "decl", "dec 1"},
|
||||
{ "subl", "sub 2, 1"},
|
||||
{ "mull", "mul 2, 1"},
|
||||
{ "divl", "div 2, 1"},
|
||||
{ "pushl", "push 1"},
|
||||
{ "popl", "pop 1"},
|
||||
{ "ret", "ret"},
|
||||
{ "cmpl", "cmp 2, 1" },
|
||||
{ "testl", "test 2, 1" },
|
||||
{ "leal", "lea 2, 1" },
|
||||
{ "movl", "mov 2, 1" },
|
||||
{ "xorl", "xor 2, 1" },
|
||||
{ "andl", "and 2, 1" },
|
||||
{ "orl", "or 2, 1" },
|
||||
{ "addl", "add 2, 1" },
|
||||
{ "incl", "inc 1" },
|
||||
{ "decl", "dec 1" },
|
||||
{ "subl", "sub 2, 1" },
|
||||
{ "mull", "mul 2, 1" },
|
||||
{ "divl", "div 2, 1" },
|
||||
{ "pushl", "push 1" },
|
||||
{ "popl", "pop 1" },
|
||||
{ "ret", "ret" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -16,87 +16,87 @@ static bool replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{ "add", "A += B"},
|
||||
{ "adc", "A += B + carry"},
|
||||
{ "adiw", "A+1:A += B"},
|
||||
{ "sub", "A -= B"},
|
||||
{ "subi", "A -= B"},
|
||||
{ "sbc", "A -= (B + carry)"},
|
||||
{ "sbci", "A -= (B + carry)"},
|
||||
{ "sbiw", "A+1:A -= B"},
|
||||
{ "and", "A &= B"},
|
||||
{ "andi", "A &= B"},
|
||||
{ "or", "A |= B"},
|
||||
{ "ori", "A |= B"},
|
||||
{ "eor", "A ^= B"},
|
||||
{ "com", "A = 0xff - A"},
|
||||
{ "neg", "A = -A"},
|
||||
{ "sbr", "A |= B"},
|
||||
{ "cbr", "A &= (0xff - B)"},
|
||||
{ "inc", "A++"},
|
||||
{ "dec", "A--"},
|
||||
{ "tst", "A &= A"},
|
||||
{ "clr", "A ^= A"},
|
||||
{ "ser", "A = 0xff"},
|
||||
{ "mul", "r1:r0 = A * B"},
|
||||
{ "rjmp", "goto A"},
|
||||
{ "ijmp", "goto z"},
|
||||
{ "jmp", "goto A"},
|
||||
{ "rcall", "goto A"},
|
||||
{ "icall", "goto z"},
|
||||
{ "call", "goto A"},
|
||||
{ "ret", "return"},
|
||||
{ "iret", "return_interrupt()"},
|
||||
{ "cp", "var = A - B"},
|
||||
{ "cpc", "var = A - B - carry"},
|
||||
{ "cpi", "var = A - B"},
|
||||
{ "breq", "if (!var) goto A"},
|
||||
{ "brne", "if (var) goto A"},
|
||||
{ "brsh", "if (var >= 0) goto A"},
|
||||
{ "brlo", "if (var < 0) goto A"},
|
||||
{ "brmi", "if (var < 0) goto A"},
|
||||
{ "brpl", "if (var > 0) goto A"},
|
||||
{ "brge", "if (var >= 0) goto A"},
|
||||
{ "brlt", "if (var < 0) goto A"},
|
||||
{ "mov", "A = B"},
|
||||
{ "movw", "A+1:A = B+1:B"},
|
||||
{ "ldi", "A = B"},
|
||||
{ "lds", "A = *(B)"},
|
||||
{ "ld", "A = *(B)"},
|
||||
{ "ldd", "A = *(B)"},
|
||||
{ "lpm", "r0 = z"},
|
||||
{ "in", "A = B"},
|
||||
{ "out", "A = B"},
|
||||
{ "push", "push(A)"},
|
||||
{ "pop", "A = pop()"},
|
||||
{ "lsl", "A <<= 1"},
|
||||
{ "lsr", "A >>= 1"},
|
||||
{ "rol", "A = (A << 1) | (A >> 7)"},
|
||||
{ "ror", "A = (A << 7) | (A >> 1)"},
|
||||
{ "asr", "A >>= 1"},
|
||||
{ "swap", "A = ((A & 0xf0) >> 4) | ((A & 0x0f) << 4)"},
|
||||
{ "sec", "c = 1"},
|
||||
{ "clc", "c = 0"},
|
||||
{ "sen", "n = 1"},
|
||||
{ "cln", "n = 0"},
|
||||
{ "sez", "z = 1"},
|
||||
{ "clz", "z = 0"},
|
||||
{ "sei", "i = 1"},
|
||||
{ "cli", "i = 0"},
|
||||
{ "ses", "s = 1"},
|
||||
{ "cls", "s = 0"},
|
||||
{ "sev", "v = 1"},
|
||||
{ "clv", "v = 0"},
|
||||
{ "set", "t = 1"},
|
||||
{ "clt", "t = 0"},
|
||||
{ "seh", "h = 1"},
|
||||
{ "clh", "h = 0"},
|
||||
{ "nop", ""},
|
||||
{ "halt", "_halt()"},
|
||||
{ "wdr", "_watchdog_reset()"},
|
||||
{ "std", "*(A) = B"},
|
||||
{ "st", "*(A) = B"},
|
||||
{ "sts", "*(A) = B"},
|
||||
{ "add", "A += B" },
|
||||
{ "adc", "A += B + carry" },
|
||||
{ "adiw", "A+1:A += B" },
|
||||
{ "sub", "A -= B" },
|
||||
{ "subi", "A -= B" },
|
||||
{ "sbc", "A -= (B + carry)" },
|
||||
{ "sbci", "A -= (B + carry)" },
|
||||
{ "sbiw", "A+1:A -= B" },
|
||||
{ "and", "A &= B" },
|
||||
{ "andi", "A &= B" },
|
||||
{ "or", "A |= B" },
|
||||
{ "ori", "A |= B" },
|
||||
{ "eor", "A ^= B" },
|
||||
{ "com", "A = 0xff - A" },
|
||||
{ "neg", "A = -A" },
|
||||
{ "sbr", "A |= B" },
|
||||
{ "cbr", "A &= (0xff - B)" },
|
||||
{ "inc", "A++" },
|
||||
{ "dec", "A--" },
|
||||
{ "tst", "A &= A" },
|
||||
{ "clr", "A ^= A" },
|
||||
{ "ser", "A = 0xff" },
|
||||
{ "mul", "r1:r0 = A * B" },
|
||||
{ "rjmp", "goto A" },
|
||||
{ "ijmp", "goto z" },
|
||||
{ "jmp", "goto A" },
|
||||
{ "rcall", "goto A" },
|
||||
{ "icall", "goto z" },
|
||||
{ "call", "goto A" },
|
||||
{ "ret", "return" },
|
||||
{ "iret", "return_interrupt()" },
|
||||
{ "cp", "var = A - B" },
|
||||
{ "cpc", "var = A - B - carry" },
|
||||
{ "cpi", "var = A - B" },
|
||||
{ "breq", "if (!var) goto A" },
|
||||
{ "brne", "if (var) goto A" },
|
||||
{ "brsh", "if (var >= 0) goto A" },
|
||||
{ "brlo", "if (var < 0) goto A" },
|
||||
{ "brmi", "if (var < 0) goto A" },
|
||||
{ "brpl", "if (var > 0) goto A" },
|
||||
{ "brge", "if (var >= 0) goto A" },
|
||||
{ "brlt", "if (var < 0) goto A" },
|
||||
{ "mov", "A = B" },
|
||||
{ "movw", "A+1:A = B+1:B" },
|
||||
{ "ldi", "A = B" },
|
||||
{ "lds", "A = *(B)" },
|
||||
{ "ld", "A = *(B)" },
|
||||
{ "ldd", "A = *(B)" },
|
||||
{ "lpm", "r0 = z" },
|
||||
{ "in", "A = B" },
|
||||
{ "out", "A = B" },
|
||||
{ "push", "push(A)" },
|
||||
{ "pop", "A = pop()" },
|
||||
{ "lsl", "A <<= 1" },
|
||||
{ "lsr", "A >>= 1" },
|
||||
{ "rol", "A = (A << 1) | (A >> 7)" },
|
||||
{ "ror", "A = (A << 7) | (A >> 1)" },
|
||||
{ "asr", "A >>= 1" },
|
||||
{ "swap", "A = ((A & 0xf0) >> 4) | ((A & 0x0f) << 4)" },
|
||||
{ "sec", "c = 1" },
|
||||
{ "clc", "c = 0" },
|
||||
{ "sen", "n = 1" },
|
||||
{ "cln", "n = 0" },
|
||||
{ "sez", "z = 1" },
|
||||
{ "clz", "z = 0" },
|
||||
{ "sei", "i = 1" },
|
||||
{ "cli", "i = 0" },
|
||||
{ "ses", "s = 1" },
|
||||
{ "cls", "s = 0" },
|
||||
{ "sev", "v = 1" },
|
||||
{ "clv", "v = 0" },
|
||||
{ "set", "t = 1" },
|
||||
{ "clt", "t = 0" },
|
||||
{ "seh", "h = 1" },
|
||||
{ "clh", "h = 0" },
|
||||
{ "nop", "" },
|
||||
{ "halt", "_halt()" },
|
||||
{ "wdr", "_watchdog_reset()" },
|
||||
{ "std", "*(A) = B" },
|
||||
{ "st", "*(A) = B" },
|
||||
{ "sts", "*(A) = B" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,181 +15,181 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{ "rsub-int", "1 = 2 - 3"},
|
||||
{ "float-to-double", "1 = (double)(float) 2"},
|
||||
{ "float-to-long", "1 = (long)(float) 2"},
|
||||
{ "float-to-int", "1 = (int)(float) 2"},
|
||||
{ "long-to-float", "1 = (float)(long) 2"},
|
||||
{ "long-to-int", "1 = (int)(long) 2"},
|
||||
{ "long-to-double", "1 = (double) 2"},
|
||||
{ "double-to-long", "1 = (long) 2"},
|
||||
{ "double-to-int", "1 = (int) 2"},
|
||||
{ "int-to-double", "1 = (double) 2"},
|
||||
{ "int-to-long", "1 = (long) 2"},
|
||||
{ "int-to-byte", "1 = (byte) 2"},
|
||||
{ "aget-byte", "1 = (byte) 2[3]"},
|
||||
{ "aget-short", "1 = (short) 2[3]"},
|
||||
{ "aget-object", "1 = (object) 2[3]"},
|
||||
{ "sput-wide", "1 = 2"},
|
||||
{ "sput-object", "1 = 2"},
|
||||
{ "add-long", "1 = 2 + 3"},
|
||||
{ "add-double", "1 = 2 + 3"},
|
||||
{ "mul-long", "1 = 2 * 3"},
|
||||
{ "const-string/jumbo", "1 = (jumbo-string) 2"},
|
||||
{ "const-string", "1 = (string) 2"},
|
||||
{ "const-wide", "1 = (wide) 2"},
|
||||
{ "const/4", "1 = (wide) 2"},
|
||||
{ "cmp-int", "1 = (2 == 3)"},
|
||||
{ "cmp-long", "1 = (2 == 3)"},
|
||||
{ "cmpl-double", "1 = (double)(2 == 3)"},
|
||||
{ "cmpl-float", "1 = (float)(2 == 3)"},
|
||||
{ "cmpl-int", "1 = (int)(2 == 3)"},
|
||||
{ "cmpg-double", "1 = (2 == 3)"},
|
||||
{ "cmpg-float", "1 = (2 == 3)"},
|
||||
{ "or-int/2addr", "1 |= 2"},
|
||||
{ "or-long", "1 |= 2"},
|
||||
{ "and-long/2addr", "1 &= (long) 2"},
|
||||
{ "and-int", "1 &= (int) 2"},
|
||||
{ "and-byte", "1 &= (byte) 2"},
|
||||
{ "sub-float/2addr", "1 -= 2"},
|
||||
{ "sub-float", "1 = 2 - 3"},
|
||||
{ "sub-int", "1 = (int) 2 - 3"},
|
||||
{ "sub-long", "1 = (long) 2 - 3"},
|
||||
{ "sub-long/2addr", "1 -= (long) 2"},
|
||||
{ "sub-int/2addr", "1 -= 2"},
|
||||
{ "move", "1 = 2"},
|
||||
{ "move/16", "1 = 2"},
|
||||
{ "move-object", "1 = (object) 2"},
|
||||
{ "move-object/16", "1 = (object) 2"},
|
||||
{ "move-object/from16", "1 = (object) 2"},
|
||||
{ "move-wide/from16", "1 = (wide) 2"},
|
||||
{ "array-length", "1 = Array.length (2)"},
|
||||
{ "new-array", "1 = new array (2, 3)"},
|
||||
{ "new-instance", "1 = new 2"},
|
||||
{ "shr-long/2addr", "1 >>= 2"},
|
||||
{ "shr-long", "1 = (long) 2 >> 3"},
|
||||
{ "shr-int", "1 = (int) 2 >> 3"},
|
||||
{ "ushr-int", "1 = (int) 2 >>> 3"},
|
||||
{ "ushr-int/2addr", "1 >>>= 2"},
|
||||
{ "ushr-long", "1 = (long) 2 >>> 3"},
|
||||
{ "ushl-int/2addr", "1 <<<= 2"},
|
||||
{ "shl-int/2addr", "1 <<<= 2"},
|
||||
{ "shl-int", "1 = (int) 2 << 3"},
|
||||
{ "shl-long", "1 = (long) 2 << 3"},
|
||||
{ "move/from16", "1 = 2"},
|
||||
{ "move-exception", "1 = exception"},
|
||||
{ "move-result", "1 = result"},
|
||||
{ "move-result-wide", "1 = (wide) result"},
|
||||
{ "move-result-object", "1 = (object) result"},
|
||||
{ "const-wide/high16", "1 = 2"},
|
||||
{ "const/16", "1 = 2"},
|
||||
{ "const-wide/16", "1 = 2"},
|
||||
{ "const-wide/32", "1 = 2"},
|
||||
{ "const-class", "1 = (class) 2"},
|
||||
{ "const/high16", "1 = 2"},
|
||||
{ "const", "1 = 2"},
|
||||
{ "rem-long", "1 = (long) 2 % 3"},
|
||||
{ "rem-double", "1 = (double) 2 % 3"},
|
||||
{ "rem-float", "1 = (float) 2 % 3"},
|
||||
{ "rem-long/2addr", "1 %= 2"},
|
||||
{ "rem-float/2addr", "1 %= (float) 2"},
|
||||
{ "rem-double/2addr", "1 %= (double) 2"},
|
||||
{ "instance-of", "1 = insteanceof (2) == 3"},
|
||||
{ "aput", "2[3] = 1"},
|
||||
{ "aput-byte", "2[3] = (byte) 1"},
|
||||
{ "aput-short", "2[3] = (short) 1"},
|
||||
{ "aput-object", "2[3] = (object) 1"},
|
||||
{ "aput-wide", "2[3] = (wide) 1"},
|
||||
{ "aput-char", "2[3] = (char) 1"},
|
||||
{ "aput-boolean", "2[3] = (bool) 1"},
|
||||
{ "aget", "1 = 2[3]"},
|
||||
{ "aget-wide", "1 = (wide) 2[3]"},
|
||||
{ "aget-char", "1 = (char) 2[3]"},
|
||||
{ "aget-boolean", "1 = (boolean) 2[3]"},
|
||||
{ "sget", "1 = 2"},
|
||||
{ "sget-char", "1 = (char) 2"},
|
||||
{ "sget-short", "1 = (short) 2"},
|
||||
{ "sget-boolean", "1 = (bool) 2"},
|
||||
{ "sget-object", "1 = (object) 2"},
|
||||
{ "iput", "2[3] = 1"},
|
||||
{ "iput-object", "2[3] = (object) 1"},
|
||||
{ "iput-byte", "2[3] = (byte) 1"},
|
||||
{ "iput-char", "2[3] = (char) 1"},
|
||||
{ "iput-boolean", "2[3] = (bool) 1"},
|
||||
{ "sput-boolean", "2[3] = (bool) 1"},
|
||||
{ "sput-char", "2[3] = (char) 1"},
|
||||
{ "iput-int", "2[3] = (int) 1"},
|
||||
{ "iget", "1 = 2[3]"},
|
||||
{ "sget-byte", "1 = (byte) 2 [3]"},
|
||||
{ "iget-byte", "1 = (byte) 2 [3]"},
|
||||
{ "iget-char", "1 = (char) 2 [3]"},
|
||||
{ "iget-short", "1 = (short) 2 [3]"},
|
||||
{ "iget-wide", "1 = (wide) 2 [3]"},
|
||||
{ "iget-object", "1 = (2) 3"},
|
||||
{ "iget-boolean", "1 = (bool) 2 [3]"},
|
||||
{ "+iget-wide-volatile", "1 = (wide-volatile) 2 [3]"},
|
||||
{ "if-eq", "if (1 == 2) goto 3"},
|
||||
{ "if-lt", "if (1 < 2) goto 3"},
|
||||
{ "if-ne", "if (1 != 2) goto 3"},
|
||||
{ "if-eqz", "if (!1) goto 2"},
|
||||
{ "if-ge", "if (1 > zero) goto 2"},
|
||||
{ "if-le", "if (1 <= 2) goto 3"},
|
||||
{ "if-gtz", "if (1 > 0) goto 2"},
|
||||
{ "filled-new-array", "1 = new Array(2)"},
|
||||
{ "neg-long", "1 = -2"},
|
||||
{ "neg-double", "1 = -2"},
|
||||
{ "neg-float", "1 = -2"},
|
||||
{ "not-int", "1 = !2"},
|
||||
{ "packed-switch", "switch 2"},
|
||||
{ "sparse-switch", "switch 2"},
|
||||
{ "invoke-direct", "call 2 1"},
|
||||
{ "invoke-direct/range", "call 2 1"},
|
||||
{ "invoke-interface", "call 2 1"},
|
||||
{ "invoke-static", "call 2 1"},
|
||||
{ "invoke-super", "call super 2 1"},
|
||||
{ "invoke-super/range", "call super 2 1"},
|
||||
{ "rsub-int", "1 = 2 - 3" },
|
||||
{ "float-to-double", "1 = (double)(float) 2" },
|
||||
{ "float-to-long", "1 = (long)(float) 2" },
|
||||
{ "float-to-int", "1 = (int)(float) 2" },
|
||||
{ "long-to-float", "1 = (float)(long) 2" },
|
||||
{ "long-to-int", "1 = (int)(long) 2" },
|
||||
{ "long-to-double", "1 = (double) 2" },
|
||||
{ "double-to-long", "1 = (long) 2" },
|
||||
{ "double-to-int", "1 = (int) 2" },
|
||||
{ "int-to-double", "1 = (double) 2" },
|
||||
{ "int-to-long", "1 = (long) 2" },
|
||||
{ "int-to-byte", "1 = (byte) 2" },
|
||||
{ "aget-byte", "1 = (byte) 2[3]" },
|
||||
{ "aget-short", "1 = (short) 2[3]" },
|
||||
{ "aget-object", "1 = (object) 2[3]" },
|
||||
{ "sput-wide", "1 = 2" },
|
||||
{ "sput-object", "1 = 2" },
|
||||
{ "add-long", "1 = 2 + 3" },
|
||||
{ "add-double", "1 = 2 + 3" },
|
||||
{ "mul-long", "1 = 2 * 3" },
|
||||
{ "const-string/jumbo", "1 = (jumbo-string) 2" },
|
||||
{ "const-string", "1 = (string) 2" },
|
||||
{ "const-wide", "1 = (wide) 2" },
|
||||
{ "const/4", "1 = (wide) 2" },
|
||||
{ "cmp-int", "1 = (2 == 3)" },
|
||||
{ "cmp-long", "1 = (2 == 3)" },
|
||||
{ "cmpl-double", "1 = (double)(2 == 3)" },
|
||||
{ "cmpl-float", "1 = (float)(2 == 3)" },
|
||||
{ "cmpl-int", "1 = (int)(2 == 3)" },
|
||||
{ "cmpg-double", "1 = (2 == 3)" },
|
||||
{ "cmpg-float", "1 = (2 == 3)" },
|
||||
{ "or-int/2addr", "1 |= 2" },
|
||||
{ "or-long", "1 |= 2" },
|
||||
{ "and-long/2addr", "1 &= (long) 2" },
|
||||
{ "and-int", "1 &= (int) 2" },
|
||||
{ "and-byte", "1 &= (byte) 2" },
|
||||
{ "sub-float/2addr", "1 -= 2" },
|
||||
{ "sub-float", "1 = 2 - 3" },
|
||||
{ "sub-int", "1 = (int) 2 - 3" },
|
||||
{ "sub-long", "1 = (long) 2 - 3" },
|
||||
{ "sub-long/2addr", "1 -= (long) 2" },
|
||||
{ "sub-int/2addr", "1 -= 2" },
|
||||
{ "move", "1 = 2" },
|
||||
{ "move/16", "1 = 2" },
|
||||
{ "move-object", "1 = (object) 2" },
|
||||
{ "move-object/16", "1 = (object) 2" },
|
||||
{ "move-object/from16", "1 = (object) 2" },
|
||||
{ "move-wide/from16", "1 = (wide) 2" },
|
||||
{ "array-length", "1 = Array.length (2)" },
|
||||
{ "new-array", "1 = new array (2, 3)" },
|
||||
{ "new-instance", "1 = new 2" },
|
||||
{ "shr-long/2addr", "1 >>= 2" },
|
||||
{ "shr-long", "1 = (long) 2 >> 3" },
|
||||
{ "shr-int", "1 = (int) 2 >> 3" },
|
||||
{ "ushr-int", "1 = (int) 2 >>> 3" },
|
||||
{ "ushr-int/2addr", "1 >>>= 2" },
|
||||
{ "ushr-long", "1 = (long) 2 >>> 3" },
|
||||
{ "ushl-int/2addr", "1 <<<= 2" },
|
||||
{ "shl-int/2addr", "1 <<<= 2" },
|
||||
{ "shl-int", "1 = (int) 2 << 3" },
|
||||
{ "shl-long", "1 = (long) 2 << 3" },
|
||||
{ "move/from16", "1 = 2" },
|
||||
{ "move-exception", "1 = exception" },
|
||||
{ "move-result", "1 = result" },
|
||||
{ "move-result-wide", "1 = (wide) result" },
|
||||
{ "move-result-object", "1 = (object) result" },
|
||||
{ "const-wide/high16", "1 = 2" },
|
||||
{ "const/16", "1 = 2" },
|
||||
{ "const-wide/16", "1 = 2" },
|
||||
{ "const-wide/32", "1 = 2" },
|
||||
{ "const-class", "1 = (class) 2" },
|
||||
{ "const/high16", "1 = 2" },
|
||||
{ "const", "1 = 2" },
|
||||
{ "rem-long", "1 = (long) 2 % 3" },
|
||||
{ "rem-double", "1 = (double) 2 % 3" },
|
||||
{ "rem-float", "1 = (float) 2 % 3" },
|
||||
{ "rem-long/2addr", "1 %= 2" },
|
||||
{ "rem-float/2addr", "1 %= (float) 2" },
|
||||
{ "rem-double/2addr", "1 %= (double) 2" },
|
||||
{ "instance-of", "1 = insteanceof (2) == 3" },
|
||||
{ "aput", "2[3] = 1" },
|
||||
{ "aput-byte", "2[3] = (byte) 1" },
|
||||
{ "aput-short", "2[3] = (short) 1" },
|
||||
{ "aput-object", "2[3] = (object) 1" },
|
||||
{ "aput-wide", "2[3] = (wide) 1" },
|
||||
{ "aput-char", "2[3] = (char) 1" },
|
||||
{ "aput-boolean", "2[3] = (bool) 1" },
|
||||
{ "aget", "1 = 2[3]" },
|
||||
{ "aget-wide", "1 = (wide) 2[3]" },
|
||||
{ "aget-char", "1 = (char) 2[3]" },
|
||||
{ "aget-boolean", "1 = (boolean) 2[3]" },
|
||||
{ "sget", "1 = 2" },
|
||||
{ "sget-char", "1 = (char) 2" },
|
||||
{ "sget-short", "1 = (short) 2" },
|
||||
{ "sget-boolean", "1 = (bool) 2" },
|
||||
{ "sget-object", "1 = (object) 2" },
|
||||
{ "iput", "2[3] = 1" },
|
||||
{ "iput-object", "2[3] = (object) 1" },
|
||||
{ "iput-byte", "2[3] = (byte) 1" },
|
||||
{ "iput-char", "2[3] = (char) 1" },
|
||||
{ "iput-boolean", "2[3] = (bool) 1" },
|
||||
{ "sput-boolean", "2[3] = (bool) 1" },
|
||||
{ "sput-char", "2[3] = (char) 1" },
|
||||
{ "iput-int", "2[3] = (int) 1" },
|
||||
{ "iget", "1 = 2[3]" },
|
||||
{ "sget-byte", "1 = (byte) 2 [3]" },
|
||||
{ "iget-byte", "1 = (byte) 2 [3]" },
|
||||
{ "iget-char", "1 = (char) 2 [3]" },
|
||||
{ "iget-short", "1 = (short) 2 [3]" },
|
||||
{ "iget-wide", "1 = (wide) 2 [3]" },
|
||||
{ "iget-object", "1 = (2) 3" },
|
||||
{ "iget-boolean", "1 = (bool) 2 [3]" },
|
||||
{ "+iget-wide-volatile", "1 = (wide-volatile) 2 [3]" },
|
||||
{ "if-eq", "if (1 == 2) goto 3" },
|
||||
{ "if-lt", "if (1 < 2) goto 3" },
|
||||
{ "if-ne", "if (1 != 2) goto 3" },
|
||||
{ "if-eqz", "if (!1) goto 2" },
|
||||
{ "if-ge", "if (1 > zero) goto 2" },
|
||||
{ "if-le", "if (1 <= 2) goto 3" },
|
||||
{ "if-gtz", "if (1 > 0) goto 2" },
|
||||
{ "filled-new-array", "1 = new Array(2)" },
|
||||
{ "neg-long", "1 = -2" },
|
||||
{ "neg-double", "1 = -2" },
|
||||
{ "neg-float", "1 = -2" },
|
||||
{ "not-int", "1 = !2" },
|
||||
{ "packed-switch", "switch 2" },
|
||||
{ "sparse-switch", "switch 2" },
|
||||
{ "invoke-direct", "call 2 1" },
|
||||
{ "invoke-direct/range", "call 2 1" },
|
||||
{ "invoke-interface", "call 2 1" },
|
||||
{ "invoke-static", "call 2 1" },
|
||||
{ "invoke-super", "call super 2 1" },
|
||||
{ "invoke-super/range", "call super 2 1" },
|
||||
{ "invoke-polymorphic", "call polymorphic 2 1" },
|
||||
{ "invoke-virtual/range", "call 2 1"},
|
||||
{ "invoke-virtual", "call 2 1"},
|
||||
{ "+invoke-virtual-quick", "call 2 1"},
|
||||
{ "+invoke-interface/range", "call 2 1"},
|
||||
{ "invoke-interface/range", "call 2 1"},
|
||||
{ "div-float/2addr", "1 /= (float) 2"},
|
||||
{ "div-double/2addr", "1 /= (double) 2"},
|
||||
{ "div-double", "1 = (double) 2 / 3"},
|
||||
{ "div-float", "1 = 2 / 3"},
|
||||
{ "div-int/lit8", "1 = 2 / 3"},
|
||||
{ "div-int/lit16", "1 = 2 / 3"},
|
||||
{ "div-int/2addr", "1 /= 2"},
|
||||
{ "div-int", "1 = (int)(2 / 3)"},
|
||||
{ "goto/16", "goto 1"},
|
||||
{ "goto/32", "goto 1"},
|
||||
{ "or-int", "1 = (int)(2 | 3)"},
|
||||
{ "xor-int", "1 = (int)(2 ^ 3)"},
|
||||
{ "xor-int/2addr", "1 ^= 2"},
|
||||
{ "xor-byte", "1 = (byte)(2 ^ 3)"},
|
||||
{ "xor-short", "1 = (short)(2 ^ 3)"},
|
||||
{ "sub-int", "1 = (int)(2 - 3)"},
|
||||
{ "if-nez", "if (1) goto 2"},
|
||||
{ "if-ltz", "if (1 <=) goto 2"},
|
||||
{ "mul-int", "1 = (int)(2 * 3)"},
|
||||
{ "mul-int/lit8", "1 = (2 * 3)"},
|
||||
{ "check-cast", "if (1 instanceof 2)"},
|
||||
{ "add-int", "1 = (int)(2 + 3)"},
|
||||
{ "add-int/lit8", "1 = 2 + 3"},
|
||||
{ "add-int/lit16", "1 = 2 + 3"},
|
||||
{ "add-int/2addr", "1 += 2"},
|
||||
{ "add-double", "1 = (double)(2 + 3)"},
|
||||
{ "add-double/2addr", "1 += (double)2"},
|
||||
{ "mul-float/2addr", "1 *= 2"},
|
||||
{ "mul-float", "1 = 2 * 3"},
|
||||
{ "xor-long", "1 = (long)(2 ^ 3)"},
|
||||
{ "mul-double", "1 = 2 * 3"},
|
||||
{ "move-wide", "1 = 2"},
|
||||
{ "move-wide/16", "1 = 2"},
|
||||
{ "return-wide", "return (wide) 1"},
|
||||
{ "return-object", "return (object) 1"},
|
||||
// { "sget", "1 = 2[3]"},
|
||||
{ "invoke-virtual/range", "call 2 1" },
|
||||
{ "invoke-virtual", "call 2 1" },
|
||||
{ "+invoke-virtual-quick", "call 2 1" },
|
||||
{ "+invoke-interface/range", "call 2 1" },
|
||||
{ "invoke-interface/range", "call 2 1" },
|
||||
{ "div-float/2addr", "1 /= (float) 2" },
|
||||
{ "div-double/2addr", "1 /= (double) 2" },
|
||||
{ "div-double", "1 = (double) 2 / 3" },
|
||||
{ "div-float", "1 = 2 / 3" },
|
||||
{ "div-int/lit8", "1 = 2 / 3" },
|
||||
{ "div-int/lit16", "1 = 2 / 3" },
|
||||
{ "div-int/2addr", "1 /= 2" },
|
||||
{ "div-int", "1 = (int)(2 / 3)" },
|
||||
{ "goto/16", "goto 1" },
|
||||
{ "goto/32", "goto 1" },
|
||||
{ "or-int", "1 = (int)(2 | 3)" },
|
||||
{ "xor-int", "1 = (int)(2 ^ 3)" },
|
||||
{ "xor-int/2addr", "1 ^= 2" },
|
||||
{ "xor-byte", "1 = (byte)(2 ^ 3)" },
|
||||
{ "xor-short", "1 = (short)(2 ^ 3)" },
|
||||
{ "sub-int", "1 = (int)(2 - 3)" },
|
||||
{ "if-nez", "if (1) goto 2" },
|
||||
{ "if-ltz", "if (1 <=) goto 2" },
|
||||
{ "mul-int", "1 = (int)(2 * 3)" },
|
||||
{ "mul-int/lit8", "1 = (2 * 3)" },
|
||||
{ "check-cast", "if (1 instanceof 2)" },
|
||||
{ "add-int", "1 = (int)(2 + 3)" },
|
||||
{ "add-int/lit8", "1 = 2 + 3" },
|
||||
{ "add-int/lit16", "1 = 2 + 3" },
|
||||
{ "add-int/2addr", "1 += 2" },
|
||||
{ "add-double", "1 = (double)(2 + 3)" },
|
||||
{ "add-double/2addr", "1 += (double)2" },
|
||||
{ "mul-float/2addr", "1 *= 2" },
|
||||
{ "mul-float", "1 = 2 * 3" },
|
||||
{ "xor-long", "1 = (long)(2 ^ 3)" },
|
||||
{ "mul-double", "1 = 2 * 3" },
|
||||
{ "move-wide", "1 = 2" },
|
||||
{ "move-wide/16", "1 = 2" },
|
||||
{ "return-wide", "return (wide) 1" },
|
||||
{ "return-object", "return (object) 1" },
|
||||
// { "sget", "1 = 2[3]" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
{ "lsr", "2 >>= 1", 2},
|
||||
{ "lsl", "2 <<= 1", 2},
|
||||
{ "andi", "2 &= 1", 2},
|
||||
{ "nop", ""},
|
||||
{ "nop", "" },
|
||||
//
|
||||
{ NULL }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,111 +16,111 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{ "add", "B += A"},
|
||||
{ "addc", "B += A + t"},
|
||||
{ "addv", "B += A; t = int_overflow (B)"},
|
||||
{ "and", "B &= A"},
|
||||
{ "and.b", "B &= A"},
|
||||
{ "bf", "if (!t) goto A"},
|
||||
{ "bf.s", "if (!t) goto A"},
|
||||
{ "bra", "goto A"},
|
||||
{ "brk", "_break_exception ()"},
|
||||
{ "bsr", "A ()"},
|
||||
{ "bsrf", "A ()"},
|
||||
{ "bt", "if (t) goto A"},
|
||||
{ "bt.s", "if (t) goto A"},
|
||||
{ "clrmac", "_clrmac ()"},
|
||||
{ "clrs", "_clrs ()"},
|
||||
{ "clrt", "_clrt ()"},
|
||||
{ "cmp/eq", "t = B == A ? 1 : 0"},
|
||||
{ "cmp/ge", "t = B >= A ? 1 : 0"},
|
||||
{ "cmp/gt", "t = B > A ? 1 : 0"},
|
||||
{ "cmp/hi", "t = (unsigned) B > (unsigned) A ? 1 : 0"},
|
||||
{ "cmp/hs", "t = (unsigned) B >= (unsigned) A ? 1 : 0"},
|
||||
{ "cmp/pl", "t = A > 0 ? 1 : 0"},
|
||||
{ "cmp/pz", "t = A >= 0 ? 1 : 0"},
|
||||
{ "cmp/str", "t = A ^ B ? 1 : 0"},
|
||||
{ "div1", "B /= A"},
|
||||
{ "dmuls.l", "mac = B * A"},
|
||||
{ "dmulu.l", "mac = (unsigned) B * (unsigned) A"},
|
||||
{ "dt", "A--; t = !A ? 1 : 0"},
|
||||
{ "exts.b", "B = (int) A"},
|
||||
{ "extu.b", "B = (unsigned int) A"},
|
||||
{ "exts.w", "B = (int) A"},
|
||||
{ "extu.w", "B = (unsigned int) A"},
|
||||
{ "fabs", "A = abs (A)"},
|
||||
{ "fadd", "B += A"},
|
||||
{ "fcmp/eq", "t = B == A ? 1 : 0"},
|
||||
{ "fcmp/gt", "t = B > A ? 1 : 0"},
|
||||
{ "fcnvds", "B = A"},
|
||||
{ "fdiv", "B /= A"},
|
||||
{ "flds", "B = A"},
|
||||
{ "fldi0", "A = 0.0f"},
|
||||
{ "fldi1", "A = 1.0f"},
|
||||
{ "float", "B = A"},
|
||||
{ "fmac", "C += A * B"},
|
||||
{ "fmov", "B = A"},
|
||||
{ "fmov.s", "B = A"},
|
||||
{ "fmul", "B *= A"},
|
||||
{ "fneg", "A = -A"},
|
||||
{ "fsqrt", "A = sqrt (A)"},
|
||||
{ "fsts", "B = A"},
|
||||
{ "fsub", "B -= A"},
|
||||
{ "ftrc", "B = trunc (A)"},
|
||||
{ "ftrv", "B *= A"},
|
||||
{ "jmp", "goto A"},
|
||||
{ "jsr", "A ()"},
|
||||
{ "ldr", "B = A"},
|
||||
{ "ldr.l", "B = A"},
|
||||
{ "lds", "B = A"},
|
||||
{ "lds.l", "B = A"},
|
||||
{ "mov", "B = A"},
|
||||
{ "mov.b", "B = A"},
|
||||
{ "mov.l", "B = A"},
|
||||
{ "mov.w", "B = A"},
|
||||
{ "movca.l", "B = A"},
|
||||
{ "movt", "A = t"},
|
||||
{ "muls.w", "macl = A * B"},
|
||||
{ "mulu.w", "macl = (unsigned) A * (unsigned) B"},
|
||||
{ "neg", "A = -A"},
|
||||
{ "negc", "A = (-A) - t"},
|
||||
{ "nop", ""},
|
||||
{ "not", "A = !A"},
|
||||
{ "or", "B |= A"},
|
||||
{ "rotcl", "t = A & 0x80000000 ? 0 : 1; A = (A << 1) | t"},
|
||||
{ "rotl", "A = (A << 1) | (A >> 31)"},
|
||||
{ "rotr", "A = (A << 31) | (A >> 1)"},
|
||||
{ "rte", "_rte ()"},
|
||||
{ "rts", "return"},
|
||||
{ "sets", "s = 1"},
|
||||
{ "sett", "t = 1"},
|
||||
{ "shad", "B = A >= 0 ? B << A : B >> (31 - A)"},
|
||||
{ "shal", "A <<= 1"},
|
||||
{ "shar", "A >>= 1"},
|
||||
{ "shld", "B = A >= 0 ? B << A : B >> (31 - A)"},
|
||||
{ "shll", "A <<= 1"},
|
||||
{ "shll2", "A <<= 2"},
|
||||
{ "shll8", "A <<= 8"},
|
||||
{ "shll16", "A <<= 16"},
|
||||
{ "shlr", "A >>= 1"},
|
||||
{ "shlr2", "A >>= 2"},
|
||||
{ "shlr8", "A >>= 8"},
|
||||
{ "shlr16", "A >>= 16"},
|
||||
{ "sleep", "_halt ()"},
|
||||
{ "stc", "B = A"},
|
||||
{ "stc.l", "B = A"},
|
||||
{ "sts", "B = A"},
|
||||
{ "sts.l", "B = A"},
|
||||
{ "sub", "B -= A"},
|
||||
{ "subc", "B -= A - t"},
|
||||
{ "subv", "B -= A; t = int_underflow (B)"},
|
||||
{ "swap.b", "swap_byte (B, A)"},
|
||||
{ "swap.w", "swap_word (B, A)"},
|
||||
{ "tas.b", "test_and_set (A)"},
|
||||
{ "trapa", "trap (A)"},
|
||||
{ "tst", "t = B & A ? 0 : 1"},
|
||||
{ "xor", "B ^= A"},
|
||||
{ "xor.b", "B ^= A"},
|
||||
{ "add", "B += A" },
|
||||
{ "addc", "B += A + t" },
|
||||
{ "addv", "B += A; t = int_overflow (B)" },
|
||||
{ "and", "B &= A" },
|
||||
{ "and.b", "B &= A" },
|
||||
{ "bf", "if (!t) goto A" },
|
||||
{ "bf.s", "if (!t) goto A" },
|
||||
{ "bra", "goto A" },
|
||||
{ "brk", "_break_exception ()" },
|
||||
{ "bsr", "A ()" },
|
||||
{ "bsrf", "A ()" },
|
||||
{ "bt", "if (t) goto A" },
|
||||
{ "bt.s", "if (t) goto A" },
|
||||
{ "clrmac", "_clrmac ()" },
|
||||
{ "clrs", "_clrs ()" },
|
||||
{ "clrt", "_clrt ()" },
|
||||
{ "cmp/eq", "t = B == A ? 1 : 0" },
|
||||
{ "cmp/ge", "t = B >= A ? 1 : 0" },
|
||||
{ "cmp/gt", "t = B > A ? 1 : 0" },
|
||||
{ "cmp/hi", "t = (unsigned) B > (unsigned) A ? 1 : 0" },
|
||||
{ "cmp/hs", "t = (unsigned) B >= (unsigned) A ? 1 : 0" },
|
||||
{ "cmp/pl", "t = A > 0 ? 1 : 0" },
|
||||
{ "cmp/pz", "t = A >= 0 ? 1 : 0" },
|
||||
{ "cmp/str", "t = A ^ B ? 1 : 0" },
|
||||
{ "div1", "B /= A" },
|
||||
{ "dmuls.l", "mac = B * A" },
|
||||
{ "dmulu.l", "mac = (unsigned) B * (unsigned) A" },
|
||||
{ "dt", "A--; t = !A ? 1 : 0" },
|
||||
{ "exts.b", "B = (int) A" },
|
||||
{ "extu.b", "B = (unsigned int) A" },
|
||||
{ "exts.w", "B = (int) A" },
|
||||
{ "extu.w", "B = (unsigned int) A" },
|
||||
{ "fabs", "A = abs (A)" },
|
||||
{ "fadd", "B += A" },
|
||||
{ "fcmp/eq", "t = B == A ? 1 : 0" },
|
||||
{ "fcmp/gt", "t = B > A ? 1 : 0" },
|
||||
{ "fcnvds", "B = A" },
|
||||
{ "fdiv", "B /= A" },
|
||||
{ "flds", "B = A" },
|
||||
{ "fldi0", "A = 0.0f" },
|
||||
{ "fldi1", "A = 1.0f" },
|
||||
{ "float", "B = A" },
|
||||
{ "fmac", "C += A * B" },
|
||||
{ "fmov", "B = A" },
|
||||
{ "fmov.s", "B = A" },
|
||||
{ "fmul", "B *= A" },
|
||||
{ "fneg", "A = -A" },
|
||||
{ "fsqrt", "A = sqrt (A)" },
|
||||
{ "fsts", "B = A" },
|
||||
{ "fsub", "B -= A" },
|
||||
{ "ftrc", "B = trunc (A)" },
|
||||
{ "ftrv", "B *= A" },
|
||||
{ "jmp", "goto A" },
|
||||
{ "jsr", "A ()" },
|
||||
{ "ldr", "B = A" },
|
||||
{ "ldr.l", "B = A" },
|
||||
{ "lds", "B = A" },
|
||||
{ "lds.l", "B = A" },
|
||||
{ "mov", "B = A" },
|
||||
{ "mov.b", "B = A" },
|
||||
{ "mov.l", "B = A" },
|
||||
{ "mov.w", "B = A" },
|
||||
{ "movca.l", "B = A" },
|
||||
{ "movt", "A = t" },
|
||||
{ "muls.w", "macl = A * B" },
|
||||
{ "mulu.w", "macl = (unsigned) A * (unsigned) B" },
|
||||
{ "neg", "A = -A" },
|
||||
{ "negc", "A = (-A) - t" },
|
||||
{ "nop", "" },
|
||||
{ "not", "A = !A" },
|
||||
{ "or", "B |= A" },
|
||||
{ "rotcl", "t = A & 0x80000000 ? 0 : 1; A = (A << 1) | t" },
|
||||
{ "rotl", "A = (A << 1) | (A >> 31)" },
|
||||
{ "rotr", "A = (A << 31) | (A >> 1)" },
|
||||
{ "rte", "_rte ()" },
|
||||
{ "rts", "return" },
|
||||
{ "sets", "s = 1" },
|
||||
{ "sett", "t = 1" },
|
||||
{ "shad", "B = A >= 0 ? B << A : B >> (31 - A)" },
|
||||
{ "shal", "A <<= 1" },
|
||||
{ "shar", "A >>= 1" },
|
||||
{ "shld", "B = A >= 0 ? B << A : B >> (31 - A)" },
|
||||
{ "shll", "A <<= 1" },
|
||||
{ "shll2", "A <<= 2" },
|
||||
{ "shll8", "A <<= 8" },
|
||||
{ "shll16", "A <<= 16" },
|
||||
{ "shlr", "A >>= 1" },
|
||||
{ "shlr2", "A >>= 2" },
|
||||
{ "shlr8", "A >>= 8" },
|
||||
{ "shlr16", "A >>= 16" },
|
||||
{ "sleep", "_halt ()" },
|
||||
{ "stc", "B = A" },
|
||||
{ "stc.l", "B = A" },
|
||||
{ "sts", "B = A" },
|
||||
{ "sts.l", "B = A" },
|
||||
{ "sub", "B -= A" },
|
||||
{ "subc", "B -= A - t" },
|
||||
{ "subv", "B -= A; t = int_underflow (B)" },
|
||||
{ "swap.b", "swap_byte (B, A)" },
|
||||
{ "swap.w", "swap_word (B, A)" },
|
||||
{ "tas.b", "test_and_set (A)" },
|
||||
{ "trapa", "trap (A)" },
|
||||
{ "tst", "t = B & A ? 0 : 1" },
|
||||
{ "xor", "B ^= A" },
|
||||
{ "xor.b", "B ^= A" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,84 +14,84 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{3, "add", "3 = 1 + 2"}, // add b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "addu", "3 = 1 + 2"},
|
||||
{3, "addw", "3 = 1 + 2"},
|
||||
{3, "addaw", "3 = 1 + 2"},
|
||||
{3, "addab", "3 = 1 + 2"},
|
||||
{3, "addah", "3 = 1 + 2"},
|
||||
{2, "addk", "2 += 1"}, // addk 123, b0 -> b0 += 123
|
||||
{3, "sadd", "3 = 1 + 2"}, // sadd b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "sadd2", "3 = 1 + 2"}, // sadd2 b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "sub", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "subu", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "sub2", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "subab", "3 = 1 - 2"}, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "ssub", "3 = 1 - 2"}, // ssub b12, b1, b9 -> b9 = b12 - b1
|
||||
{2, "mv", "2 = 1"},
|
||||
{2, "mvk", "2 = 1"}, // mvk 1, a0 -> a0 = 1
|
||||
{2, "mvklh", "2 = (half) 1"},// mvk 1, a0 -> a0 = 1
|
||||
{3, "band", "3 = 1 & 2"}, //
|
||||
{1, "zero", "1 = zero"},
|
||||
{3, "andn", "4 = 1 ~ 2"}, //
|
||||
{3, "cmpgtu", "3 = 1 cmpgtu 2"}, //
|
||||
{3, "cmpeq", "3 = 1 == 2"}, //
|
||||
{3, "cmpge", "3 = 1 >= 2"}, //
|
||||
{3, "cmplt", "3 = 1 <= 2"}, //
|
||||
{3, "smpylh", "3 = 1 * 2"}, //
|
||||
{3, "smpy", "3 = 1 * 2"}, //
|
||||
{3, "smpyh", "3 = 1 * 2"}, //
|
||||
{3, "mpyu4", "3 = 1 * 2"}, //
|
||||
{3, "avg2", "3 = 1 avg 2"}, //
|
||||
{3, "pack2", "3 = 1 pack 2"}, //
|
||||
{3, "smpy", "3 = 1 * 2"}, //
|
||||
{3, "max2", "3 = max(1, 2)"}, //
|
||||
{3, "mpy", "3 = 1 * 2"}, //
|
||||
{3, "mpy2", "3 = 1 * 2"}, //
|
||||
{3, "mpyu", "3 = 1 * 2"}, //
|
||||
{3, "mpyh", "3 = 1 * 2"}, //
|
||||
{3, "mpyhl", "3 = 1 * 2"}, //
|
||||
{3, "mpyhl", "3 = 1 * 2"}, //
|
||||
{3, "mpylh", "3 = 1 * 2"}, //
|
||||
{3, "mpysu", "3 = 1 * 2"}, //
|
||||
{3, "smpyhl", "3 = 1 * 2"}, //
|
||||
{3, "mpyhlu", "3 = 1 * 2"}, //
|
||||
{3, "mpyhslu", "3 = 1 * 2"}, //
|
||||
{3, "mpyluhs", "3 = 1 * 2"}, //
|
||||
{3, "mpyhi", "3 = 1 * 2"}, //
|
||||
{3, "mpyhu", "3 = 1 * 2"}, //
|
||||
{3, "mpyhus", "3 = 1 * 2"}, //
|
||||
{3, "mpyhsu", "3 = 1 * 2"}, //
|
||||
{3, "mpyhul", "3 = 1 * 2"}, //
|
||||
{3, "mpyhuls", "3 = 1 * 2"}, //
|
||||
{3, "mpyhir", "3 = 1 * 2"}, //
|
||||
{3, "mpyli", "3 = 1 * 2"}, //
|
||||
{3, "mpylir", "3 = 1 * 2"}, //
|
||||
{4, "ext", "4 = 2 ext 1 .. 3"}, //
|
||||
{4, "extu", "4 = 2 ext 1 .. 3"}, //
|
||||
{0, "reti", "ret"}, // reti -> ret
|
||||
{2, "lddw", "2 = (word)1"}, // lddw
|
||||
{2, "ldhu", "2 = (half)1"}, // ldhu
|
||||
{2, "ldb", "2 = (byte)1"}, // ldb
|
||||
{2, "ldbu", "2 = (byte)1"}, // ldbu
|
||||
{2, "ldndw", "2 = 1"}, // ldbu
|
||||
{2, "ldnw", "2 = 1"}, // ldbu
|
||||
{2, "ldw", "2 = (word)1"}, // ldw
|
||||
{2, "ldh", "2 = (half)1"}, // ldw
|
||||
{2, "stb", "2 = (byte)1"}, // stb
|
||||
{2, "stw", "2 = (word)1"}, // stw
|
||||
{2, "sth", "2 = (half)1"}, // stw
|
||||
{2, "stnw", "2 = (word)1"}, // stw
|
||||
{2, "stdw", "2 = (half)1"}, // stw
|
||||
{2, "stndw", "2 = (half)1"}, // stw
|
||||
{3, "or", "3 = 2 | 1"},
|
||||
{3, "shl", "3 = (2 & Oxffffff) << 1"},
|
||||
{3, "shr", "3 = (2 & Oxffffff) << 1"},
|
||||
{3, "shlmb", "3 = << 1"},
|
||||
{4, "set", "4 = 2 .bitset 1 .. 2"}, // set a29,0x1a, 1, a19
|
||||
{4, "clr", "4 = 2 .bitclear 1 .. 2"}, // clr a29,0x1a, 1, a19
|
||||
{0, "invalid", ""},
|
||||
{0, "nop", ""},
|
||||
{3, "add", "3 = 1 + 2" }, // add b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "addu", "3 = 1 + 2" },
|
||||
{3, "addw", "3 = 1 + 2" },
|
||||
{3, "addaw", "3 = 1 + 2" },
|
||||
{3, "addab", "3 = 1 + 2" },
|
||||
{3, "addah", "3 = 1 + 2" },
|
||||
{2, "addk", "2 += 1" }, // addk 123, b0 -> b0 += 123
|
||||
{3, "sadd", "3 = 1 + 2" }, // sadd b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "sadd2", "3 = 1 + 2" }, // sadd2 b12, b1, b9 -> b9 = b12 + b1
|
||||
{3, "sub", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "subu", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "sub2", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "subab", "3 = 1 - 2" }, // sub b12, b1, b9 -> b9 = b12 - b1
|
||||
{3, "ssub", "3 = 1 - 2" }, // ssub b12, b1, b9 -> b9 = b12 - b1
|
||||
{2, "mv", "2 = 1" },
|
||||
{2, "mvk", "2 = 1" }, // mvk 1, a0 -> a0 = 1
|
||||
{2, "mvklh", "2 = (half) 1" },// mvk 1, a0 -> a0 = 1
|
||||
{3, "band", "3 = 1 & 2" }, //
|
||||
{1, "zero", "1 = zero" },
|
||||
{3, "andn", "4 = 1 ~ 2" }, //
|
||||
{3, "cmpgtu", "3 = 1 cmpgtu 2" }, //
|
||||
{3, "cmpeq", "3 = 1 == 2" }, //
|
||||
{3, "cmpge", "3 = 1 >= 2" }, //
|
||||
{3, "cmplt", "3 = 1 <= 2" }, //
|
||||
{3, "smpylh", "3 = 1 * 2" }, //
|
||||
{3, "smpy", "3 = 1 * 2" }, //
|
||||
{3, "smpyh", "3 = 1 * 2" }, //
|
||||
{3, "mpyu4", "3 = 1 * 2" }, //
|
||||
{3, "avg2", "3 = 1 avg 2" }, //
|
||||
{3, "pack2", "3 = 1 pack 2" }, //
|
||||
{3, "smpy", "3 = 1 * 2" }, //
|
||||
{3, "max2", "3 = max(1, 2)" }, //
|
||||
{3, "mpy", "3 = 1 * 2" }, //
|
||||
{3, "mpy2", "3 = 1 * 2" }, //
|
||||
{3, "mpyu", "3 = 1 * 2" }, //
|
||||
{3, "mpyh", "3 = 1 * 2" }, //
|
||||
{3, "mpyhl", "3 = 1 * 2" }, //
|
||||
{3, "mpyhl", "3 = 1 * 2" }, //
|
||||
{3, "mpylh", "3 = 1 * 2" }, //
|
||||
{3, "mpysu", "3 = 1 * 2" }, //
|
||||
{3, "smpyhl", "3 = 1 * 2" }, //
|
||||
{3, "mpyhlu", "3 = 1 * 2" }, //
|
||||
{3, "mpyhslu", "3 = 1 * 2" }, //
|
||||
{3, "mpyluhs", "3 = 1 * 2" }, //
|
||||
{3, "mpyhi", "3 = 1 * 2" }, //
|
||||
{3, "mpyhu", "3 = 1 * 2" }, //
|
||||
{3, "mpyhus", "3 = 1 * 2" }, //
|
||||
{3, "mpyhsu", "3 = 1 * 2" }, //
|
||||
{3, "mpyhul", "3 = 1 * 2" }, //
|
||||
{3, "mpyhuls", "3 = 1 * 2" }, //
|
||||
{3, "mpyhir", "3 = 1 * 2" }, //
|
||||
{3, "mpyli", "3 = 1 * 2" }, //
|
||||
{3, "mpylir", "3 = 1 * 2" }, //
|
||||
{4, "ext", "4 = 2 ext 1 .. 3" }, //
|
||||
{4, "extu", "4 = 2 ext 1 .. 3" }, //
|
||||
{0, "reti", "ret" }, // reti -> ret
|
||||
{2, "lddw", "2 = (word)1" }, // lddw
|
||||
{2, "ldhu", "2 = (half)1" }, // ldhu
|
||||
{2, "ldb", "2 = (byte)1" }, // ldb
|
||||
{2, "ldbu", "2 = (byte)1" }, // ldbu
|
||||
{2, "ldndw", "2 = 1" }, // ldbu
|
||||
{2, "ldnw", "2 = 1" }, // ldbu
|
||||
{2, "ldw", "2 = (word)1" }, // ldw
|
||||
{2, "ldh", "2 = (half)1" }, // ldw
|
||||
{2, "stb", "2 = (byte)1" }, // stb
|
||||
{2, "stw", "2 = (word)1" }, // stw
|
||||
{2, "sth", "2 = (half)1" }, // stw
|
||||
{2, "stnw", "2 = (word)1" }, // stw
|
||||
{2, "stdw", "2 = (half)1" }, // stw
|
||||
{2, "stndw", "2 = (half)1" }, // stw
|
||||
{3, "or", "3 = 2 | 1" },
|
||||
{3, "shl", "3 = (2 & Oxffffff) << 1" },
|
||||
{3, "shr", "3 = (2 & Oxffffff) << 1" },
|
||||
{3, "shlmb", "3 = << 1" },
|
||||
{4, "set", "4 = 2 .bitset 1 .. 2" }, // set a29,0x1a, 1, a19
|
||||
{4, "clr", "4 = 2 .bitclear 1 .. 2" }, // clr a29,0x1a, 1, a19
|
||||
{0, "invalid", "" },
|
||||
{0, "nop", "" },
|
||||
{0, NULL}
|
||||
};
|
||||
if (!newstr) {
|
||||
|
|
|
|||
|
|
@ -14,55 +14,55 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{0, "ei", "enable-interrupts"},
|
||||
{0, "di", "disable-interrupts"},
|
||||
{0, "reti", "ret"},
|
||||
{2, "ld.hu", "2 = 1"},
|
||||
{1, "zxb", "1 = O"},
|
||||
{1, "zxh", "1 = O"},
|
||||
{1, "zxw", "1 = O"},
|
||||
{2, "set1", "2 |= (I << 2)"},
|
||||
{2, "clr1", "2 &= ~(I << 2)"},
|
||||
{2, "sld.w", "2 = (word) 1"},
|
||||
{2, "sld.h", "2 = (half) 1"},
|
||||
{2, "sld.b", "2 = (byte) 1"},
|
||||
{2, "ld.bu", "2 = 1"},
|
||||
{2, "ld.w", "2 = (word) 1"},
|
||||
{2, "ld.h", "2 = (half) 1"},
|
||||
{2, "ld.b", "2 = (byte) 1"},
|
||||
{2, "st.h", "2 = (half) 1"},
|
||||
{2, "st.w", "2 = (word) 1"},
|
||||
{2, "st.b", "2 = (byte) 1"},
|
||||
{2, "sst.w", "2 = (word) 1"},
|
||||
{2, "sst.h", "2 = (half) 1"},
|
||||
{2, "sst.b", "2 = (byte) 1"},
|
||||
{2, "stsr", "2 = 1"},
|
||||
{2, "ldsr", "2 = 1"},
|
||||
{2, "and", "3 = 2 & 1"},
|
||||
{3, "andi", "3 = 2 & 1"},
|
||||
{2, "add", "2 += 1"},
|
||||
{3, "addi", "3 = 2 + 1"},
|
||||
{2, "sub", "2 -= 1"},
|
||||
{2, "divh", "2 /= 1"},
|
||||
{3, "divh", "3 = 2 / 1"},
|
||||
{2, "mulh", "2 *= 1"},
|
||||
{3, "mul", "3 = 2 * 1"},
|
||||
{3, "mulf.s", "3 = 2 * 1"},
|
||||
{2, "shl", "2 <<= 1"},
|
||||
{2, "shr", "2 >>= 1"},
|
||||
{2, "xor", "2 ^= 1"},
|
||||
{3, "xori", "3 = 1 ^ 2"},
|
||||
{2, "tst", "2 == 1"},
|
||||
{2, "tst1", "2 == 1"},
|
||||
{1, "jr", "goto 1"},
|
||||
{1, "jmp", "goto 1"},
|
||||
{2, "cmp", "2 == 1"},
|
||||
{4, "cmov", "4 == 1 ? 2 : 3"},
|
||||
{2, "mov", "2 = 1"},
|
||||
{3, "movhi", "3 = (1 << XX) + 2"},
|
||||
{3, "movea", "3 = 1 & 2"},
|
||||
{3, "ori", "3 = 1 | 2"},
|
||||
{2, "jarl", "call 1 # 2"},
|
||||
{0, "ei", "enable-interrupts" },
|
||||
{0, "di", "disable-interrupts" },
|
||||
{0, "reti", "ret" },
|
||||
{2, "ld.hu", "2 = 1" },
|
||||
{1, "zxb", "1 = O" },
|
||||
{1, "zxh", "1 = O" },
|
||||
{1, "zxw", "1 = O" },
|
||||
{2, "set1", "2 |= (I << 2)" },
|
||||
{2, "clr1", "2 &= ~(I << 2)" },
|
||||
{2, "sld.w", "2 = (word) 1" },
|
||||
{2, "sld.h", "2 = (half) 1" },
|
||||
{2, "sld.b", "2 = (byte) 1" },
|
||||
{2, "ld.bu", "2 = 1" },
|
||||
{2, "ld.w", "2 = (word) 1" },
|
||||
{2, "ld.h", "2 = (half) 1" },
|
||||
{2, "ld.b", "2 = (byte) 1" },
|
||||
{2, "st.h", "2 = (half) 1" },
|
||||
{2, "st.w", "2 = (word) 1" },
|
||||
{2, "st.b", "2 = (byte) 1" },
|
||||
{2, "sst.w", "2 = (word) 1" },
|
||||
{2, "sst.h", "2 = (half) 1" },
|
||||
{2, "sst.b", "2 = (byte) 1" },
|
||||
{2, "stsr", "2 = 1" },
|
||||
{2, "ldsr", "2 = 1" },
|
||||
{2, "and", "3 = 2 & 1" },
|
||||
{3, "andi", "3 = 2 & 1" },
|
||||
{2, "add", "2 += 1" },
|
||||
{3, "addi", "3 = 2 + 1" },
|
||||
{2, "sub", "2 -= 1" },
|
||||
{2, "divh", "2 /= 1" },
|
||||
{3, "divh", "3 = 2 / 1" },
|
||||
{2, "mulh", "2 *= 1" },
|
||||
{3, "mul", "3 = 2 * 1" },
|
||||
{3, "mulf.s", "3 = 2 * 1" },
|
||||
{2, "shl", "2 <<= 1" },
|
||||
{2, "shr", "2 >>= 1" },
|
||||
{2, "xor", "2 ^= 1" },
|
||||
{3, "xori", "3 = 1 ^ 2" },
|
||||
{2, "tst", "2 == 1" },
|
||||
{2, "tst1", "2 == 1" },
|
||||
{1, "jr", "goto 1" },
|
||||
{1, "jmp", "goto 1" },
|
||||
{2, "cmp", "2 == 1" },
|
||||
{4, "cmov", "4 == 1 ? 2 : 3" },
|
||||
{2, "mov", "2 = 1" },
|
||||
{3, "movhi", "3 = (1 << XX) + 2" },
|
||||
{3, "movea", "3 = 1 & 2" },
|
||||
{3, "ori", "3 = 1 | 2" },
|
||||
{2, "jarl", "call 1 # 2" },
|
||||
{0, NULL}
|
||||
};
|
||||
if (!newstr) {
|
||||
|
|
|
|||
|
|
@ -11,29 +11,29 @@ static int replace(int argc, const char *argv[], char *newstr) {
|
|||
const char *op;
|
||||
const char *str;
|
||||
} ops[] = {
|
||||
{ "adc", "1 = 1 + 2"},
|
||||
{ "add", "1 = 1 + 2"},
|
||||
{ "and", "1 = 1 & 2"},
|
||||
{ "cpl", "1 = ~1"},
|
||||
{ "ex", "swap(1, 2)"},
|
||||
{ "in", "1 = [2]"},
|
||||
{ "jp", "goto [1]"},
|
||||
{ "jp", "goto 1"},
|
||||
{ "jr", "goto +1"},
|
||||
{ "ld", "1 = 2"},
|
||||
{ "ldd", "1 = 2--"},
|
||||
{ "neg", "1 = -1"},
|
||||
{ "nop", ""},
|
||||
{ "or", "1 = 1 | 2"},
|
||||
{ "pop", "pop 1"},
|
||||
{ "push", "push 1"},
|
||||
{ "rr", "1 = 1 << 2"},
|
||||
{ "sbc", "1 = 1 - 2"},
|
||||
{ "sla", "1 = 1 << 2"},
|
||||
{ "sra", "1 = 1 >> 2"},
|
||||
{ "srl", "1 = 1 >> 2"},
|
||||
{ "sub", "1 = 1 - 2"},
|
||||
{ "xor", "1 = 1 ^ 2"},
|
||||
{ "adc", "1 = 1 + 2" },
|
||||
{ "add", "1 = 1 + 2" },
|
||||
{ "and", "1 = 1 & 2" },
|
||||
{ "cpl", "1 = ~1" },
|
||||
{ "ex", "swap(1, 2)" },
|
||||
{ "in", "1 = [2]" },
|
||||
{ "jp", "goto [1]" },
|
||||
{ "jp", "goto 1" },
|
||||
{ "jr", "goto +1" },
|
||||
{ "ld", "1 = 2" },
|
||||
{ "ldd", "1 = 2--" },
|
||||
{ "neg", "1 = -1" },
|
||||
{ "nop", "" },
|
||||
{ "or", "1 = 1 | 2" },
|
||||
{ "pop", "pop 1" },
|
||||
{ "push", "push 1" },
|
||||
{ "rr", "1 = 1 << 2" },
|
||||
{ "sbc", "1 = 1 - 2" },
|
||||
{ "sla", "1 = 1 << 2" },
|
||||
{ "sra", "1 = 1 >> 2" },
|
||||
{ "srl", "1 = 1 >> 2" },
|
||||
{ "sub", "1 = 1 - 2" },
|
||||
{ "xor", "1 = 1 ^ 2" },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
#!/bin/sh
|
||||
grep '{ "'|tr '{",}' ' ' |sed -e 's,NULL,,g' | awk '{ print $1"="$2","$3","$4","$5}'
|
||||
grep '{ "'|tr '{ ",}' ' ' |sed -e 's,NULL,,g' | awk '{ print $1"="$2","$3","$4","$5}'
|
||||
|
|
|
|||
|
|
@ -11,67 +11,67 @@ RSyscallPort sysport_x86[] = {
|
|||
RSyscallPort sysport_avr[] = {
|
||||
{ 0x3f, "SREG: flags" },
|
||||
{ 0x3e, "SPH: Stack higher bits SP8-SP10" },
|
||||
{ 0x3d, "SPL: Stack lower bits SP0-SP7"},
|
||||
{ 0x3c, "OCR0: Timer/Counter0 Output Compare Register."},
|
||||
{ 0x3d, "SPL: Stack lower bits SP0-SP7" },
|
||||
{ 0x3c, "OCR0: Timer/Counter0 Output Compare Register." },
|
||||
{ 0x3b, "GICR: General Interrupt Control Register" },
|
||||
{ 0x3a, "GIFR: General Interrupt Flag Register"},
|
||||
{ 0x39, "TIMSK: Timer/Counter Interrupt Mask"},
|
||||
{ 0x38, "TIFR: Timer/Counter Interrupt Flag Register"},
|
||||
{ 0x37, "SPMCR: Store Program Memory Control Register"},
|
||||
{ 0x36, "TWCR: I2C (Two-wire) Control Register"},
|
||||
{ 0x35, "MCUCR: MCU (Power Management) Control Register"},
|
||||
{ 0x3a, "GIFR: General Interrupt Flag Register" },
|
||||
{ 0x39, "TIMSK: Timer/Counter Interrupt Mask" },
|
||||
{ 0x38, "TIFR: Timer/Counter Interrupt Flag Register" },
|
||||
{ 0x37, "SPMCR: Store Program Memory Control Register" },
|
||||
{ 0x36, "TWCR: I2C (Two-wire) Control Register" },
|
||||
{ 0x35, "MCUCR: MCU (Power Management) Control Register" },
|
||||
{ 0x34, "MCUCSR: MCU Control and Status Register. Watchdog, Brown-out, Power-on..." },
|
||||
{ 0x33, "TCCR0: Timer/Counter Control Register 0"},
|
||||
{ 0x32, "TCNT0: Timer/Counter Register 0 (8 bits)"},
|
||||
{ 0x31, "OSCCAL: (Internal) Oscillator Calibration Register"},
|
||||
{ 0x30, "SFIOR: Special Function IO Register"},
|
||||
{ 0x2f, "TCCR1A: Timer/Counter Control Register 1A (16 bits). Used for (fast) PWM."},
|
||||
{ 0x2e, "TCCR1B: Timer/Counter Control Register 1B (16 bits). PWM mode select."},
|
||||
{ 0x2d, "TCNT1H: Timer/Counter1 Register High byte."},
|
||||
{ 0x2c, "TCNT1L: Timer/Counter1 Register Low byte."},
|
||||
{ 0x2b, "OCR1AH: Timer/Counter1 Output Compare Register A High byte."},
|
||||
{ 0x2a, "OCR1AL: Timer/Counter1 Output Compare Register A Low byte."},
|
||||
{ 0x29, "OCR1BH: Timer/Counter1 Output Compare Register B High byte."},
|
||||
{ 0x28, "OCR1BL: Timer/Counter1 Output Compare Register B Low byte."},
|
||||
{ 0x27, "ICR1H: Timer/Counter1 Input Capture Register High byte."},
|
||||
{ 0x26, "ICR1L: Timer/Counter1 Input Capture Register Low byte."},
|
||||
{ 0x25, "TCCR2: Timer/Counter2 Control Register (8 bits)."},
|
||||
{ 0x24, "TCNT2: Timer/Counter2 (8 bits)."},
|
||||
{ 0x23, "OCR2: Timer/Counter2 Output Compare Register."},
|
||||
{ 0x22, "ASSR: Asynchronous Operation of the Timer/Counter."},
|
||||
{ 0x21, "WDTCR: Watchdog Timer Control Register."},
|
||||
{ 0x20, "UBRRH, UCSRC: USART Baud Rate Registers, High byte and Control. A.k.a setting serial port speed."},
|
||||
{ 0x1f, "EEARH: EEPROM Address Register High byte."},
|
||||
{ 0x1e, "EEARL: EEPROM Address Register Low byte."},
|
||||
{ 0x1d, "EEDR: EEPROM Data Register."},
|
||||
{ 0x1c, "EECR: EEPROM Control Register."},
|
||||
{ 0x1b, "PORTA: Output pins/pullups address for port A."},
|
||||
{ 0x1a, "DDRA: Data Direction Register for Port A."},
|
||||
{ 0x19, "PINA: Input Pins Address for Port A."},
|
||||
{ 0x18, "PORTB: Output pins/pullups address for port B."},
|
||||
{ 0x17, "DDRB: Data Direction Register for Port B."},
|
||||
{ 0x16, "PINB: Input Pins Address for Port B."},
|
||||
{ 0x15, "PORTC: Output pins/pullups address for port C."},
|
||||
{ 0x14, "DDRC: Data Direction Register for Port C."},
|
||||
{ 0x13, "PINC: Input Pins Address for Port C."},
|
||||
{ 0x12, "PORTD: Output pins/pullups address for port D."},
|
||||
{ 0x11, "DDRD: Data Direction Register for Port D."},
|
||||
{ 0x10, "PIND: Input Pins Address for Port D."},
|
||||
{ 0x0f, "SPDR: SPI Data Register."},
|
||||
{ 0x0e, "SPSR: SPI Status Register."},
|
||||
{ 0x0d, "SPCR: SPI Control Register."},
|
||||
{ 0x0c, "UDR: USART I/O Data Register."},
|
||||
{ 0x0b, "UCSRA: USART Control and Status Register A."},
|
||||
{ 0x0a, "UCSRB: USART Control and Status Register B."},
|
||||
{ 0x09, "UBRRL: USART Baud Rate Registers Low byte. A.k.a setting serial port speed."},
|
||||
{ 0x08, "ACSR: Analog Comparator Control and Status Register."},
|
||||
{ 0x07, "ADMUX: ADC Multiplexer Selection Register."},
|
||||
{ 0x06, "ADCSRA: ADC Control and Status Register A."},
|
||||
{ 0x05, "ADCH: ADC Data Register High byte."},
|
||||
{ 0x04, "ADCL: ADC Data Register Low byte."},
|
||||
{ 0x03, "TWDR: I2C (Two-wire) Serial Interface Data Register."},
|
||||
{ 0x02, "TWAR: I2C (Two-wire) Serial Interface (Slave) Address Register."},
|
||||
{ 0x01, "TWSR: I2C (Two-wire) Serial Interface Status Register."},
|
||||
{ 0x00, "TWBR: I2C (Two-wire) Serial Interface Bit Rate Register."},
|
||||
{ 0x33, "TCCR0: Timer/Counter Control Register 0" },
|
||||
{ 0x32, "TCNT0: Timer/Counter Register 0 (8 bits)" },
|
||||
{ 0x31, "OSCCAL: (Internal) Oscillator Calibration Register" },
|
||||
{ 0x30, "SFIOR: Special Function IO Register" },
|
||||
{ 0x2f, "TCCR1A: Timer/Counter Control Register 1A (16 bits). Used for (fast) PWM." },
|
||||
{ 0x2e, "TCCR1B: Timer/Counter Control Register 1B (16 bits). PWM mode select." },
|
||||
{ 0x2d, "TCNT1H: Timer/Counter1 Register High byte." },
|
||||
{ 0x2c, "TCNT1L: Timer/Counter1 Register Low byte." },
|
||||
{ 0x2b, "OCR1AH: Timer/Counter1 Output Compare Register A High byte." },
|
||||
{ 0x2a, "OCR1AL: Timer/Counter1 Output Compare Register A Low byte." },
|
||||
{ 0x29, "OCR1BH: Timer/Counter1 Output Compare Register B High byte." },
|
||||
{ 0x28, "OCR1BL: Timer/Counter1 Output Compare Register B Low byte." },
|
||||
{ 0x27, "ICR1H: Timer/Counter1 Input Capture Register High byte." },
|
||||
{ 0x26, "ICR1L: Timer/Counter1 Input Capture Register Low byte." },
|
||||
{ 0x25, "TCCR2: Timer/Counter2 Control Register (8 bits)." },
|
||||
{ 0x24, "TCNT2: Timer/Counter2 (8 bits)." },
|
||||
{ 0x23, "OCR2: Timer/Counter2 Output Compare Register." },
|
||||
{ 0x22, "ASSR: Asynchronous Operation of the Timer/Counter." },
|
||||
{ 0x21, "WDTCR: Watchdog Timer Control Register." },
|
||||
{ 0x20, "UBRRH, UCSRC: USART Baud Rate Registers, High byte and Control. A.k.a setting serial port speed." },
|
||||
{ 0x1f, "EEARH: EEPROM Address Register High byte." },
|
||||
{ 0x1e, "EEARL: EEPROM Address Register Low byte." },
|
||||
{ 0x1d, "EEDR: EEPROM Data Register." },
|
||||
{ 0x1c, "EECR: EEPROM Control Register." },
|
||||
{ 0x1b, "PORTA: Output pins/pullups address for port A." },
|
||||
{ 0x1a, "DDRA: Data Direction Register for Port A." },
|
||||
{ 0x19, "PINA: Input Pins Address for Port A." },
|
||||
{ 0x18, "PORTB: Output pins/pullups address for port B." },
|
||||
{ 0x17, "DDRB: Data Direction Register for Port B." },
|
||||
{ 0x16, "PINB: Input Pins Address for Port B." },
|
||||
{ 0x15, "PORTC: Output pins/pullups address for port C." },
|
||||
{ 0x14, "DDRC: Data Direction Register for Port C." },
|
||||
{ 0x13, "PINC: Input Pins Address for Port C." },
|
||||
{ 0x12, "PORTD: Output pins/pullups address for port D." },
|
||||
{ 0x11, "DDRD: Data Direction Register for Port D." },
|
||||
{ 0x10, "PIND: Input Pins Address for Port D." },
|
||||
{ 0x0f, "SPDR: SPI Data Register." },
|
||||
{ 0x0e, "SPSR: SPI Status Register." },
|
||||
{ 0x0d, "SPCR: SPI Control Register." },
|
||||
{ 0x0c, "UDR: USART I/O Data Register." },
|
||||
{ 0x0b, "UCSRA: USART Control and Status Register A." },
|
||||
{ 0x0a, "UCSRB: USART Control and Status Register B." },
|
||||
{ 0x09, "UBRRL: USART Baud Rate Registers Low byte. A.k.a setting serial port speed." },
|
||||
{ 0x08, "ACSR: Analog Comparator Control and Status Register." },
|
||||
{ 0x07, "ADMUX: ADC Multiplexer Selection Register." },
|
||||
{ 0x06, "ADCSRA: ADC Control and Status Register A." },
|
||||
{ 0x05, "ADCH: ADC Data Register High byte." },
|
||||
{ 0x04, "ADCL: ADC Data Register Low byte." },
|
||||
{ 0x03, "TWDR: I2C (Two-wire) Serial Interface Data Register." },
|
||||
{ 0x02, "TWAR: I2C (Two-wire) Serial Interface (Slave) Address Register." },
|
||||
{ 0x01, "TWSR: I2C (Two-wire) Serial Interface Status Register." },
|
||||
{ 0x00, "TWBR: I2C (Two-wire) Serial Interface Bit Rate Register." },
|
||||
{ 0, NULL }
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -668,7 +668,7 @@ static void r_print_format_hex(const RPrint* p, int endian, int mode, const char
|
|||
if (elem > -1) {
|
||||
elem--;
|
||||
}
|
||||
i +=4;
|
||||
i += 4;
|
||||
}
|
||||
p->cb_printf (" ]");
|
||||
}
|
||||
|
|
@ -722,7 +722,7 @@ static void r_print_format_int(const RPrint* p, int endian, int mode, const char
|
|||
if (size == -1) {
|
||||
p->cb_printf ("%"PFMT64d, addr);
|
||||
} else {
|
||||
p->cb_printf ("[ ");
|
||||
p->cb_printf ("[");
|
||||
while (size--) {
|
||||
updateAddr (buf + i, size - i, endian, &addr, NULL);
|
||||
if (elem == -1 || elem == 0) {
|
||||
|
|
@ -955,7 +955,7 @@ static int r_print_format_10bytes(const RPrint* p, int mode, const char *setval,
|
|||
for (; j < 10; j++) {
|
||||
p->cb_printf (", %d", buf[j]);
|
||||
}
|
||||
p->cb_printf ("]");
|
||||
p->cb_printf (" ]");
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -998,7 +998,7 @@ static int r_print_format_hexpairs(const RPrint* p, int endian, int mode, const
|
|||
for (; j < 10; j++) {
|
||||
p->cb_printf (", %d", buf[j]);
|
||||
}
|
||||
p->cb_printf ("]");
|
||||
p->cb_printf (" ]");
|
||||
if (MUSTSEEJSON) {
|
||||
p->cb_printf ("}");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,14 +1,15 @@
|
|||
/* radare - LGPL - Copyright 2007-2020 - pancake, ret2libc */
|
||||
|
||||
#include <r_core.h>
|
||||
#include <r_util/r_graph_drawable.h>
|
||||
|
||||
R_API void r_graph_free_node_info(void *ptr) {
|
||||
if (!ptr) {
|
||||
return;
|
||||
if (ptr) {
|
||||
RGraphNodeInfo *info = ptr;
|
||||
free (info->body);
|
||||
free (info->title);
|
||||
free (info);
|
||||
}
|
||||
RGraphNodeInfo *info = ptr;
|
||||
free (info->body);
|
||||
free (info->title);
|
||||
free (info);
|
||||
}
|
||||
|
||||
R_API RGraphNodeInfo *r_graph_create_node_info(const char *title, const char *body, ut64 offset) {
|
||||
|
|
|
|||
|
|
@ -1650,7 +1650,7 @@ R_API void r_print_c(RPrint *p, const ut8 *str, int len) {
|
|||
p->cb_printf ("\n");
|
||||
}
|
||||
}
|
||||
p->cb_printf (" };\n");
|
||||
p->cb_printf ("};\n");
|
||||
}
|
||||
|
||||
// HACK :D
|
||||
|
|
|
|||
|
|
@ -293,7 +293,7 @@ R_API void r_print_code(RPrint *p, ut64 addr, const ut8 *buf, int len, char lang
|
|||
p->cb_printf (" %02x", buf[i] & 0xff);
|
||||
r_print_cursor (p, i, 1, 0);
|
||||
}
|
||||
p->cb_printf (" }\n");
|
||||
p->cb_printf ("}\n");
|
||||
break;
|
||||
case 'j': // "pcj"
|
||||
p->cb_printf ("[");
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ static char *decode_buffer(PJ *pj, const ut8* start, const ut8* end, int padcnt,
|
|||
if (mode == 'j' || mode == 'J') {
|
||||
pj_o (pj);
|
||||
} else {
|
||||
r_strbuf_append (sb, " {\n");
|
||||
r_strbuf_append (sb, "{\n");
|
||||
}
|
||||
padcnt++;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -994,7 +994,7 @@ static void setModuleBounded(ut8 qrcode[], int x, int y, bool isBlack) {
|
|||
static char qrcode_utf8_expansions[16][7] = { " ","▀ "," ▀","▀▀",
|
||||
"▄ ","█ ","▄▀","█▀",
|
||||
" ▄","▀▄"," █","▀█",
|
||||
"▄▄","█▄","▄█","██"};
|
||||
"▄▄","█▄","▄█","██" };
|
||||
|
||||
R_API char *r_qrcode_gen(const ut8 *text, int len, bool utf8, bool inverted) {
|
||||
uint8_t qrcode[qrcodegen_BUFFER_LEN_MAX] = {
|
||||
|
|
|
|||
|
|
@ -41,17 +41,17 @@ static struct cclass {
|
|||
const char *chars;
|
||||
const char *multis;
|
||||
} cclasses[] = {
|
||||
{ "alnum", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789", ""},
|
||||
{ "alpha", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz", ""},
|
||||
{ "blank", " \t", ""},
|
||||
{ "cntrl", "\007\b\t\n\v\f\r\1\2\3\4\5\6\16\17\20\21\22\23\24\25\26\27\30\31\32\33\34\35\36\37\177", ""},
|
||||
{ "digit", "0123456789", ""},
|
||||
{ "graph", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz 0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", ""},
|
||||
{ "lower", "abcdefghijklmnopqrstuvwxyz", ""},
|
||||
{ "print", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~ ", ""},
|
||||
{ "punct", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", ""},
|
||||
{ "space", "\t\n\v\f\r ", ""},
|
||||
{ "upper", "ABCDEFGHIJKLMNOPQRSTUVWXYZ", ""},
|
||||
{ "xdigit", "0123456789ABCDEFabcdef", ""},
|
||||
{ "alnum", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789", "" },
|
||||
{ "alpha", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz", "" },
|
||||
{ "blank", " \t", "" },
|
||||
{ "cntrl", "\007\b\t\n\v\f\r\1\2\3\4\5\6\16\17\20\21\22\23\24\25\26\27\30\31\32\33\34\35\36\37\177", "" },
|
||||
{ "digit", "0123456789", "" },
|
||||
{ "graph", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz 0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", "" },
|
||||
{ "lower", "abcdefghijklmnopqrstuvwxyz", "" },
|
||||
{ "print", "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~ ", "" },
|
||||
{ "punct", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", "" },
|
||||
{ "space", "\t\n\v\f\r ", "" },
|
||||
{ "upper", "ABCDEFGHIJKLMNOPQRSTUVWXYZ", "" },
|
||||
{ "xdigit", "0123456789ABCDEFabcdef", "" },
|
||||
{ NULL, NULL, "" }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,441 +9,441 @@ typedef struct {
|
|||
|
||||
// seven segment ascii-art text
|
||||
static const SevenSegments ss_lc[] = {
|
||||
{ '0', {" __ ",
|
||||
{ '0', { " __ ",
|
||||
"| /|",
|
||||
"|/_|"}
|
||||
"|/_|" }
|
||||
},
|
||||
{ '1', {" ",
|
||||
{ '1', { " ",
|
||||
" | ",
|
||||
" | "}
|
||||
" | " }
|
||||
},
|
||||
{ '2', {" __ ",
|
||||
{ '2', { " __ ",
|
||||
" __|",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ '3', {" __ ",
|
||||
{ '3', { " __ ",
|
||||
" __|",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '4', {" ",
|
||||
{ '4', { " ",
|
||||
"|__|",
|
||||
" |"}
|
||||
" |" }
|
||||
},
|
||||
{ '5', {" __ ",
|
||||
{ '5', { " __ ",
|
||||
"|__ ",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '6', {" __ ",
|
||||
{ '6', { " __ ",
|
||||
"|__ ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ '7', {" __ ",
|
||||
{ '7', { " __ ",
|
||||
" |",
|
||||
" |"}
|
||||
" |" }
|
||||
},
|
||||
{ '8', {" __ ",
|
||||
{ '8', { " __ ",
|
||||
"|__|",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ '9', {" __ ",
|
||||
{ '9', { " __ ",
|
||||
"|__|",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '$', {" __ ",
|
||||
{ '$', { " __ ",
|
||||
"||_ ",
|
||||
" _||"}
|
||||
" _||" }
|
||||
},
|
||||
{ '_', {" ",
|
||||
{ '_', { " ",
|
||||
" ",
|
||||
" __ "}
|
||||
" __ " }
|
||||
},
|
||||
{ '.', {" ",
|
||||
{ '.', { " ",
|
||||
" ",
|
||||
" _ "}
|
||||
" _ " }
|
||||
},
|
||||
{ ',', {" ",
|
||||
{ ',', { " ",
|
||||
" ",
|
||||
" _ "}
|
||||
" _ " }
|
||||
},
|
||||
{ '/', {" ",
|
||||
{ '/', { " ",
|
||||
" / ",
|
||||
" / "}
|
||||
" / " }
|
||||
},
|
||||
{ '%', {" ",
|
||||
{ '%', { " ",
|
||||
" O/ ",
|
||||
" /O "}
|
||||
" /O " }
|
||||
},
|
||||
{ '=', {" ",
|
||||
{ '=', { " ",
|
||||
" __ ",
|
||||
" __ "}
|
||||
" __ " }
|
||||
},
|
||||
{ '"', {" __ ",
|
||||
{ '"', { " __ ",
|
||||
" ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ '?', {" __ ",
|
||||
{ '?', { " __ ",
|
||||
" _|",
|
||||
" _\\ "}
|
||||
" _\\ " }
|
||||
},
|
||||
{ '+', {" ",
|
||||
{ '+', { " ",
|
||||
" _|_",
|
||||
" | "}
|
||||
" | " }
|
||||
},
|
||||
{ '-', {" ",
|
||||
{ '-', { " ",
|
||||
" __ ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ '*', {" ",
|
||||
{ '*', { " ",
|
||||
"_\\/_",
|
||||
" /\\ "}
|
||||
" /\\ " }
|
||||
},
|
||||
{ '(', {" _ ",
|
||||
{ '(', { " _ ",
|
||||
"| ",
|
||||
"|_ "}
|
||||
"|_ " }
|
||||
},
|
||||
{ ')', {" _ ",
|
||||
{ ')', { " _ ",
|
||||
" |",
|
||||
" _|"}
|
||||
" _|" }
|
||||
},
|
||||
{ '[', {" _ ",
|
||||
{ '[', { " _ ",
|
||||
"| ",
|
||||
"|_ "}
|
||||
"|_ " }
|
||||
},
|
||||
{ ']', {" _ ",
|
||||
{ ']', { " _ ",
|
||||
" |",
|
||||
" _|"}
|
||||
" _|" }
|
||||
},
|
||||
{ '>', {" ",
|
||||
{ '>', { " ",
|
||||
" \\ ",
|
||||
" / "}
|
||||
" / " }
|
||||
},
|
||||
{ ' ', {" ",
|
||||
{ ' ', { " ",
|
||||
" ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ 'a', {" _ ",
|
||||
{ 'a', { " _ ",
|
||||
" _|",
|
||||
" /_|"}
|
||||
" /_|" }
|
||||
},
|
||||
{ 'b', {" ",
|
||||
{ 'b', { " ",
|
||||
"|_ ",
|
||||
"|_\\ "}
|
||||
"|_\\ " }
|
||||
},
|
||||
{ 'c', {" ",
|
||||
{ 'c', { " ",
|
||||
" __ ",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ 'd', {" ",
|
||||
{ 'd', { " ",
|
||||
" _|",
|
||||
" /_|"}
|
||||
" /_|" }
|
||||
},
|
||||
{ 'e', {" _ ",
|
||||
{ 'e', { " _ ",
|
||||
"|_\\ ",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ 'f', {" __ ",
|
||||
{ 'f', { " __ ",
|
||||
"|_ ",
|
||||
"| "}
|
||||
"| " }
|
||||
},
|
||||
{ 'g', {" __ ",
|
||||
{ 'g', { " __ ",
|
||||
" \\_|",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'h', {" ",
|
||||
{ 'h', { " ",
|
||||
"|_ ",
|
||||
"| \\ "}
|
||||
"| \\ " }
|
||||
},
|
||||
{ 'i', {" ",
|
||||
{ 'i', { " ",
|
||||
" _ ",
|
||||
" | "}
|
||||
" | " }
|
||||
},
|
||||
{ 'j', {" __ ",
|
||||
{ 'j', { " __ ",
|
||||
" | ",
|
||||
"|_| "}
|
||||
"|_| " }
|
||||
},
|
||||
{ 'k', {" ",
|
||||
{ 'k', { " ",
|
||||
"|_/ ",
|
||||
"| \\ "}
|
||||
"| \\ " }
|
||||
},
|
||||
{ 'l', {" ",
|
||||
{ 'l', { " ",
|
||||
" ",
|
||||
"|___"}
|
||||
"|___" }
|
||||
},
|
||||
{ 'm', {" ",
|
||||
{ 'm', { " ",
|
||||
" ",
|
||||
"|\\/|"}
|
||||
"|\\/|" }
|
||||
},
|
||||
{ 'n', {" ",
|
||||
{ 'n', { " ",
|
||||
" __ ",
|
||||
"| |"}
|
||||
"| |" }
|
||||
},
|
||||
{ 'o', {" ",
|
||||
{ 'o', { " ",
|
||||
" __ ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'p', {" __ ",
|
||||
{ 'p', { " __ ",
|
||||
"|__|",
|
||||
"| "}
|
||||
"| " }
|
||||
},
|
||||
{ 'q', {" __ ",
|
||||
{ 'q', { " __ ",
|
||||
"|__|",
|
||||
" \\ "}
|
||||
" \\ " }
|
||||
},
|
||||
{ 'r', {" __ ",
|
||||
{ 'r', { " __ ",
|
||||
"|__|",
|
||||
"| \\ "}
|
||||
"| \\ " }
|
||||
},
|
||||
{ 's', {" ",
|
||||
{ 's', { " ",
|
||||
" _ ",
|
||||
" _\\"}
|
||||
" _\\" }
|
||||
},
|
||||
{ 't', {" ",
|
||||
{ 't', { " ",
|
||||
"_|_ ",
|
||||
" |__"}
|
||||
" |__" }
|
||||
},
|
||||
{ 'u', {" ",
|
||||
{ 'u', { " ",
|
||||
" ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'v', {" ",
|
||||
{ 'v', { " ",
|
||||
"| |",
|
||||
" \\/ "}
|
||||
" \\/ " }
|
||||
},
|
||||
{ 'w', {" ",
|
||||
{ 'w', { " ",
|
||||
" ",
|
||||
"|/\\|"}
|
||||
"|/\\|" }
|
||||
},
|
||||
{ 'x', {" ",
|
||||
{ 'x', { " ",
|
||||
" \\/ ",
|
||||
" /\\ "}
|
||||
" /\\ " }
|
||||
},
|
||||
{ 'y', {" ",
|
||||
{ 'y', { " ",
|
||||
" \\_|",
|
||||
" _|"}
|
||||
" _|" }
|
||||
},
|
||||
{ 'z', {" ",
|
||||
{ 'z', { " ",
|
||||
" _ ",
|
||||
" /_ "}
|
||||
" /_ " }
|
||||
},
|
||||
{ '\0', {0}}
|
||||
};
|
||||
|
||||
static const SevenSegments ss[] = {
|
||||
{ '0', {" __ ",
|
||||
{ '0', { " __ ",
|
||||
"| |",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ '1', {" ",
|
||||
{ '1', { " ",
|
||||
" | ",
|
||||
" | "}
|
||||
" | " }
|
||||
},
|
||||
{ '2', {" __ ",
|
||||
{ '2', { " __ ",
|
||||
" __|",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ '3', {" __ ",
|
||||
{ '3', { " __ ",
|
||||
" __|",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '4', {" ",
|
||||
{ '4', { " ",
|
||||
"|__|",
|
||||
" |"}
|
||||
" |" }
|
||||
},
|
||||
{ '5', {" __ ",
|
||||
{ '5', { " __ ",
|
||||
"|__ ",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '6', {" __ ",
|
||||
{ '6', { " __ ",
|
||||
"|__ ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ '7', {" __ ",
|
||||
{ '7', { " __ ",
|
||||
" |",
|
||||
" |"}
|
||||
" |" }
|
||||
},
|
||||
{ '8', {" __ ",
|
||||
{ '8', { " __ ",
|
||||
"|__|",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ '9', {" __ ",
|
||||
{ '9', { " __ ",
|
||||
"|__|",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ '$', {" __ ",
|
||||
{ '$', { " __ ",
|
||||
"||_ ",
|
||||
" _||"}
|
||||
" _||" }
|
||||
},
|
||||
{ '_', {" ",
|
||||
{ '_', { " ",
|
||||
" ",
|
||||
" __ "}
|
||||
" __ " }
|
||||
},
|
||||
{ '.', {" ",
|
||||
{ '.', { " ",
|
||||
" ",
|
||||
" _ "}
|
||||
" _ " }
|
||||
},
|
||||
{ ',', {" ",
|
||||
{ ',', { " ",
|
||||
" ",
|
||||
" _ "}
|
||||
" _ " }
|
||||
},
|
||||
{ '/', {" ",
|
||||
{ '/', { " ",
|
||||
" / ",
|
||||
" / "}
|
||||
" / " }
|
||||
},
|
||||
{ '%', {" ",
|
||||
{ '%', { " ",
|
||||
" O/ ",
|
||||
" /O "}
|
||||
" /O " }
|
||||
},
|
||||
{ '=', {" ",
|
||||
{ '=', { " ",
|
||||
" __ ",
|
||||
" __ "}
|
||||
" __ " }
|
||||
},
|
||||
{ '"', {" __ ",
|
||||
{ '"', { " __ ",
|
||||
" ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ '?', {" __ ",
|
||||
{ '?', { " __ ",
|
||||
" _|",
|
||||
" _\\ "}
|
||||
" _\\ " }
|
||||
},
|
||||
{ '+', {" ",
|
||||
{ '+', { " ",
|
||||
" _|_",
|
||||
" | "}
|
||||
" | " }
|
||||
},
|
||||
{ '-', {" ",
|
||||
{ '-', { " ",
|
||||
" __ ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ '*', {" ",
|
||||
{ '*', { " ",
|
||||
"_\\/_",
|
||||
" /\\ "}
|
||||
" /\\ " }
|
||||
},
|
||||
{ '(', {" _ ",
|
||||
{ '(', { " _ ",
|
||||
"| ",
|
||||
"|_ "}
|
||||
"|_ " }
|
||||
},
|
||||
{ ')', {" _ ",
|
||||
{ ')', { " _ ",
|
||||
" |",
|
||||
" _|"}
|
||||
" _|" }
|
||||
},
|
||||
{ '[', {" _ ",
|
||||
{ '[', { " _ ",
|
||||
"| ",
|
||||
"|_ "}
|
||||
"|_ " }
|
||||
},
|
||||
{ ']', {" _ ",
|
||||
{ ']', { " _ ",
|
||||
" |",
|
||||
" _|"}
|
||||
" _|" }
|
||||
},
|
||||
{ '>', {" ",
|
||||
{ '>', { " ",
|
||||
" \\ ",
|
||||
" / "}
|
||||
" / " }
|
||||
},
|
||||
{ ' ', {" ",
|
||||
{ ' ', { " ",
|
||||
" ",
|
||||
" "}
|
||||
" " }
|
||||
},
|
||||
{ 'a', {" __ ",
|
||||
{ 'a', { " __ ",
|
||||
"|__|",
|
||||
"| |"}
|
||||
"| |" }
|
||||
},
|
||||
{ 'b', {" ",
|
||||
{ 'b', { " ",
|
||||
"|__ ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'c', {" ",
|
||||
{ 'c', { " ",
|
||||
" __ ",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ 'd', {" ",
|
||||
{ 'd', { " ",
|
||||
" __|",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'e', {" __ ",
|
||||
{ 'e', { " __ ",
|
||||
"|_ ",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ 'f', {" __ ",
|
||||
{ 'f', { " __ ",
|
||||
"|_ ",
|
||||
"| "}
|
||||
"| " }
|
||||
},
|
||||
{ 'g', {" __ ",
|
||||
{ 'g', { " __ ",
|
||||
"| _ ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'h', {" ",
|
||||
{ 'h', { " ",
|
||||
"|__|",
|
||||
"| |"}
|
||||
"| |" }
|
||||
},
|
||||
{ 'i', {" ___",
|
||||
{ 'i', { " ___",
|
||||
" | ",
|
||||
" _|_"}
|
||||
" _|_" }
|
||||
},
|
||||
{ 'j', {" __ ",
|
||||
{ 'j', { " __ ",
|
||||
" | ",
|
||||
"|_| "}
|
||||
"|_| " }
|
||||
},
|
||||
{ 'k', {" ",
|
||||
{ 'k', { " ",
|
||||
"|_/ ",
|
||||
"| \\ "}
|
||||
"| \\ " }
|
||||
},
|
||||
{ 'l', {" ",
|
||||
{ 'l', { " ",
|
||||
"| ",
|
||||
"|__ "}
|
||||
"|__ " }
|
||||
},
|
||||
{ 'm', {" ",
|
||||
{ 'm', { " ",
|
||||
"|\\/|",
|
||||
"| |"}
|
||||
"| |" }
|
||||
},
|
||||
{ 'n', {" ",
|
||||
{ 'n', { " ",
|
||||
"|\\ |",
|
||||
"| \\|"}
|
||||
"| \\|" }
|
||||
},
|
||||
{ 'o', {" __ ",
|
||||
{ 'o', { " __ ",
|
||||
"| |",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'p', {" __ ",
|
||||
{ 'p', { " __ ",
|
||||
"|__|",
|
||||
"| "}
|
||||
"| " }
|
||||
},
|
||||
{ 'q', {" __ ",
|
||||
{ 'q', { " __ ",
|
||||
"|__|",
|
||||
" \\ "}
|
||||
" \\ " }
|
||||
},
|
||||
{ 'r', {" __ ",
|
||||
{ 'r', { " __ ",
|
||||
"|__|",
|
||||
"| \\ "}
|
||||
"| \\ " }
|
||||
},
|
||||
{ 's', {" __ ",
|
||||
{ 's', { " __ ",
|
||||
"|__ ",
|
||||
" __\\"}
|
||||
" __\\" }
|
||||
},
|
||||
{ 't', {" ",
|
||||
{ 't', { " ",
|
||||
"_|_ ",
|
||||
" |_ "}
|
||||
" |_ " }
|
||||
},
|
||||
{ 'u', {" ",
|
||||
{ 'u', { " ",
|
||||
" ",
|
||||
"|__|"}
|
||||
"|__|" }
|
||||
},
|
||||
{ 'v', {" ",
|
||||
{ 'v', { " ",
|
||||
"| |",
|
||||
" \\/ "}
|
||||
" \\/ " }
|
||||
},
|
||||
{ 'w', {" ",
|
||||
{ 'w', { " ",
|
||||
"| |",
|
||||
"|/\\|"}
|
||||
"|/\\|" }
|
||||
},
|
||||
{ 'x', {" ",
|
||||
{ 'x', { " ",
|
||||
" \\/ ",
|
||||
" /\\ "}
|
||||
" /\\ " }
|
||||
},
|
||||
{ 'y', {" ",
|
||||
{ 'y', { " ",
|
||||
"|__|",
|
||||
" __|"}
|
||||
" __|" }
|
||||
},
|
||||
{ 'z', {" __ ",
|
||||
{ 'z', { " __ ",
|
||||
" / ",
|
||||
" /_ "}
|
||||
" /_ " }
|
||||
},
|
||||
{ '\0', {0}}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -117,28 +117,28 @@ R_LIB_VERSION (r_util);
|
|||
#endif
|
||||
|
||||
static const struct {const char* name; ut64 bit;} arch_bit_array[] = {
|
||||
{"x86", R_SYS_ARCH_X86},
|
||||
{"arm", R_SYS_ARCH_ARM},
|
||||
{"ppc", R_SYS_ARCH_PPC},
|
||||
{"m68k", R_SYS_ARCH_M68K},
|
||||
{"java", R_SYS_ARCH_JAVA},
|
||||
{"mips", R_SYS_ARCH_MIPS},
|
||||
{"sparc", R_SYS_ARCH_SPARC},
|
||||
{"xap", R_SYS_ARCH_XAP},
|
||||
{"tms320", R_SYS_ARCH_TMS320},
|
||||
{"msil", R_SYS_ARCH_MSIL},
|
||||
{"objd", R_SYS_ARCH_OBJD},
|
||||
{"bf", R_SYS_ARCH_BF},
|
||||
{"sh", R_SYS_ARCH_SH},
|
||||
{"avr", R_SYS_ARCH_AVR},
|
||||
{"dalvik", R_SYS_ARCH_DALVIK},
|
||||
{"z80", R_SYS_ARCH_Z80},
|
||||
{"arc", R_SYS_ARCH_ARC},
|
||||
{"i8080", R_SYS_ARCH_I8080},
|
||||
{"rar", R_SYS_ARCH_RAR},
|
||||
{"lm32", R_SYS_ARCH_LM32},
|
||||
{"v850", R_SYS_ARCH_V850},
|
||||
{"bpf", R_SYS_ARCH_BPF},
|
||||
{ "x86", R_SYS_ARCH_X86},
|
||||
{ "arm", R_SYS_ARCH_ARM},
|
||||
{ "ppc", R_SYS_ARCH_PPC},
|
||||
{ "m68k", R_SYS_ARCH_M68K},
|
||||
{ "java", R_SYS_ARCH_JAVA},
|
||||
{ "mips", R_SYS_ARCH_MIPS},
|
||||
{ "sparc", R_SYS_ARCH_SPARC},
|
||||
{ "xap", R_SYS_ARCH_XAP},
|
||||
{ "tms320", R_SYS_ARCH_TMS320},
|
||||
{ "msil", R_SYS_ARCH_MSIL},
|
||||
{ "objd", R_SYS_ARCH_OBJD},
|
||||
{ "bf", R_SYS_ARCH_BF},
|
||||
{ "sh", R_SYS_ARCH_SH},
|
||||
{ "avr", R_SYS_ARCH_AVR},
|
||||
{ "dalvik", R_SYS_ARCH_DALVIK},
|
||||
{ "z80", R_SYS_ARCH_Z80},
|
||||
{ "arc", R_SYS_ARCH_ARC},
|
||||
{ "i8080", R_SYS_ARCH_I8080},
|
||||
{ "rar", R_SYS_ARCH_RAR},
|
||||
{ "lm32", R_SYS_ARCH_LM32},
|
||||
{ "v850", R_SYS_ARCH_V850},
|
||||
{ "bpf", R_SYS_ARCH_BPF},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
|
|
@ -833,7 +833,13 @@ R_API int r_sys_cmdbg(const char *str) {
|
|||
return pid;
|
||||
}
|
||||
int ret = r_sandbox_system (str, 0);
|
||||
eprintf ("{exit: %d, pid: %d, cmd: \"%s\"}", ret, pid, str);
|
||||
PJ *pj = pj_new ();
|
||||
pj_kn (pj, "exit", ret);
|
||||
pj_kn (pj, "pid", pid);
|
||||
pj_ks (pj, "cmd", str);
|
||||
char *s = pj_drain (pj);
|
||||
eprintf ("%s\n", s);
|
||||
free (s);
|
||||
exit (0);
|
||||
return -1;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* Apache 2.0 - Copyright 2007-2022 - pancake and dso
|
||||
class.c rewrite: Adam Pridgen <dso@rice.edu || adam.pridgen@thecoverofnight.com>
|
||||
*/
|
||||
/* Apache 2.0 - Copyright 2007-2022 - pancake and dso */
|
||||
/* class.c rewrite: Adam Pridgen <dso@rice.edu || adam.pridgen@thecoverofnight.com> */
|
||||
#define R_LOG_ORIGIN "java.class"
|
||||
|
||||
#include <r_bin.h>
|
||||
#include <math.h>
|
||||
#include "class.h"
|
||||
|
|
@ -15,12 +16,16 @@
|
|||
|
||||
#define MAX_CPITEMS 16
|
||||
|
||||
static const ut16 R_BIN_JAVA_ELEMENT_VALUE_METAS_SZ = 14;
|
||||
static const ut32 RBIN_JAVA_ATTRS_METAS_SZ = 20;
|
||||
static R_TH_LOCAL bool R_BIN_JAVA_NULL_TYPE_INITTED = false;
|
||||
static R_TH_LOCAL RBinJavaObj *R_BIN_JAVA_GLOBAL_BIN = NULL;
|
||||
|
||||
R_API char *U(r_bin_java_unmangle_method)(const char *flags, const char *name, const char *params, const char *r_value);
|
||||
R_API int r_bin_java_is_fm_type_private(RBinJavaField *fm_type);
|
||||
R_API int r_bin_java_is_fm_type_protected(RBinJavaField *fm_type);
|
||||
R_API ut32 U(r_bin_java_swap_uint)(ut32 x);
|
||||
|
||||
// R_API const char * r_bin_java_get_this_class_name(RBinJavaObj *bin);
|
||||
R_API void U(add_cp_objs_to_sdb)(RBinJavaObj * bin);
|
||||
R_API void U(add_field_infos_to_sdb)(RBinJavaObj * bin);
|
||||
R_API void U(add_method_infos_to_sdb)(RBinJavaObj * bin);
|
||||
|
|
@ -381,9 +386,6 @@ static RBinJavaRefMetas R_BIN_JAVA_REF_METAS[] = {
|
|||
{ "NewInvokeSpecial", R_BIN_JAVA_REF_NEWINVOKESPECIAL },
|
||||
{ "InvokeInterface", R_BIN_JAVA_REF_INVOKEINTERFACE }
|
||||
};
|
||||
static const ut16 R_BIN_JAVA_ELEMENT_VALUE_METAS_SZ = 14;
|
||||
static R_TH_LOCAL bool R_BIN_JAVA_NULL_TYPE_INITTED = false;
|
||||
static R_TH_LOCAL RBinJavaObj *R_BIN_JAVA_GLOBAL_BIN = NULL;
|
||||
|
||||
static RBinJavaElementValueMetas R_BIN_JAVA_ELEMENT_VALUE_METAS[] = {
|
||||
{ "Byte", R_BIN_JAVA_EV_TAG_BYTE, NULL },
|
||||
|
|
@ -492,8 +494,6 @@ static RBinJavaAttrInfoObjectAllocs RBIN_JAVA_ATTRS_ALLOCS[] = {
|
|||
{ r_bin_java_synthetic_attr_new, r_bin_java_synthetic_attr_free, r_bin_java_print_synthetic_attr_summary, r_bin_java_synthetic_attr_calc_size },
|
||||
{ r_bin_java_unknown_attr_new, r_bin_java_unknown_attr_free, r_bin_java_print_unknown_attr_summary, r_bin_java_unknown_attr_calc_size }
|
||||
};
|
||||
// R_API ut32 RBIN_JAVA_ATTRS_METAS_SZ = 21;
|
||||
static ut32 RBIN_JAVA_ATTRS_METAS_SZ = 20;
|
||||
static RBinJavaAttrMetas RBIN_JAVA_ATTRS_METAS[] = {
|
||||
{ "AnnotationDefault", R_BIN_JAVA_ATTR_TYPE_ANNOTATION_DEFAULT_ATTR, &RBIN_JAVA_ATTRS_ALLOCS[0] },
|
||||
{ "BootstrapMethods", R_BIN_JAVA_ATTR_TYPE_BOOTSTRAP_METHODS_ATTR, &RBIN_JAVA_ATTRS_ALLOCS[1] },
|
||||
|
|
@ -1644,80 +1644,59 @@ R_API RBinJavaInterfaceInfo *r_bin_java_read_next_interface_item(RBinJavaObj *bi
|
|||
}
|
||||
return ifobj;
|
||||
}
|
||||
// R_API void addrow (RBinJavaObj *bin, int addr, int line) {
|
||||
// int n = bin->lines.count++;
|
||||
//// XXX. possible memleak
|
||||
// bin->lines.addr = realloc (bin->lines.addr, sizeof (int)*n+1);
|
||||
// bin->lines.addr[n] = addr;
|
||||
// bin->lines.line = realloc (bin->lines.line, sizeof (int)*n+1);
|
||||
// bin->lines.line[n] = line;
|
||||
// }
|
||||
// R_API struct r_bin_java_cp_item_t* r_bin_java_get_item_from_cp_CP(RBinJavaObj *bin, int i) {
|
||||
// return (i<0||i>bin->cf.cp_count)? &cp_null_item: &bin->cp_items[i];
|
||||
// }
|
||||
|
||||
R_API char *r_bin_java_get_utf8_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) {
|
||||
r_return_val_if_fail (bin, NULL);
|
||||
/*
|
||||
Search through the Constant Pool list for the given CP Index.
|
||||
If the idx not found by directly going to the list index,
|
||||
the list will be walked and then the IDX will be checked.
|
||||
rvalue: new char* for caller to free.
|
||||
*/
|
||||
if (bin == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
return r_bin_java_get_utf8_from_cp_item_list (bin->cp_list, idx);
|
||||
}
|
||||
|
||||
R_API ut32 r_bin_java_get_utf8_len_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) {
|
||||
r_return_val_if_fail (bin, 0);
|
||||
/*
|
||||
Search through the Constant Pool list for the given CP Index.
|
||||
If the idx not found by directly going to the list index,
|
||||
the list will be walked and then the IDX will be checked.
|
||||
rvalue: new char* for caller to free.
|
||||
*/
|
||||
if (bin == NULL) {
|
||||
return 0;
|
||||
}
|
||||
return r_bin_java_get_utf8_len_from_cp_item_list (bin->cp_list, idx);
|
||||
}
|
||||
|
||||
R_API char *r_bin_java_get_name_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) {
|
||||
r_return_val_if_fail (bin, NULL);
|
||||
/*
|
||||
Search through the Constant Pool list for the given CP Index.
|
||||
If the idx not found by directly going to the list index,
|
||||
the list will be walked and then the IDX will be checked.
|
||||
rvalue: new char* for caller to free.
|
||||
*/
|
||||
if (bin == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
return r_bin_java_get_name_from_cp_item_list (bin->cp_list, idx);
|
||||
}
|
||||
|
||||
R_API char *r_bin_java_get_desc_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) {
|
||||
r_return_val_if_fail (bin, NULL);
|
||||
/*
|
||||
Search through the Constant Pool list for the given CP Index.
|
||||
If the idx not found by directly going to the list index,
|
||||
the list will be walked and then the IDX will be checked.
|
||||
rvalue: new char* for caller to free.
|
||||
*/
|
||||
if (bin == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
return r_bin_java_get_desc_from_cp_item_list (bin->cp_list, idx);
|
||||
}
|
||||
|
||||
R_API RBinJavaCPTypeObj *r_bin_java_get_item_from_bin_cp_list(RBinJavaObj *bin, ut64 idx) {
|
||||
r_return_val_if_fail (bin, NULL);
|
||||
/*
|
||||
Search through the Constant Pool list for the given CP Index.
|
||||
If the idx not found by directly going to the list index,
|
||||
the list will be walked and then the IDX will be checked.
|
||||
rvalue: RBinJavaObj* (user does NOT free).
|
||||
*/
|
||||
if (bin == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
if (idx > bin->cp_count || idx == 0) {
|
||||
return r_bin_java_get_java_null_cp ();
|
||||
}
|
||||
|
|
@ -2013,16 +1992,13 @@ R_API RBinJavaAttrInfo *r_bin_java_read_next_attr(RBinJavaObj *bin, const ut64 o
|
|||
const ut8 *a_buf = offset + buf;
|
||||
ut8 attr_idx_len = 6;
|
||||
if (offset + 6 > buf_len) {
|
||||
eprintf ("[X] r_bin_java: Error unable to parse remainder of classfile in Attribute offset "
|
||||
"(0x%"PFMT64x ") > len of remaining bytes (0x%"PFMT64x ").\n", offset, buf_len);
|
||||
R_LOG_ERROR ("unable to parse Attribute offset (0x%"PFMT64x ") > len (0x%"PFMT64x ")", offset, buf_len);
|
||||
return NULL;
|
||||
}
|
||||
// ut16 attr_idx, ut32 length of attr.
|
||||
ut32 sz = R_BIN_JAVA_UINT (a_buf, 2) + attr_idx_len; // r_bin_java_read_int (bin, buf_offset+2) + attr_idx_len;
|
||||
if (sz + offset > buf_len) {
|
||||
eprintf ("[X] r_bin_java: Error unable to parse remainder of classfile in Attribute len "
|
||||
"(0x%x) + offset (0x%"PFMT64x ") exceeds length of buffer (0x%"PFMT64x ").\n",
|
||||
sz, offset, buf_len);
|
||||
R_LOG_ERROR ("Unable to parse class Attribute len (0x%x) + offset (0x%"PFMT64x ") exceeds length of buffer (0x%"PFMT64x ")", sz, offset, buf_len);
|
||||
return NULL;
|
||||
}
|
||||
// when reading the attr bytes, need to also
|
||||
|
|
|
|||
|
|
@ -3,6 +3,9 @@
|
|||
cd "$(dirname $0)"/..
|
||||
|
||||
# (git grep -e '_[a-z][a-z](' libr | grep -v '{'| grep c:) && exit 1
|
||||
# TODO : also check for '{0x'
|
||||
(git grep '\t{"' libr | grep -v strcmp | grep -v format | grep -v '{",' | grep -v esil | grep c:) && exit 1
|
||||
(git grep '"},' libr | grep -v strcmp | grep -v format | grep -v '"},' | grep -v '"}{' | grep -v esil | grep -v anal/p | grep c:) && exit 1
|
||||
(git grep '^\ \ \ ' libr | grep -v '/arch/' | grep -v dotnet | grep -v mangl | grep c:) && exit 1
|
||||
(git grep 'TODO' libr | grep R_LOG_INFO) && exit 1
|
||||
( git grep r_config_set libr binr | grep -e '"fal' -e '"tru') && exit 1
|
||||
|
|
|
|||
|
|
@ -1454,10 +1454,10 @@ s sym.range_or
|
|||
pd 1~4h
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
| ; var signed int64_t var_4h { > 0xa} @ rbp-0x4
|
||||
| ; var signed int64_t var_14h { > 0x0 && <= 0x9} @ rbp-0x14
|
||||
| ; var signed int64_t var_4h { > 0x64 && <= 0xc7} @ rbp-0x4
|
||||
| ; var signed int64_t var_4h { > 0xff && <= 0x12b || > 0x14 && <= 0x31 || > 0x6f && <= 0xdd} @ rbp-0x4
|
||||
| ; var signed int64_t var_4h { > 0xa } @ rbp-0x4
|
||||
| ; var signed int64_t var_14h { > 0x0 && <= 0x9 } @ rbp-0x14
|
||||
| ; var signed int64_t var_4h { > 0x64 && <= 0xc7 } @ rbp-0x4
|
||||
| ; var signed int64_t var_4h { > 0xff && <= 0x12b || > 0x14 && <= 0x31 || > 0x6f && <= 0xdd } @ rbp-0x4
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue