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fix(xram_flash): fix `xram_falsh` for the cache consistency

This commit is contained in:
taorye 2022-11-10 22:17:03 +08:00
parent 3a74749d21
commit 8a40141e08
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GPG Key ID: EDFFE0AD344F5FE0
2 changed files with 31 additions and 17 deletions
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32
components/sipeed/c906/m1s_c906_xram/src/m1s_c906_xram_flash.c
View File

@ -9,8 +9,6 @@
/****************************************************************************
* Send Handle
****************************************************************************/
static m1s_xram_flash_t op = {0};
static int m1s_xram_flash_operation(m1s_xram_flash_t *obj, enum flash_operation operation)
{
struct xram_hdr tx_hdr;
@ -36,6 +34,7 @@ static int m1s_xram_flash_operation(m1s_xram_flash_t *obj, enum flash_operation
obj->offset += 0x1000;
bytes = XRAMRingWrite(XRAM_OP_QUEUE, &tx_hdr, sizeof(struct xram_hdr));
bytes += XRAMRingWrite(XRAM_OP_QUEUE, obj, sizeof(m1s_xram_flash_t));
csi_dcache_clean_invalid();
if (bytes != sizeof(struct xram_hdr) + sizeof(m1s_xram_flash_t)) {
printf("xram write operate err.\r\n");
} else {
@ -48,19 +47,18 @@ static int m1s_xram_flash_operation(m1s_xram_flash_t *obj, enum flash_operation
}
m1s_c906_xram_mutex_unlock();
if (0 == ret && XRAM_FLASH_ERASE != operation) {
csi_dcache_clean_invalid_range((uint64_t)obj->addr, obj->len);
}
return ret;
}
int m1s_xram_flash_read(uint32_t offset, void *const addr, uint32_t len)
{
if (0 == len) return 0;
op.offset = offset;
op.addr = addr;
op.len = len;
csi_dcache_clean_invalid();
m1s_xram_flash_t op = {
.offset = offset,
.addr = addr,
.len = len,
};
int ret = m1s_xram_flash_operation(&op, XRAM_FLASH_READ);
return ret;
}
@ -68,17 +66,21 @@ int m1s_xram_flash_read(uint32_t offset, void *const addr, uint32_t len)
int m1s_xram_flash_write(uint32_t offset, void *const addr, uint32_t len)
{
if (0 == len) return 0;
op.offset = offset;
op.addr = addr;
op.len = len;
csi_dcache_clean();
m1s_xram_flash_t op = {
.offset = offset,
.addr = addr,
.len = len,
};
return m1s_xram_flash_operation(&op, XRAM_FLASH_WRITE);
}
int m1s_xram_flash_erase(uint32_t offset, uint32_t len)
{
if (0 == len) return 0;
op.offset = offset;
op.len = len;
m1s_xram_flash_t op = {
.offset = offset,
.addr = 0,
.len = len,
};
return m1s_xram_flash_operation(&op, XRAM_FLASH_ERASE);
}

16
components/sipeed/e907/m1s_e907_xram/src/m1s_e907_xram_flash.c
View File

@ -16,6 +16,16 @@
/****************************************************************************
* Recv Handle
****************************************************************************/
// static inline void log_hex(unsigned int *a, uint32_t l)
// {
// l /= 4;
// for (uint32_t i = 0; i < l; i++) {
// if ((i & 0x3) == 0) printf("%08x:", (unsigned int)&a[i]);
// printf(" %08x", a[i]);
// if ((i & 0x3) == 0x3) printf("\r\n");
// }
// if (l & 0x3) printf("\r\n");
// }
static int xram_flash_read(m1s_xram_flash_t *op)
{
@ -27,7 +37,8 @@ static int xram_flash_read(m1s_xram_flash_t *op)
if (0 != bl_flash_read(op->offset, op->addr, op->len)) {
err = FLASH_OP_ERR;
}
csi_dcache_clean_range((uint32_t)op->addr, op->len);
// log_hex(op->addr, op->len);
csi_dcache_clean_invalid_range((uint8_t *)op->addr, op->len);
/* xram response */
hdr.type = M1S_XRAM_TYPE_FLASH;
@ -48,7 +59,8 @@ static int xram_flash_write(m1s_xram_flash_t *op)
uint32_t bytes;
enum flash_op_err err = FLASH_OP_OK;
csi_dcache_invalid_range((uint32_t)op->addr, op->len);
csi_dcache_invalid_range((uint8_t *)op->addr, op->len);
// log_hex(op->addr, op->len);
/* flash deinit */
if (0 != bl_flash_write(op->offset, op->addr, op->len)) {
err = FLASH_OP_ERR;