anolis: iommu/vt-d: add kh40000_iommu_dma_ops for KH-40000
ANBZ: #4330 Add kh40000_iommu_dma_ops for KH-40000 platform. For coherent DMA access, memory can be allocated only from the memory node of the node where the device resides. For streaming DMA access, add a PCI read operation at the end of DMA access. Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> Reviewed-by: Artie Ding <artie.ding@linux.alibaba.com> Link: https://gitee.com/anolis/cloud-kernel/pulls/3375
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leoliu-oc
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81e1e12eef
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cc48a6b845
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@ -5408,3 +5408,7 @@
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A hex value specifying bitmask with supplemental xhci
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host controller quirks. Meaning of each bit can be
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consulted in header drivers/usb/host/xhci.h.
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zhaoxin_patch_bitmask=
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[X86] Bitmask for Zhaoxin Platform's patch.
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bit 0: enable KH-40000 dma patch's node check function
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@ -32,6 +32,12 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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extern bool is_zhaoxin_kh40000(void);
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#if IS_BUILTIN(CONFIG_INTEL_IOMMU) && IS_BUILTIN(CONFIG_X86_64)
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phys_addr_t kh40000_iommu_iova_to_phys(struct device *dev, dma_addr_t paddr);
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void kh40000_sync_single_dma_for_cpu(struct device *dev, dma_addr_t paddr,
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enum dma_data_direction dir, bool is_iommu);
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#endif /* CONFIG_INTEL_IOMMU && CONFIG_X86_64 */
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bool arch_dma_alloc_attrs(struct device **dev);
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#define arch_dma_alloc_attrs arch_dma_alloc_attrs
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@ -175,6 +175,87 @@ static int __init pci_iommu_init(void)
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/* Must execute after PCI subsystem */
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rootfs_initcall(pci_iommu_init);
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#if IS_BUILTIN(CONFIG_INTEL_IOMMU) && IS_BUILTIN(CONFIG_X86_64)
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/***
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* usage:
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* set "zhaoxin_patch_bitmask=<value>" in cmdline
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* value description:
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* bit 0: enable(1) node check or not(0). default 1
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*/
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enum {
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ZHAOXIN_P2CW_NODE_CHECK = BIT(0),
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ZHAOXIN_PATCH_CODE_MAX = ZHAOXIN_P2CW_NODE_CHECK,
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};
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#define ZHAOXIN_PATCH_CODE_DEFAULT ZHAOXIN_P2CW_NODE_CHECK
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unsigned long zhaoxin_patch_code = ZHAOXIN_PATCH_CODE_DEFAULT;
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static int __init zhaoxin_patch_code_setup(char *str)
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{
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int err = kstrtoul(str, 0, &zhaoxin_patch_code);
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if (err || (zhaoxin_patch_code > ZHAOXIN_PATCH_CODE_MAX)) {
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pr_err("cmdline 'zhaoxin_patch_bitmask=%s' inappropriate\n", str);
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zhaoxin_patch_code = ZHAOXIN_PATCH_CODE_DEFAULT;
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return err;
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}
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if (ZHAOXIN_P2CW_NODE_CHECK & zhaoxin_patch_code)
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pr_info("zhaoxin dma patch node check is enabled\n");
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return 0;
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}
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__setup("zhaoxin_patch_bitmask=", zhaoxin_patch_code_setup);
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static struct pci_dev *kh40000_get_pci_dev(struct device *dev)
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{
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if (dev_is_pci(dev))
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return to_pci_dev(dev);
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if (dev->parent)
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return kh40000_get_pci_dev(dev->parent);
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return NULL;
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}
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void kh40000_sync_single_dma_for_cpu(struct device *dev, dma_addr_t paddr,
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enum dma_data_direction dir, bool is_iommu)
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{
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u8 vid;
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struct pci_dev *pci;
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u64 dma_mask = *dev->dma_mask;
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/* check direction */
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if ((dir != DMA_FROM_DEVICE) && (dir != DMA_BIDIRECTIONAL))
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return;
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/* check dma capability */
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if (dma_mask <= DMA_BIT_MASK(32))
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return;
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/* check device type */
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pci = kh40000_get_pci_dev(dev);
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if (pci == NULL)
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return;
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/* get real physical address */
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if (is_iommu)
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paddr = kh40000_iommu_iova_to_phys(dev, paddr);
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/* check node or not */
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if ((zhaoxin_patch_code & ZHAOXIN_P2CW_NODE_CHECK)) {
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unsigned long pfn = PFN_DOWN(paddr);
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if (pfn_to_nid(pfn) == dev_to_node(dev))
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return;
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}
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pci_read_config_byte(pci, PCI_VENDOR_ID, &vid);
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}
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#endif /* CONFIG_INTEL_IOMMU && IS_BUILTIN(CONFIG_X86_64) */
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#ifdef CONFIG_PCI
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/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
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@ -4757,6 +4757,7 @@ const struct attribute_group *intel_iommu_groups[] = {
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NULL,
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};
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const struct dma_map_ops kh40000_iommu_dma_ops;
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int __init intel_iommu_init(void)
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{
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int ret = -ENODEV;
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@ -4850,6 +4851,9 @@ int __init intel_iommu_init(void)
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#endif
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dma_ops = &intel_dma_ops;
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if (is_zhaoxin_kh40000())
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dma_ops = &kh40000_iommu_dma_ops;
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init_iommu_pm_ops();
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for_each_active_iommu(iommu, drhd) {
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@ -5499,3 +5503,111 @@ static void __init check_tylersburg_isoch(void)
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pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
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vtisochctrl);
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}
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#if IS_BUILTIN(CONFIG_INTEL_IOMMU) && IS_BUILTIN(CONFIG_X86_64)
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static void *kh40000_iommu_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t flags, unsigned long attrs)
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{
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struct page *page = NULL;
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int order;
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nodemask_t nodemask;
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int node = dev_to_node(dev);
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nodes_clear(nodemask);
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size = PAGE_ALIGN(size);
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order = get_order(size);
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if (!iommu_no_mapping(dev))
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flags &= ~(GFP_DMA | GFP_DMA32);
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else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
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if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
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flags |= GFP_DMA;
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else
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flags |= GFP_DMA32;
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}
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if (node == NUMA_NO_NODE) {
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page = __alloc_pages_nodemask(flags, order, numa_mem_id(), NULL);
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} else {
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if (!(flags & (GFP_DMA | GFP_DMA32))) {
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node_set(node, nodemask);
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page = __alloc_pages_nodemask(flags | __GFP_HIGH, order, node, &nodemask);
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} else {
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page = __alloc_pages_nodemask(flags | __GFP_HIGH, order, node, NULL);
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}
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}
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if (!page)
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return NULL;
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memset(page_address(page), 0, size);
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*dma_handle = __intel_map_single(dev, page_to_phys(page), size, DMA_BIDIRECTIONAL,
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dev->coherent_dma_mask);
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if (*dma_handle)
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return page_address(page);
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return NULL;
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}
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phys_addr_t kh40000_iommu_iova_to_phys(struct device *dev, dma_addr_t paddr)
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{
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/* only patch remote DMA access */
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if (!iommu_no_mapping(dev)) {
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struct dmar_domain *domain = find_domain(dev);
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paddr = intel_iommu_iova_to_phys(&(domain->domain), paddr);
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}
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return paddr;
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}
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static void kh40000_iommu_sync_single_for_cpu(struct device *dev, dma_addr_t addr, size_t size,
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enum dma_data_direction dir)
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{
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kh40000_sync_single_dma_for_cpu(dev, addr, dir, 1);
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}
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static void kh40000_iommu_unmap_page(struct device *dev, dma_addr_t addr, size_t size,
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enum dma_data_direction dir, unsigned long attrs)
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{
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kh40000_sync_single_dma_for_cpu(dev, addr, dir, 1);
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intel_unmap_page(dev, addr, size, dir, attrs);
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}
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static void kh40000_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist, int nelems,
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enum dma_data_direction dir, unsigned long attrs)
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{
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dma_addr_t startaddr = sg_dma_address(sglist) & PAGE_MASK;
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unsigned long nrpages = 0;
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struct scatterlist *sg;
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int i;
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for_each_sg(sglist, sg, nelems, i) {
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nrpages += aligned_nrpages(sg_dma_address(sg), sg_dma_len(sg));
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kh40000_iommu_sync_single_for_cpu(dev, sg->dma_address, sg_dma_len(sg), dir);
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}
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intel_unmap(dev, startaddr, nrpages << VTD_PAGE_SHIFT);
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}
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static void kh40000_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl, int nelems,
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enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nelems, i)
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kh40000_iommu_sync_single_for_cpu(dev, sg->dma_address, sg_dma_len(sg), dir);
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}
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const struct dma_map_ops kh40000_iommu_dma_ops = {
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.alloc = kh40000_iommu_alloc_coherent,
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.free = intel_free_coherent,
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.map_sg = intel_map_sg,
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.unmap_sg = kh40000_iommu_unmap_sg,
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.map_page = intel_map_page,
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.unmap_page = kh40000_iommu_unmap_page,
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.sync_single_for_cpu = kh40000_iommu_sync_single_for_cpu,
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.sync_sg_for_cpu = kh40000_iommu_sync_sg_for_cpu,
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.mapping_error = intel_mapping_error,
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.dma_supported = dma_direct_supported,
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};
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#endif /* IS_BUILTIN(CONFIG_INTEL_IOMMU) && IS_BUILTIN(CONFIG_X86_64) */
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