261 lines
7.1 KiB
C
261 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2019 Christoph Hellwig.
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/bitfield.h>
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#include <asm/soc.h>
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#define K210_SYSCTL_CLK0_FREQ 26000000UL
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/* Registers base address */
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#define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL
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/* Registers */
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#define K210_SYSCTL_PLL0 0x08
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#define K210_SYSCTL_PLL1 0x0c
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/* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
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#define PLL_RESET (1 << 20)
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#define PLL_PWR (1 << 21)
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#define PLL_INTFB (1 << 22)
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#define PLL_BYPASS (1 << 23)
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#define PLL_TEST (1 << 24)
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#define PLL_OUT_EN (1 << 25)
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#define PLL_TEST_EN (1 << 26)
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#define K210_SYSCTL_PLL_LOCK 0x18
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#define PLL0_LOCK1 (1 << 0)
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#define PLL0_LOCK2 (1 << 1)
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#define PLL0_SLIP_CLEAR (1 << 2)
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#define PLL0_TEST_CLK_OUT (1 << 3)
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#define PLL1_LOCK1 (1 << 8)
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#define PLL1_LOCK2 (1 << 9)
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#define PLL1_SLIP_CLEAR (1 << 10)
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#define PLL1_TEST_CLK_OUT (1 << 11)
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#define PLL2_LOCK1 (1 << 16)
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#define PLL2_LOCK2 (1 << 16)
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#define PLL2_SLIP_CLEAR (1 << 18)
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#define PLL2_TEST_CLK_OUT (1 << 19)
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#define K210_SYSCTL_CLKSEL0 0x20
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#define CLKSEL_ACLK (1 << 0)
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#define K210_SYSCTL_CLKEN_CENT 0x28
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#define CLKEN_CPU (1 << 0)
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#define CLKEN_SRAM0 (1 << 1)
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#define CLKEN_SRAM1 (1 << 2)
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#define CLKEN_APB0 (1 << 3)
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#define CLKEN_APB1 (1 << 4)
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#define CLKEN_APB2 (1 << 5)
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#define K210_SYSCTL_CLKEN_PERI 0x2c
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#define CLKEN_ROM (1 << 0)
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#define CLKEN_DMA (1 << 1)
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#define CLKEN_AI (1 << 2)
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#define CLKEN_DVP (1 << 3)
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#define CLKEN_FFT (1 << 4)
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#define CLKEN_GPIO (1 << 5)
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#define CLKEN_SPI0 (1 << 6)
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#define CLKEN_SPI1 (1 << 7)
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#define CLKEN_SPI2 (1 << 8)
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#define CLKEN_SPI3 (1 << 9)
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#define CLKEN_I2S0 (1 << 10)
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#define CLKEN_I2S1 (1 << 11)
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#define CLKEN_I2S2 (1 << 12)
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#define CLKEN_I2C0 (1 << 13)
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#define CLKEN_I2C1 (1 << 14)
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#define CLKEN_I2C2 (1 << 15)
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#define CLKEN_UART1 (1 << 16)
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#define CLKEN_UART2 (1 << 17)
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#define CLKEN_UART3 (1 << 18)
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#define CLKEN_AES (1 << 19)
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#define CLKEN_FPIO (1 << 20)
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#define CLKEN_TIMER0 (1 << 21)
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#define CLKEN_TIMER1 (1 << 22)
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#define CLKEN_TIMER2 (1 << 23)
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#define CLKEN_WDT0 (1 << 24)
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#define CLKEN_WDT1 (1 << 25)
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#define CLKEN_SHA (1 << 26)
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#define CLKEN_OTP (1 << 27)
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#define CLKEN_RTC (1 << 29)
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struct k210_sysctl {
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void __iomem *regs;
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struct clk_hw hw;
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};
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static void k210_set_bits(u32 val, void __iomem *reg)
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{
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writel(readl(reg) | val, reg);
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}
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static void k210_clear_bits(u32 val, void __iomem *reg)
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{
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writel(readl(reg) & ~val, reg);
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}
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static void k210_pll1_enable(void __iomem *regs)
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{
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u32 val;
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val = readl(regs + K210_SYSCTL_PLL1);
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val &= ~GENMASK(19, 0); /* clkr1 = 0 */
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val |= FIELD_PREP(GENMASK(9, 4), 0x3B); /* clkf1 = 59 */
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val |= FIELD_PREP(GENMASK(13, 10), 0x3); /* clkod1 = 3 */
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val |= FIELD_PREP(GENMASK(19, 14), 0x3B); /* bwadj1 = 59 */
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writel(val, regs + K210_SYSCTL_PLL1);
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k210_clear_bits(PLL_BYPASS, regs + K210_SYSCTL_PLL1);
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k210_set_bits(PLL_PWR, regs + K210_SYSCTL_PLL1);
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/*
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* Reset the pll. The magic NOPs come from the Kendryte reference SDK.
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*/
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k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
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k210_set_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
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nop();
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nop();
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k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
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for (;;) {
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val = readl(regs + K210_SYSCTL_PLL_LOCK);
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if (val & PLL1_LOCK2)
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break;
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writel(val | PLL1_SLIP_CLEAR, regs + K210_SYSCTL_PLL_LOCK);
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}
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k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL1);
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}
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static unsigned long k210_sysctl_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw);
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u32 clksel0, pll0;
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u64 pll0_freq, clkr0, clkf0, clkod0;
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/*
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* If the clock selector is not set, use the base frequency.
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* Otherwise, use PLL0 frequency with a frequency divisor.
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*/
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clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0);
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if (!(clksel0 & CLKSEL_ACLK))
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return K210_SYSCTL_CLK0_FREQ;
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/*
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* Get PLL0 frequency:
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* freq = base frequency * clkf0 / (clkr0 * clkod0)
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*/
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pll0 = readl(s->regs + K210_SYSCTL_PLL0);
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clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0);
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clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0);
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clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0);
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pll0_freq = clkf0 * K210_SYSCTL_CLK0_FREQ / (clkr0 * clkod0);
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/* Get the frequency divisor from the clock selector */
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return pll0_freq / (2ULL << FIELD_GET(0x00000006, clksel0));
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}
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static const struct clk_ops k210_sysctl_clk_ops = {
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.recalc_rate = k210_sysctl_clk_recalc_rate,
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};
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static const struct clk_init_data k210_clk_init_data = {
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.name = "k210-sysctl-pll1",
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.ops = &k210_sysctl_clk_ops,
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};
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static int k210_sysctl_probe(struct platform_device *pdev)
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{
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struct k210_sysctl *s;
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int error;
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pr_info("Kendryte K210 SoC sysctl\n");
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s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
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if (!s)
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return -ENOMEM;
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s->regs = devm_ioremap_resource(&pdev->dev,
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platform_get_resource(pdev, IORESOURCE_MEM, 0));
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if (IS_ERR(s->regs))
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return PTR_ERR(s->regs);
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s->hw.init = &k210_clk_init_data;
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error = devm_clk_hw_register(&pdev->dev, &s->hw);
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if (error) {
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dev_err(&pdev->dev, "failed to register clk");
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return error;
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}
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error = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
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&s->hw);
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if (error) {
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dev_err(&pdev->dev, "adding clk provider failed\n");
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return error;
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}
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return 0;
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}
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static const struct of_device_id k210_sysctl_of_match[] = {
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{ .compatible = "kendryte,k210-sysctl", },
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{}
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};
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static struct platform_driver k210_sysctl_driver = {
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.driver = {
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.name = "k210-sysctl",
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.of_match_table = k210_sysctl_of_match,
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},
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.probe = k210_sysctl_probe,
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};
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static int __init k210_sysctl_init(void)
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{
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return platform_driver_register(&k210_sysctl_driver);
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}
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core_initcall(k210_sysctl_init);
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/*
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* This needs to be called very early during initialization, given that
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* PLL1 needs to be enabled to be able to use all SRAM.
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*/
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static void __init k210_soc_early_init(const void *fdt)
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{
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void __iomem *regs;
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regs = ioremap(K210_SYSCTL_SYSCTL_BASE_ADDR, 0x1000);
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if (!regs)
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panic("K210 sysctl ioremap");
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/* Enable PLL1 to make the KPU SRAM useable */
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k210_pll1_enable(regs);
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k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0);
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k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1,
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regs + K210_SYSCTL_CLKEN_CENT);
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k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC,
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regs + K210_SYSCTL_CLKEN_PERI);
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k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_CLKSEL0);
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iounmap(regs);
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}
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SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init);
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#ifdef CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN
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/*
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* Generic entry for the default k210.dtb embedded DTB for boards with:
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* - Vendor ID: 0x4B5
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* - Arch ID: 0xE59889E6A5A04149 (= "Canaan AI" in UTF-8 encoded Chinese)
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* - Impl ID: 0x4D41495832303030 (= "MAIX2000")
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* These values are reported by the SiPEED MAXDUINO, SiPEED MAIX GO and
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* SiPEED Dan dock boards.
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*/
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SOC_BUILTIN_DTB_DECLARE(k210, 0x4B5, 0xE59889E6A5A04149, 0x4D41495832303030);
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#endif
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