51 lines
1.0 KiB
Plaintext
51 lines
1.0 KiB
Plaintext
/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx27-phytec-phycore-som.dts"
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/ {
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model = "Phytec pcm970";
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compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
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};
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&cspi1 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
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};
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&sdhci2 {
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bus-width = <4>;
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cd-gpios = <&gpio3 29 0>;
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wp-gpios = <&gpio3 28 0>;
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vmmc-supply = <&vmmc1_reg>;
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status = "okay";
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};
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&uart1 {
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fsl,uart-has-rtscts;
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};
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&uart2 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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&weim {
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can@d4000000 {
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compatible = "nxp,sja1000";
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reg = <4 0x00000000 0x00000100>;
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interrupt-parent = <&gpio5>;
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interrupts = <19 0x2>;
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nxp,external-clock-frequency = <16000000>;
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nxp,tx-output-config = <0x16>;
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nxp,no-comparator-bypass;
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fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
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};
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};
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