244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
/*
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* Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _VIA_DRM_H_
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#define _VIA_DRM_H_
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/* WARNING: These defines must be the same as what the Xserver uses.
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* if you change them, you must change the defines in the Xserver.
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*/
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#ifndef _VIA_DEFINES_
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#define _VIA_DEFINES_
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#ifndef __KERNEL__
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#include "via_drmclient.h"
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#endif
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#define VIA_NR_SAREA_CLIPRECTS 8
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#define VIA_NR_XVMC_PORTS 10
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#define VIA_NR_XVMC_LOCKS 5
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#define VIA_MAX_CACHELINE_SIZE 64
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#define XVMCLOCKPTR(saPriv,lockNo) \
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((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
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(VIA_MAX_CACHELINE_SIZE - 1)) & \
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~(VIA_MAX_CACHELINE_SIZE - 1)) + \
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VIA_MAX_CACHELINE_SIZE*(lockNo)))
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/* Each region is a minimum of 64k, and there are at most 64 of them.
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*/
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#define VIA_NR_TEX_REGIONS 64
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#define VIA_LOG_MIN_TEX_REGION_SIZE 16
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#endif
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#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
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#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
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#define VIA_UPLOAD_CTX 0x4
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#define VIA_UPLOAD_BUFFERS 0x8
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#define VIA_UPLOAD_TEX0 0x10
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#define VIA_UPLOAD_TEX1 0x20
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#define VIA_UPLOAD_CLIPRECTS 0x40
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#define VIA_UPLOAD_ALL 0xff
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/* VIA specific ioctls */
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#define DRM_VIA_ALLOCMEM 0x00
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#define DRM_VIA_FREEMEM 0x01
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#define DRM_VIA_AGP_INIT 0x02
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#define DRM_VIA_FB_INIT 0x03
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#define DRM_VIA_MAP_INIT 0x04
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#define DRM_VIA_DEC_FUTEX 0x05
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#define NOT_USED
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#define DRM_VIA_DMA_INIT 0x07
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#define DRM_VIA_CMDBUFFER 0x08
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#define DRM_VIA_FLUSH 0x09
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#define DRM_VIA_PCICMD 0x0a
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#define DRM_VIA_CMDBUF_SIZE 0x0b
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#define NOT_USED
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#define DRM_VIA_WAIT_IRQ 0x0d
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#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
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#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
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#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
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#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
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#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
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#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
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#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
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#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
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#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
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#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
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#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
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drm_via_cmdbuf_size_t)
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#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
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/* Indices into buf.Setup where various bits of state are mirrored per
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* context and per buffer. These can be fired at the card as a unit,
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* or in a piecewise fashion as required.
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*/
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#define VIA_TEX_SETUP_SIZE 8
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/* Flags for clear ioctl
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*/
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#define VIA_FRONT 0x1
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#define VIA_BACK 0x2
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#define VIA_DEPTH 0x4
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#define VIA_STENCIL 0x8
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#define VIDEO 0
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#define AGP 1
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typedef struct {
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uint32_t offset;
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uint32_t size;
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} drm_via_agp_t;
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typedef struct {
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uint32_t offset;
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uint32_t size;
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} drm_via_fb_t;
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typedef struct {
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uint32_t context;
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uint32_t type;
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uint32_t size;
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unsigned long index;
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unsigned long offset;
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} drm_via_mem_t;
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typedef struct _drm_via_init {
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enum {
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VIA_INIT_MAP = 0x01,
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VIA_CLEANUP_MAP = 0x02
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} func;
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unsigned long sarea_priv_offset;
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long agpAddr;
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} drm_via_init_t;
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typedef struct _drm_via_futex {
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enum {
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VIA_FUTEX_WAIT = 0x00,
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VIA_FUTEX_WAKE = 0X01
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} func;
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uint32_t ms;
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uint32_t lock;
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uint32_t val;
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} drm_via_futex_t;
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typedef struct _drm_via_dma_init {
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enum {
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VIA_INIT_DMA = 0x01,
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VIA_CLEANUP_DMA = 0x02,
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VIA_DMA_INITIALIZED = 0x03
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} func;
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unsigned long offset;
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unsigned long size;
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unsigned long reg_pause_addr;
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} drm_via_dma_init_t;
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typedef struct _drm_via_cmdbuffer {
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char __user *buf;
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unsigned long size;
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} drm_via_cmdbuffer_t;
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/* Warning: If you change the SAREA structure you must change the Xserver
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* structure as well */
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typedef struct _drm_via_tex_region {
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unsigned char next, prev; /* indices to form a circular LRU */
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unsigned char inUse; /* owned by a client, or free? */
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int age; /* tracked by clients to update local LRU's */
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} drm_via_tex_region_t;
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typedef struct _drm_via_sarea {
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unsigned int dirty;
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unsigned int nbox;
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drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
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drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
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int texAge; /* last time texture was uploaded */
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int ctxOwner; /* last context to upload state */
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int vertexPrim;
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/*
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* Below is for XvMC.
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* We want the lock integers alone on, and aligned to, a cache line.
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* Therefore this somewhat strange construct.
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*/
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char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
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unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
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unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
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unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
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} drm_via_sarea_t;
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typedef struct _drm_via_cmdbuf_size {
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enum {
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VIA_CMDBUF_SPACE = 0x01,
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VIA_CMDBUF_LAG = 0x02
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} func;
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int wait;
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uint32_t size;
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} drm_via_cmdbuf_size_t;
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typedef enum {
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VIA_IRQ_ABSOLUTE = 0x0,
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VIA_IRQ_RELATIVE = 0x1,
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VIA_IRQ_SIGNAL = 0x10000000,
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VIA_IRQ_FORCE_SEQUENCE = 0x20000000
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} via_irq_seq_type_t;
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#define VIA_IRQ_FLAGS_MASK 0xF0000000
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struct drm_via_wait_irq_request {
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unsigned irq;
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via_irq_seq_type_t type;
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uint32_t sequence;
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uint32_t signal;
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};
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typedef union drm_via_irqwait {
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struct drm_via_wait_irq_request request;
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struct drm_wait_vblank_reply reply;
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} drm_via_irqwait_t;
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#ifdef __KERNEL__
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int via_fb_init(DRM_IOCTL_ARGS);
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int via_mem_alloc(DRM_IOCTL_ARGS);
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int via_mem_free(DRM_IOCTL_ARGS);
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int via_agp_init(DRM_IOCTL_ARGS);
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int via_map_init(DRM_IOCTL_ARGS);
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int via_decoder_futex(DRM_IOCTL_ARGS);
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int via_dma_init(DRM_IOCTL_ARGS);
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int via_cmdbuffer(DRM_IOCTL_ARGS);
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int via_flush_ioctl(DRM_IOCTL_ARGS);
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int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
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int via_cmdbuf_size(DRM_IOCTL_ARGS);
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int via_wait_irq(DRM_IOCTL_ARGS);
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#endif
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#endif /* _VIA_DRM_H_ */
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