117 lines
3.8 KiB
C
117 lines
3.8 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "df_v3_6.h"
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#include "df/df_3_6_default.h"
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#include "df/df_3_6_offset.h"
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#include "df/df_3_6_sh_mask.h"
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static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
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16, 32, 0, 0, 0, 2, 4, 8};
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static void df_v3_6_init(struct amdgpu_device *adev)
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{
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}
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static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp;
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if (enable) {
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tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
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tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
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WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
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} else
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WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
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mmFabricConfigAccessControl_DEFAULT);
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}
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static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
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tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
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tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
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return tmp;
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}
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static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
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{
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int fb_channel_number;
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fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
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if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
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fb_channel_number = 0;
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return df_v3_6_channel_number[fb_channel_number];
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}
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static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp;
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/* Put DF on broadcast mode */
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adev->df_funcs->enable_broadcast_mode(adev, true);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
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tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
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tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
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tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
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WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
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} else {
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tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
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tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
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tmp |= DF_V3_6_MGCG_DISABLE;
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WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
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}
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/* Exit broadcast mode */
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adev->df_funcs->enable_broadcast_mode(adev, false);
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}
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static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags)
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{
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u32 tmp;
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/* AMD_CG_SUPPORT_DF_MGCG */
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tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
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if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
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*flags |= AMD_CG_SUPPORT_DF_MGCG;
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}
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const struct amdgpu_df_funcs df_v3_6_funcs = {
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.init = df_v3_6_init,
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.enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
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.get_fb_channel_number = df_v3_6_get_fb_channel_number,
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.get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
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.update_medium_grain_clock_gating =
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df_v3_6_update_medium_grain_clock_gating,
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.get_clockgating_state = df_v3_6_get_clockgating_state,
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};
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