216 lines
6.8 KiB
C
216 lines
6.8 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include "amdgpu.h"
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/**
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* amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
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*
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* @bo: the BO to get the PDE for
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* @level: the level in the PD hirarchy
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* @addr: resulting addr
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* @flags: resulting flags
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*
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* Get the address and flags to be used for a PDE (Page Directory Entry).
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*/
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void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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uint64_t *addr, uint64_t *flags)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct ttm_dma_tt *ttm;
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switch (bo->tbo.mem.mem_type) {
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case TTM_PL_TT:
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ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
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*addr = ttm->dma_address[0];
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break;
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case TTM_PL_VRAM:
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*addr = amdgpu_bo_gpu_offset(bo);
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break;
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default:
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*addr = 0;
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break;
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}
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*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
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amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
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}
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/**
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* amdgpu_gmc_pd_addr - return the address of the root directory
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*
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*/
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uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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uint64_t pd_addr;
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/* TODO: move that into ASIC specific code */
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if (adev->asic_type >= CHIP_VEGA10) {
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uint64_t flags = AMDGPU_PTE_VALID;
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amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
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pd_addr |= flags;
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} else {
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pd_addr = amdgpu_bo_gpu_offset(bo);
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}
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return pd_addr;
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}
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/**
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* amdgpu_gmc_agp_addr - return the address in the AGP address space
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*
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* @tbo: TTM BO which needs the address, must be in GTT domain
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*
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* Tries to figure out how to access the BO through the AGP aperture. Returns
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* AMDGPU_BO_INVALID_OFFSET if that is not possible.
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*/
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uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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struct ttm_dma_tt *ttm;
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if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
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return AMDGPU_BO_INVALID_OFFSET;
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ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
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if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
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return AMDGPU_BO_INVALID_OFFSET;
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return adev->gmc.agp_start + ttm->dma_address[0];
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}
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/**
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* amdgpu_gmc_vram_location - try to find VRAM location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will try to place VRAM at base address provided
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* as parameter.
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*/
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void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
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u64 base)
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{
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uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
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mc->vram_start = base;
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (limit && limit < mc->real_vram_size)
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mc->real_vram_size = limit;
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if (mc->xgmi.num_physical_nodes == 0) {
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mc->fb_start = mc->vram_start;
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mc->fb_end = mc->vram_end;
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}
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/**
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* amdgpu_gmc_gart_location - try to find GART location
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*
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to place GART before or after VRAM.
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*
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* If GART size is bigger than space left then we ajust GART size.
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* Thus function will never fails.
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*/
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void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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const uint64_t four_gb = 0x100000000ULL;
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u64 size_af, size_bf;
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/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
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u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
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mc->gart_size += adev->pm.smu_prv_buffer_size;
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/* VCE doesn't like it when BOs cross a 4GB segment, so align
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* the GART base on a 4GB boundary as well.
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*/
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size_bf = mc->fb_start;
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size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
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if (mc->gart_size > max(size_bf, size_af)) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = max(size_bf, size_af);
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}
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if ((size_bf >= mc->gart_size && size_bf < size_af) ||
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(size_af < mc->gart_size))
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mc->gart_start = 0;
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else
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mc->gart_start = max_mc_address - mc->gart_size + 1;
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mc->gart_start &= ~(four_gb - 1);
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
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dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
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mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}
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/**
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* amdgpu_gmc_agp_location - try to find AGP location
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* @adev: amdgpu device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to find a place for the AGP BAR in the MC address
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* space.
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*
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* AGP BAR will be assigned the largest available hole in the address space.
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* Should be called after VRAM and GART locations are setup.
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*/
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void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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const uint64_t sixteen_gb = 1ULL << 34;
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const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
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u64 size_af, size_bf;
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if (mc->fb_start > mc->gart_start) {
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size_bf = (mc->fb_start & sixteen_gb_mask) -
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ALIGN(mc->gart_end + 1, sixteen_gb);
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size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
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} else {
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size_bf = mc->fb_start & sixteen_gb_mask;
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size_af = (mc->gart_start & sixteen_gb_mask) -
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ALIGN(mc->fb_end + 1, sixteen_gb);
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}
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if (size_bf > size_af) {
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mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
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mc->agp_size = size_bf;
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} else {
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mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
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mc->agp_size = size_af;
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}
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mc->agp_end = mc->agp_start + mc->agp_size - 1;
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dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
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mc->agp_size >> 20, mc->agp_start, mc->agp_end);
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}
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