349 lines
9.0 KiB
C
349 lines
9.0 KiB
C
/*
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* Copyright © 2009 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/i2c.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drmP.h>
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/**
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* DOC: dp helpers
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*
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* These functions contain some common logic and helpers at various abstraction
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* levels to deal with Display Port sink devices and related things like DP aux
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* channel transfers, EDID reading over DP aux channels, decoding certain DPCD
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* blocks, ...
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*/
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/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
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static int
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i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
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uint8_t write_byte, uint8_t *read_byte)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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ret = (*algo_data->aux_ch)(adapter, mode,
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write_byte, read_byte);
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return ret;
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}
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/*
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* I2C over AUX CH
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*/
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/*
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* Send the address. If the I2C link is running, this 'restarts'
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* the connection with the new address, this is used for doing
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* a write followed by a read (as needed for DDC)
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*/
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static int
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i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int mode = MODE_I2C_START;
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int ret;
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if (reading)
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mode |= MODE_I2C_READ;
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else
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mode |= MODE_I2C_WRITE;
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algo_data->address = address;
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algo_data->running = true;
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ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
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return ret;
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}
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/*
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* Stop the I2C transaction. This closes out the link, sending
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* a bare address packet with the MOT bit turned off
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*/
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static void
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i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int mode = MODE_I2C_STOP;
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if (reading)
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mode |= MODE_I2C_READ;
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else
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mode |= MODE_I2C_WRITE;
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if (algo_data->running) {
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(void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
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algo_data->running = false;
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}
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}
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/*
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* Write a single byte to the current I2C address, the
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* the I2C link must be running or this returns -EIO
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*/
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static int
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i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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if (!algo_data->running)
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return -EIO;
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ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
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return ret;
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}
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/*
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* Read a single byte from the current I2C address, the
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* I2C link must be running or this returns -EIO
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*/
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static int
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i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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int ret;
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if (!algo_data->running)
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return -EIO;
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ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
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return ret;
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}
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static int
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i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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int ret = 0;
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bool reading = false;
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int m;
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int b;
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for (m = 0; m < num; m++) {
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u16 len = msgs[m].len;
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u8 *buf = msgs[m].buf;
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reading = (msgs[m].flags & I2C_M_RD) != 0;
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ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
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if (ret < 0)
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break;
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if (reading) {
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for (b = 0; b < len; b++) {
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ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
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if (ret < 0)
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break;
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}
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} else {
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for (b = 0; b < len; b++) {
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ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
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if (ret < 0)
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break;
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}
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}
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if (ret < 0)
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break;
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}
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if (ret >= 0)
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ret = num;
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i2c_algo_dp_aux_stop(adapter, reading);
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DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
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return ret;
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}
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static u32
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i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
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I2C_FUNC_SMBUS_READ_BLOCK_DATA |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
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I2C_FUNC_10BIT_ADDR;
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}
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static const struct i2c_algorithm i2c_dp_aux_algo = {
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.master_xfer = i2c_algo_dp_aux_xfer,
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.functionality = i2c_algo_dp_aux_functionality,
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};
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static void
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i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
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{
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(void) i2c_algo_dp_aux_address(adapter, 0, false);
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(void) i2c_algo_dp_aux_stop(adapter, false);
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}
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static int
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i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
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{
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adapter->algo = &i2c_dp_aux_algo;
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adapter->retries = 3;
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i2c_dp_aux_reset_bus(adapter);
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return 0;
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}
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/**
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* i2c_dp_aux_add_bus() - register an i2c adapter using the aux ch helper
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* @adapter: i2c adapter to register
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*
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* This registers an i2c adapater that uses dp aux channel as it's underlaying
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* transport. The driver needs to fill out the &i2c_algo_dp_aux_data structure
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* and store it in the algo_data member of the @adapter argument. This will be
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* used by the i2c over dp aux algorithm to drive the hardware.
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*
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* RETURNS:
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* 0 on success, -ERRNO on failure.
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*/
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int
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i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
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{
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int error;
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error = i2c_dp_aux_prepare_bus(adapter);
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if (error)
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return error;
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error = i2c_add_adapter(adapter);
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return error;
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}
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EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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/* Helpers for DP link training */
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static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_channel_eq_ok);
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
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u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
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u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(100);
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else
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mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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udelay(400);
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else
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mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
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u8 drm_dp_link_rate_to_bw_code(int link_rate)
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{
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switch (link_rate) {
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case 162000:
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default:
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return DP_LINK_BW_1_62;
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case 270000:
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return DP_LINK_BW_2_7;
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case 540000:
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return DP_LINK_BW_5_4;
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}
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}
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EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
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int drm_dp_bw_code_to_link_rate(u8 link_bw)
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{
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switch (link_bw) {
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case DP_LINK_BW_1_62:
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default:
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return 162000;
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case DP_LINK_BW_2_7:
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return 270000;
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case DP_LINK_BW_5_4:
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return 540000;
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}
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}
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EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
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