160 lines
3.7 KiB
C
160 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-dove/mpp.c
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*
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* MPP functions for Marvell Dove SoCs
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <plat/mpp.h>
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#include <plat/orion-gpio.h>
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#include "dove.h"
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#include "mpp.h"
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struct dove_mpp_grp {
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int start;
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int end;
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};
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/* Map a group to a range of GPIO pins in that group */
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static const struct dove_mpp_grp dove_mpp_grp[] = {
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[MPP_24_39] = {
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.start = 24,
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.end = 39,
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},
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[MPP_40_45] = {
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.start = 40,
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.end = 45,
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},
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[MPP_46_51] = {
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.start = 46,
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.end = 51,
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},
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[MPP_58_61] = {
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.start = 58,
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.end = 61,
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},
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[MPP_62_63] = {
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.start = 62,
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.end = 63,
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},
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};
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/* Enable gpio for a range of pins. mode should be a combination of
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GPIO_OUTPUT_OK | GPIO_INPUT_OK */
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static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
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{
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int i;
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for (i = start; i <= end; i++)
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orion_gpio_set_valid(i, gpio_mode);
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}
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/* Dump all the extra MPP registers. The platform code will dump the
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registers for pins 0-23. */
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static void __init dove_mpp_dump_regs(void)
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{
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pr_debug("PMU_CTRL4_CTRL: %08x\n",
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readl(DOVE_MPP_CTRL4_VIRT_BASE));
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pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
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readl(DOVE_PMU_MPP_GENERAL_CTRL));
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pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
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}
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static void __init dove_mpp_cfg_nfc(int sel)
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{
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u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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mpp_gen_cfg &= ~0x1;
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mpp_gen_cfg |= sel;
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writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
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dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
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}
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static void __init dove_mpp_cfg_au1(int sel)
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{
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u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
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u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
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mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
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ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
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mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
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global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
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if (!sel || sel == 0x2)
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dove_mpp_gpio_mode(52, 57, 0);
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else
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dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
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if (sel & 0x1) {
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global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
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dove_mpp_gpio_mode(56, 57, 0);
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}
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if (sel & 0x2) {
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mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
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dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
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}
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if (sel & 0x4) {
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ssp_ctrl1 |= DOVE_SSP_ON_AU1;
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dove_mpp_gpio_mode(52, 55, 0);
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}
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if (sel & 0x8)
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mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
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writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
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writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
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writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
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writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
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}
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/* Configure the group registers, enabling GPIO if sel indicates the
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pin is to be used for GPIO */
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static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
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{
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u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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int gpio_mode;
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for ( ; *mpp_grp_list; mpp_grp_list++) {
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unsigned int num = MPP_NUM(*mpp_grp_list);
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unsigned int sel = MPP_SEL(*mpp_grp_list);
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if (num > MPP_GRP_MAX) {
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pr_err("dove: invalid MPP GRP number (%u)\n", num);
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continue;
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}
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mpp_ctrl4 &= ~(0x1 << num);
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mpp_ctrl4 |= sel << num;
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gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
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dove_mpp_gpio_mode(dove_mpp_grp[num].start,
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dove_mpp_grp[num].end, gpio_mode);
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}
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writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
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}
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/* Configure the various MPP pins on Dove */
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void __init dove_mpp_conf(unsigned int *mpp_list,
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unsigned int *mpp_grp_list,
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unsigned int grp_au1_52_57,
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unsigned int grp_nfc_64_71)
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{
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dove_mpp_dump_regs();
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/* Use platform code for pins 0-23 */
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orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
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dove_mpp_conf_grp(mpp_grp_list);
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dove_mpp_cfg_au1(grp_au1_52_57);
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dove_mpp_cfg_nfc(grp_nfc_64_71);
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dove_mpp_dump_regs();
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}
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