157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (c) 2016 AmLogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*/
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/*
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* MultiPhase Locked Loops are outputs from a PLL with additional frequency
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* scaling capabilities. MPLL rates are calculated as:
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*
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* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include "clk-regmap.h"
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#include "clk-mpll.h"
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#define SDM_DEN 16384
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#define N2_MIN 4
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#define N2_MAX 511
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static inline struct meson_clk_mpll_data *
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meson_clk_mpll_data(struct clk_regmap *clk)
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{
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return (struct meson_clk_mpll_data *)clk->data;
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}
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static long rate_from_params(unsigned long parent_rate,
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unsigned int sdm,
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unsigned int n2)
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{
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unsigned long divisor = (SDM_DEN * n2) + sdm;
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if (n2 < N2_MIN)
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return -EINVAL;
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return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
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}
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static void params_from_rate(unsigned long requested_rate,
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unsigned long parent_rate,
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unsigned int *sdm,
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unsigned int *n2,
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u8 flags)
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{
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uint64_t div = parent_rate;
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uint64_t frac = do_div(div, requested_rate);
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frac *= SDM_DEN;
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if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
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*sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
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else
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*sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
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if (*sdm == SDM_DEN) {
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*sdm = 0;
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div += 1;
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}
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if (div < N2_MIN) {
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*n2 = N2_MIN;
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*sdm = 0;
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} else if (div > N2_MAX) {
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*n2 = N2_MAX;
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*sdm = SDM_DEN - 1;
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} else {
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*n2 = div;
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}
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}
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static unsigned long mpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
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unsigned int sdm, n2;
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long rate;
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sdm = meson_parm_read(clk->map, &mpll->sdm);
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n2 = meson_parm_read(clk->map, &mpll->n2);
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rate = rate_from_params(parent_rate, sdm, n2);
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return rate < 0 ? 0 : rate;
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}
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static long mpll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
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unsigned int sdm, n2;
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params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
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return rate_from_params(*parent_rate, sdm, n2);
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}
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static int mpll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
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unsigned int sdm, n2;
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unsigned long flags = 0;
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params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
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if (mpll->lock)
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spin_lock_irqsave(mpll->lock, flags);
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else
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__acquire(mpll->lock);
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/* Enable and set the fractional part */
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meson_parm_write(clk->map, &mpll->sdm, sdm);
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meson_parm_write(clk->map, &mpll->sdm_en, 1);
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/* Set additional fractional part enable if required */
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if (MESON_PARM_APPLICABLE(&mpll->ssen))
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meson_parm_write(clk->map, &mpll->ssen, 1);
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/* Set the integer divider part */
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meson_parm_write(clk->map, &mpll->n2, n2);
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/* Set the magic misc bit if required */
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if (MESON_PARM_APPLICABLE(&mpll->misc))
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meson_parm_write(clk->map, &mpll->misc, 1);
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if (mpll->lock)
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spin_unlock_irqrestore(mpll->lock, flags);
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else
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__release(mpll->lock);
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return 0;
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}
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const struct clk_ops meson_clk_mpll_ro_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);
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const struct clk_ops meson_clk_mpll_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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.set_rate = mpll_set_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
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MODULE_DESCRIPTION("Amlogic MPLL driver");
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MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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