109 lines
3.2 KiB
C
109 lines
3.2 KiB
C
/****************************************************************************\
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*
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* File Name ta_ras_if.h
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* Project AMD PSP SW IP Module
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*
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* Description Interface to the RAS Trusted Application
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*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
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* and associated documentation files (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _TA_RAS_IF_H
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#define _TA_RAS_IF_H
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/* Responses have bit 31 set */
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#define RSP_ID_MASK (1U << 31)
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#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
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#define TA_NUM_BLOCK_MAX 14
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enum ras_command {
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TA_RAS_COMMAND__ENABLE_FEATURES = 0,
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TA_RAS_COMMAND__DISABLE_FEATURES,
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TA_RAS_COMMAND__TRIGGER_ERROR,
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};
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enum ta_ras_status {
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TA_RAS_STATUS__SUCCESS = 0x00,
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TA_RAS_STATUS__RESET_NEEDED = 0x01,
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TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02,
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TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03,
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TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04,
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TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05
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};
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enum ta_ras_block {
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TA_RAS_BLOCK__UMC = 0,
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TA_RAS_BLOCK__SDMA,
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TA_RAS_BLOCK__GFX,
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TA_RAS_BLOCK__MMHUB,
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TA_RAS_BLOCK__ATHUB,
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TA_RAS_BLOCK__PCIE_BIF,
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TA_RAS_BLOCK__HDP,
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TA_RAS_BLOCK__XGMI_WAFL,
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TA_RAS_BLOCK__DF,
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TA_RAS_BLOCK__SMN,
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TA_RAS_BLOCK__SEM,
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TA_RAS_BLOCK__MP0,
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TA_RAS_BLOCK__MP1,
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TA_RAS_BLOCK__FUSE = (TA_NUM_BLOCK_MAX - 1),
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};
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enum ta_ras_error_type {
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TA_RAS_ERROR__NONE = 0,
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TA_RAS_ERROR__PARITY = 1,
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TA_RAS_ERROR__SINGLE_CORRECTABLE = 2,
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TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
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TA_RAS_ERROR__POISON = 8
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};
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struct ta_ras_enable_features_input {
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enum ta_ras_block block_id;
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enum ta_ras_error_type error_type;
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};
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struct ta_ras_disable_features_input {
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enum ta_ras_block block_id;
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enum ta_ras_error_type error_type;
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};
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struct ta_ras_trigger_error_input {
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enum ta_ras_block block_id;
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enum ta_ras_error_type inject_error_type;
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uint32_t sub_block_index;
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uint64_t address;
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uint64_t value;
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};
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union ta_ras_cmd_input {
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struct ta_ras_enable_features_input enable_features;
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struct ta_ras_disable_features_input disable_features;
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struct ta_ras_trigger_error_input trigger_error;
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};
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struct ta_ras_shared_memory {
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uint32_t cmd_id;
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uint32_t resp_id;
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enum ta_ras_status ras_status;
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uint32_t reserved;
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union ta_ras_cmd_input ras_in_message;
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};
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#endif // TL_RAS_IF_H_
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