605 lines
14 KiB
C
605 lines
14 KiB
C
/*
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* mmconfig-shared.c - Low-level direct PCI config space access via
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* MMCONFIG - common code between i386 and x86-64.
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*
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* This code does:
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* - known chipset handling
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* - ACPI decoding and validation
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*
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* Per-architecture code takes care of the mappings and accesses
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* themselves.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <linux/sort.h>
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#include <asm/e820.h>
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#include <asm/pci_x86.h>
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/* aperture is up to 256MB but BIOS may reserve less */
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#define MMCONFIG_APER_MIN (2 * 1024*1024)
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#define MMCONFIG_APER_MAX (256 * 1024*1024)
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/* Indicate if the mmcfg resources have been placed into the resource table. */
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static int __initdata pci_mmcfg_resources_inserted;
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static __init int extend_mmcfg(int num)
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{
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struct acpi_mcfg_allocation *new;
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int new_num = pci_mmcfg_config_num + num;
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new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
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if (!new)
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return -1;
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if (pci_mmcfg_config) {
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memcpy(new, pci_mmcfg_config,
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sizeof(pci_mmcfg_config[0]) * new_num);
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kfree(pci_mmcfg_config);
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}
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pci_mmcfg_config = new;
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return 0;
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}
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static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
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{
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int i = pci_mmcfg_config_num;
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pci_mmcfg_config_num++;
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pci_mmcfg_config[i].address = addr;
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pci_mmcfg_config[i].pci_segment = segment;
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pci_mmcfg_config[i].start_bus_number = start;
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pci_mmcfg_config[i].end_bus_number = end;
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}
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static const char __init *pci_mmcfg_e7520(void)
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{
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u32 win;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
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win = win & 0xf000;
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if (win == 0x0000 || win == 0xf000)
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return NULL;
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if (extend_mmcfg(1) == -1)
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return NULL;
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fill_one_mmcfg(win << 16, 0, 0, 255);
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return "Intel Corporation E7520 Memory Controller Hub";
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}
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static const char __init *pci_mmcfg_intel_945(void)
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{
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u32 pciexbar, mask = 0, len = 0;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
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/* Enable bit */
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if (!(pciexbar & 1))
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return NULL;
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/* Size bits */
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switch ((pciexbar >> 1) & 3) {
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case 0:
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mask = 0xf0000000U;
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len = 0x10000000U;
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break;
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case 1:
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mask = 0xf8000000U;
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len = 0x08000000U;
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break;
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case 2:
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mask = 0xfc000000U;
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len = 0x04000000U;
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break;
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default:
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return NULL;
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}
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/* Errata #2, things break when not aligned on a 256Mb boundary */
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/* Can only happen in 64M/128M mode */
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if ((pciexbar & mask) & 0x0fffffffU)
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return NULL;
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/* Don't hit the APIC registers and their friends */
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if ((pciexbar & mask) >= 0xf0000000U)
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return NULL;
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if (extend_mmcfg(1) == -1)
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return NULL;
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fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
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return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
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}
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static const char __init *pci_mmcfg_amd_fam10h(void)
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{
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u32 low, high, address;
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u64 base, msr;
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int i;
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unsigned segnbits = 0, busnbits;
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if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
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return NULL;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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if (rdmsr_safe(address, &low, &high))
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return NULL;
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msr = high;
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msr <<= 32;
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msr |= low;
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/* mmconfig is not enable */
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if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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return NULL;
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base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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/*
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* only handle bus 0 ?
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* need to skip it
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*/
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if (!busnbits)
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return NULL;
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if (busnbits > 8) {
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segnbits = busnbits - 8;
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busnbits = 8;
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}
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if (extend_mmcfg(1 << segnbits) == -1)
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return NULL;
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for (i = 0; i < (1 << segnbits); i++)
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fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
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return "AMD Family 10h NB";
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}
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static bool __initdata mcp55_checked;
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static const char __init *pci_mmcfg_nvidia_mcp55(void)
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{
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int bus;
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int mcp55_mmconf_found = 0;
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static const u32 extcfg_regnum = 0x90;
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static const u32 extcfg_regsize = 4;
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static const u32 extcfg_enable_mask = 1<<31;
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static const u32 extcfg_start_mask = 0xff<<16;
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static const int extcfg_start_shift = 16;
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static const u32 extcfg_size_mask = 0x3<<28;
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static const int extcfg_size_shift = 28;
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static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
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static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
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static const int extcfg_base_lshift = 25;
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/*
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* do check if amd fam10h already took over
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*/
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if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
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return NULL;
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mcp55_checked = true;
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for (bus = 0; bus < 256; bus++) {
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u64 base;
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u32 l, extcfg;
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u16 vendor, device;
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int start, size_index, end;
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raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
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continue;
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raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
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extcfg_regsize, &extcfg);
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if (!(extcfg & extcfg_enable_mask))
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continue;
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if (extend_mmcfg(1) == -1)
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continue;
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size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
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base = extcfg & extcfg_base_mask[size_index];
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/* base could > 4G */
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base <<= extcfg_base_lshift;
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start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
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end = start + extcfg_sizebus[size_index] - 1;
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fill_one_mmcfg(base, 0, start, end);
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mcp55_mmconf_found++;
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}
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if (!mcp55_mmconf_found)
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return NULL;
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return "nVidia MCP55";
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}
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struct pci_mmcfg_hostbridge_probe {
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u32 bus;
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u32 devfn;
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u32 vendor;
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u32 device;
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const char *(*probe)(void);
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};
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static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
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{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
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0x1200, pci_mmcfg_amd_fam10h },
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{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
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0x1200, pci_mmcfg_amd_fam10h },
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
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0x0369, pci_mmcfg_nvidia_mcp55 },
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};
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static int __init cmp_mmcfg(const void *x1, const void *x2)
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{
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const typeof(pci_mmcfg_config[0]) *m1 = x1;
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const typeof(pci_mmcfg_config[0]) *m2 = x2;
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int start1, start2;
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start1 = m1->start_bus_number;
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start2 = m2->start_bus_number;
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return start1 - start2;
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}
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static void __init pci_mmcfg_check_end_bus_number(void)
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{
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int i;
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typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
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/* sort them at first */
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sort(pci_mmcfg_config, pci_mmcfg_config_num,
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sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
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/* last one*/
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if (pci_mmcfg_config_num > 0) {
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i = pci_mmcfg_config_num - 1;
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cfg = &pci_mmcfg_config[i];
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if (cfg->end_bus_number < cfg->start_bus_number)
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cfg->end_bus_number = 255;
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}
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/* don't overlap please */
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for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
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cfg = &pci_mmcfg_config[i];
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cfgx = &pci_mmcfg_config[i+1];
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if (cfg->end_bus_number < cfg->start_bus_number)
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cfg->end_bus_number = 255;
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if (cfg->end_bus_number >= cfgx->start_bus_number)
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cfg->end_bus_number = cfgx->start_bus_number - 1;
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}
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}
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static int __init pci_mmcfg_check_hostbridge(void)
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{
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u32 l;
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u32 bus, devfn;
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u16 vendor, device;
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int i;
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const char *name;
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if (!raw_pci_ops)
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return 0;
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pci_mmcfg_config_num = 0;
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pci_mmcfg_config = NULL;
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for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
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bus = pci_mmcfg_probes[i].bus;
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devfn = pci_mmcfg_probes[i].devfn;
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raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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name = NULL;
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if (pci_mmcfg_probes[i].vendor == vendor &&
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pci_mmcfg_probes[i].device == device)
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name = pci_mmcfg_probes[i].probe();
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if (name)
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printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
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name);
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}
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/* some end_bus_number is crazy, fix it */
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pci_mmcfg_check_end_bus_number();
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return pci_mmcfg_config_num != 0;
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}
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static void __init pci_mmcfg_insert_resources(void)
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{
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#define PCI_MMCFG_RESOURCE_NAME_LEN 24
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int i;
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struct resource *res;
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char *names;
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unsigned num_buses;
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res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
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pci_mmcfg_config_num, GFP_KERNEL);
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if (!res) {
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printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
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return;
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}
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names = (void *)&res[pci_mmcfg_config_num];
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for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
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struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
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num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
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res->name = names;
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snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
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"PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
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cfg->start_bus_number, cfg->end_bus_number);
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res->start = cfg->address + (cfg->start_bus_number << 20);
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res->end = res->start + (num_buses << 20) - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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insert_resource(&iomem_resource, res);
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names += PCI_MMCFG_RESOURCE_NAME_LEN;
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}
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/* Mark that the resources have been inserted. */
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pci_mmcfg_resources_inserted = 1;
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}
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static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
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void *data)
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{
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struct resource *mcfg_res = data;
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struct acpi_resource_address64 address;
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acpi_status status;
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if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
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struct acpi_resource_fixed_memory32 *fixmem32 =
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&res->data.fixed_memory32;
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if (!fixmem32)
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return AE_OK;
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if ((mcfg_res->start >= fixmem32->address) &&
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(mcfg_res->end < (fixmem32->address +
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fixmem32->address_length))) {
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mcfg_res->flags = 1;
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return AE_CTRL_TERMINATE;
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}
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}
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if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
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(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
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return AE_OK;
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status = acpi_resource_to_address64(res, &address);
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if (ACPI_FAILURE(status) ||
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(address.address_length <= 0) ||
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(address.resource_type != ACPI_MEMORY_RANGE))
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return AE_OK;
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if ((mcfg_res->start >= address.minimum) &&
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(mcfg_res->end < (address.minimum + address.address_length))) {
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mcfg_res->flags = 1;
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return AE_CTRL_TERMINATE;
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}
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return AE_OK;
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}
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static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
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void *context, void **rv)
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{
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struct resource *mcfg_res = context;
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acpi_walk_resources(handle, METHOD_NAME__CRS,
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check_mcfg_resource, context);
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if (mcfg_res->flags)
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return AE_CTRL_TERMINATE;
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return AE_OK;
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}
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static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
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{
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struct resource mcfg_res;
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mcfg_res.start = start;
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mcfg_res.end = end;
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mcfg_res.flags = 0;
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acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
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if (!mcfg_res.flags)
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acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
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NULL);
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return mcfg_res.flags;
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}
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typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
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static int __init is_mmconf_reserved(check_reserved_t is_reserved,
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u64 addr, u64 size, int i,
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typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
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{
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u64 old_size = size;
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int valid = 0;
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while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) {
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size >>= 1;
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if (size < (16UL<<20))
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break;
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}
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if (size >= (16UL<<20) || size == old_size) {
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printk(KERN_NOTICE
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"PCI: MCFG area at %Lx reserved in %s\n",
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addr, with_e820?"E820":"ACPI motherboard resources");
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valid = 1;
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if (old_size != size) {
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/* update end_bus_number */
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cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
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printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
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"segment %hu buses %u - %u\n",
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i, (unsigned long)cfg->address, cfg->pci_segment,
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(unsigned int)cfg->start_bus_number,
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(unsigned int)cfg->end_bus_number);
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}
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}
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return valid;
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}
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static void __init pci_mmcfg_reject_broken(int early)
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{
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typeof(pci_mmcfg_config[0]) *cfg;
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int i;
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].address == 0))
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return;
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for (i = 0; i < pci_mmcfg_config_num; i++) {
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int valid = 0;
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u64 addr, size;
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cfg = &pci_mmcfg_config[i];
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addr = cfg->start_bus_number;
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addr <<= 20;
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addr += cfg->address;
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size = cfg->end_bus_number + 1 - cfg->start_bus_number;
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size <<= 20;
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printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
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"segment %hu buses %u - %u\n",
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i, (unsigned long)cfg->address, cfg->pci_segment,
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(unsigned int)cfg->start_bus_number,
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(unsigned int)cfg->end_bus_number);
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if (!early)
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valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
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if (valid)
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continue;
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if (!early)
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printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
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" reserved in ACPI motherboard resources\n",
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cfg->address);
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/* Don't try to do this check unless configuration
|
|
type 1 is available. how about type 2 ?*/
|
|
if (raw_pci_ops)
|
|
valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
|
|
|
|
if (!valid)
|
|
goto reject;
|
|
}
|
|
|
|
return;
|
|
|
|
reject:
|
|
printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
|
|
pci_mmcfg_arch_free();
|
|
kfree(pci_mmcfg_config);
|
|
pci_mmcfg_config = NULL;
|
|
pci_mmcfg_config_num = 0;
|
|
}
|
|
|
|
static int __initdata known_bridge;
|
|
|
|
static void __init __pci_mmcfg_init(int early)
|
|
{
|
|
/* MMCONFIG disabled */
|
|
if ((pci_probe & PCI_PROBE_MMCONF) == 0)
|
|
return;
|
|
|
|
/* MMCONFIG already enabled */
|
|
if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
|
|
return;
|
|
|
|
/* for late to exit */
|
|
if (known_bridge)
|
|
return;
|
|
|
|
if (early) {
|
|
if (pci_mmcfg_check_hostbridge())
|
|
known_bridge = 1;
|
|
}
|
|
|
|
if (!known_bridge)
|
|
acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
|
|
|
|
pci_mmcfg_reject_broken(early);
|
|
|
|
if ((pci_mmcfg_config_num == 0) ||
|
|
(pci_mmcfg_config == NULL) ||
|
|
(pci_mmcfg_config[0].address == 0))
|
|
return;
|
|
|
|
if (pci_mmcfg_arch_init())
|
|
pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
|
|
else {
|
|
/*
|
|
* Signal not to attempt to insert mmcfg resources because
|
|
* the architecture mmcfg setup could not initialize.
|
|
*/
|
|
pci_mmcfg_resources_inserted = 1;
|
|
}
|
|
}
|
|
|
|
void __init pci_mmcfg_early_init(void)
|
|
{
|
|
__pci_mmcfg_init(1);
|
|
}
|
|
|
|
void __init pci_mmcfg_late_init(void)
|
|
{
|
|
__pci_mmcfg_init(0);
|
|
}
|
|
|
|
static int __init pci_mmcfg_late_insert_resources(void)
|
|
{
|
|
/*
|
|
* If resources are already inserted or we are not using MMCONFIG,
|
|
* don't insert the resources.
|
|
*/
|
|
if ((pci_mmcfg_resources_inserted == 1) ||
|
|
(pci_probe & PCI_PROBE_MMCONF) == 0 ||
|
|
(pci_mmcfg_config_num == 0) ||
|
|
(pci_mmcfg_config == NULL) ||
|
|
(pci_mmcfg_config[0].address == 0))
|
|
return 1;
|
|
|
|
/*
|
|
* Attempt to insert the mmcfg resources but not with the busy flag
|
|
* marked so it won't cause request errors when __request_region is
|
|
* called.
|
|
*/
|
|
pci_mmcfg_insert_resources();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Perform MMCONFIG resource insertion after PCI initialization to allow for
|
|
* misprogrammed MCFG tables that state larger sizes but actually conflict
|
|
* with other system resources.
|
|
*/
|
|
late_initcall(pci_mmcfg_late_insert_resources);
|