729 lines
19 KiB
C
729 lines
19 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2011 Cavium Networks
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/usb.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-helper-board.h>
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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{
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struct platform_device *pd;
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int ret = 0;
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struct resource rng_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
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.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
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}, {
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.flags = IORESOURCE_MEM,
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.start = cvmx_build_io_address(8, 0),
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.end = cvmx_build_io_address(8, 0) + 0x7
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}
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};
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pd = platform_device_alloc("octeon_rng", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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ret = platform_device_add_resources(pd, rng_resources,
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ARRAY_SIZE(rng_resources));
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_rng_device_init);
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#ifdef CONFIG_USB
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static int __init octeon_ehci_device_init(void)
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{
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struct platform_device *pd;
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int ret = 0;
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struct resource usb_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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}, {
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.flags = IORESOURCE_IRQ,
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}
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};
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/* Only Octeon2 has ehci/ohci */
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if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
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return 0;
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if (octeon_is_simulation() || usb_disabled())
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return 0; /* No USB in the simulator. */
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pd = platform_device_alloc("octeon-ehci", 0);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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usb_resources[0].start = 0x00016F0000000000ULL;
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usb_resources[0].end = usb_resources[0].start + 0x100;
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usb_resources[1].start = OCTEON_IRQ_USB0;
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usb_resources[1].end = OCTEON_IRQ_USB0;
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ret = platform_device_add_resources(pd, usb_resources,
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ARRAY_SIZE(usb_resources));
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_ehci_device_init);
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static int __init octeon_ohci_device_init(void)
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{
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struct platform_device *pd;
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int ret = 0;
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struct resource usb_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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}, {
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.flags = IORESOURCE_IRQ,
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}
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};
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/* Only Octeon2 has ehci/ohci */
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if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
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return 0;
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if (octeon_is_simulation() || usb_disabled())
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return 0; /* No USB in the simulator. */
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pd = platform_device_alloc("octeon-ohci", 0);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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usb_resources[0].start = 0x00016F0000000400ULL;
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usb_resources[0].end = usb_resources[0].start + 0x100;
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usb_resources[1].start = OCTEON_IRQ_USB0;
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usb_resources[1].end = OCTEON_IRQ_USB0;
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ret = platform_device_add_resources(pd, usb_resources,
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ARRAY_SIZE(usb_resources));
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_ohci_device_init);
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#endif /* CONFIG_USB */
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static struct of_device_id __initdata octeon_ids[] = {
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{ .compatible = "simple-bus", },
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{ .compatible = "cavium,octeon-6335-uctl", },
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{ .compatible = "cavium,octeon-5750-usbn", },
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{ .compatible = "cavium,octeon-3860-bootbus", },
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{ .compatible = "cavium,mdio-mux", },
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{ .compatible = "gpio-leds", },
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{},
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};
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static bool __init octeon_has_88e1145(void)
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{
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return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
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!OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
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!OCTEON_IS_MODEL(OCTEON_CN56XX);
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}
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static void __init octeon_fdt_set_phy(int eth, int phy_addr)
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{
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const __be32 *phy_handle;
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const __be32 *alt_phy_handle;
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const __be32 *reg;
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u32 phandle;
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int phy;
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int alt_phy;
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const char *p;
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int current_len;
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char new_name[20];
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phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
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if (!phy_handle)
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return;
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phandle = be32_to_cpup(phy_handle);
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phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
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alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
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if (alt_phy_handle) {
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u32 alt_phandle = be32_to_cpup(alt_phy_handle);
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alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
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} else {
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alt_phy = -1;
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}
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if (phy_addr < 0 || phy < 0) {
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/* Delete the PHY things */
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fdt_nop_property(initial_boot_params, eth, "phy-handle");
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/* This one may fail */
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fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
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if (phy >= 0)
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fdt_nop_node(initial_boot_params, phy);
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if (alt_phy >= 0)
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fdt_nop_node(initial_boot_params, alt_phy);
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return;
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}
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if (phy_addr >= 256 && alt_phy > 0) {
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const struct fdt_property *phy_prop;
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struct fdt_property *alt_prop;
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u32 phy_handle_name;
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/* Use the alt phy node instead.*/
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phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
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phy_handle_name = phy_prop->nameoff;
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fdt_nop_node(initial_boot_params, phy);
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fdt_nop_property(initial_boot_params, eth, "phy-handle");
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alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
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alt_prop->nameoff = phy_handle_name;
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phy = alt_phy;
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}
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phy_addr &= 0xff;
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if (octeon_has_88e1145()) {
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fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
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memset(new_name, 0, sizeof(new_name));
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strcpy(new_name, "marvell,88e1145");
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p = fdt_getprop(initial_boot_params, phy, "compatible",
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¤t_len);
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if (p && current_len >= strlen(new_name))
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fdt_setprop_inplace(initial_boot_params, phy,
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"compatible", new_name, current_len);
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}
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reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
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if (phy_addr == be32_to_cpup(reg))
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return;
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fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
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snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
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p = fdt_get_name(initial_boot_params, phy, ¤t_len);
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if (p && current_len == strlen(new_name))
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fdt_set_name(initial_boot_params, phy, new_name);
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else
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pr_err("Error: could not rename ethernet phy: <%s>", p);
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}
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static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
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{
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u8 new_mac[6];
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u64 mac = *pmac;
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int r;
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new_mac[0] = (mac >> 40) & 0xff;
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new_mac[1] = (mac >> 32) & 0xff;
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new_mac[2] = (mac >> 24) & 0xff;
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new_mac[3] = (mac >> 16) & 0xff;
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new_mac[4] = (mac >> 8) & 0xff;
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new_mac[5] = mac & 0xff;
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r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
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new_mac, sizeof(new_mac));
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if (r) {
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pr_err("Setting \"local-mac-address\" failed %d", r);
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return;
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}
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*pmac = mac + 1;
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}
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static void __init octeon_fdt_rm_ethernet(int node)
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{
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const __be32 *phy_handle;
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phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
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if (phy_handle) {
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u32 ph = be32_to_cpup(phy_handle);
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int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
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if (p >= 0)
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fdt_nop_node(initial_boot_params, p);
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}
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fdt_nop_node(initial_boot_params, node);
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}
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static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
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{
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char name_buffer[20];
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int eth;
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int phy_addr;
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int ipd_port;
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snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
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eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
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if (eth < 0)
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return;
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if (p > max) {
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pr_debug("Deleting port %x:%x\n", i, p);
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octeon_fdt_rm_ethernet(eth);
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return;
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}
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
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else
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ipd_port = 16 * i + p;
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phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
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octeon_fdt_set_phy(eth, phy_addr);
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octeon_fdt_set_mac_addr(eth, pmac);
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}
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static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
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{
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char name_buffer[20];
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int iface;
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int p;
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int count = 0;
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snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
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iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
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if (iface < 0)
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return;
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if (cvmx_helper_interface_enumerate(idx) == 0)
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count = cvmx_helper_ports_on_interface(idx);
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for (p = 0; p < 16; p++)
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octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
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}
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int __init octeon_prune_device_tree(void)
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{
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int i, max_port, uart_mask;
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const char *pip_path;
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const char *alias_prop;
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char name_buffer[20];
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int aliases;
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u64 mac_addr_base;
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if (fdt_check_header(initial_boot_params))
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panic("Corrupt Device Tree.");
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aliases = fdt_path_offset(initial_boot_params, "/aliases");
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if (aliases < 0) {
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pr_err("Error: No /aliases node in device tree.");
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return -EINVAL;
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}
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mac_addr_base =
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((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
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((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
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((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
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((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
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((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
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(octeon_bootinfo->mac_addr_base[5] & 0xffull);
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if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
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max_port = 2;
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else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
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max_port = 1;
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else
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max_port = 0;
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if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
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max_port = 0;
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for (i = 0; i < 2; i++) {
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int mgmt;
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snprintf(name_buffer, sizeof(name_buffer),
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"mix%d", i);
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alias_prop = fdt_getprop(initial_boot_params, aliases,
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name_buffer, NULL);
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if (alias_prop) {
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mgmt = fdt_path_offset(initial_boot_params, alias_prop);
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if (mgmt < 0)
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continue;
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if (i >= max_port) {
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pr_debug("Deleting mix%d\n", i);
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octeon_fdt_rm_ethernet(mgmt);
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fdt_nop_property(initial_boot_params, aliases,
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name_buffer);
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} else {
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int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
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octeon_fdt_set_phy(mgmt, phy_addr);
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octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
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}
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}
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}
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pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
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if (pip_path) {
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int pip = fdt_path_offset(initial_boot_params, pip_path);
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if (pip >= 0)
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for (i = 0; i <= 4; i++)
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octeon_fdt_pip_iface(pip, i, &mac_addr_base);
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}
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/* I2C */
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if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
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OCTEON_IS_MODEL(OCTEON_CN63XX) ||
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OCTEON_IS_MODEL(OCTEON_CN68XX) ||
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OCTEON_IS_MODEL(OCTEON_CN56XX))
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max_port = 2;
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else
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max_port = 1;
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for (i = 0; i < 2; i++) {
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int i2c;
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snprintf(name_buffer, sizeof(name_buffer),
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"twsi%d", i);
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alias_prop = fdt_getprop(initial_boot_params, aliases,
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name_buffer, NULL);
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if (alias_prop) {
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i2c = fdt_path_offset(initial_boot_params, alias_prop);
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if (i2c < 0)
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continue;
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if (i >= max_port) {
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pr_debug("Deleting twsi%d\n", i);
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fdt_nop_node(initial_boot_params, i2c);
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fdt_nop_property(initial_boot_params, aliases,
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name_buffer);
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}
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}
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}
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/* SMI/MDIO */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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max_port = 4;
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else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
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OCTEON_IS_MODEL(OCTEON_CN63XX) ||
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OCTEON_IS_MODEL(OCTEON_CN56XX))
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max_port = 2;
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else
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max_port = 1;
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for (i = 0; i < 2; i++) {
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int i2c;
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snprintf(name_buffer, sizeof(name_buffer),
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"smi%d", i);
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alias_prop = fdt_getprop(initial_boot_params, aliases,
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name_buffer, NULL);
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if (alias_prop) {
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i2c = fdt_path_offset(initial_boot_params, alias_prop);
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if (i2c < 0)
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continue;
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if (i >= max_port) {
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pr_debug("Deleting smi%d\n", i);
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fdt_nop_node(initial_boot_params, i2c);
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fdt_nop_property(initial_boot_params, aliases,
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name_buffer);
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}
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}
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}
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/* Serial */
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uart_mask = 3;
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/* Right now CN52XX is the only chip with a third uart */
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if (OCTEON_IS_MODEL(OCTEON_CN52XX))
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uart_mask |= 4; /* uart2 */
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for (i = 0; i < 3; i++) {
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int uart;
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snprintf(name_buffer, sizeof(name_buffer),
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"uart%d", i);
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alias_prop = fdt_getprop(initial_boot_params, aliases,
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name_buffer, NULL);
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if (alias_prop) {
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uart = fdt_path_offset(initial_boot_params, alias_prop);
|
|
if (uart_mask & (1 << i)) {
|
|
__be32 f;
|
|
|
|
f = cpu_to_be32(octeon_get_io_clock_rate());
|
|
fdt_setprop_inplace(initial_boot_params,
|
|
uart, "clock-frequency",
|
|
&f, sizeof(f));
|
|
continue;
|
|
}
|
|
pr_debug("Deleting uart%d\n", i);
|
|
fdt_nop_node(initial_boot_params, uart);
|
|
fdt_nop_property(initial_boot_params, aliases,
|
|
name_buffer);
|
|
}
|
|
}
|
|
|
|
/* Compact Flash */
|
|
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
|
"cf0", NULL);
|
|
if (alias_prop) {
|
|
union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
|
|
unsigned long base_ptr, region_base, region_size;
|
|
unsigned long region1_base = 0;
|
|
unsigned long region1_size = 0;
|
|
int cs, bootbus;
|
|
bool is_16bit = false;
|
|
bool is_true_ide = false;
|
|
__be32 new_reg[6];
|
|
__be32 *ranges;
|
|
int len;
|
|
|
|
int cf = fdt_path_offset(initial_boot_params, alias_prop);
|
|
base_ptr = 0;
|
|
if (octeon_bootinfo->major_version == 1
|
|
&& octeon_bootinfo->minor_version >= 1) {
|
|
if (octeon_bootinfo->compact_flash_common_base_addr)
|
|
base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
|
|
} else {
|
|
base_ptr = 0x1d000800;
|
|
}
|
|
|
|
if (!base_ptr)
|
|
goto no_cf;
|
|
|
|
/* Find CS0 region. */
|
|
for (cs = 0; cs < 8; cs++) {
|
|
mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
|
|
region_base = mio_boot_reg_cfg.s.base << 16;
|
|
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
|
|
if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
|
|
&& base_ptr < region_base + region_size) {
|
|
is_16bit = mio_boot_reg_cfg.s.width;
|
|
break;
|
|
}
|
|
}
|
|
if (cs >= 7) {
|
|
/* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
|
|
goto no_cf;
|
|
}
|
|
|
|
if (!(base_ptr & 0xfffful)) {
|
|
/*
|
|
* Boot loader signals availability of DMA (true_ide
|
|
* mode) by setting low order bits of base_ptr to
|
|
* zero.
|
|
*/
|
|
|
|
/* Asume that CS1 immediately follows. */
|
|
mio_boot_reg_cfg.u64 =
|
|
cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
|
|
region1_base = mio_boot_reg_cfg.s.base << 16;
|
|
region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
|
|
if (!mio_boot_reg_cfg.s.en)
|
|
goto no_cf;
|
|
is_true_ide = true;
|
|
|
|
} else {
|
|
fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
|
|
fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
|
|
if (!is_16bit) {
|
|
__be32 width = cpu_to_be32(8);
|
|
fdt_setprop_inplace(initial_boot_params, cf,
|
|
"cavium,bus-width", &width, sizeof(width));
|
|
}
|
|
}
|
|
new_reg[0] = cpu_to_be32(cs);
|
|
new_reg[1] = cpu_to_be32(0);
|
|
new_reg[2] = cpu_to_be32(0x10000);
|
|
new_reg[3] = cpu_to_be32(cs + 1);
|
|
new_reg[4] = cpu_to_be32(0);
|
|
new_reg[5] = cpu_to_be32(0x10000);
|
|
fdt_setprop_inplace(initial_boot_params, cf,
|
|
"reg", new_reg, sizeof(new_reg));
|
|
|
|
bootbus = fdt_parent_offset(initial_boot_params, cf);
|
|
if (bootbus < 0)
|
|
goto no_cf;
|
|
ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
|
|
if (!ranges || len < (5 * 8 * sizeof(__be32)))
|
|
goto no_cf;
|
|
|
|
ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
|
|
ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
|
|
ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
|
|
if (is_true_ide) {
|
|
cs++;
|
|
ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
|
|
ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
|
|
ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
|
|
}
|
|
goto end_cf;
|
|
no_cf:
|
|
fdt_nop_node(initial_boot_params, cf);
|
|
|
|
end_cf:
|
|
;
|
|
}
|
|
|
|
/* 8 char LED */
|
|
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
|
"led0", NULL);
|
|
if (alias_prop) {
|
|
union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
|
|
unsigned long base_ptr, region_base, region_size;
|
|
int cs, bootbus;
|
|
__be32 new_reg[6];
|
|
__be32 *ranges;
|
|
int len;
|
|
int led = fdt_path_offset(initial_boot_params, alias_prop);
|
|
|
|
base_ptr = octeon_bootinfo->led_display_base_addr;
|
|
if (base_ptr == 0)
|
|
goto no_led;
|
|
/* Find CS0 region. */
|
|
for (cs = 0; cs < 8; cs++) {
|
|
mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
|
|
region_base = mio_boot_reg_cfg.s.base << 16;
|
|
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
|
|
if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
|
|
&& base_ptr < region_base + region_size)
|
|
break;
|
|
}
|
|
|
|
if (cs > 7)
|
|
goto no_led;
|
|
|
|
new_reg[0] = cpu_to_be32(cs);
|
|
new_reg[1] = cpu_to_be32(0x20);
|
|
new_reg[2] = cpu_to_be32(0x20);
|
|
new_reg[3] = cpu_to_be32(cs);
|
|
new_reg[4] = cpu_to_be32(0);
|
|
new_reg[5] = cpu_to_be32(0x20);
|
|
fdt_setprop_inplace(initial_boot_params, led,
|
|
"reg", new_reg, sizeof(new_reg));
|
|
|
|
bootbus = fdt_parent_offset(initial_boot_params, led);
|
|
if (bootbus < 0)
|
|
goto no_led;
|
|
ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
|
|
if (!ranges || len < (5 * 8 * sizeof(__be32)))
|
|
goto no_led;
|
|
|
|
ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
|
|
ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
|
|
ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
|
|
goto end_led;
|
|
|
|
no_led:
|
|
fdt_nop_node(initial_boot_params, led);
|
|
end_led:
|
|
;
|
|
}
|
|
|
|
/* OHCI/UHCI USB */
|
|
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
|
"uctl", NULL);
|
|
if (alias_prop) {
|
|
int uctl = fdt_path_offset(initial_boot_params, alias_prop);
|
|
|
|
if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
|
|
octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
|
|
pr_debug("Deleting uctl\n");
|
|
fdt_nop_node(initial_boot_params, uctl);
|
|
fdt_nop_property(initial_boot_params, aliases, "uctl");
|
|
} else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
|
|
octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
|
|
/* Missing "refclk-type" defaults to crystal. */
|
|
fdt_nop_property(initial_boot_params, uctl, "refclk-type");
|
|
}
|
|
}
|
|
|
|
/* DWC2 USB */
|
|
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
|
"usbn", NULL);
|
|
if (alias_prop) {
|
|
int usbn = fdt_path_offset(initial_boot_params, alias_prop);
|
|
|
|
if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
|
|
!octeon_has_feature(OCTEON_FEATURE_USB))) {
|
|
pr_debug("Deleting usbn\n");
|
|
fdt_nop_node(initial_boot_params, usbn);
|
|
fdt_nop_property(initial_boot_params, aliases, "usbn");
|
|
} else {
|
|
__be32 new_f[1];
|
|
enum cvmx_helper_board_usb_clock_types c;
|
|
c = __cvmx_helper_board_usb_get_clock_type();
|
|
switch (c) {
|
|
case USB_CLOCK_TYPE_REF_48:
|
|
new_f[0] = cpu_to_be32(48000000);
|
|
fdt_setprop_inplace(initial_boot_params, usbn,
|
|
"refclk-frequency", new_f, sizeof(new_f));
|
|
/* Fall through ...*/
|
|
case USB_CLOCK_TYPE_REF_12:
|
|
/* Missing "refclk-type" defaults to external. */
|
|
fdt_nop_property(initial_boot_params, usbn, "refclk-type");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init octeon_publish_devices(void)
|
|
{
|
|
return of_platform_bus_probe(NULL, octeon_ids, NULL);
|
|
}
|
|
device_initcall(octeon_publish_devices);
|
|
|
|
MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Platform driver for Octeon SOC");
|