280 lines
7.6 KiB
C
280 lines
7.6 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Xiao Zheng <xiao.zheng@intel.com>
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*
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* Contributors:
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#ifndef _GVT_GTT_H_
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#define _GVT_GTT_H_
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#define I915_GTT_PAGE_SHIFT 12
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struct intel_vgpu_mm;
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#define INTEL_GVT_INVALID_ADDR (~0UL)
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struct intel_gvt_gtt_entry {
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u64 val64;
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int type;
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};
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struct intel_gvt_gtt_pte_ops {
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int (*get_entry)(void *pt,
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struct intel_gvt_gtt_entry *e,
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unsigned long index,
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bool hypervisor_access,
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unsigned long gpa,
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struct intel_vgpu *vgpu);
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int (*set_entry)(void *pt,
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struct intel_gvt_gtt_entry *e,
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unsigned long index,
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bool hypervisor_access,
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unsigned long gpa,
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struct intel_vgpu *vgpu);
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bool (*test_present)(struct intel_gvt_gtt_entry *e);
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void (*clear_present)(struct intel_gvt_gtt_entry *e);
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void (*set_present)(struct intel_gvt_gtt_entry *e);
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bool (*test_pse)(struct intel_gvt_gtt_entry *e);
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void (*clear_pse)(struct intel_gvt_gtt_entry *e);
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bool (*test_ips)(struct intel_gvt_gtt_entry *e);
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void (*clear_ips)(struct intel_gvt_gtt_entry *e);
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bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
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unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
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};
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struct intel_gvt_gtt_gma_ops {
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unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
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unsigned long (*gma_to_pte_index)(unsigned long gma);
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unsigned long (*gma_to_pde_index)(unsigned long gma);
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unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
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unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
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unsigned long (*gma_to_pml4_index)(unsigned long gma);
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};
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struct intel_gvt_gtt {
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struct intel_gvt_gtt_pte_ops *pte_ops;
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struct intel_gvt_gtt_gma_ops *gma_ops;
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int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
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void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
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struct list_head oos_page_use_list_head;
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struct list_head oos_page_free_list_head;
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struct list_head ppgtt_mm_lru_list_head;
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struct page *scratch_page;
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unsigned long scratch_mfn;
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};
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typedef enum {
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GTT_TYPE_INVALID = -1,
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GTT_TYPE_GGTT_PTE,
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GTT_TYPE_PPGTT_PTE_4K_ENTRY,
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GTT_TYPE_PPGTT_PTE_64K_ENTRY,
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GTT_TYPE_PPGTT_PTE_2M_ENTRY,
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GTT_TYPE_PPGTT_PTE_1G_ENTRY,
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GTT_TYPE_PPGTT_PTE_ENTRY,
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GTT_TYPE_PPGTT_PDE_ENTRY,
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GTT_TYPE_PPGTT_PDP_ENTRY,
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GTT_TYPE_PPGTT_PML4_ENTRY,
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GTT_TYPE_PPGTT_ROOT_ENTRY,
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GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
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GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
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GTT_TYPE_PPGTT_ENTRY,
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GTT_TYPE_PPGTT_PTE_PT,
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GTT_TYPE_PPGTT_PDE_PT,
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GTT_TYPE_PPGTT_PDP_PT,
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GTT_TYPE_PPGTT_PML4_PT,
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GTT_TYPE_MAX,
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} intel_gvt_gtt_type_t;
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enum intel_gvt_mm_type {
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INTEL_GVT_MM_GGTT,
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INTEL_GVT_MM_PPGTT,
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};
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#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
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struct intel_gvt_partial_pte {
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unsigned long offset;
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u64 data;
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struct list_head list;
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};
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struct intel_vgpu_mm {
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enum intel_gvt_mm_type type;
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struct intel_vgpu *vgpu;
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struct kref ref;
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atomic_t pincount;
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union {
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struct {
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intel_gvt_gtt_type_t root_entry_type;
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/*
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* The 4 PDPs in ring context. For 48bit addressing,
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* only PDP0 is valid and point to PML4. For 32it
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* addressing, all 4 are used as true PDPs.
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*/
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u64 guest_pdps[GVT_RING_CTX_NR_PDPS];
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u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];
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bool shadowed;
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struct list_head list;
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struct list_head lru_list;
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} ppgtt_mm;
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struct {
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void *virtual_ggtt;
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struct list_head partial_pte_list;
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} ggtt_mm;
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};
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};
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struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
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intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
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static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
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{
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kref_get(&mm->ref);
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}
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void _intel_vgpu_mm_release(struct kref *mm_ref);
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static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm)
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{
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kref_put(&mm->ref, _intel_vgpu_mm_release);
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}
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static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm)
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{
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intel_vgpu_mm_put(mm);
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}
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struct intel_vgpu_guest_page;
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struct intel_vgpu_scratch_pt {
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struct page *page;
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unsigned long page_mfn;
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};
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struct intel_vgpu_gtt {
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struct intel_vgpu_mm *ggtt_mm;
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unsigned long active_ppgtt_mm_bitmap;
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struct list_head ppgtt_mm_list_head;
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struct radix_tree_root spt_tree;
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struct list_head oos_page_list_head;
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struct list_head post_shadow_list_head;
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struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
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};
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extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
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extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
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void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
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void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
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extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
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void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
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extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
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extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
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int page_table_level, void *root_entry);
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struct intel_vgpu_oos_page {
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struct intel_vgpu_ppgtt_spt *spt;
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struct list_head list;
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struct list_head vm_list;
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int id;
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unsigned char mem[I915_GTT_PAGE_SIZE];
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};
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#define GTT_ENTRY_NUM_IN_ONE_PAGE 512
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/* Represent a vgpu shadow page table. */
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struct intel_vgpu_ppgtt_spt {
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atomic_t refcount;
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struct intel_vgpu *vgpu;
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struct {
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intel_gvt_gtt_type_t type;
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bool pde_ips; /* for 64KB PTEs */
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void *vaddr;
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struct page *page;
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unsigned long mfn;
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} shadow_page;
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struct {
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intel_gvt_gtt_type_t type;
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bool pde_ips; /* for 64KB PTEs */
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unsigned long gfn;
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unsigned long write_cnt;
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struct intel_vgpu_oos_page *oos_page;
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} guest_page;
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DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
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struct list_head post_shadow_list;
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};
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int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);
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int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);
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int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);
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void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);
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unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,
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unsigned long gma);
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struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
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u64 pdps[]);
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struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
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intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
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int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);
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int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
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unsigned int off, void *p_data, unsigned int bytes);
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int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
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unsigned int off, void *p_data, unsigned int bytes);
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#endif /* _GVT_GTT_H_ */
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