354 lines
8.7 KiB
C
354 lines
8.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Tomasz Figa <t.figa@samsung.com>
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*
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* Device Tree binding constants for Samsung Exynos3250 clock controllers.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/*
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* Main CMU
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*/
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#define CLK_OSCSEL 1
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#define CLK_FIN_PLL 2
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#define CLK_FOUT_APLL 3
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#define CLK_FOUT_VPLL 4
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#define CLK_FOUT_UPLL 5
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#define CLK_FOUT_MPLL 6
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#define CLK_ARM_CLK 7
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/* Muxes */
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#define CLK_MOUT_MPLL_USER_L 16
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#define CLK_MOUT_GDL 17
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#define CLK_MOUT_MPLL_USER_R 18
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#define CLK_MOUT_GDR 19
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#define CLK_MOUT_EBI 20
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#define CLK_MOUT_ACLK_200 21
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#define CLK_MOUT_ACLK_160 22
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#define CLK_MOUT_ACLK_100 23
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#define CLK_MOUT_ACLK_266_1 24
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#define CLK_MOUT_ACLK_266_0 25
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#define CLK_MOUT_ACLK_266 26
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#define CLK_MOUT_VPLL 27
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#define CLK_MOUT_EPLL_USER 28
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#define CLK_MOUT_EBI_1 29
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#define CLK_MOUT_UPLL 30
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#define CLK_MOUT_ACLK_400_MCUISP_SUB 31
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#define CLK_MOUT_MPLL 32
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#define CLK_MOUT_ACLK_400_MCUISP 33
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#define CLK_MOUT_VPLLSRC 34
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#define CLK_MOUT_CAM1 35
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#define CLK_MOUT_CAM_BLK 36
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#define CLK_MOUT_MFC 37
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#define CLK_MOUT_MFC_1 38
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#define CLK_MOUT_MFC_0 39
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#define CLK_MOUT_G3D 40
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#define CLK_MOUT_G3D_1 41
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#define CLK_MOUT_G3D_0 42
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#define CLK_MOUT_MIPI0 43
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#define CLK_MOUT_FIMD0 44
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#define CLK_MOUT_UART_ISP 45
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#define CLK_MOUT_SPI1_ISP 46
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#define CLK_MOUT_SPI0_ISP 47
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#define CLK_MOUT_TSADC 48
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#define CLK_MOUT_MMC1 49
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#define CLK_MOUT_MMC0 50
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#define CLK_MOUT_UART1 51
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#define CLK_MOUT_UART0 52
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#define CLK_MOUT_SPI1 53
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#define CLK_MOUT_SPI0 54
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#define CLK_MOUT_AUDIO 55
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#define CLK_MOUT_MPLL_USER_C 56
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#define CLK_MOUT_HPM 57
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#define CLK_MOUT_CORE 58
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#define CLK_MOUT_APLL 59
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#define CLK_MOUT_ACLK_266_SUB 60
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#define CLK_MOUT_UART2 61
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#define CLK_MOUT_MMC2 62
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/* Dividers */
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#define CLK_DIV_GPL 64
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#define CLK_DIV_GDL 65
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#define CLK_DIV_GPR 66
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#define CLK_DIV_GDR 67
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#define CLK_DIV_MPLL_PRE 68
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#define CLK_DIV_ACLK_400_MCUISP 69
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#define CLK_DIV_EBI 70
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#define CLK_DIV_ACLK_200 71
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#define CLK_DIV_ACLK_160 72
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#define CLK_DIV_ACLK_100 73
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#define CLK_DIV_ACLK_266 74
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#define CLK_DIV_CAM1 75
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#define CLK_DIV_CAM_BLK 76
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#define CLK_DIV_MFC 77
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#define CLK_DIV_G3D 78
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#define CLK_DIV_MIPI0_PRE 79
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#define CLK_DIV_MIPI0 80
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#define CLK_DIV_FIMD0 81
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#define CLK_DIV_UART_ISP 82
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#define CLK_DIV_SPI1_ISP_PRE 83
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#define CLK_DIV_SPI1_ISP 84
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#define CLK_DIV_SPI0_ISP_PRE 85
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#define CLK_DIV_SPI0_ISP 86
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#define CLK_DIV_TSADC_PRE 87
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#define CLK_DIV_TSADC 88
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#define CLK_DIV_MMC1_PRE 89
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#define CLK_DIV_MMC1 90
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#define CLK_DIV_MMC0_PRE 91
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#define CLK_DIV_MMC0 92
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#define CLK_DIV_UART1 93
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#define CLK_DIV_UART0 94
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#define CLK_DIV_SPI1_PRE 95
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#define CLK_DIV_SPI1 96
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#define CLK_DIV_SPI0_PRE 97
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#define CLK_DIV_SPI0 98
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#define CLK_DIV_PCM 99
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#define CLK_DIV_AUDIO 100
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#define CLK_DIV_I2S 101
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#define CLK_DIV_CORE2 102
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#define CLK_DIV_APLL 103
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#define CLK_DIV_PCLK_DBG 104
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#define CLK_DIV_ATB 105
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#define CLK_DIV_COREM 106
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#define CLK_DIV_CORE 107
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#define CLK_DIV_HPM 108
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#define CLK_DIV_COPY 109
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#define CLK_DIV_UART2 110
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#define CLK_DIV_MMC2_PRE 111
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#define CLK_DIV_MMC2 112
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/* Gates */
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#define CLK_ASYNC_G3D 128
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#define CLK_ASYNC_MFCL 129
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#define CLK_PPMULEFT 130
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#define CLK_GPIO_LEFT 131
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#define CLK_ASYNC_ISPMX 132
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#define CLK_ASYNC_FSYSD 133
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#define CLK_ASYNC_LCD0X 134
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#define CLK_ASYNC_CAMX 135
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#define CLK_PPMURIGHT 136
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#define CLK_GPIO_RIGHT 137
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#define CLK_MONOCNT 138
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#define CLK_TZPC6 139
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#define CLK_PROVISIONKEY1 140
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#define CLK_PROVISIONKEY0 141
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#define CLK_CMU_ISPPART 142
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#define CLK_TMU_APBIF 143
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#define CLK_KEYIF 144
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#define CLK_RTC 145
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#define CLK_WDT 146
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#define CLK_MCT 147
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#define CLK_SECKEY 148
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#define CLK_TZPC5 149
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#define CLK_TZPC4 150
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#define CLK_TZPC3 151
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#define CLK_TZPC2 152
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#define CLK_TZPC1 153
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#define CLK_TZPC0 154
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#define CLK_CMU_COREPART 155
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#define CLK_CMU_TOPPART 156
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#define CLK_PMU_APBIF 157
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#define CLK_SYSREG 158
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#define CLK_CHIP_ID 159
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#define CLK_QEJPEG 160
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#define CLK_PIXELASYNCM1 161
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#define CLK_PIXELASYNCM0 162
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#define CLK_PPMUCAMIF 163
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#define CLK_QEM2MSCALER 164
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#define CLK_QEGSCALER1 165
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#define CLK_QEGSCALER0 166
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#define CLK_SMMUJPEG 167
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#define CLK_SMMUM2M2SCALER 168
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#define CLK_SMMUGSCALER1 169
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#define CLK_SMMUGSCALER0 170
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#define CLK_JPEG 171
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#define CLK_M2MSCALER 172
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#define CLK_GSCALER1 173
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#define CLK_GSCALER0 174
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#define CLK_QEMFC 175
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#define CLK_PPMUMFC_L 176
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#define CLK_SMMUMFC_L 177
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#define CLK_MFC 178
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#define CLK_SMMUG3D 179
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#define CLK_QEG3D 180
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#define CLK_PPMUG3D 181
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#define CLK_G3D 182
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#define CLK_QE_CH1_LCD 183
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#define CLK_QE_CH0_LCD 184
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#define CLK_PPMULCD0 185
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#define CLK_SMMUFIMD0 186
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#define CLK_DSIM0 187
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#define CLK_FIMD0 188
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#define CLK_CAM1 189
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#define CLK_UART_ISP_TOP 190
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#define CLK_SPI1_ISP_TOP 191
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#define CLK_SPI0_ISP_TOP 192
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#define CLK_TSADC 193
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#define CLK_PPMUFILE 194
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#define CLK_USBOTG 195
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#define CLK_USBHOST 196
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#define CLK_SROMC 197
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#define CLK_SDMMC1 198
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#define CLK_SDMMC0 199
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#define CLK_PDMA1 200
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#define CLK_PDMA0 201
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#define CLK_PWM 202
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#define CLK_PCM 203
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#define CLK_I2S 204
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#define CLK_SPI1 205
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#define CLK_SPI0 206
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#define CLK_I2C7 207
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#define CLK_I2C6 208
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#define CLK_I2C5 209
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#define CLK_I2C4 210
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#define CLK_I2C3 211
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#define CLK_I2C2 212
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#define CLK_I2C1 213
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#define CLK_I2C0 214
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#define CLK_UART1 215
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#define CLK_UART0 216
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#define CLK_BLOCK_LCD 217
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#define CLK_BLOCK_G3D 218
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#define CLK_BLOCK_MFC 219
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#define CLK_BLOCK_CAM 220
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#define CLK_SMIES 221
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#define CLK_UART2 222
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#define CLK_SDMMC2 223
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/* Special clocks */
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#define CLK_SCLK_JPEG 224
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#define CLK_SCLK_M2MSCALER 225
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#define CLK_SCLK_GSCALER1 226
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#define CLK_SCLK_GSCALER0 227
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#define CLK_SCLK_MFC 228
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#define CLK_SCLK_G3D 229
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#define CLK_SCLK_MIPIDPHY2L 230
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#define CLK_SCLK_MIPI0 231
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#define CLK_SCLK_FIMD0 232
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#define CLK_SCLK_CAM1 233
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#define CLK_SCLK_UART_ISP 234
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#define CLK_SCLK_SPI1_ISP 235
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#define CLK_SCLK_SPI0_ISP 236
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#define CLK_SCLK_UPLL 237
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#define CLK_SCLK_TSADC 238
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#define CLK_SCLK_EBI 239
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#define CLK_SCLK_MMC1 240
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#define CLK_SCLK_MMC0 241
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#define CLK_SCLK_I2S 242
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#define CLK_SCLK_PCM 243
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#define CLK_SCLK_SPI1 244
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#define CLK_SCLK_SPI0 245
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#define CLK_SCLK_UART1 246
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#define CLK_SCLK_UART0 247
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#define CLK_SCLK_UART2 248
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#define CLK_SCLK_MMC2 249
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/*
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* Total number of clocks of main CMU.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define CLK_NR_CLKS 250
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/*
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* CMU DMC
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*/
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#define CLK_FOUT_BPLL 1
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#define CLK_FOUT_EPLL 2
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/* Muxes */
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#define CLK_MOUT_MPLL_MIF 8
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#define CLK_MOUT_BPLL 9
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#define CLK_MOUT_DPHY 10
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#define CLK_MOUT_DMC_BUS 11
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#define CLK_MOUT_EPLL 12
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/* Dividers */
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#define CLK_DIV_DMC 16
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#define CLK_DIV_DPHY 17
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#define CLK_DIV_DMC_PRE 18
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#define CLK_DIV_DMCP 19
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#define CLK_DIV_DMCD 20
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/*
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* Total number of clocks of main CMU.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define NR_CLKS_DMC 21
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/*
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* CMU ISP
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*/
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/* Dividers */
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#define CLK_DIV_ISP1 1
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#define CLK_DIV_ISP0 2
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#define CLK_DIV_MCUISP1 3
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#define CLK_DIV_MCUISP0 4
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#define CLK_DIV_MPWM 5
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/* Gates */
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#define CLK_UART_ISP 8
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#define CLK_WDT_ISP 9
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#define CLK_PWM_ISP 10
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#define CLK_I2C1_ISP 11
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#define CLK_I2C0_ISP 12
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#define CLK_MPWM_ISP 13
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#define CLK_MCUCTL_ISP 14
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#define CLK_PPMUISPX 15
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#define CLK_PPMUISPMX 16
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#define CLK_QE_LITE1 17
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#define CLK_QE_LITE0 18
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#define CLK_QE_FD 19
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#define CLK_QE_DRC 20
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#define CLK_QE_ISP 21
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#define CLK_CSIS1 22
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#define CLK_SMMU_LITE1 23
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#define CLK_SMMU_LITE0 24
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#define CLK_SMMU_FD 25
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#define CLK_SMMU_DRC 26
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#define CLK_SMMU_ISP 27
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#define CLK_GICISP 28
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#define CLK_CSIS0 29
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#define CLK_MCUISP 30
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#define CLK_LITE1 31
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#define CLK_LITE0 32
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#define CLK_FD 33
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#define CLK_DRC 34
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#define CLK_ISP 35
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#define CLK_QE_ISPCX 36
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#define CLK_QE_SCALERP 37
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#define CLK_QE_SCALERC 38
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#define CLK_SMMU_SCALERP 39
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#define CLK_SMMU_SCALERC 40
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#define CLK_SCALERP 41
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#define CLK_SCALERC 42
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#define CLK_SPI1_ISP 43
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#define CLK_SPI0_ISP 44
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#define CLK_SMMU_ISPCX 45
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#define CLK_ASYNCAXIM 46
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#define CLK_SCLK_MPWM_ISP 47
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/*
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* Total number of clocks of CMU_ISP.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define NR_CLKS_ISP 48
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
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