250 lines
6.9 KiB
C
250 lines
6.9 KiB
C
#ifndef __ASM_POWERPC_PCI_H
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#define __ASM_POWERPC_PCI_H
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#ifdef __KERNEL__
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <asm/machdep.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm-generic/pci-dma-compat.h>
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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struct pci_dev;
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/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
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#define IOBASE_BRIDGE_NUMBER 0
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#define IOBASE_MEMORY 1
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#define IOBASE_IO 2
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#define IOBASE_ISA_IO 3
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#define IOBASE_ISA_MEM 4
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/*
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* Set this to 1 if you want the kernel to re-assign all PCI
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* bus numbers
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*/
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extern int pci_assign_all_buses;
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#define pcibios_assign_all_busses() (pci_assign_all_buses)
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#define pcibios_scan_all_fns(a, b) 0
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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if (ppc_md.pci_get_legacy_ide_irq)
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return ppc_md.pci_get_legacy_ide_irq(dev, channel);
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return channel ? 15 : 14;
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}
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#ifdef CONFIG_PPC64
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#define HAVE_ARCH_PCI_MWI 1
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static inline int pcibios_prep_mwi(struct pci_dev *dev)
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{
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/*
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* We would like to avoid touching the cacheline size or MWI bit
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* but we cant do that with the current pcibios_prep_mwi
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* interface. pSeries firmware sets the cacheline size (which is not
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* the cpu cacheline size in all cases) and hardware treats MWI
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* the same as memory write. So we dont touch the cacheline size
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* here and allow the generic code to set the MWI bit.
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*/
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return 0;
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}
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extern struct dma_mapping_ops pci_dma_ops;
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/* For DAC DMA, we currently don't support it by default, but
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* we let 64-bit platforms override this.
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*/
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static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
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{
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if (pci_dma_ops.dac_dma_supported)
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return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
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return 0;
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#endif
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extern int pci_domain_nr(struct pci_bus *bus);
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/* Decide whether to display the domain number in /proc */
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extern int pci_proc_domain(struct pci_bus *bus);
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#else /* 32-bit */
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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*strat = PCI_DMA_BURST_INFINITY;
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*strategy_parameter = ~0UL;
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}
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#endif
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/*
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* At present there are very few 32-bit PPC machines that can have
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* memory above the 4GB point, and we don't support that.
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*/
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#define pci_dac_dma_supported(pci_dev, mask) (0)
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/* Return the index of the PCI controller for device PDEV. */
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#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
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/* Set the name of the bus as it appears in /proc/bus/pci */
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return 0;
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}
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#endif /* CONFIG_PPC64 */
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struct vm_area_struct;
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/* Map a range of PCI memory or I/O space for a device into user space */
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int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
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#define HAVE_PCI_MMAP 1
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#ifdef CONFIG_PPC64
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/* The PCI address space does not equal the physical memory address
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* space (we have an IOMMU). The IDE and SCSI device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#else /* 32-bit */
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/* The PCI address space does equal the physical memory
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* address space (no IOMMU). The IDE and SCSI device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (1)
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/* pci_unmap_{page,single} is a nop so... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
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#define pci_unmap_addr(PTR, ADDR_NAME) (0)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
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#define pci_unmap_len(PTR, LEN_NAME) (0)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
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#endif /* CONFIG_PPC64 */
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extern void pcibios_resource_to_bus(struct pci_dev *dev,
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struct pci_bus_region *region,
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struct resource *res);
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extern void pcibios_bus_to_resource(struct pci_dev *dev,
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struct resource *res,
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struct pci_bus_region *region);
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static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
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struct resource *res)
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{
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struct resource *root = NULL;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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return root;
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}
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extern int unmap_bus_range(struct pci_bus *bus);
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extern int remap_bus_range(struct pci_bus *bus);
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extern void pcibios_fixup_device_resources(struct pci_dev *dev,
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struct pci_bus *bus);
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extern void pcibios_claim_one_bus(struct pci_bus *b);
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extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
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extern struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn);
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extern void of_scan_pci_bridge(struct device_node *node,
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struct pci_dev *dev);
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extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
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extern int pci_read_irq_line(struct pci_dev *dev);
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extern void pcibios_add_platform_entries(struct pci_dev *dev);
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struct file;
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extern pgprot_t pci_phys_mem_access_prot(struct file *file,
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unsigned long pfn,
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unsigned long size,
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pgprot_t prot);
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#if defined(CONFIG_PPC_MULTIPLATFORM) || defined(CONFIG_PPC32)
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#define HAVE_ARCH_PCI_RESOURCE_TO_USER
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extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc,
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resource_size_t *start, resource_size_t *end);
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#endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_PCI_H */
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