839 lines
30 KiB
C
839 lines
30 KiB
C
#ifdef __KERNEL__
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#ifndef _ASM_POWERPC_IRQ_H
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#define _ASM_POWERPC_IRQ_H
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <linux/list.h>
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#include <linux/radix-tree.h>
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#include <asm/types.h>
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#include <asm/atomic.h>
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#define get_irq_desc(irq) (&irq_desc[(irq)])
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/* Define a way to iterate across irqs. */
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#define for_each_irq(i) \
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for ((i) = 0; (i) < NR_IRQS; ++(i))
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extern atomic_t ppc_n_lost_interrupts;
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#ifdef CONFIG_PPC_MERGE
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/* This number is used when no interrupt has been assigned */
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#define NO_IRQ (0)
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/* This is a special irq number to return from get_irq() to tell that
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* no interrupt happened _and_ ignore it (don't count it as bad). Some
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* platforms like iSeries rely on that.
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*/
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#define NO_IRQ_IGNORE ((unsigned int)-1)
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/* Total number of virq in the platform (make it a CONFIG_* option ? */
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#define NR_IRQS 512
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/* Number of irqs reserved for the legacy controller */
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#define NUM_ISA_INTERRUPTS 16
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/* This type is the placeholder for a hardware interrupt number. It has to
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* be big enough to enclose whatever representation is used by a given
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* platform.
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*/
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typedef unsigned long irq_hw_number_t;
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/* Interrupt controller "host" data structure. This could be defined as a
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* irq domain controller. That is, it handles the mapping between hardware
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* and virtual interrupt numbers for a given interrupt domain. The host
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* structure is generally created by the PIC code for a given PIC instance
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* (though a host can cover more than one PIC if they have a flat number
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* model). It's the host callbacks that are responsible for setting the
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* irq_chip on a given irq_desc after it's been mapped.
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*
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* The host code and data structures are fairly agnostic to the fact that
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* we use an open firmware device-tree. We do have references to struct
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* device_node in two places: in irq_find_host() to find the host matching
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* a given interrupt controller node, and of course as an argument to its
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* counterpart host->ops->match() callback. However, those are treated as
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* generic pointers by the core and the fact that it's actually a device-node
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* pointer is purely a convention between callers and implementation. This
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* code could thus be used on other architectures by replacing those two
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* by some sort of arch-specific void * "token" used to identify interrupt
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* controllers.
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*/
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struct irq_host;
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struct radix_tree_root;
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/* Functions below are provided by the host and called whenever a new mapping
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* is created or an old mapping is disposed. The host can then proceed to
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* whatever internal data structures management is required. It also needs
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* to setup the irq_desc when returning from map().
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*/
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struct irq_host_ops {
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/* Match an interrupt controller device node to a host, returns
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* 1 on a match
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*/
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int (*match)(struct irq_host *h, struct device_node *node);
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/* Create or update a mapping between a virtual irq number and a hw
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* irq number. This is called only once for a given mapping.
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*/
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int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
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/* Dispose of such a mapping */
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void (*unmap)(struct irq_host *h, unsigned int virq);
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/* Translate device-tree interrupt specifier from raw format coming
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* from the firmware to a irq_hw_number_t (interrupt line number) and
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* type (sense) that can be passed to set_irq_type(). In the absence
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* of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
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* will return the hw number in the first cell and IRQ_TYPE_NONE for
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* the type (which amount to keeping whatever default value the
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* interrupt controller has for that line)
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*/
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int (*xlate)(struct irq_host *h, struct device_node *ctrler,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type);
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};
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struct irq_host {
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struct list_head link;
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/* type of reverse mapping technique */
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unsigned int revmap_type;
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#define IRQ_HOST_MAP_LEGACY 0 /* legacy 8259, gets irqs 1..15 */
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#define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
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#define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
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#define IRQ_HOST_MAP_TREE 3 /* radix tree */
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union {
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struct {
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unsigned int size;
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unsigned int *revmap;
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} linear;
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struct radix_tree_root tree;
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} revmap_data;
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struct irq_host_ops *ops;
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void *host_data;
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irq_hw_number_t inval_irq;
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};
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/* The main irq map itself is an array of NR_IRQ entries containing the
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* associate host and irq number. An entry with a host of NULL is free.
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* An entry can be allocated if it's free, the allocator always then sets
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* hwirq first to the host's invalid irq number and then fills ops.
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*/
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struct irq_map_entry {
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irq_hw_number_t hwirq;
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struct irq_host *host;
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};
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extern struct irq_map_entry irq_map[NR_IRQS];
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/**
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* irq_alloc_host - Allocate a new irq_host data structure
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* @node: device-tree node of the interrupt controller
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* @revmap_type: type of reverse mapping to use
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* @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
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* @ops: map/unmap host callbacks
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* @inval_irq: provide a hw number in that host space that is always invalid
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*
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* Allocates and initialize and irq_host structure. Note that in the case of
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* IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
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* for all legacy interrupts except 0 (which is always the invalid irq for
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* a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
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* this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
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* later during boot automatically (the reverse mapping will use the slow path
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* until that happens).
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*/
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extern struct irq_host *irq_alloc_host(unsigned int revmap_type,
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unsigned int revmap_arg,
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struct irq_host_ops *ops,
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irq_hw_number_t inval_irq);
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/**
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* irq_find_host - Locates a host for a given device node
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* @node: device-tree node of the interrupt controller
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*/
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extern struct irq_host *irq_find_host(struct device_node *node);
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/**
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* irq_set_default_host - Set a "default" host
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* @host: default host pointer
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*
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* For convenience, it's possible to set a "default" host that will be used
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* whenever NULL is passed to irq_create_mapping(). It makes life easier for
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* platforms that want to manipulate a few hard coded interrupt numbers that
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* aren't properly represented in the device-tree.
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*/
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extern void irq_set_default_host(struct irq_host *host);
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/**
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* irq_set_virq_count - Set the maximum number of virt irqs
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* @count: number of linux virtual irqs, capped with NR_IRQS
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*
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* This is mainly for use by platforms like iSeries who want to program
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* the virtual irq number in the controller to avoid the reverse mapping
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*/
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extern void irq_set_virq_count(unsigned int count);
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/**
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* irq_create_mapping - Map a hardware interrupt into linux virq space
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* @host: host owning this hardware interrupt or NULL for default host
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* @hwirq: hardware irq number in that host space
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*
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* Only one mapping per hardware interrupt is permitted. Returns a linux
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* virq number.
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* If the sense/trigger is to be specified, set_irq_type() should be called
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* on the number returned from that call.
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*/
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extern unsigned int irq_create_mapping(struct irq_host *host,
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irq_hw_number_t hwirq);
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/**
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* irq_dispose_mapping - Unmap an interrupt
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* @virq: linux virq number of the interrupt to unmap
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*/
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extern void irq_dispose_mapping(unsigned int virq);
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/**
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* irq_find_mapping - Find a linux virq from an hw irq number.
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* @host: host owning this hardware interrupt
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* @hwirq: hardware irq number in that host space
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*
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* This is a slow path, for use by generic code. It's expected that an
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* irq controller implementation directly calls the appropriate low level
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* mapping function.
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*/
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extern unsigned int irq_find_mapping(struct irq_host *host,
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irq_hw_number_t hwirq);
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/**
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* irq_radix_revmap - Find a linux virq from a hw irq number.
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* @host: host owning this hardware interrupt
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* @hwirq: hardware irq number in that host space
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*
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* This is a fast path, for use by irq controller code that uses radix tree
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* revmaps
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*/
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extern unsigned int irq_radix_revmap(struct irq_host *host,
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irq_hw_number_t hwirq);
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/**
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* irq_linear_revmap - Find a linux virq from a hw irq number.
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* @host: host owning this hardware interrupt
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* @hwirq: hardware irq number in that host space
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*
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* This is a fast path, for use by irq controller code that uses linear
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* revmaps. It does fallback to the slow path if the revmap doesn't exist
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* yet and will create the revmap entry with appropriate locking
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*/
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extern unsigned int irq_linear_revmap(struct irq_host *host,
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irq_hw_number_t hwirq);
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/**
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* irq_alloc_virt - Allocate virtual irq numbers
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* @host: host owning these new virtual irqs
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* @count: number of consecutive numbers to allocate
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* @hint: pass a hint number, the allocator will try to use a 1:1 mapping
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*
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* This is a low level function that is used internally by irq_create_mapping()
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* and that can be used by some irq controllers implementations for things
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* like allocating ranges of numbers for MSIs. The revmaps are left untouched.
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*/
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extern unsigned int irq_alloc_virt(struct irq_host *host,
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unsigned int count,
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unsigned int hint);
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/**
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* irq_free_virt - Free virtual irq numbers
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* @virq: virtual irq number of the first interrupt to free
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* @count: number of interrupts to free
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*
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* This function is the opposite of irq_alloc_virt. It will not clear reverse
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* maps, this should be done previously by unmap'ing the interrupt. In fact,
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* all interrupts covered by the range being freed should have been unmapped
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* prior to calling this.
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*/
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extern void irq_free_virt(unsigned int virq, unsigned int count);
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/* -- OF helpers -- */
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/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
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* @controller: Device node of the interrupt controller
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* @inspec: Interrupt specifier from the device-tree
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* @intsize: Size of the interrupt specifier from the device-tree
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*
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* This function is identical to irq_create_mapping except that it takes
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* as input informations straight from the device-tree (typically the results
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* of the of_irq_map_*() functions.
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*/
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extern unsigned int irq_create_of_mapping(struct device_node *controller,
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u32 *intspec, unsigned int intsize);
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/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
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* @device: Device node of the device whose interrupt is to be mapped
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* @index: Index of the interrupt to map
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*
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* This function is a wrapper that chains of_irq_map_one() and
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* irq_create_of_mapping() to make things easier to callers
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*/
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extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
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/* -- End OF helpers -- */
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/**
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* irq_early_init - Init irq remapping subsystem
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*/
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extern void irq_early_init(void);
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static __inline__ int irq_canonicalize(int irq)
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{
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return irq;
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}
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#else /* CONFIG_PPC_MERGE */
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/* This number is used when no interrupt has been assigned */
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#define NO_IRQ (-1)
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#define NO_IRQ_IGNORE (-2)
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/*
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* These constants are used for passing information about interrupt
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* signal polarity and level/edge sensing to the low-level PIC chip
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* drivers.
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*/
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#define IRQ_SENSE_MASK 0x1
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#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
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#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
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#define IRQ_POLARITY_MASK 0x2
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#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
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#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
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#if defined(CONFIG_40x)
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#include <asm/ibm4xx.h>
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#ifndef NR_BOARD_IRQS
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#define NR_BOARD_IRQS 0
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#endif
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#ifndef UIC_WIDTH /* Number of interrupts per device */
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#define UIC_WIDTH 32
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#endif
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#ifndef NR_UICS /* number of UIC devices */
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#define NR_UICS 1
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#endif
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#if defined (CONFIG_403)
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/*
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* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
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* 32 possible interrupts, a majority of which are not implemented on
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* all cores. There are six configurable, external interrupt pins and
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* there are eight internal interrupts for the on-chip serial port
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* (SPU), DMA controller, and JTAG controller.
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*
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*/
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#define NR_AIC_IRQS 32
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#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
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#elif !defined (CONFIG_403)
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/*
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* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
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* possible interrupts as well. There are seven, configurable external
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* interrupt pins and there are 17 internal interrupts for the on-chip
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* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
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*
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*/
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#define NR_UIC_IRQS UIC_WIDTH
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#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
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#endif
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#elif defined(CONFIG_44x)
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#include <asm/ibm44x.h>
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#define NR_UIC_IRQS 32
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#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
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#elif defined(CONFIG_8xx)
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/* Now include the board configuration specific associations.
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*/
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#include <asm/mpc8xx.h>
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/* The MPC8xx cores have 16 possible interrupts. There are eight
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* possible level sensitive interrupts assigned and generated internally
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* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
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* There are eight external interrupts (IRQs) that can be configured
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* as either level or edge sensitive.
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*
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* On some implementations, there is also the possibility of an 8259
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* through the PCI and PCI-ISA bridges.
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*
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* We are "flattening" the interrupt vectors of the cascaded CPM
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* and 8259 interrupt controllers so that we can uniquely identify
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* any interrupt source with a single integer.
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*/
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#define NR_SIU_INTS 16
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#define NR_CPM_INTS 32
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#ifndef NR_8259_INTS
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#define NR_8259_INTS 0
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#endif
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#define SIU_IRQ_OFFSET 0
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#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
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#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
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#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
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/* These values must be zero-based and map 1:1 with the SIU configuration.
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* They are used throughout the 8xx I/O subsystem to generate
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* interrupt masks, flags, and other control patterns. This is why the
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* current kernel assumption of the 8259 as the base controller is such
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* a pain in the butt.
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*/
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#define SIU_IRQ0 (0) /* Highest priority */
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#define SIU_LEVEL0 (1)
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#define SIU_IRQ1 (2)
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#define SIU_LEVEL1 (3)
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#define SIU_IRQ2 (4)
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#define SIU_LEVEL2 (5)
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#define SIU_IRQ3 (6)
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#define SIU_LEVEL3 (7)
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#define SIU_IRQ4 (8)
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#define SIU_LEVEL4 (9)
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#define SIU_IRQ5 (10)
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#define SIU_LEVEL5 (11)
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#define SIU_IRQ6 (12)
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#define SIU_LEVEL6 (13)
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#define SIU_IRQ7 (14)
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#define SIU_LEVEL7 (15)
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#define MPC8xx_INT_FEC1 SIU_LEVEL1
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#define MPC8xx_INT_FEC2 SIU_LEVEL3
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#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
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#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
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#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
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#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
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#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
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#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
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/* The internal interrupts we can configure as we see fit.
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* My personal preference is CPM at level 2, which puts it above the
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* MBX PCI/ISA/IDE interrupts.
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*/
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#ifndef PIT_INTERRUPT
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#define PIT_INTERRUPT SIU_LEVEL0
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#endif
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#ifndef CPM_INTERRUPT
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#define CPM_INTERRUPT SIU_LEVEL2
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#endif
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#ifndef PCMCIA_INTERRUPT
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#define PCMCIA_INTERRUPT SIU_LEVEL6
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#endif
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#ifndef DEC_INTERRUPT
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#define DEC_INTERRUPT SIU_LEVEL7
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#endif
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/* Some internal interrupt registers use an 8-bit mask for the interrupt
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* level instead of a number.
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*/
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#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
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#elif defined(CONFIG_83xx)
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#include <asm/mpc83xx.h>
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#define NR_IRQS (NR_IPIC_INTS)
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#elif defined(CONFIG_85xx)
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/* Now include the board configuration specific associations.
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*/
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#include <asm/mpc85xx.h>
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/* The MPC8548 openpic has 48 internal interrupts and 12 external
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* interrupts.
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*
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* We are "flattening" the interrupt vectors of the cascaded CPM
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* so that we can uniquely identify any interrupt source with a
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* single integer.
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*/
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|
#define NR_CPM_INTS 64
|
|
#define NR_EPIC_INTS 60
|
|
#ifndef NR_8259_INTS
|
|
#define NR_8259_INTS 0
|
|
#endif
|
|
#define NUM_8259_INTERRUPTS NR_8259_INTS
|
|
|
|
#ifndef CPM_IRQ_OFFSET
|
|
#define CPM_IRQ_OFFSET 0
|
|
#endif
|
|
|
|
#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
|
|
|
|
/* Internal IRQs on MPC85xx OpenPIC */
|
|
|
|
#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
|
|
#ifdef CONFIG_CPM2
|
|
#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
|
|
#else
|
|
#define MPC85xx_OPENPIC_IRQ_OFFSET 0
|
|
#endif
|
|
#endif
|
|
|
|
/* Not all of these exist on all MPC85xx implementations */
|
|
#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
|
|
/* The 12 external interrupt lines */
|
|
#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
|
|
|
|
/* CPM related interrupts */
|
|
#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
|
|
|
|
#elif defined(CONFIG_PPC_86xx)
|
|
#include <asm/mpc86xx.h>
|
|
|
|
#define NR_EPIC_INTS 48
|
|
#ifndef NR_8259_INTS
|
|
#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
|
|
#endif
|
|
#define NUM_8259_INTERRUPTS NR_8259_INTS
|
|
|
|
#ifndef I8259_OFFSET
|
|
#define I8259_OFFSET 0
|
|
#endif
|
|
|
|
#define NR_IRQS 256
|
|
|
|
/* Internal IRQs on MPC86xx OpenPIC */
|
|
|
|
#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
|
|
#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
|
|
#endif
|
|
|
|
/* The 48 internal sources */
|
|
#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
|
|
/* no 10,11 */
|
|
#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
/* no 25 */
|
|
#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
/* no 29,30,31 */
|
|
#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
/* no 35,36 */
|
|
#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
|
|
/* The 12 external interrupt lines */
|
|
#define MPC86xx_IRQ_EXT_BASE 48
|
|
#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
|
|
+ MPC86xx_OPENPIC_IRQ_OFFSET)
|
|
|
|
#else /* CONFIG_40x + CONFIG_8xx */
|
|
/*
|
|
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
|
|
* so it is the max of them all
|
|
*/
|
|
#define NR_IRQS 256
|
|
#define __DO_IRQ_CANON 1
|
|
|
|
#ifndef CONFIG_8260
|
|
|
|
#define NUM_8259_INTERRUPTS 16
|
|
|
|
#else /* CONFIG_8260 */
|
|
|
|
/* The 8260 has an internal interrupt controller with a maximum of
|
|
* 64 IRQs. We will use NR_IRQs from above since it is large enough.
|
|
* Don't be confused by the 8260 documentation where they list an
|
|
* "interrupt number" and "interrupt vector". We are only interested
|
|
* in the interrupt vector. There are "reserved" holes where the
|
|
* vector number increases, but the interrupt number in the table does not.
|
|
* (Document errata updates have fixed this...make sure you have up to
|
|
* date processor documentation -- Dan).
|
|
*/
|
|
|
|
#ifndef CPM_IRQ_OFFSET
|
|
#define CPM_IRQ_OFFSET 0
|
|
#endif
|
|
|
|
#define NR_CPM_INTS 64
|
|
|
|
#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
|
|
#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
|
|
|
|
#endif /* CONFIG_8260 */
|
|
|
|
#endif /* Whatever way too big #ifdef */
|
|
|
|
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
|
/* pedantic: these are long because they are used with set_bit --RR */
|
|
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
|
|
|
|
/*
|
|
* Because many systems have two overlapping names spaces for
|
|
* interrupts (ISA and XICS for example), and the ISA interrupts
|
|
* have historically not been easy to renumber, we allow ISA
|
|
* interrupts to take values 0 - 15, and shift up the remaining
|
|
* interrupts by 0x10.
|
|
*/
|
|
#define NUM_ISA_INTERRUPTS 0x10
|
|
extern int __irq_offset_value;
|
|
|
|
static inline int irq_offset_up(int irq)
|
|
{
|
|
return(irq + __irq_offset_value);
|
|
}
|
|
|
|
static inline int irq_offset_down(int irq)
|
|
{
|
|
return(irq - __irq_offset_value);
|
|
}
|
|
|
|
static inline int irq_offset_value(void)
|
|
{
|
|
return __irq_offset_value;
|
|
}
|
|
|
|
#ifdef __DO_IRQ_CANON
|
|
extern int ppc_do_canonicalize_irqs;
|
|
#else
|
|
#define ppc_do_canonicalize_irqs 0
|
|
#endif
|
|
|
|
static __inline__ int irq_canonicalize(int irq)
|
|
{
|
|
if (ppc_do_canonicalize_irqs && irq == 2)
|
|
irq = 9;
|
|
return irq;
|
|
}
|
|
#endif /* CONFIG_PPC_MERGE */
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extern int distribute_irqs;
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struct irqaction;
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struct pt_regs;
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#define __ARCH_HAS_DO_SOFTIRQ
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extern void __do_softirq(void);
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#ifdef CONFIG_IRQSTACKS
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/*
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* Per-cpu stacks for handling hard and soft interrupts.
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*/
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extern struct thread_info *hardirq_ctx[NR_CPUS];
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extern struct thread_info *softirq_ctx[NR_CPUS];
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extern void irq_ctx_init(void);
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extern void call_do_softirq(struct thread_info *tp);
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extern int call_handle_irq(int irq, void *p1,
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struct thread_info *tp, void *func);
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#else
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#define irq_ctx_init()
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#endif /* CONFIG_IRQSTACKS */
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extern void do_IRQ(struct pt_regs *regs);
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#endif /* _ASM_IRQ_H */
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#endif /* __KERNEL__ */
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