129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/****************************************************************************/
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/*
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* mcfsim.h -- ColdFire System Integration Module support.
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*
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* (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef mcfsim_h
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#define mcfsim_h
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/****************************************************************************/
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/*
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* Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282,
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* 5307 or 5407 specific addresses.
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*/
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#if defined(CONFIG_M5204)
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#include <asm/m5204sim.h>
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#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
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#include <asm/m5206sim.h>
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#elif defined(CONFIG_M520x)
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#include <asm/m520xsim.h>
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#elif defined(CONFIG_M523x)
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#include <asm/m523xsim.h>
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#elif defined(CONFIG_M5249)
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#include <asm/m5249sim.h>
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#elif defined(CONFIG_M527x)
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#include <asm/m527xsim.h>
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#elif defined(CONFIG_M5272)
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#include <asm/m5272sim.h>
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#elif defined(CONFIG_M528x)
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#include <asm/m528xsim.h>
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#elif defined(CONFIG_M5307)
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#include <asm/m5307sim.h>
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#elif defined(CONFIG_M532x)
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#include <asm/m532xsim.h>
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#elif defined(CONFIG_M5407)
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#include <asm/m5407sim.h>
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#endif
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/*
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* Define the base address of the SIM within the MBAR address space.
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*/
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#define MCFSIM_BASE 0x0 /* Base address of SIM */
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/*
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* Bit definitions for the ICR family of registers.
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*/
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#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
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#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
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#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
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#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
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#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
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#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
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#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
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#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
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#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
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#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
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#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
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#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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/*
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* Bit definitions for the Interrupt Mask register (IMR).
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*/
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#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
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#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
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#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
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#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
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#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
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#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
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#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
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#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
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#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
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#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
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#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
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#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
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#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
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#if defined(CONFIG_M5206e)
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#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
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#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
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#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
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#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
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#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
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#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
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#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
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#endif
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/*
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* Mask for all of the SIM devices. Some parts have more or less
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* SIM devices. This is a catchall for the sandard set.
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*/
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#ifndef MCFSIM_IMR_MASKALL
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#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
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#endif
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/*
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* PIT interrupt settings, if not found in mXXXXsim.h file.
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*/
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#ifndef ICR_INTRCONF
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#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
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#endif
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#ifndef MCFPIT_IMR
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#define MCFPIT_IMR MCFINTC_IMRH
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#endif
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#ifndef MCFPIT_IMR_IBIT
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#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
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#endif
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#ifndef __ASSEMBLY__
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/*
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* Definition for the interrupt auto-vectoring support.
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*/
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extern void mcf_autovector(unsigned int vec);
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#endif /* __ASSEMBLY__ */
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/****************************************************************************/
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#endif /* mcfsim_h */
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