287 lines
7.9 KiB
C
287 lines
7.9 KiB
C
#ifndef __ASM_AVR32_IO_H
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#define __ASM_AVR32_IO_H
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#include <linux/string.h>
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#ifdef __KERNEL__
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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/* virt_to_phys will only work when address is in P1 or P2 */
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static __inline__ unsigned long virt_to_phys(volatile void *address)
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{
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return PHYSADDR(address);
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}
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static __inline__ void * phys_to_virt(unsigned long address)
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{
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return (void *)P1SEGADDR(address);
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}
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#define cached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
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#define uncached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
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#define phys_to_cached(addr) ((void *)P1SEGADDR(addr))
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#define phys_to_uncached(addr) ((void *)P2SEGADDR(addr))
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
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extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
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extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
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extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
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extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
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extern void __raw_readsl(unsigned int addr, void *data, int longlen);
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static inline void writeb(unsigned char b, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *)addr = b;
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}
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static inline void writew(unsigned short b, volatile void __iomem *addr)
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{
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*(volatile unsigned short __force *)addr = b;
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}
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static inline void writel(unsigned int b, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *)addr = b;
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}
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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static inline unsigned char readb(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned char __force *)addr;
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}
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static inline unsigned short readw(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned short __force *)addr;
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}
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static inline unsigned int readl(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned int __force *)addr;
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}
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l)
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#define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l)
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#define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l)
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#define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l)
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#define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l)
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#define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l)
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/*
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* io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
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*/
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#ifndef ioread8
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#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
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#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
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#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
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#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
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#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
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#define iowrite8(v,p) __raw_writeb(v, p)
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#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
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#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p)
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#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
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#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p)
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#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
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#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
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#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
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#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
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#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
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#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
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#endif
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/*
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* These two are only here because ALSA _thinks_ it needs them...
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*/
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static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
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unsigned long count)
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{
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char *p = to;
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while (count) {
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count--;
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*p = readb(from);
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p++;
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from++;
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}
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}
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static inline void memcpy_toio(volatile void __iomem *to, const void * from,
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unsigned long count)
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{
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const char *p = from;
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while (count) {
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count--;
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writeb(*p, to);
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p++;
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to++;
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}
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}
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static inline void memset_io(volatile void __iomem *addr, unsigned char val,
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unsigned long count)
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{
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memset((void __force *)addr, val, count);
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}
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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#define IO_SPACE_LIMIT 0xffffffff
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/* Convert I/O port address to virtual address */
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#define __io(p) ((void __iomem *)phys_to_uncached(p))
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/*
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* IO port access primitives
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* -------------------------
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*
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* The AVR32 doesn't have special IO access instructions; all IO is memory
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* mapped. Note that these are defined to perform little endian accesses
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* only. Their primary purpose is to access PCI and ISA peripherals.
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*
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* Note that for a big endian machine, this implies that the following
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* big endian mode connectivity is in place.
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*
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* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#define outb(v, p) __raw_writeb(v, __io(p))
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#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
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#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
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#define inb(p) __raw_readb(__io(p))
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#define inw(p) le16_to_cpu(__raw_readw(__io(p)))
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#define inl(p) le32_to_cpu(__raw_readl(__io(p)))
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static inline void __outsb(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outb(*(u8 *)addr, port);
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addr++;
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}
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}
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static inline void __insb(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u8 *)addr = inb(port);
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addr++;
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}
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}
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static inline void __outsw(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outw(*(u16 *)addr, port);
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addr += 2;
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}
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}
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static inline void __insw(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u16 *)addr = inw(port);
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addr += 2;
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}
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}
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static inline void __outsl(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outl(*(u32 *)addr, port);
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addr += 4;
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}
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}
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static inline void __insl(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u32 *)addr = inl(port);
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addr += 4;
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}
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}
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#define outsb(port, addr, count) __outsb(port, addr, count)
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#define insb(port, addr, count) __insb(port, addr, count)
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#define outsw(port, addr, count) __outsw(port, addr, count)
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#define insw(port, addr, count) __insw(port, addr, count)
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#define outsl(port, addr, count) __outsl(port, addr, count)
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#define insl(port, addr, count) __insl(port, addr, count)
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extern void __iomem *__ioremap(unsigned long offset, size_t size,
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unsigned long flags);
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extern void __iounmap(void __iomem *addr);
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/*
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* ioremap - map bus memory into CPU space
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* @offset bus address of the memory
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* @size size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to make
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* bus memory CPU accessible via the readb/.../writel functions and
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* the other mmio helpers. The returned address is not guaranteed to
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* be usable directly as a virtual address.
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*/
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#define ioremap(offset, size) \
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__ioremap((offset), (size), 0)
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#define iounmap(addr) \
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__iounmap(addr)
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#define cached(addr) P1SEGADDR(addr)
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#define uncached(addr) P2SEGADDR(addr)
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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#define page_to_bus page_to_phys
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#define bus_to_page phys_to_page
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#define dma_cache_wback_inv(_start, _size) \
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flush_dcache_region(_start, _size)
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#define dma_cache_inv(_start, _size) \
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invalidate_dcache_region(_start, _size)
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#define dma_cache_wback(_start, _size) \
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clean_dcache_region(_start, _size)
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_AVR32_IO_H */
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