1093 lines
24 KiB
ArmAsm
1093 lines
24 KiB
ArmAsm
/*
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* PARISC TLB and cache flushing support
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* Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
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* Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
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* Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* NOTE: fdc,fic, and pdc instructions that use base register modification
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* should only use index and base registers that are not shadowed,
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* so that the fast path emulation in the non access miss handler
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* can be used.
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*/
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#ifdef CONFIG_64BIT
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#define ADDIB addib,*
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#define CMPB cmpb,*
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#define ANDCM andcm,*
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.level 2.0w
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#else
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#define ADDIB addib,
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#define CMPB cmpb,
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#define ANDCM andcm
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.level 2.0
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#endif
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#include <asm/psw.h>
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#include <asm/assembly.h>
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#include <asm/pgtable.h>
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#include <asm/cache.h>
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.text
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.align 128
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.export flush_tlb_all_local,code
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flush_tlb_all_local:
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.proc
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.callinfo NO_CALLS
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.entry
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/*
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* The pitlbe and pdtlbe instructions should only be used to
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* flush the entire tlb. Also, there needs to be no intervening
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* tlb operations, e.g. tlb misses, so the operation needs
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* to happen in real mode with all interruptions disabled.
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*/
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/* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
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rsm PSW_SM_I, %r19 /* save I-bit state */
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load32 PA(1f), %r1
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nop
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nop
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nop
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nop
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nop
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rsm PSW_SM_Q, %r0 /* prep to load iia queue */
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mtctl %r0, %cr17 /* Clear IIASQ tail */
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mtctl %r0, %cr17 /* Clear IIASQ head */
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mtctl %r1, %cr18 /* IIAOQ head */
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ldo 4(%r1), %r1
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mtctl %r1, %cr18 /* IIAOQ tail */
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load32 REAL_MODE_PSW, %r1
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mtctl %r1, %ipsw
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rfi
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nop
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1: load32 PA(cache_info), %r1
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/* Flush Instruction Tlb */
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LDREG ITLB_SID_BASE(%r1), %r20
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LDREG ITLB_SID_STRIDE(%r1), %r21
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LDREG ITLB_SID_COUNT(%r1), %r22
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LDREG ITLB_OFF_BASE(%r1), %arg0
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LDREG ITLB_OFF_STRIDE(%r1), %arg1
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LDREG ITLB_OFF_COUNT(%r1), %arg2
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LDREG ITLB_LOOP(%r1), %arg3
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ADDIB= -1, %arg3, fitoneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
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copy %arg0, %r28 /* Init base addr */
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fitmanyloop: /* Loop if LOOP >= 2 */
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mtsp %r20, %sr1
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add %r21, %r20, %r20 /* increment space */
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copy %arg2, %r29 /* Init middle loop count */
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fitmanymiddle: /* Loop if LOOP >= 2 */
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ADDIB> -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
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pitlbe 0(%sr1, %r28)
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pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
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ADDIB> -1, %r29, fitmanymiddle /* Middle loop decr */
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copy %arg3, %r31 /* Re-init inner loop count */
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movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
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ADDIB<=,n -1, %r22, fitdone /* Outer loop count decr */
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fitoneloop: /* Loop if LOOP = 1 */
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mtsp %r20, %sr1
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copy %arg0, %r28 /* init base addr */
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copy %arg2, %r29 /* init middle loop count */
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fitonemiddle: /* Loop if LOOP = 1 */
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ADDIB> -1, %r29, fitonemiddle /* Middle loop count decr */
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pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
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ADDIB> -1, %r22, fitoneloop /* Outer loop count decr */
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add %r21, %r20, %r20 /* increment space */
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fitdone:
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/* Flush Data Tlb */
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LDREG DTLB_SID_BASE(%r1), %r20
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LDREG DTLB_SID_STRIDE(%r1), %r21
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LDREG DTLB_SID_COUNT(%r1), %r22
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LDREG DTLB_OFF_BASE(%r1), %arg0
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LDREG DTLB_OFF_STRIDE(%r1), %arg1
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LDREG DTLB_OFF_COUNT(%r1), %arg2
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LDREG DTLB_LOOP(%r1), %arg3
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ADDIB= -1, %arg3, fdtoneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
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copy %arg0, %r28 /* Init base addr */
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fdtmanyloop: /* Loop if LOOP >= 2 */
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mtsp %r20, %sr1
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add %r21, %r20, %r20 /* increment space */
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copy %arg2, %r29 /* Init middle loop count */
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fdtmanymiddle: /* Loop if LOOP >= 2 */
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ADDIB> -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
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pdtlbe 0(%sr1, %r28)
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pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
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ADDIB> -1, %r29, fdtmanymiddle /* Middle loop decr */
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copy %arg3, %r31 /* Re-init inner loop count */
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movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
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ADDIB<=,n -1, %r22,fdtdone /* Outer loop count decr */
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fdtoneloop: /* Loop if LOOP = 1 */
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mtsp %r20, %sr1
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copy %arg0, %r28 /* init base addr */
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copy %arg2, %r29 /* init middle loop count */
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fdtonemiddle: /* Loop if LOOP = 1 */
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ADDIB> -1, %r29, fdtonemiddle /* Middle loop count decr */
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pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
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ADDIB> -1, %r22, fdtoneloop /* Outer loop count decr */
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add %r21, %r20, %r20 /* increment space */
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fdtdone:
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/*
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* Switch back to virtual mode
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*/
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/* pcxt_ssm_bug */
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rsm PSW_SM_I, %r0
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load32 2f, %r1
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nop
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nop
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nop
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nop
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nop
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rsm PSW_SM_Q, %r0 /* prep to load iia queue */
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mtctl %r0, %cr17 /* Clear IIASQ tail */
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mtctl %r0, %cr17 /* Clear IIASQ head */
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mtctl %r1, %cr18 /* IIAOQ head */
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ldo 4(%r1), %r1
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mtctl %r1, %cr18 /* IIAOQ tail */
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load32 KERNEL_PSW, %r1
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or %r1, %r19, %r1 /* I-bit to state on entry */
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mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
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rfi
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nop
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2: bv %r0(%r2)
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nop
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.exit
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.procend
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.export flush_instruction_cache_local,code
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.import cache_info,data
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flush_instruction_cache_local:
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.proc
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.callinfo NO_CALLS
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.entry
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mtsp %r0, %sr1
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load32 cache_info, %r1
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/* Flush Instruction Cache */
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LDREG ICACHE_BASE(%r1), %arg0
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LDREG ICACHE_STRIDE(%r1), %arg1
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LDREG ICACHE_COUNT(%r1), %arg2
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LDREG ICACHE_LOOP(%r1), %arg3
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rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
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ADDIB= -1, %arg3, fioneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
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fimanyloop: /* Loop if LOOP >= 2 */
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ADDIB> -1, %r31, fimanyloop /* Adjusted inner loop decr */
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fice %r0(%sr1, %arg0)
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fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
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movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
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ADDIB<=,n -1, %arg2, fisync /* Outer loop decr */
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fioneloop: /* Loop if LOOP = 1 */
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ADDIB> -1, %arg2, fioneloop /* Outer loop count decr */
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fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
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fisync:
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sync
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mtsm %r22 /* restore I-bit */
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bv %r0(%r2)
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nop
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.exit
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.procend
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.export flush_data_cache_local, code
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.import cache_info, data
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flush_data_cache_local:
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.proc
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.callinfo NO_CALLS
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.entry
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mtsp %r0, %sr1
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load32 cache_info, %r1
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/* Flush Data Cache */
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LDREG DCACHE_BASE(%r1), %arg0
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LDREG DCACHE_STRIDE(%r1), %arg1
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LDREG DCACHE_COUNT(%r1), %arg2
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LDREG DCACHE_LOOP(%r1), %arg3
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rsm PSW_SM_I, %r22
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ADDIB= -1, %arg3, fdoneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
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fdmanyloop: /* Loop if LOOP >= 2 */
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ADDIB> -1, %r31, fdmanyloop /* Adjusted inner loop decr */
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fdce %r0(%sr1, %arg0)
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fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
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movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
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ADDIB<=,n -1, %arg2, fdsync /* Outer loop decr */
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fdoneloop: /* Loop if LOOP = 1 */
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ADDIB> -1, %arg2, fdoneloop /* Outer loop count decr */
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fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
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fdsync:
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syncdma
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sync
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mtsm %r22 /* restore I-bit */
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bv %r0(%r2)
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nop
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.exit
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.procend
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.export copy_user_page_asm,code
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.align 16
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copy_user_page_asm:
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.proc
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.callinfo NO_CALLS
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.entry
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#ifdef CONFIG_64BIT
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/* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
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* Unroll the loop by hand and arrange insn appropriately.
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* GCC probably can do this just as well.
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*/
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ldd 0(%r25), %r19
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ldi ASM_PAGE_SIZE_DIV128, %r1
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ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
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ldw 128(%r25), %r0 /* prefetch 2 */
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1: ldd 8(%r25), %r20
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ldw 192(%r25), %r0 /* prefetch 3 */
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ldw 256(%r25), %r0 /* prefetch 4 */
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ldd 16(%r25), %r21
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ldd 24(%r25), %r22
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std %r19, 0(%r26)
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std %r20, 8(%r26)
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ldd 32(%r25), %r19
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ldd 40(%r25), %r20
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std %r21, 16(%r26)
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std %r22, 24(%r26)
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ldd 48(%r25), %r21
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ldd 56(%r25), %r22
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std %r19, 32(%r26)
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std %r20, 40(%r26)
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ldd 64(%r25), %r19
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ldd 72(%r25), %r20
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std %r21, 48(%r26)
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std %r22, 56(%r26)
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ldd 80(%r25), %r21
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ldd 88(%r25), %r22
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std %r19, 64(%r26)
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std %r20, 72(%r26)
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ldd 96(%r25), %r19
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ldd 104(%r25), %r20
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std %r21, 80(%r26)
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std %r22, 88(%r26)
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ldd 112(%r25), %r21
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ldd 120(%r25), %r22
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std %r19, 96(%r26)
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std %r20, 104(%r26)
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ldo 128(%r25), %r25
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std %r21, 112(%r26)
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std %r22, 120(%r26)
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ldo 128(%r26), %r26
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/* conditional branches nullify on forward taken branch, and on
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* non-taken backward branch. Note that .+4 is a backwards branch.
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* The ldd should only get executed if the branch is taken.
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*/
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ADDIB>,n -1, %r1, 1b /* bundle 10 */
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ldd 0(%r25), %r19 /* start next loads */
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#else
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/*
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* This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
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* bundles (very restricted rules for bundling).
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* Note that until (if) we start saving
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* the full 64 bit register values on interrupt, we can't
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* use ldd/std on a 32 bit kernel.
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*/
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ldw 0(%r25), %r19
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ldi ASM_PAGE_SIZE_DIV64, %r1
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1:
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ldw 4(%r25), %r20
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ldw 8(%r25), %r21
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ldw 12(%r25), %r22
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stw %r19, 0(%r26)
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stw %r20, 4(%r26)
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stw %r21, 8(%r26)
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stw %r22, 12(%r26)
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ldw 16(%r25), %r19
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ldw 20(%r25), %r20
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ldw 24(%r25), %r21
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ldw 28(%r25), %r22
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stw %r19, 16(%r26)
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stw %r20, 20(%r26)
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stw %r21, 24(%r26)
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stw %r22, 28(%r26)
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ldw 32(%r25), %r19
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ldw 36(%r25), %r20
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ldw 40(%r25), %r21
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ldw 44(%r25), %r22
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stw %r19, 32(%r26)
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stw %r20, 36(%r26)
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stw %r21, 40(%r26)
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stw %r22, 44(%r26)
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ldw 48(%r25), %r19
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ldw 52(%r25), %r20
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ldw 56(%r25), %r21
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ldw 60(%r25), %r22
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stw %r19, 48(%r26)
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stw %r20, 52(%r26)
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ldo 64(%r25), %r25
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stw %r21, 56(%r26)
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stw %r22, 60(%r26)
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ldo 64(%r26), %r26
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ADDIB>,n -1, %r1, 1b
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ldw 0(%r25), %r19
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#endif
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bv %r0(%r2)
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nop
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.exit
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.procend
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/*
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* NOTE: Code in clear_user_page has a hard coded dependency on the
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* maximum alias boundary being 4 Mb. We've been assured by the
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* parisc chip designers that there will not ever be a parisc
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* chip with a larger alias boundary (Never say never :-) ).
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*
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* Subtle: the dtlb miss handlers support the temp alias region by
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* "knowing" that if a dtlb miss happens within the temp alias
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* region it must have occurred while in clear_user_page. Since
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* this routine makes use of processor local translations, we
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* don't want to insert them into the kernel page table. Instead,
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* we load up some general registers (they need to be registers
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* which aren't shadowed) with the physical page numbers (preshifted
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* for tlb insertion) needed to insert the translations. When we
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* miss on the translation, the dtlb miss handler inserts the
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* translation into the tlb using these values:
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*
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* %r26 physical page (shifted for tlb insert) of "to" translation
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* %r23 physical page (shifted for tlb insert) of "from" translation
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*/
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#if 0
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/*
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* We can't do this since copy_user_page is used to bring in
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* file data that might have instructions. Since the data would
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* then need to be flushed out so the i-fetch can see it, it
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* makes more sense to just copy through the kernel translation
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* and flush it.
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*
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* I'm still keeping this around because it may be possible to
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* use it if more information is passed into copy_user_page().
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* Have to do some measurements to see if it is worthwhile to
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* lobby for such a change.
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*/
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.export copy_user_page_asm,code
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copy_user_page_asm:
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.proc
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.callinfo NO_CALLS
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.entry
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ldil L%(__PAGE_OFFSET), %r1
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sub %r26, %r1, %r26
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sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
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ldil L%(TMPALIAS_MAP_START), %r28
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/* FIXME for different page sizes != 4k */
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#ifdef CONFIG_64BIT
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extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
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extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
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depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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copy %r28, %r29
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depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
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#else
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extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
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extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
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depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
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depwi 0, 31,12, %r28 /* Clear any offset bits */
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copy %r28, %r29
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depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
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#endif
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/* Purge any old translations */
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|
|
pdtlb 0(%r28)
|
|
pdtlb 0(%r29)
|
|
|
|
ldi 64, %r1
|
|
|
|
/*
|
|
* This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
|
|
* bundles (very restricted rules for bundling). It probably
|
|
* does OK on PCXU and better, but we could do better with
|
|
* ldd/std instructions. Note that until (if) we start saving
|
|
* the full 64 bit register values on interrupt, we can't
|
|
* use ldd/std on a 32 bit kernel.
|
|
*/
|
|
|
|
|
|
1:
|
|
ldw 0(%r29), %r19
|
|
ldw 4(%r29), %r20
|
|
ldw 8(%r29), %r21
|
|
ldw 12(%r29), %r22
|
|
stw %r19, 0(%r28)
|
|
stw %r20, 4(%r28)
|
|
stw %r21, 8(%r28)
|
|
stw %r22, 12(%r28)
|
|
ldw 16(%r29), %r19
|
|
ldw 20(%r29), %r20
|
|
ldw 24(%r29), %r21
|
|
ldw 28(%r29), %r22
|
|
stw %r19, 16(%r28)
|
|
stw %r20, 20(%r28)
|
|
stw %r21, 24(%r28)
|
|
stw %r22, 28(%r28)
|
|
ldw 32(%r29), %r19
|
|
ldw 36(%r29), %r20
|
|
ldw 40(%r29), %r21
|
|
ldw 44(%r29), %r22
|
|
stw %r19, 32(%r28)
|
|
stw %r20, 36(%r28)
|
|
stw %r21, 40(%r28)
|
|
stw %r22, 44(%r28)
|
|
ldw 48(%r29), %r19
|
|
ldw 52(%r29), %r20
|
|
ldw 56(%r29), %r21
|
|
ldw 60(%r29), %r22
|
|
stw %r19, 48(%r28)
|
|
stw %r20, 52(%r28)
|
|
stw %r21, 56(%r28)
|
|
stw %r22, 60(%r28)
|
|
ldo 64(%r28), %r28
|
|
ADDIB> -1, %r1,1b
|
|
ldo 64(%r29), %r29
|
|
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
#endif
|
|
|
|
.export __clear_user_page_asm,code
|
|
|
|
__clear_user_page_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
tophys_r1 %r26
|
|
|
|
ldil L%(TMPALIAS_MAP_START), %r28
|
|
#ifdef CONFIG_64BIT
|
|
#if (TMPALIAS_MAP_START >= 0x80000000)
|
|
depdi 0, 31,32, %r28 /* clear any sign extension */
|
|
/* FIXME: page size dependend */
|
|
#endif
|
|
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
|
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
|
|
depdi 0, 63,12, %r28 /* Clear any offset bits */
|
|
#else
|
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
|
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
|
|
depwi 0, 31,12, %r28 /* Clear any offset bits */
|
|
#endif
|
|
|
|
/* Purge any old translation */
|
|
|
|
pdtlb 0(%r28)
|
|
|
|
#ifdef CONFIG_64BIT
|
|
ldi ASM_PAGE_SIZE_DIV128, %r1
|
|
|
|
/* PREFETCH (Write) has not (yet) been proven to help here */
|
|
/* #define PREFETCHW_OP ldd 256(%0), %r0 */
|
|
|
|
1: std %r0, 0(%r28)
|
|
std %r0, 8(%r28)
|
|
std %r0, 16(%r28)
|
|
std %r0, 24(%r28)
|
|
std %r0, 32(%r28)
|
|
std %r0, 40(%r28)
|
|
std %r0, 48(%r28)
|
|
std %r0, 56(%r28)
|
|
std %r0, 64(%r28)
|
|
std %r0, 72(%r28)
|
|
std %r0, 80(%r28)
|
|
std %r0, 88(%r28)
|
|
std %r0, 96(%r28)
|
|
std %r0, 104(%r28)
|
|
std %r0, 112(%r28)
|
|
std %r0, 120(%r28)
|
|
ADDIB> -1, %r1, 1b
|
|
ldo 128(%r28), %r28
|
|
|
|
#else /* ! CONFIG_64BIT */
|
|
ldi ASM_PAGE_SIZE_DIV64, %r1
|
|
|
|
1:
|
|
stw %r0, 0(%r28)
|
|
stw %r0, 4(%r28)
|
|
stw %r0, 8(%r28)
|
|
stw %r0, 12(%r28)
|
|
stw %r0, 16(%r28)
|
|
stw %r0, 20(%r28)
|
|
stw %r0, 24(%r28)
|
|
stw %r0, 28(%r28)
|
|
stw %r0, 32(%r28)
|
|
stw %r0, 36(%r28)
|
|
stw %r0, 40(%r28)
|
|
stw %r0, 44(%r28)
|
|
stw %r0, 48(%r28)
|
|
stw %r0, 52(%r28)
|
|
stw %r0, 56(%r28)
|
|
stw %r0, 60(%r28)
|
|
ADDIB> -1, %r1, 1b
|
|
ldo 64(%r28), %r28
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_kernel_dcache_page_asm
|
|
|
|
flush_kernel_dcache_page_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
|
#else
|
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
|
#endif
|
|
add %r26, %r25, %r25
|
|
sub %r25, %r23, %r25
|
|
|
|
|
|
1: fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
fdc,m %r23(%r26)
|
|
CMPB<< %r26, %r25,1b
|
|
fdc,m %r23(%r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_user_dcache_page
|
|
|
|
flush_user_dcache_page:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1,63-PAGE_SHIFT,1, %r25
|
|
#else
|
|
depwi,z 1,31-PAGE_SHIFT,1, %r25
|
|
#endif
|
|
add %r26, %r25, %r25
|
|
sub %r25, %r23, %r25
|
|
|
|
|
|
1: fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
fdc,m %r23(%sr3, %r26)
|
|
CMPB<< %r26, %r25,1b
|
|
fdc,m %r23(%sr3, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_user_icache_page
|
|
|
|
flush_user_icache_page:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
|
#else
|
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
|
#endif
|
|
add %r26, %r25, %r25
|
|
sub %r25, %r23, %r25
|
|
|
|
|
|
1: fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
fic,m %r23(%sr3, %r26)
|
|
CMPB<< %r26, %r25,1b
|
|
fic,m %r23(%sr3, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
|
|
.export purge_kernel_dcache_page
|
|
|
|
purge_kernel_dcache_page:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
|
#else
|
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
|
#endif
|
|
add %r26, %r25, %r25
|
|
sub %r25, %r23, %r25
|
|
|
|
1: pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
pdc,m %r23(%r26)
|
|
CMPB<< %r26, %r25, 1b
|
|
pdc,m %r23(%r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
#if 0
|
|
/* Currently not used, but it still is a possible alternate
|
|
* solution.
|
|
*/
|
|
|
|
.export flush_alias_page
|
|
|
|
flush_alias_page:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
tophys_r1 %r26
|
|
|
|
ldil L%(TMPALIAS_MAP_START), %r28
|
|
#ifdef CONFIG_64BIT
|
|
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
|
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
|
|
depdi 0, 63,12, %r28 /* Clear any offset bits */
|
|
#else
|
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
|
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
|
|
depwi 0, 31,12, %r28 /* Clear any offset bits */
|
|
#endif
|
|
|
|
/* Purge any old translation */
|
|
|
|
pdtlb 0(%r28)
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1, 63-PAGE_SHIFT,1, %r29
|
|
#else
|
|
depwi,z 1, 31-PAGE_SHIFT,1, %r29
|
|
#endif
|
|
add %r28, %r29, %r29
|
|
sub %r29, %r23, %r29
|
|
|
|
1: fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
fdc,m %r23(%r28)
|
|
CMPB<< %r28, %r29, 1b
|
|
fdc,m %r23(%r28)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
#endif
|
|
|
|
.export flush_user_dcache_range_asm
|
|
|
|
flush_user_dcache_range_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
ldo -1(%r23), %r21
|
|
ANDCM %r26, %r21, %r26
|
|
|
|
1: CMPB<<,n %r26, %r25, 1b
|
|
fdc,m %r23(%sr3, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_kernel_dcache_range_asm
|
|
|
|
flush_kernel_dcache_range_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%dcache_stride, %r1
|
|
ldw R%dcache_stride(%r1), %r23
|
|
ldo -1(%r23), %r21
|
|
ANDCM %r26, %r21, %r26
|
|
|
|
1: CMPB<<,n %r26, %r25,1b
|
|
fdc,m %r23(%r26)
|
|
|
|
sync
|
|
syncdma
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_user_icache_range_asm
|
|
|
|
flush_user_icache_range_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%icache_stride, %r1
|
|
ldw R%icache_stride(%r1), %r23
|
|
ldo -1(%r23), %r21
|
|
ANDCM %r26, %r21, %r26
|
|
|
|
1: CMPB<<,n %r26, %r25,1b
|
|
fic,m %r23(%sr3, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_kernel_icache_page
|
|
|
|
flush_kernel_icache_page:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%icache_stride, %r1
|
|
ldw R%icache_stride(%r1), %r23
|
|
|
|
#ifdef CONFIG_64BIT
|
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
|
#else
|
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
|
#endif
|
|
add %r26, %r25, %r25
|
|
sub %r25, %r23, %r25
|
|
|
|
|
|
1: fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
fic,m %r23(%sr4, %r26)
|
|
CMPB<< %r26, %r25, 1b
|
|
fic,m %r23(%sr4, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.export flush_kernel_icache_range_asm
|
|
|
|
flush_kernel_icache_range_asm:
|
|
.proc
|
|
.callinfo NO_CALLS
|
|
.entry
|
|
|
|
ldil L%icache_stride, %r1
|
|
ldw R%icache_stride(%r1), %r23
|
|
ldo -1(%r23), %r21
|
|
ANDCM %r26, %r21, %r26
|
|
|
|
1: CMPB<<,n %r26, %r25, 1b
|
|
fic,m %r23(%sr4, %r26)
|
|
|
|
sync
|
|
bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
.procend
|
|
|
|
/* align should cover use of rfi in disable_sr_hashing_asm and
|
|
* srdis_done.
|
|
*/
|
|
.align 256
|
|
.export disable_sr_hashing_asm,code
|
|
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disable_sr_hashing_asm:
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.proc
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.callinfo NO_CALLS
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.entry
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/*
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* Switch to real mode
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*/
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/* pcxt_ssm_bug */
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rsm PSW_SM_I, %r0
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load32 PA(1f), %r1
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nop
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nop
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nop
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nop
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nop
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rsm PSW_SM_Q, %r0 /* prep to load iia queue */
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mtctl %r0, %cr17 /* Clear IIASQ tail */
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mtctl %r0, %cr17 /* Clear IIASQ head */
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mtctl %r1, %cr18 /* IIAOQ head */
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ldo 4(%r1), %r1
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mtctl %r1, %cr18 /* IIAOQ tail */
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load32 REAL_MODE_PSW, %r1
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mtctl %r1, %ipsw
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rfi
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nop
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1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
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cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
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cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
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b,n srdis_done
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srdis_pcxs:
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/* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
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.word 0x141c1a00 /* mfdiag %dr0, %r28 */
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.word 0x141c1a00 /* must issue twice */
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depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
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depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
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.word 0x141c1600 /* mtdiag %r28, %dr0 */
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.word 0x141c1600 /* must issue twice */
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b,n srdis_done
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|
|
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srdis_pcxl:
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|
|
|
/* Disable Space Register Hashing for PCXL */
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|
|
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.word 0x141c0600 /* mfdiag %dr0, %r28 */
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|
depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
|
|
.word 0x141c0240 /* mtdiag %r28, %dr0 */
|
|
b,n srdis_done
|
|
|
|
srdis_pa20:
|
|
|
|
/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
|
|
|
|
.word 0x144008bc /* mfdiag %dr2, %r28 */
|
|
depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
|
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.word 0x145c1840 /* mtdiag %r28, %dr2 */
|
|
|
|
|
|
srdis_done:
|
|
/* Switch back to virtual mode */
|
|
rsm PSW_SM_I, %r0 /* prep to load iia queue */
|
|
load32 2f, %r1
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
rsm PSW_SM_Q, %r0 /* prep to load iia queue */
|
|
mtctl %r0, %cr17 /* Clear IIASQ tail */
|
|
mtctl %r0, %cr17 /* Clear IIASQ head */
|
|
mtctl %r1, %cr18 /* IIAOQ head */
|
|
ldo 4(%r1), %r1
|
|
mtctl %r1, %cr18 /* IIAOQ tail */
|
|
load32 KERNEL_PSW, %r1
|
|
mtctl %r1, %ipsw
|
|
rfi
|
|
nop
|
|
|
|
2: bv %r0(%r2)
|
|
nop
|
|
.exit
|
|
|
|
.procend
|
|
|
|
.end
|