941 lines
38 KiB
C
941 lines
38 KiB
C
/**
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* \file amdgpu_drv.c
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* AMD Amdgpu driver
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*
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* \author Gareth Hughes <gareth@valinux.com>
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*/
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/*
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include <drm/drm_gem.h>
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#include "amdgpu_drv.h"
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#include <drm/drm_pciids.h>
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/vga_switcheroo.h>
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#include <drm/drm_crtc_helper.h>
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#include "amdgpu.h"
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#include "amdgpu_irq.h"
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#include "amdgpu_amdkfd.h"
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/*
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* KMS wrapper.
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* - 3.0.0 - initial driver
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* - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
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* - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
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* at the end of IBs.
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* - 3.3.0 - Add VM support for UVD on supported hardware.
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* - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
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* - 3.5.0 - Add support for new UVD_NO_OP register.
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* - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
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* - 3.7.0 - Add support for VCE clock list packet
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* - 3.8.0 - Add support raster config init in the kernel
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* - 3.9.0 - Add support for memory query info about VRAM and GTT.
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* - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
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* - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
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* - 3.12.0 - Add query for double offchip LDS buffers
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* - 3.13.0 - Add PRT support
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* - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
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* - 3.15.0 - Export more gpu info for gfx9
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* - 3.16.0 - Add reserved vmid support
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* - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
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* - 3.18.0 - Export gpu always on cu bitmap
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* - 3.19.0 - Add support for UVD MJPEG decode
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* - 3.20.0 - Add support for local BOs
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* - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 21
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#define KMS_DRIVER_PATCHLEVEL 0
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int amdgpu_vram_limit = 0;
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int amdgpu_vis_vram_limit = 0;
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int amdgpu_gart_size = -1; /* auto */
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int amdgpu_gtt_size = -1; /* auto */
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int amdgpu_moverate = -1; /* auto */
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int amdgpu_benchmarking = 0;
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int amdgpu_testing = 0;
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int amdgpu_audio = -1;
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int amdgpu_disp_priority = 0;
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int amdgpu_hw_i2c = 0;
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int amdgpu_pcie_gen2 = -1;
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int amdgpu_msi = -1;
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int amdgpu_lockup_timeout = 0;
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int amdgpu_dpm = -1;
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int amdgpu_fw_load_type = -1;
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int amdgpu_aspm = -1;
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int amdgpu_runtime_pm = -1;
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uint amdgpu_ip_block_mask = 0xffffffff;
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int amdgpu_bapm = -1;
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int amdgpu_deep_color = 0;
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int amdgpu_vm_size = -1;
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int amdgpu_vm_fragment_size = -1;
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int amdgpu_vm_block_size = -1;
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int amdgpu_vm_fault_stop = 0;
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int amdgpu_vm_debug = 0;
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int amdgpu_vram_page_split = 512;
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int amdgpu_vm_update_mode = -1;
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int amdgpu_exp_hw_support = 0;
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int amdgpu_sched_jobs = 32;
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int amdgpu_sched_hw_submission = 2;
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int amdgpu_no_evict = 0;
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int amdgpu_direct_gma_size = 0;
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uint amdgpu_pcie_gen_cap = 0;
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uint amdgpu_pcie_lane_cap = 0;
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uint amdgpu_cg_mask = 0xffffffff;
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uint amdgpu_pg_mask = 0xffffffff;
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uint amdgpu_sdma_phase_quantum = 32;
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char *amdgpu_disable_cu = NULL;
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char *amdgpu_virtual_display = NULL;
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uint amdgpu_pp_feature_mask = 0xffffffff;
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int amdgpu_ngg = 0;
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int amdgpu_prim_buf_per_se = 0;
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int amdgpu_pos_buf_per_se = 0;
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int amdgpu_cntl_sb_buf_per_se = 0;
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int amdgpu_param_buf_per_se = 0;
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int amdgpu_job_hang_limit = 0;
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int amdgpu_lbpw = -1;
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int amdgpu_compute_multipipe = -1;
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MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
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module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
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MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
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module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
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MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
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module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
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MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
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module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
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MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
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module_param_named(moverate, amdgpu_moverate, int, 0600);
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MODULE_PARM_DESC(benchmark, "Run benchmark");
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module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
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MODULE_PARM_DESC(test, "Run tests");
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module_param_named(test, amdgpu_testing, int, 0444);
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MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
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module_param_named(audio, amdgpu_audio, int, 0444);
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MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
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module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
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MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
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module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
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MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
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module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
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MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(msi, amdgpu_msi, int, 0444);
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
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module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
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MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(dpm, amdgpu_dpm, int, 0444);
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MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
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module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
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MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(aspm, amdgpu_aspm, int, 0444);
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MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
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module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
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MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
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module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
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MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(bapm, amdgpu_bapm, int, 0444);
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MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
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module_param_named(deep_color, amdgpu_deep_color, int, 0444);
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MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
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module_param_named(vm_size, amdgpu_vm_size, int, 0444);
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MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
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module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
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MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
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module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
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MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
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module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
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MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
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module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
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MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
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module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
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MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
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module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
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MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
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module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
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MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
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module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
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MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
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module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
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MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
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module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
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MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
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module_param_named(no_evict, amdgpu_no_evict, int, 0444);
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MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
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module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
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MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
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module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
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MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
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module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
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MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
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module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
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MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
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module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
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MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
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module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
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MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
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module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
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MODULE_PARM_DESC(virtual_display,
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"Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
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module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
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MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
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module_param_named(ngg, amdgpu_ngg, int, 0444);
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MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
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module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
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MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
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module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
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MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
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module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
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MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
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module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
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MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
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module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
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MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(lbpw, amdgpu_lbpw, int, 0444);
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MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
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#ifdef CONFIG_DRM_AMDGPU_SI
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#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
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int amdgpu_si_support = 0;
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MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
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#else
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int amdgpu_si_support = 1;
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MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
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#endif
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module_param_named(si_support, amdgpu_si_support, int, 0444);
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#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
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#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
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int amdgpu_cik_support = 0;
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MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
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#else
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int amdgpu_cik_support = 1;
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MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
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#endif
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module_param_named(cik_support, amdgpu_cik_support, int, 0444);
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#endif
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static const struct pci_device_id pciidlist[] = {
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#ifdef CONFIG_DRM_AMDGPU_SI
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{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
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{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
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{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
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{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
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{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
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{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
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{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
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{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
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{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
|
|
{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
|
|
{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
|
|
{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
|
|
{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
|
|
{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
|
|
{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
|
|
#endif
|
|
#ifdef CONFIG_DRM_AMDGPU_CIK
|
|
/* Kaveri */
|
|
{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
|
|
/* Bonaire */
|
|
{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
|
|
{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
|
|
/* Hawaii */
|
|
{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
|
|
/* Kabini */
|
|
{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
|
|
/* mullins */
|
|
{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
|
|
#endif
|
|
/* topaz */
|
|
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
|
|
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
|
|
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
|
|
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
|
|
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
|
|
/* tonga */
|
|
{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
|
|
/* fiji */
|
|
{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
|
|
{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
|
|
/* carrizo */
|
|
{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
|
|
{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
|
|
{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
|
|
{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
|
|
{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
|
|
/* stoney */
|
|
{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
|
|
/* Polaris11 */
|
|
{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
|
|
/* Polaris10 */
|
|
{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
|
|
/* Polaris12 */
|
|
{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
|
|
/* Vega 10 */
|
|
{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
|
|
/* Raven */
|
|
{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
|
|
|
|
{0, 0, 0}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
static struct drm_driver kms_driver;
|
|
|
|
static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
|
|
{
|
|
struct apertures_struct *ap;
|
|
bool primary = false;
|
|
|
|
ap = alloc_apertures(1);
|
|
if (!ap)
|
|
return -ENOMEM;
|
|
|
|
ap->ranges[0].base = pci_resource_start(pdev, 0);
|
|
ap->ranges[0].size = pci_resource_len(pdev, 0);
|
|
|
|
#ifdef CONFIG_X86
|
|
primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
|
|
#endif
|
|
drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
|
|
kfree(ap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_pci_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct drm_device *dev;
|
|
unsigned long flags = ent->driver_data;
|
|
int ret;
|
|
|
|
if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
|
|
DRM_INFO("This hardware requires experimental hardware support.\n"
|
|
"See modparam exp_hw_support\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* Initialize amdkfd before starting radeon. If it was not loaded yet,
|
|
* defer radeon probing
|
|
*/
|
|
ret = amdgpu_amdkfd_init();
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
|
|
/* Get rid of things like offb */
|
|
ret = amdgpu_kick_out_firmware_fb(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev = drm_dev_alloc(&kms_driver, &pdev->dev);
|
|
if (IS_ERR(dev))
|
|
return PTR_ERR(dev);
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
goto err_free;
|
|
|
|
dev->pdev = pdev;
|
|
|
|
pci_set_drvdata(pdev, dev);
|
|
|
|
ret = drm_dev_register(dev, ent->driver_data);
|
|
if (ret)
|
|
goto err_pci;
|
|
|
|
return 0;
|
|
|
|
err_pci:
|
|
pci_disable_device(pdev);
|
|
err_free:
|
|
drm_dev_unref(dev);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
amdgpu_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
drm_dev_unregister(dev);
|
|
drm_dev_unref(dev);
|
|
pci_disable_device(pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
static void
|
|
amdgpu_pci_shutdown(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
/* if we are running in a VM, make sure the device
|
|
* torn down properly on reboot/shutdown.
|
|
* unfortunately we can't detect certain
|
|
* hypervisors so just do this all the time.
|
|
*/
|
|
amdgpu_suspend(adev);
|
|
}
|
|
|
|
static int amdgpu_pmops_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return amdgpu_device_suspend(drm_dev, true, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
/* GPU comes up enabled by the bios on resume */
|
|
if (amdgpu_device_is_px(drm_dev)) {
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
}
|
|
|
|
return amdgpu_device_resume(drm_dev, true, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_freeze(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return amdgpu_device_suspend(drm_dev, false, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_thaw(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return amdgpu_device_resume(drm_dev, false, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_poweroff(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return amdgpu_device_suspend(drm_dev, true, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_restore(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return amdgpu_device_resume(drm_dev, false, true);
|
|
}
|
|
|
|
static int amdgpu_pmops_runtime_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
if (!amdgpu_device_is_px(drm_dev)) {
|
|
pm_runtime_forbid(dev);
|
|
return -EBUSY;
|
|
}
|
|
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
drm_kms_helper_poll_disable(drm_dev);
|
|
vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
|
|
|
|
ret = amdgpu_device_suspend(drm_dev, false, false);
|
|
pci_save_state(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_ignore_hotplug(pdev);
|
|
if (amdgpu_is_atpx_hybrid())
|
|
pci_set_power_state(pdev, PCI_D3cold);
|
|
else if (!amdgpu_has_atpx_dgpu_power_cntl())
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_pmops_runtime_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
if (!amdgpu_device_is_px(drm_dev))
|
|
return -EINVAL;
|
|
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
|
|
if (amdgpu_is_atpx_hybrid() ||
|
|
!amdgpu_has_atpx_dgpu_power_cntl())
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
pci_set_master(pdev);
|
|
|
|
ret = amdgpu_device_resume(drm_dev, false, false);
|
|
drm_kms_helper_poll_enable(drm_dev);
|
|
vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_pmops_runtime_idle(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
struct drm_crtc *crtc;
|
|
|
|
if (!amdgpu_device_is_px(drm_dev)) {
|
|
pm_runtime_forbid(dev);
|
|
return -EBUSY;
|
|
}
|
|
|
|
list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
|
|
if (crtc->enabled) {
|
|
DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_autosuspend(dev);
|
|
/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
|
|
return 1;
|
|
}
|
|
|
|
long amdgpu_drm_ioctl(struct file *filp,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
struct drm_file *file_priv = filp->private_data;
|
|
struct drm_device *dev;
|
|
long ret;
|
|
dev = file_priv->minor->dev;
|
|
ret = pm_runtime_get_sync(dev->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = drm_ioctl(filp, cmd, arg);
|
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops amdgpu_pm_ops = {
|
|
.suspend = amdgpu_pmops_suspend,
|
|
.resume = amdgpu_pmops_resume,
|
|
.freeze = amdgpu_pmops_freeze,
|
|
.thaw = amdgpu_pmops_thaw,
|
|
.poweroff = amdgpu_pmops_poweroff,
|
|
.restore = amdgpu_pmops_restore,
|
|
.runtime_suspend = amdgpu_pmops_runtime_suspend,
|
|
.runtime_resume = amdgpu_pmops_runtime_resume,
|
|
.runtime_idle = amdgpu_pmops_runtime_idle,
|
|
};
|
|
|
|
static const struct file_operations amdgpu_driver_kms_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = amdgpu_drm_ioctl,
|
|
.mmap = amdgpu_mmap,
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = amdgpu_kms_compat_ioctl,
|
|
#endif
|
|
};
|
|
|
|
static bool
|
|
amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
|
|
bool in_vblank_irq, int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
|
|
stime, etime, mode);
|
|
}
|
|
|
|
static struct drm_driver kms_driver = {
|
|
.driver_features =
|
|
DRIVER_USE_AGP |
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
|
|
DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
|
|
.load = amdgpu_driver_load_kms,
|
|
.open = amdgpu_driver_open_kms,
|
|
.postclose = amdgpu_driver_postclose_kms,
|
|
.lastclose = amdgpu_driver_lastclose_kms,
|
|
.unload = amdgpu_driver_unload_kms,
|
|
.get_vblank_counter = amdgpu_get_vblank_counter_kms,
|
|
.enable_vblank = amdgpu_enable_vblank_kms,
|
|
.disable_vblank = amdgpu_disable_vblank_kms,
|
|
.get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
|
|
.get_scanout_position = amdgpu_get_crtc_scanout_position,
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
.debugfs_init = amdgpu_debugfs_init,
|
|
#endif
|
|
.irq_preinstall = amdgpu_irq_preinstall,
|
|
.irq_postinstall = amdgpu_irq_postinstall,
|
|
.irq_uninstall = amdgpu_irq_uninstall,
|
|
.irq_handler = amdgpu_irq_handler,
|
|
.ioctls = amdgpu_ioctls_kms,
|
|
.gem_free_object_unlocked = amdgpu_gem_object_free,
|
|
.gem_open_object = amdgpu_gem_object_open,
|
|
.gem_close_object = amdgpu_gem_object_close,
|
|
.dumb_create = amdgpu_mode_dumb_create,
|
|
.dumb_map_offset = amdgpu_mode_dumb_mmap,
|
|
.fops = &amdgpu_driver_kms_fops,
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_export = amdgpu_gem_prime_export,
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
.gem_prime_pin = amdgpu_gem_prime_pin,
|
|
.gem_prime_unpin = amdgpu_gem_prime_unpin,
|
|
.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
|
|
.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
|
|
.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
|
|
.gem_prime_vmap = amdgpu_gem_prime_vmap,
|
|
.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
|
|
.gem_prime_mmap = amdgpu_gem_prime_mmap,
|
|
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = KMS_DRIVER_MAJOR,
|
|
.minor = KMS_DRIVER_MINOR,
|
|
.patchlevel = KMS_DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
static struct drm_driver *driver;
|
|
static struct pci_driver *pdriver;
|
|
|
|
static struct pci_driver amdgpu_kms_pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
.probe = amdgpu_pci_probe,
|
|
.remove = amdgpu_pci_remove,
|
|
.shutdown = amdgpu_pci_shutdown,
|
|
.driver.pm = &amdgpu_pm_ops,
|
|
};
|
|
|
|
|
|
|
|
static int __init amdgpu_init(void)
|
|
{
|
|
int r;
|
|
|
|
r = amdgpu_sync_init();
|
|
if (r)
|
|
goto error_sync;
|
|
|
|
r = amdgpu_fence_slab_init();
|
|
if (r)
|
|
goto error_fence;
|
|
|
|
r = amd_sched_fence_slab_init();
|
|
if (r)
|
|
goto error_sched;
|
|
|
|
if (vgacon_text_force()) {
|
|
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
|
|
return -EINVAL;
|
|
}
|
|
DRM_INFO("amdgpu kernel modesetting enabled.\n");
|
|
driver = &kms_driver;
|
|
pdriver = &amdgpu_kms_pci_driver;
|
|
driver->num_ioctls = amdgpu_max_kms_ioctl;
|
|
amdgpu_register_atpx_handler();
|
|
/* let modprobe override vga console setting */
|
|
return pci_register_driver(pdriver);
|
|
|
|
error_sched:
|
|
amdgpu_fence_slab_fini();
|
|
|
|
error_fence:
|
|
amdgpu_sync_fini();
|
|
|
|
error_sync:
|
|
return r;
|
|
}
|
|
|
|
static void __exit amdgpu_exit(void)
|
|
{
|
|
amdgpu_amdkfd_fini();
|
|
pci_unregister_driver(pdriver);
|
|
amdgpu_unregister_atpx_handler();
|
|
amdgpu_sync_fini();
|
|
amd_sched_fence_slab_fini();
|
|
amdgpu_fence_slab_fini();
|
|
}
|
|
|
|
module_init(amdgpu_init);
|
|
module_exit(amdgpu_exit);
|
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL and additional rights");
|