433 lines
12 KiB
C
433 lines
12 KiB
C
/*
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* General Purpose functions for the global management of the
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* Communication Processor Module.
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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* The amount of space available is platform dependent. On the
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* MBX, the EPPC software loads additional microcode into the
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* communication processor, and uses some of the DP ram for this
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* purpose. Current, the first 512 bytes and the last 256 bytes of
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* memory are used. Right now I am conservative and only use the
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* memory that can never be used for microcode. If there are
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* applications that require more DP ram, we can expand the boundaries
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* but then we have to be careful of any downloaded microcode.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/mpc8xx.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/8xx_immap.h>
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#include <asm/cpm1.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/rheap.h>
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#define immr_map(member) \
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({ \
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u32 offset = offsetof(immap_t, member); \
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void *addr = ioremap (IMAP_ADDR + offset, \
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FIELD_SIZEOF(immap_t, member)); \
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addr; \
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})
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#define immr_map_size(member, size) \
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({ \
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u32 offset = offsetof(immap_t, member); \
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void *addr = ioremap (IMAP_ADDR + offset, size); \
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addr; \
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})
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static void m8xx_cpm_dpinit(void);
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cpm8xx_t *cpmp; /* Pointer to comm processor space */
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/* CPM interrupt vector functions.
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*/
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struct cpm_action {
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void (*handler)(void *);
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void *dev_id;
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};
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static struct cpm_action cpm_vecs[CPMVEC_NR];
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static irqreturn_t cpm_interrupt(int irq, void * dev);
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static irqreturn_t cpm_error_interrupt(int irq, void *dev);
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/* Define a table of names to identify CPM interrupt handlers in
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* /proc/interrupts.
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*/
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const char *cpm_int_name[] =
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{ "error", "PC4", "PC5", "SMC2",
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"SMC1", "SPI", "PC6", "Timer 4",
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"", "PC7", "PC8", "PC9",
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"Timer 3", "", "PC10", "PC11",
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"I2C", "RISC Timer", "Timer 2", "",
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"IDMA2", "IDMA1", "SDMA error", "PC12",
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"PC13", "Timer 1", "PC14", "SCC4",
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"SCC3", "SCC2", "SCC1", "PC15"
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};
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static void
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cpm_mask_irq(unsigned int irq)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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clrbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
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}
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static void
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cpm_unmask_irq(unsigned int irq)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
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}
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static void
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cpm_ack(unsigned int irq)
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{
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/* We do not need to do anything here. */
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}
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static void
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cpm_eoi(unsigned int irq)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr, (1 << cpm_vec));
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}
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struct hw_interrupt_type cpm_pic = {
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.typename = " CPM ",
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.enable = cpm_unmask_irq,
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.disable = cpm_mask_irq,
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.ack = cpm_ack,
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.end = cpm_eoi,
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};
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void
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m8xx_cpm_reset(void)
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{
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volatile immap_t *imp;
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volatile cpm8xx_t *commproc;
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imp = (immap_t *)IMAP_ADDR;
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commproc = (cpm8xx_t *)&imp->im_cpm;
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#ifdef CONFIG_UCODE_PATCH
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/* Perform a reset.
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*/
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commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);
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/* Wait for it.
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*/
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while (commproc->cp_cpcr & CPM_CR_FLG);
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cpm_load_patch(imp);
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#endif
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/* Set SDMA Bus Request priority 5.
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* On 860T, this also enables FEC priority 6. I am not sure
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* this is what we really want for some applications, but the
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* manual recommends it.
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* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
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*/
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out_be32(&imp->im_siu_conf.sc_sdcr, 1),
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/* Reclaim the DP memory for our use. */
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m8xx_cpm_dpinit();
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = (cpm8xx_t *)commproc;
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}
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/* This is called during init_IRQ. We used to do it above, but this
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* was too early since init_IRQ was not yet called.
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*/
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static struct irqaction cpm_error_irqaction = {
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.handler = cpm_error_interrupt,
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.mask = CPU_MASK_NONE,
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};
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static struct irqaction cpm_interrupt_irqaction = {
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.handler = cpm_interrupt,
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.mask = CPU_MASK_NONE,
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.name = "CPM cascade",
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};
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void
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cpm_interrupt_init(void)
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{
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int i;
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/* Initialize the CPM interrupt controller.
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*/
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr,
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK);
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, 0);
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/* install the CPM interrupt controller routines for the CPM
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* interrupt vectors
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*/
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for ( i = CPM_IRQ_OFFSET ; i < CPM_IRQ_OFFSET + NR_CPM_INTS ; i++ )
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irq_desc[i].chip = &cpm_pic;
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/* Set our interrupt handler with the core CPU. */
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if (setup_irq(CPM_INTERRUPT, &cpm_interrupt_irqaction))
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panic("Could not allocate CPM IRQ!");
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/* Install our own error handler. */
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cpm_error_irqaction.name = cpm_int_name[CPMVEC_ERROR];
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if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction))
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panic("Could not allocate CPM error IRQ!");
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setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, CICR_IEN);
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}
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/*
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* Get the CPM interrupt vector.
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*/
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int
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cpm_get_irq(void)
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{
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int cpm_vec;
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/* Get the vector by setting the ACK bit and then reading
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* the register.
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*/
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out_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr, 1);
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cpm_vec = in_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr);
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cpm_vec >>= 11;
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return cpm_vec;
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}
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/* CPM interrupt controller cascade interrupt.
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*/
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static irqreturn_t
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cpm_interrupt(int irq, void * dev)
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{
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/* This interrupt handler never actually gets called. It is
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* installed only to unmask the CPM cascade interrupt in the SIU
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* and to make the CPM cascade interrupt visible in /proc/interrupts.
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*/
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return IRQ_HANDLED;
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}
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/* The CPM can generate the error interrupt when there is a race condition
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* between generating and masking interrupts. All we have to do is ACK it
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* and return. This is a no-op function so we don't need any special
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* tests in the interrupt handler.
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*/
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static irqreturn_t
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cpm_error_interrupt(int irq, void *dev)
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{
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return IRQ_HANDLED;
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}
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/* A helper function to translate the handler prototype required by
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* request_irq() to the handler prototype required by cpm_install_handler().
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*/
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static irqreturn_t
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cpm_handler_helper(int irq, void *dev_id)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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(*cpm_vecs[cpm_vec].handler)(dev_id);
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return IRQ_HANDLED;
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}
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/* Install a CPM interrupt handler.
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* This routine accepts a CPM interrupt vector in the range 0 to 31.
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* This routine is retained for backward compatibility. Rather than using
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* this routine to install a CPM interrupt handler, you can now use
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* request_irq() with an IRQ in the range CPM_IRQ_OFFSET to
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* CPM_IRQ_OFFSET + NR_CPM_INTS - 1 (16 to 47).
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*
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* Notice that the prototype of the interrupt handler function must be
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* different depending on whether you install the handler with
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* request_irq() or cpm_install_handler().
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*/
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void
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cpm_install_handler(int cpm_vec, void (*handler)(void *), void *dev_id)
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{
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int err;
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/* If null handler, assume we are trying to free the IRQ.
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*/
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if (!handler) {
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free_irq(CPM_IRQ_OFFSET + cpm_vec, dev_id);
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return;
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}
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if (cpm_vecs[cpm_vec].handler != 0)
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printk(KERN_INFO "CPM interrupt %x replacing %x\n",
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(uint)handler, (uint)cpm_vecs[cpm_vec].handler);
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cpm_vecs[cpm_vec].handler = handler;
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cpm_vecs[cpm_vec].dev_id = dev_id;
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if ((err = request_irq(CPM_IRQ_OFFSET + cpm_vec, cpm_handler_helper,
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0, cpm_int_name[cpm_vec], dev_id)))
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printk(KERN_ERR "request_irq() returned %d for CPM vector %d\n",
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err, cpm_vec);
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}
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/* Free a CPM interrupt handler.
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* This routine accepts a CPM interrupt vector in the range 0 to 31.
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* This routine is retained for backward compatibility.
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*/
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void
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cpm_free_handler(int cpm_vec)
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{
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request_irq(CPM_IRQ_OFFSET + cpm_vec, NULL, 0, 0,
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cpm_vecs[cpm_vec].dev_id);
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cpm_vecs[cpm_vec].handler = NULL;
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cpm_vecs[cpm_vec].dev_id = NULL;
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* four BRGs, any of which can be wired to any channel.
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* The internal baud rate clock is the system clock divided by 16.
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* This assumes the baudrate is 16x oversampled by the uart.
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*/
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#define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq)
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
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void
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cpm_setbrg(uint brg, uint rate)
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{
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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bp = (uint *)&cpmp->cp_brgc1;
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bp += brg;
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/* The BRG has a 12-bit counter. For really slow baud rates (or
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* really fast processors), we may have to further divide by 16.
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*/
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if (((BRG_UART_CLK / rate) - 1) < 4096)
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*bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
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else
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*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
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CPM_BRG_EN | CPM_BRG_DIV16;
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}
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/*
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* dpalloc / dpfree bits.
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*/
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static spinlock_t cpm_dpmem_lock;
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/*
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* 16 blocks should be enough to satisfy all requests
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* until the memory subsystem goes up...
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*/
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static rh_block_t cpm_boot_dpmem_rh_block[16];
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static rh_info_t cpm_dpmem_info;
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#define CPM_DPMEM_ALIGNMENT 8
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static u8* dpram_vbase;
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static uint dpram_pbase;
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void m8xx_cpm_dpinit(void)
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{
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spin_lock_init(&cpm_dpmem_lock);
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dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
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dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;
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/* Initialize the info header */
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rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
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sizeof(cpm_boot_dpmem_rh_block) /
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sizeof(cpm_boot_dpmem_rh_block[0]),
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cpm_boot_dpmem_rh_block);
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/*
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* Attach the usable dpmem area.
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* XXX: This is actually crap. CPM_DATAONLY_BASE and
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* CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
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* with the processor and the microcode patches applied / activated.
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* But the following should be at least safe.
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*/
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rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
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}
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/*
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* Allocate the requested size worth of DP memory.
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* This function returns an offset into the DPRAM area.
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* Use cpm_dpram_addr() to get the virtual address of the area.
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*/
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unsigned long cpm_dpalloc(uint size, uint align)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc(&cpm_dpmem_info, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return start;
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}
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EXPORT_SYMBOL(cpm_dpalloc);
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int cpm_dpfree(unsigned long offset)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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ret = rh_free(&cpm_dpmem_info, offset);
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_dpfree);
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unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
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{
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unsigned long start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return start;
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}
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EXPORT_SYMBOL(cpm_dpalloc_fixed);
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void cpm_dpdump(void)
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{
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rh_dump(&cpm_dpmem_info);
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}
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EXPORT_SYMBOL(cpm_dpdump);
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void *cpm_dpram_addr(unsigned long offset)
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{
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return (void *)(dpram_vbase + offset);
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}
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EXPORT_SYMBOL(cpm_dpram_addr);
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uint cpm_dpram_phys(u8* addr)
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{
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return (dpram_pbase + (uint)(addr - dpram_vbase));
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}
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EXPORT_SYMBOL(cpm_dpram_phys);
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