740 lines
17 KiB
C
740 lines
17 KiB
C
/*
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* SuperH MSIOF SPI Master Interface
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*
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* Copyright (c) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/sh_msiof.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <asm/unaligned.h>
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struct sh_msiof_spi_priv {
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struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
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void __iomem *mapbase;
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struct clk *clk;
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struct platform_device *pdev;
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struct sh_msiof_spi_info *info;
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struct completion done;
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unsigned long flags;
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int tx_fifo_size;
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int rx_fifo_size;
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};
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#define TMDR1 0x00
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#define TMDR2 0x04
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#define TMDR3 0x08
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#define RMDR1 0x10
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#define RMDR2 0x14
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#define RMDR3 0x18
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#define TSCR 0x20
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#define RSCR 0x22
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#define CTR 0x28
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#define FCTR 0x30
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#define STR 0x40
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#define IER 0x44
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#define TDR1 0x48
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#define TDR2 0x4c
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#define TFDR 0x50
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#define RDR1 0x58
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#define RDR2 0x5c
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#define RFDR 0x60
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#define CTR_TSCKE (1 << 15)
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#define CTR_TFSE (1 << 14)
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#define CTR_TXE (1 << 9)
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#define CTR_RXE (1 << 8)
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#define STR_TEOF (1 << 23)
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#define STR_REOF (1 << 7)
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static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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return ioread16(p->mapbase + reg_offs);
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default:
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return ioread32(p->mapbase + reg_offs);
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}
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}
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static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
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u32 value)
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{
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switch (reg_offs) {
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case TSCR:
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case RSCR:
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iowrite16(value, p->mapbase + reg_offs);
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break;
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default:
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iowrite32(value, p->mapbase + reg_offs);
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break;
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}
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}
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static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
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u32 clr, u32 set)
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{
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u32 mask = clr | set;
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u32 data;
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int k;
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data = sh_msiof_read(p, CTR);
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data &= ~clr;
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data |= set;
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sh_msiof_write(p, CTR, data);
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for (k = 100; k > 0; k--) {
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if ((sh_msiof_read(p, CTR) & mask) == set)
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break;
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udelay(10);
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}
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return k > 0 ? 0 : -ETIMEDOUT;
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}
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static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
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{
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struct sh_msiof_spi_priv *p = data;
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/* just disable the interrupt and wake up */
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sh_msiof_write(p, IER, 0);
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complete(&p->done);
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return IRQ_HANDLED;
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}
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static struct {
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unsigned short div;
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unsigned short scr;
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} const sh_msiof_spi_clk_table[] = {
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{ 1, 0x0007 },
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{ 2, 0x0000 },
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{ 4, 0x0001 },
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{ 8, 0x0002 },
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{ 16, 0x0003 },
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{ 32, 0x0004 },
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{ 64, 0x1f00 },
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{ 128, 0x1f01 },
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{ 256, 0x1f02 },
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{ 512, 0x1f03 },
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{ 1024, 0x1f04 },
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};
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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unsigned long parent_rate,
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unsigned long spi_hz)
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{
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unsigned long div = 1024;
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size_t k;
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if (!WARN_ON(!spi_hz || !parent_rate))
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div = parent_rate / spi_hz;
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/* TODO: make more fine grained */
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for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
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if (sh_msiof_spi_clk_table[k].div >= div)
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break;
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}
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k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
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sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
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sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
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}
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static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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u32 cpol, u32 cpha,
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u32 tx_hi_z, u32 lsb_first)
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{
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u32 tmp;
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int edge;
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/*
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* CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
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* 0 0 10 10 1 1
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* 0 1 10 10 0 0
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* 1 0 11 11 0 0
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* 1 1 11 11 1 1
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*/
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sh_msiof_write(p, FCTR, 0);
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sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
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sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
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tmp = 0xa0000000;
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tmp |= cpol << 30; /* TSCKIZ */
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tmp |= cpol << 28; /* RSCKIZ */
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edge = cpol ^ !cpha;
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tmp |= edge << 27; /* TEDG */
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tmp |= edge << 26; /* REDG */
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tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
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sh_msiof_write(p, CTR, tmp);
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}
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static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
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const void *tx_buf, void *rx_buf,
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u32 bits, u32 words)
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{
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u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
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if (tx_buf)
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sh_msiof_write(p, TMDR2, dr2);
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else
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sh_msiof_write(p, TMDR2, dr2 | 1);
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if (rx_buf)
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sh_msiof_write(p, RMDR2, dr2);
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sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
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}
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static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
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{
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sh_msiof_write(p, STR, sh_msiof_read(p, STR));
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}
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static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u8 *buf_8 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, buf_8[k] << fs);
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}
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static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u16 *buf_16 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, buf_16[k] << fs);
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}
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static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u16 *buf_16 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
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}
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static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u32 *buf_32 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, buf_32[k] << fs);
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}
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static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u32 *buf_32 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
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}
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static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u32 *buf_32 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
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}
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static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
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const void *tx_buf, int words, int fs)
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{
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const u32 *buf_32 = tx_buf;
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int k;
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for (k = 0; k < words; k++)
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sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
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}
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static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u8 *buf_8 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
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}
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static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u16 *buf_16 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
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}
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static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u16 *buf_16 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
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}
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static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u32 *buf_32 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
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}
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static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u32 *buf_32 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
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}
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static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u32 *buf_32 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
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}
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static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
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void *rx_buf, int words, int fs)
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{
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u32 *buf_32 = rx_buf;
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int k;
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for (k = 0; k < words; k++)
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put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
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}
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static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
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{
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int bits;
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bits = t ? t->bits_per_word : 0;
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if (!bits)
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bits = spi->bits_per_word;
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return bits;
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}
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static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
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struct spi_transfer *t)
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{
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unsigned long hz;
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hz = t ? t->speed_hz : 0;
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if (!hz)
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hz = spi->max_speed_hz;
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return hz;
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}
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static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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int bits;
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/* noting to check hz values against since parent clock is disabled */
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bits = sh_msiof_spi_bits(spi, t);
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if (bits < 8)
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return -EINVAL;
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if (bits > 32)
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return -EINVAL;
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return spi_bitbang_setup_transfer(spi, t);
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}
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static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
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int value;
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/* chip select is active low unless SPI_CS_HIGH is set */
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if (spi->mode & SPI_CS_HIGH)
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value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
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else
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value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
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if (is_on == BITBANG_CS_ACTIVE) {
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if (!test_and_set_bit(0, &p->flags)) {
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pm_runtime_get_sync(&p->pdev->dev);
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clk_enable(p->clk);
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}
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/* Configure pins before asserting CS */
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sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
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!!(spi->mode & SPI_CPHA),
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!!(spi->mode & SPI_3WIRE),
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!!(spi->mode & SPI_LSB_FIRST));
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}
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/* use spi->controller data for CS (same strategy as spi_gpio) */
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gpio_set_value((unsigned)spi->controller_data, value);
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if (is_on == BITBANG_CS_INACTIVE) {
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if (test_and_clear_bit(0, &p->flags)) {
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clk_disable(p->clk);
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pm_runtime_put(&p->pdev->dev);
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}
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}
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}
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static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
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void (*tx_fifo)(struct sh_msiof_spi_priv *,
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const void *, int, int),
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void (*rx_fifo)(struct sh_msiof_spi_priv *,
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void *, int, int),
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const void *tx_buf, void *rx_buf,
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int words, int bits)
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{
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int fifo_shift;
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int ret;
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/* limit maximum word transfer to rx/tx fifo size */
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if (tx_buf)
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words = min_t(int, words, p->tx_fifo_size);
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if (rx_buf)
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words = min_t(int, words, p->rx_fifo_size);
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/* the fifo contents need shifting */
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fifo_shift = 32 - bits;
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/* setup msiof transfer mode registers */
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sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
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/* write tx fifo */
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if (tx_buf)
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tx_fifo(p, tx_buf, words, fifo_shift);
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/* setup clock and rx/tx signals */
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ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
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if (rx_buf)
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
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/* start by setting frame bit */
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INIT_COMPLETION(p->done);
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
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if (ret) {
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dev_err(&p->pdev->dev, "failed to start hardware\n");
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goto err;
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}
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/* wait for tx fifo to be emptied / rx fifo to be filled */
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wait_for_completion(&p->done);
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/* read rx fifo */
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if (rx_buf)
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rx_fifo(p, rx_buf, words, fifo_shift);
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/* clear status bits */
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sh_msiof_reset_str(p);
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/* shut down frame, tx/tx and clock signals */
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ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
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if (rx_buf)
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
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ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
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if (ret) {
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dev_err(&p->pdev->dev, "failed to shut down hardware\n");
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goto err;
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}
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return words;
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|
|
|
err:
|
|
sh_msiof_write(p, IER, 0);
|
|
return ret;
|
|
}
|
|
|
|
static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
|
{
|
|
struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
|
|
void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
|
|
void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
|
|
int bits;
|
|
int bytes_per_word;
|
|
int bytes_done;
|
|
int words;
|
|
int n;
|
|
bool swab;
|
|
|
|
bits = sh_msiof_spi_bits(spi, t);
|
|
|
|
if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
|
|
bits = 32;
|
|
swab = true;
|
|
} else {
|
|
swab = false;
|
|
}
|
|
|
|
/* setup bytes per word and fifo read/write functions */
|
|
if (bits <= 8) {
|
|
bytes_per_word = 1;
|
|
tx_fifo = sh_msiof_spi_write_fifo_8;
|
|
rx_fifo = sh_msiof_spi_read_fifo_8;
|
|
} else if (bits <= 16) {
|
|
bytes_per_word = 2;
|
|
if ((unsigned long)t->tx_buf & 0x01)
|
|
tx_fifo = sh_msiof_spi_write_fifo_16u;
|
|
else
|
|
tx_fifo = sh_msiof_spi_write_fifo_16;
|
|
|
|
if ((unsigned long)t->rx_buf & 0x01)
|
|
rx_fifo = sh_msiof_spi_read_fifo_16u;
|
|
else
|
|
rx_fifo = sh_msiof_spi_read_fifo_16;
|
|
} else if (swab) {
|
|
bytes_per_word = 4;
|
|
if ((unsigned long)t->tx_buf & 0x03)
|
|
tx_fifo = sh_msiof_spi_write_fifo_s32u;
|
|
else
|
|
tx_fifo = sh_msiof_spi_write_fifo_s32;
|
|
|
|
if ((unsigned long)t->rx_buf & 0x03)
|
|
rx_fifo = sh_msiof_spi_read_fifo_s32u;
|
|
else
|
|
rx_fifo = sh_msiof_spi_read_fifo_s32;
|
|
} else {
|
|
bytes_per_word = 4;
|
|
if ((unsigned long)t->tx_buf & 0x03)
|
|
tx_fifo = sh_msiof_spi_write_fifo_32u;
|
|
else
|
|
tx_fifo = sh_msiof_spi_write_fifo_32;
|
|
|
|
if ((unsigned long)t->rx_buf & 0x03)
|
|
rx_fifo = sh_msiof_spi_read_fifo_32u;
|
|
else
|
|
rx_fifo = sh_msiof_spi_read_fifo_32;
|
|
}
|
|
|
|
/* setup clocks (clock already enabled in chipselect()) */
|
|
sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
|
|
sh_msiof_spi_hz(spi, t));
|
|
|
|
/* transfer in fifo sized chunks */
|
|
words = t->len / bytes_per_word;
|
|
bytes_done = 0;
|
|
|
|
while (bytes_done < t->len) {
|
|
void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
|
|
const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
|
|
n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
|
|
tx_buf,
|
|
rx_buf,
|
|
words, bits);
|
|
if (n < 0)
|
|
break;
|
|
|
|
bytes_done += n * bytes_per_word;
|
|
words -= n;
|
|
}
|
|
|
|
return bytes_done;
|
|
}
|
|
|
|
static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
|
|
u32 word, u8 bits)
|
|
{
|
|
BUG(); /* unused but needed by bitbang code */
|
|
return 0;
|
|
}
|
|
|
|
static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *r;
|
|
struct spi_master *master;
|
|
struct sh_msiof_spi_priv *p;
|
|
char clk_name[16];
|
|
int i;
|
|
int ret;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
|
|
if (master == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
|
ret = -ENOMEM;
|
|
goto err0;
|
|
}
|
|
|
|
p = spi_master_get_devdata(master);
|
|
|
|
platform_set_drvdata(pdev, p);
|
|
p->info = pdev->dev.platform_data;
|
|
init_completion(&p->done);
|
|
|
|
snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id);
|
|
p->clk = clk_get(&pdev->dev, clk_name);
|
|
if (IS_ERR(p->clk)) {
|
|
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
|
|
ret = PTR_ERR(p->clk);
|
|
goto err1;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
i = platform_get_irq(pdev, 0);
|
|
if (!r || i < 0) {
|
|
dev_err(&pdev->dev, "cannot get platform resources\n");
|
|
ret = -ENOENT;
|
|
goto err2;
|
|
}
|
|
p->mapbase = ioremap_nocache(r->start, resource_size(r));
|
|
if (!p->mapbase) {
|
|
dev_err(&pdev->dev, "unable to ioremap\n");
|
|
ret = -ENXIO;
|
|
goto err2;
|
|
}
|
|
|
|
ret = request_irq(i, sh_msiof_spi_irq, 0,
|
|
dev_name(&pdev->dev), p);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to request irq\n");
|
|
goto err3;
|
|
}
|
|
|
|
p->pdev = pdev;
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
/* The standard version of MSIOF use 64 word FIFOs */
|
|
p->tx_fifo_size = 64;
|
|
p->rx_fifo_size = 64;
|
|
|
|
/* Platform data may override FIFO sizes */
|
|
if (p->info->tx_fifo_override)
|
|
p->tx_fifo_size = p->info->tx_fifo_override;
|
|
if (p->info->rx_fifo_override)
|
|
p->rx_fifo_size = p->info->rx_fifo_override;
|
|
|
|
/* init master and bitbang code */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
|
|
master->flags = 0;
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = p->info->num_chipselect;
|
|
master->setup = spi_bitbang_setup;
|
|
master->cleanup = spi_bitbang_cleanup;
|
|
|
|
p->bitbang.master = master;
|
|
p->bitbang.chipselect = sh_msiof_spi_chipselect;
|
|
p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
|
|
p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
|
|
p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
|
|
p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
|
|
p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
|
|
p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
|
|
|
|
ret = spi_bitbang_start(&p->bitbang);
|
|
if (ret == 0)
|
|
return 0;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
err3:
|
|
iounmap(p->mapbase);
|
|
err2:
|
|
clk_put(p->clk);
|
|
err1:
|
|
spi_master_put(master);
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static int sh_msiof_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
ret = spi_bitbang_stop(&p->bitbang);
|
|
if (!ret) {
|
|
pm_runtime_disable(&pdev->dev);
|
|
free_irq(platform_get_irq(pdev, 0), p);
|
|
iounmap(p->mapbase);
|
|
clk_put(p->clk);
|
|
spi_master_put(p->bitbang.master);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int sh_msiof_spi_runtime_nop(struct device *dev)
|
|
{
|
|
/* Runtime PM callback shared between ->runtime_suspend()
|
|
* and ->runtime_resume(). Simply returns success.
|
|
*
|
|
* This driver re-initializes all registers after
|
|
* pm_runtime_get_sync() anyway so there is no need
|
|
* to save and restore registers here.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = {
|
|
.runtime_suspend = sh_msiof_spi_runtime_nop,
|
|
.runtime_resume = sh_msiof_spi_runtime_nop,
|
|
};
|
|
|
|
static struct platform_driver sh_msiof_spi_drv = {
|
|
.probe = sh_msiof_spi_probe,
|
|
.remove = sh_msiof_spi_remove,
|
|
.driver = {
|
|
.name = "spi_sh_msiof",
|
|
.owner = THIS_MODULE,
|
|
.pm = &sh_msiof_spi_dev_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(sh_msiof_spi_drv);
|
|
|
|
MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:spi_sh_msiof");
|