289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bug.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define SOC_PROCESS_CORNERS 1
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#define CPU_PROCESS_CORNERS 6
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#define FUSE_SPEEDO_CALIB_0 0x14
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#define FUSE_PACKAGE_INFO 0XFC
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#define FUSE_TEST_PROG_VER 0X28
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#define G_SPEEDO_BIT_MINUS1 58
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#define G_SPEEDO_BIT_MINUS1_R 59
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#define G_SPEEDO_BIT_MINUS2 60
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#define G_SPEEDO_BIT_MINUS2_R 61
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#define LP_SPEEDO_BIT_MINUS1 62
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#define LP_SPEEDO_BIT_MINUS1_R 63
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#define LP_SPEEDO_BIT_MINUS2 64
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#define LP_SPEEDO_BIT_MINUS2_R 65
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_2,
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THRESHOLD_INDEX_3,
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THRESHOLD_INDEX_4,
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THRESHOLD_INDEX_5,
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THRESHOLD_INDEX_6,
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THRESHOLD_INDEX_7,
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THRESHOLD_INDEX_8,
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THRESHOLD_INDEX_9,
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THRESHOLD_INDEX_10,
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THRESHOLD_INDEX_11,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
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{180},
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{170},
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{195},
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{180},
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{168},
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{192},
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{180},
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{170},
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{195},
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{180},
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{180},
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{180},
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};
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static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
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{306, 338, 360, 376, UINT_MAX},
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{295, 336, 358, 375, UINT_MAX},
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{325, 325, 358, 375, UINT_MAX},
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{325, 325, 358, 375, UINT_MAX},
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{292, 324, 348, 364, UINT_MAX},
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{324, 324, 348, 364, UINT_MAX},
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{324, 324, 348, 364, UINT_MAX},
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{295, 336, 358, 375, UINT_MAX},
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{358, 358, 358, 358, 397, UINT_MAX},
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{364, 364, 364, 364, 397, UINT_MAX},
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{295, 336, 358, 375, 391, UINT_MAX},
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{295, 336, 358, 375, 391, UINT_MAX},
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};
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static int threshold_index __initdata;
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static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
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{
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u32 reg;
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int ate_ver;
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int bit_minus1;
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int bit_minus2;
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reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
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*speedo_lp = (reg & 0xFFFF) * 4;
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*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
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ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
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pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
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if (ate_ver >= 26) {
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bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
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bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
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bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
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bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
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*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
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bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
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bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
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bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
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bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
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*speedo_g |= (bit_minus1 << 1) | bit_minus2;
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} else {
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*speedo_lp |= 0x3;
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*speedo_g |= 0x3;
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}
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}
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static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
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{
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int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
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switch (sku_info->revision) {
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case TEGRA_REVISION_A01:
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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case TEGRA_REVISION_A02:
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case TEGRA_REVISION_A03:
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switch (sku_info->sku_id) {
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case 0x87:
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case 0x82:
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sku_info->cpu_speedo_id = 1;
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sku_info->soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_1;
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break;
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case 0x81:
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switch (package_id) {
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case 1:
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sku_info->cpu_speedo_id = 2;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_2;
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break;
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case 2:
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sku_info->cpu_speedo_id = 4;
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sku_info->soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_7;
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break;
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default:
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pr_err("Tegra Unknown pkg %d\n", package_id);
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break;
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}
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break;
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case 0x80:
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switch (package_id) {
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case 1:
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sku_info->cpu_speedo_id = 5;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_8;
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break;
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case 2:
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sku_info->cpu_speedo_id = 6;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_9;
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break;
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default:
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pr_err("Tegra Unknown pkg %d\n", package_id);
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break;
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}
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break;
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case 0x83:
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switch (package_id) {
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case 1:
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sku_info->cpu_speedo_id = 7;
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sku_info->soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_10;
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break;
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case 2:
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sku_info->cpu_speedo_id = 3;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_3;
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break;
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default:
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pr_err("Tegra Unknown pkg %d\n", package_id);
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break;
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}
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break;
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case 0x8F:
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sku_info->cpu_speedo_id = 8;
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sku_info->soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_11;
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break;
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case 0x08:
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sku_info->cpu_speedo_id = 1;
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sku_info->soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_4;
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break;
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case 0x02:
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sku_info->cpu_speedo_id = 2;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_5;
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break;
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case 0x04:
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sku_info->cpu_speedo_id = 3;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_6;
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break;
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case 0:
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switch (package_id) {
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case 1:
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sku_info->cpu_speedo_id = 2;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_2;
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break;
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case 2:
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sku_info->cpu_speedo_id = 3;
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sku_info->soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_3;
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break;
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default:
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pr_err("Tegra Unknown pkg %d\n", package_id);
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break;
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}
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break;
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default:
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pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id);
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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}
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break;
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default:
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pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision);
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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}
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}
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void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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u32 cpu_speedo_val;
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u32 soc_speedo_val;
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int i;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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rev_sku_to_speedo_ids(sku_info);
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fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
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pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
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pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
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for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
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if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
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break;
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}
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sku_info->cpu_process_id = i - 1;
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if (sku_info->cpu_process_id == -1) {
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pr_warn("Tegra CPU speedo value %3d out of range",
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cpu_speedo_val);
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sku_info->cpu_process_id = 0;
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sku_info->cpu_speedo_id = 1;
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}
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for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
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if (soc_speedo_val < soc_process_speedos[threshold_index][i])
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break;
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}
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sku_info->soc_process_id = i - 1;
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if (sku_info->soc_process_id == -1) {
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pr_warn("Tegra SoC speedo value %3d out of range",
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soc_speedo_val);
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sku_info->soc_process_id = 0;
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sku_info->soc_speedo_id = 1;
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}
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}
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